Amplifier circuit building block

Abstract

A circuit for a building block of an impedance converting amplifier, in particular for use in a condenser microphone. The circuit topology comprises a pair of transistors, wherein a first terminal of a first transistor is connected to a first terminal of a third transistor and a first terminal of a second transistor is connected to a first terminal of a fourth transistor, wherein the third and fourth transistors form a differential input pair, a second terminal of the first transistor is connected to a second terminal of the second transistor; a first current source for providing a constant current, wherein the first current source is connected to the second terminal of the first transistor and the second terminal of the second transistor; a voltage follower, an output terminal of which is connected to the constant current, wherein a second terminal of the voltage follower is connected to the second terminal of the third transistor and the second terminal of the fourth transistor; and a voltage source for providing a voltage drop in the constant current, wherein the voltage source is connected between the output terminal of the voltage follower and the second terminals of the first and second transistors.

Description

Technical Field

[0001] This disclosure provides a circuit building block for use in an impedance conversion amplifier for a condenser microphone. Background Technology

[0002] In a condenser microphone, sound pressure is converted into an electrical signal. Typically, this is done by placing a charged diaphragm inside the microphone capsule near the backplate, where the two together form a capacitor. As the diaphragm vibrates in response to sound waves, the distance between the diaphragm and the backplate changes, altering the capacitance that can be converted into an electrical signal.

[0003] When air pressure changes, the voltage difference between the two electrodes in the microphone capsule changes. In most current microphone capsules, the signal voltage is large enough, but the current is extremely low. Using an impedance-transformer amplifier helps avoid the loading-down effect in condenser capsules. Impedance converters present extremely high input impedance and much lower output impedance, allowing traditional microphone preamplifiers to handle signal level matching issues during operation.

[0004] It is necessary to suppress distortion sources. One such distortion source is the inherent parasitic capacitance associated with the input transistors; this problem is particularly pronounced in settings using differential / operational amplifiers (although single-ended amplifier circuits are also used and face the same problem described here).

[0005] During normal operation, the input capacitance of the input transistor (e.g., a differential input JFET transistor with positive and negative inputs, respectively) needs to be dynamically charged and discharged by a signal source driving the gate. When the output impedance of the signal source is high, such as in the case of a capacitive microphone diaphragm with an output impedance in the range of 100kΩ to 1MΩ, the signal source cannot provide dynamic charging and discharging, which ultimately leads to nonlinear distortion in the output.

[0006] These parasitic capacitances attenuate the signal at the start of the input stage and prevent the complete signal from being transmitted; furthermore, the distortion level increases with the amount of parasitic capacitance. Since the distortion originates from the interaction of the input capsule, building a negative feedback loop around the transistor does not reduce distortion. It should be noted that in the case of a monolithic opamp, the nonlinear behavior of the capacitance between the substrate and the gate further exacerbates distortion.

[0007] Therefore, it is necessary to predict and mitigate distortion in impedance-transformer amplifiers. Typically, impedance converters must be designed with appropriate components and circuit topologies that include bootstrap elements. Combined with the common problem of parameter spread, achieving proper bootstrap operation often requires manual selection of electronic components; otherwise, the circuit may suffer severe nonlinearity due to the input transistor entering the low VDS "transistor" region, or worse, the circuit may not function at all. This presents a challenge for the mass production of bootstrap impedance converters for microphones. Summary of the Invention

[0008] According to at least one embodiment of this disclosure, a circuit or building block thereof for an impedance-converting amplifier or operational amplifier is provided, which is particularly advantageous for use in condenser microphones because it provides a nonlinear capacitance cancellation scheme. The circuit includes: a pair of transistors, including a first transistor and a second transistor, wherein a first terminal of the first transistor is configured to be connected to a first terminal of a third transistor, and a first terminal of the second transistor is configured to be connected to a first terminal of a fourth transistor, wherein the third and fourth transistors form a differential input pair, wherein a second terminal of the first transistor is connected to a second terminal of the second transistor; a first current source for providing a constant current stream, wherein the first current source is connected to a second terminal of both the first and second transistors; a voltage follower, wherein the output terminal of the voltage follower is connected to the constant current, wherein a second terminal of the voltage follower is connected to both the second terminals of the third and fourth transistors; and a voltage source for providing a voltage drop in the constant current, wherein the voltage source is connected between the output terminal of the voltage follower and the second terminals of the first and second transistors.

[0009] This circuit can be part of the differential input stage of an impedance-conversion amplifier / operational amplifier, wherein the corresponding third terminals of the third and fourth transistors are configured as input terminals for receiving (differential) input signals.

[0010] Optionally, each of the third and fourth transistors may include a field-effect transistor (FET); the FET may be a JFET or a MOSFET. Optionally, the first terminal of the third and fourth transistors is a drain terminal. Optionally, the third terminal of the third and fourth transistors is a gate terminal. Optionally, the second terminal of the third and fourth transistors is a source terminal.

[0011] Each of the first and second transistors may comprise a bipolar junction transistor (BJT) or a field-effect transistor (FET). If they are BJTs, optionally, the second terminals of the first and second transistors are their base terminals, and / or the first terminals of the first and second transistors are their emitter terminals. If they are FETs, optionally, the second terminals of the first and second transistors are their gate terminals, wherein the first and second transistors are FETs, and the first terminals of the first and second transistors are their source terminals.

[0012] A voltage follower may include a BJT, in which case the second terminal of the voltage follower may be the gate terminal and the output terminal may be the emitter terminal. A voltage follower may also include a FET, in which case the second terminal of the voltage follower may be the base terminal and the output terminal may be the source terminal.

[0013] The circuit may also include a second current source connected to the second terminals of the third and fourth transistors and the second terminal of the voltage follower.

[0014] The first transistor, the second transistor, the first current source, the voltage source, and the voltage follower can effectively form a bootstrap circuit or a portion thereof, which is configured to maintain the potential relationship between the third terminals of the third transistor and the fourth transistor relative to each other.

[0015] Optionally, the first transistor and the third transistor form a first cascaded pair, while the second transistor and the fourth transistor form a second cascaded pair.

[0016] Optionally, the first and second transistors are NPN type BJTs, the third and fourth transistors are N-channel JFETs, and the voltage follower includes a PNP type BJT; alternatively, the first and second transistors are PNP type BJTs, the third and fourth transistors are P-channel JFETs, and the voltage follower includes an NPN type BJT.

[0017] Optionally, the voltage source includes a programmable voltage reference.

[0018] Optionally, the circuit further includes a current mirror section, which preferably includes a fifth transistor and a sixth transistor coupled to a first transistor and a second transistor, wherein the first pair of transistors (the fifth transistor and the sixth transistor) is of the same type as the second pair of transistors (the fifth transistor and the sixth transistor).

[0019] This document also discloses an impedance conversion amplifier or operational amplifier that includes the circuit described above, preferably as a differential input stage or a part thereof.

[0020] A device, such as a microphone (particularly a high-impedance condenser microphone including a microphone capsule), is also disclosed, which includes the aforementioned impedance conversion amplifier / operational amplifier or circuit.

[0021] To make the invention easier to understand, various aspects of specific embodiments will now be described in conjunction with the accompanying drawings. Attached Figure Description

[0022] Figure 1 A circuit building block for use in an impedance conversion amplifier for a condenser microphone is shown according to one or more embodiments;

[0023] Figure 2 A circuit building block for use in an impedance conversion amplifier for a condenser microphone is shown according to one or more embodiments;

[0024] Figure 3 A circuit topology for an operational amplifier for a condenser microphone is shown according to one or more embodiments. Detailed Implementation

[0025] This disclosure provides circuit topologies 100, 200, and 300 for constructing an operational amplifier, and more specifically, the circuit topologies are suitable for the differential input stage 300A of an impedance-changing amplifier, which may also include a voltage amplification section and an output section, and the impedance-changing amplifier is suitable for use in a high-impedance condenser microphone.

[0026] This circuit topology includes an arrangement of connection components that can be considered as a circuit building block 100 for use in an operational amplifier or an operational amplifier-type circuit topology. This circuit topology provides a nonlinear capacitance cancellation scheme for ultra-high impedance amplifiers. In other words, the use of this circuit topology advantageously improves, for example, the linearity of the impedance-changing amplifier in a condenser microphone, as well as the linearity of the condenser microphone capsule itself.

[0027] This arrangement includes a self-biased cascade (or cascaded) configuration of transistors 110, 112, preferably a differential input pair of FETs (JFETs or MOSFETs). This is a bootstrap arrangement that maintains the potential relationship between the input terminals 110G, 112G and each other, so the source and drain terminals must follow the dynamic movement of the gate. In other words, controlled positive feedback is applied from the source to the drain. It should be noted that bipolar junction transistors (BJTs) can be used for the differential input pair 110, 112 (in which case the emitter and collector terminals follow the dynamic movement of the base), but this is not preferred for capacitive microphone impedance converters.

[0028] Advantageously, the bootstrap action reduces the input capacitance of the input stage 300A of the differential amplifier circuit 300, thereby resulting in a reduction of distortion products inherent in the microphone capsule itself. This eliminates or reduces input signal-dependent nonlinear modulation of the input transistor parasitic capacitance (counteracting the effect of the inherent capacitance on both sides of the input FET), which is typically a major source of distortion in capacitive microphone impedance converters.

[0029] Other advantages of the following circuit topology include:

[0030] 1) It can be used as a building block for integration into traditional operational amplifier circuit topologies.

[0031] 2) Its performance is not affected by parameter dispersion and has low requirements for parameter matching; therefore, it is a very stable topology.

[0032] 3) This circuit consumes low current (e.g., only about 200uA).

[0033] 4) No manual adjustment is required (in some topologies, the emitter resistor needs adjustment or better bias conditions due to a large DC offset at the output).

[0034] 5) The VDS voltage of the input transistor can be adjusted.

[0035] 6) By using a differential input stage, the output bias voltage is inherently minimized.

[0036] Detailed description

[0037] This document discloses circuit building blocks 100, 200, and 300 for use in operational amplifiers or impedance-changing amplifiers for condenser microphones. The main characteristics of the circuit topologies can be described as follows:

[0038] A voltage follower 130 is connected to the tail of the differential amplifier. This voltage follower outputs its voltage into a constant current supplied by a current source 150. Within this constant current are two cascaded transistors 120 and 122 that drive the differential input transistors 110 and 112. A voltage reference 140 is placed in a constant current between the output of the follower 130 and the bases of the cascaded transistors 120 and 122.

[0039] Figure 1 Example 100 of this circuit topology is shown. It illustrates a portion of an operational amplifier circuit according to a first embodiment. Figure 2 Further details are provided for implementation under the same or other implementation schemes.

[0040] A differential input is provided, comprising a matched and source-coupled first input transistor 110 and a second input transistor 112. Figure 2 In the preferred example shown, JFETs are used, specifically N-channel JFETs 210 and 212. Positive and negative input signals are provided at the respective gate terminals 170 and 172 of these input JFETs. Alternatively, input transistors 110 and 112 may be P-channel JFETs, N-channel MOSFETs, or P-channel MOSFETs, but these may be less preferred options.

[0041] A pair of transistors 120 and 122 are provided, preferably of the same type. Figure 2 In the preferred example shown, both are bipolar junction transistors (BJTs), specifically NPN type BJTs 220 and 222. Field-effect transistors (e.g., MOSFETs) can also be used. They are connected to the differential input pair transistors 110 / 210 and 112 / 212 and are configured to drive the differential input pair transistors. The base terminals (or gate terminals if FETs are used) of this pair of transistors 120 / 220 and 122 / 222 are connected to each other. This results in a cascaded or cascaded arrangement in the circuit, and the two transistors can be referred to as a pair of cascaded transistors 120 / 220 and 122 / 222. The cascading action occurs between the input transistor 110 / 210 or 112 / 212 (a common-source amplifier, in this example, a JFET) and its directly coupled corresponding cascaded transistor 120 / 220 or 122 / 222 (a common-base amplifier, in this example, a BJT). Due to its symmetrical nature, the circuit topology 100 / 200 can be considered to consist of two "cascaded structures." Combining the cascaded transistor pairs 120 / 220 and 122 / 222 in this way allows the bootstrap circuit implementation to maintain the potential relationship between the differential inputs 170 and 172 of the impedance converter relative to each other. It should be noted that if an N-channel FET is used as the input transistor, then an NPN BJT or N-channel FET should be used as the corresponding cascaded transistor, and vice versa.

[0042] In the illustrated example, the emitter terminal of each of the two cascaded transistors 220, 222 is connected to the drain terminal of each of the input JFETs 210, 212, respectively.

[0043] A first current source 150 (DC) is provided in the bootstrap circuit to provide a constant current. This first current source is connected to a supply voltage of 190 / 290.

[0044] A voltage source 140, also known as a voltage reference (DC), is provided.

[0045] In addition to being connected to each other, the base terminals of the two cascaded transistors 220 and 222 are further connected to the first current source 250 and the voltage source 240.

[0046] A voltage follower component 130 is provided, which is connected to the tail of the differential amplifier (the two input transistors 110, 112 are conventionally referred to as the long-tail pair), at which a second current source 160 is provided. This voltage follower is configured to provide isolation between the bootstrap circuitry and the tail of the differential amplifier, so that DC bias current does not flow from the bootstrap circuitry into the tail of the differential amplifier. The exact specific implementation of this voltage follower 130 is not limited and can be implemented in different ways. Figure 2 In the example shown, the PNP BJT transistor 230 is used as a voltage follower because the input transistors 210 and 212 are N-channel; a P-channel FET could also be used (if the input transistors are P-channel, either an NPN BJT or an N-channel FET can be used as the voltage follower component). The base terminal (or gate if using an FET) is connected to the tail, i.e., to the source terminal of each of the differential input pair FETs 210 and 212, and to the second current source 160. The emitter terminal (or source if using an FET) is connected to the bootstrap circuit current source 150. The collector terminal (or drain if using an FET) is connected to ground or to an appropriate voltage supply rail.

[0047] Voltage follower 130 / 230 outputs voltage to a constant current supplied by current source 150.

[0048] The voltage source / reference 140 is placed at the output of the voltage follower 130 / 230 (e.g. Figure 1 A constant current flows between the emitter terminal (shown) and the base of the cascaded transistors 120 / 220 and 122 / 222. Voltage source 140 generates a voltage drop. This allows two cascaded transistors, both under constant current, to properly bias different pairs of JFET input transistors 110 / 210 and 112 / 212. This helps avoid operation in the nonlinear, low-VDS transistor region.

[0049] In addition to the circuit topology 100 described above, which is suitable for use as part of the differential input stage in an operational amplifier, a current mirror circuit is preferably also connected.

[0050] Figure 2 Will Figure 1 The circuit topology 100 is shown as block 200A, in which additional components forming the current mirror loaded differential amplifier topology 200 are connected. The concept of the current mirror section 200B is known and is only briefly described here.

[0051] A pair of transistors 270 and 272 are provided, each of which is connected to a corresponding one of the aforementioned cascaded transistors 120 / 220 and 122 / 222. In the example where the cascaded transistors are a pair of NPN bipolar transistors, the two transistors 270 and 272 in the current mirror are PNP bipolar transistors. The collector of each cascaded transistor is coupled to the collector of a corresponding current mirror transistor in current mirror transistors 270 and 272. The base terminals of the current mirror transistors are interconnected. For one current mirror transistor, the base terminal and collector terminal are coupled together; in Figure 2 In the example, this is transistor 272 connected to cascaded transistor 222, which itself is connected to the negative input JFET 212. Each emitter terminal of current mirror transistors 270, 272 is connected to the power supply voltage 290.

[0052] Figure 3 An example of a prototype operational / differential amplifier circuit 300 of an impedance-converting amplifier is shown. It includes a differential input stage section 300A, a voltage amplification section 300B, and an output section 300C.

[0053] The differential input stage 300A includes Figure 1 and Figure 2 The specific implementation of building modules 100 and 200 as shown and described above.

[0054] The above about Figure 1 and 2 The generalized voltage source 140 discussed can be implemented in different ways. Preferably, a programmable voltage reference programmed via a resistor divider is provided, which generates a specific voltage drop within a constant current. Figure 3 A non-limiting example is shown, in which the specific implementation involves a Zener diode (parallel regulator) 342 whose two terminals are connected together (e.g., to generate a 2.5V voltage reference), and whose anode is coupled to a voltage follower 330 (specifically, the emitter terminal of a voltage follower of a PNP transistor).

[0055] The above about Figure 1 The generalized first current source 150 discussed can be implemented in different ways. Figure 3A non-limiting example is shown. In this example, the current source comprises two bipolar transistors 352 and 354 and two fixed resistors 356 and 358. Specifically: both transistors are PNP type BJTs; the base of the first transistor 352 is connected to the emitter of the second transistor 354 and is connected via the first resistor 356 to the power supply voltage 390 (e.g., +15V) of the operational amplifier circuit; the base of the second transistor 354 is connected to the collector of the first transistor 352 and is connected via the second resistor 358 to ground / appropriate voltage supply rail; the collector of the second transistor 354 is coupled to the pair of cascaded transistors 320 and 322 and voltage references 342 and 344.

[0056] Similarly, the above about Figure 1 The generalized second current source 160 discussed can be implemented in different ways. Figure 3 A non-limiting example is shown. In this example, the current source comprises two bipolar transistors 362 and 364 and two fixed resistors 366 and 368. Specifically: both transistors are NPN type BJTs; the base of the first transistor 362 is connected to the emitter of the second transistor 364 and is connected to a supply voltage (e.g., +15V) via the first resistor 366; the base of the second transistor 364 is connected to the collector of the first transistor 362 and is connected to ground / an appropriate voltage supply rail via the second resistor 368; the collector of the second transistor 364 is coupled to the pair of input transistors 310 and 312 and the voltage follower 330.

[0057] In the current mirror, each of the pair of transistors 370, 372, as described above, is connected to the power supply voltage via corresponding resistors 374, 376.

[0058] On the positive input signal side (i.e., the side where the cascaded transistor 320 is connected to the input JFET 310), the current mirror transistor 370 is coupled to the collector terminal of the cascaded transistor to the voltage amplification stage 300B of the operational amplifier 300. The voltage amplification stage 300B and the output stage 300C are not described in detail here.

[0059] It must be emphasized that Figure 3 Examples of how to use the circuit building blocks 100 and 200 of the amplifier differential input stage are provided; current and voltage sources can be implemented in different ways depending on the actual situation (e.g., depending on whether it is a low-current or high-current environment). Figure 1 and Figure 2 The transistor shown can also be made of other types of transistors, as appropriate. Figure 3 Replace other components and parts in it.

[0060] This invention is not limited to the aspects and embodiments described above, and many variations are within the scope of the appended claims. Various aspects and embodiments may be combined if necessary and appropriate. The accompanying drawings are provided merely as illustrative examples to aid in understanding the invention.

Claims

1. A circuit for an impedance-conversion amplifier, comprising: A pair of transistors, the pair of transistors including a first transistor and a second transistor, wherein a first terminal of the first transistor is configured to be connected to a first terminal of a third transistor, and a first terminal of the second transistor is configured to be connected to a first terminal of a fourth transistor, wherein the third transistor and the fourth transistor form a differential input pair, wherein a second terminal of the first transistor is connected to a second terminal of the second transistor; A first current source, wherein the first current source is used to provide a constant current, and wherein the first current source is connected to the second terminal of the first transistor and the second terminal of the second transistor; A voltage follower, wherein the output terminal of the voltage follower is connected to the constant current, and wherein the second terminal of the voltage follower is connected to the second terminal of the third transistor and the second terminal of the fourth transistor; as well as A voltage source for providing a voltage drop in the constant current, wherein the voltage source is connected between the output terminal of the voltage follower and the second terminal of the first transistor and the second transistor.

2. The circuit of claim 1, wherein the circuit is part of the differential input stage of a differential amplifier, wherein the respective third terminals of the third transistor and the fourth transistor are configured to receive an input signal.

3. The circuit according to any one of claims 1 to 2, wherein the third transistor and the fourth transistor are field-effect transistors (FETs).

4. The circuit of claim 3, wherein the first terminal of the third transistor and the fourth transistor is a drain terminal, and / or wherein the third terminal of the third transistor and the fourth transistor is a gate terminal.

5. The circuit according to any one of claims 1 to 4, Wherein the first transistor and the second transistor are bipolar junction transistors (BJTs), and the second terminals of the first transistor and the second transistor are their base terminals, or The first transistor and the second transistor are FETs, and the second terminals of the first transistor and the second transistor are their gate terminals.

6. The circuit according to any one of claims 1 to 5, Wherein the first transistor and the second transistor are BJTs, and the first terminals of the first transistor and the second transistor are their emitter terminals, or The first transistor and the second transistor are FETs, and the first terminals of the first transistor and the second transistor are their source terminals.

7. The circuit according to any one of claims 1 to 6, The voltage follower includes a BJT, and the second terminal of the voltage follower is a gate terminal, and the output terminal is an emitter terminal, or The voltage follower includes a FET, and the second terminal of the voltage follower is the base terminal, and the output terminal is the source terminal.

8. The circuit according to any one of claims 1 to 7, further comprising a second current source connected to the second terminals of the third transistor and the fourth transistor and the second terminal of the voltage follower.

9. The circuit according to any one of claims 1 to 8, wherein the first transistor, the second transistor, the first current source, the voltage source and the voltage follower form a bootstrap circuit or a portion thereof for maintaining the potential relationship of the third terminals of the third transistor and the fourth transistor relative to each other.

10. The circuit according to any one of claims 1 to 9, wherein the first transistor and the third transistor form a first cascaded pair, and the second transistor and the fourth transistor form a second cascaded pair.

11. The circuit according to any one of claims 1 to 10, wherein the first transistor and the second transistor are NPN type BJTs, the third transistor and the fourth transistor are N-channel JFETs, and the voltage follower includes a PNP type BJT.

12. The circuit according to any one of claims 1 to 10, wherein the first transistor and the second transistor are PNP type BJTs, the third transistor and the fourth transistor are P-channel JFETs, and the voltage follower includes an NPN type BJT.

13. The circuit according to any one of claims 1 to 12, wherein the voltage source comprises a programmable voltage reference.

14. An impedance-converting amplifier or operational amplifier comprising the circuitry of any one of claims 1 to 13, said circuitry being a differential input stage or a portion thereof.

15. A condenser microphone comprising an impedance-conversion amplifier or operational amplifier as claimed in claim 14.

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