A low-bit quantization gain control circuit and control method for a UWB receiving baseband chip

Abstract

This invention belongs to the field of gain control technology for wireless communication baseband chips. It discloses a low-bit quantization gain control circuit and method for UWB receiver baseband chips. The I / Q analog baseband signal sequentially passes through a variable gain amplification unit, an I / Q positive and negative threshold comparator array, and a low-bit quantization output unit before being sent to a digital baseband processing unit. A state control finite state machine generates gain adjustment, threshold half-width adjustment, bias center adjustment, and lock control signals based on the statistical results output by the comparison counting unit. These signals are then sent to the corresponding register units or control units via a control bus. This invention can utilize the statistical information output by the comparators themselves to collaboratively complete the convergence of variable gain, positive and negative comparison threshold half-width, and I / Q bias center before the data field arrives, and lock the control word during the data field, thereby improving weak signal detectability, strong signal anti-saturation capability, I / Q DC bias compensation capability, and low-bit quantization stability.

Description

Technical Field

[0001] This invention belongs to the field of wireless communication baseband chip gain control technology, specifically relating to a low-bit quantization gain control circuit and control method for UWB receiver baseband chips. Background Technology

[0002] Ultra-wideband (UWB) technology, with its advantages of large signal bandwidth, high time resolution, strong multipath resistance, high ranging accuracy, and low power consumption, has been widely used in short-range wireless communication, high-precision ranging, indoor positioning, digital keys, IoT terminals, and radar sensing. In a UWB receiver, the radio frequency signal received by the antenna typically undergoes low-noise amplification, down-conversion, filtering, variable gain amplification, and analog-to-digital conversion before being sent to the digital baseband for synchronization detection, preamble correlation, channel estimation, demodulation, and decoding.

[0003] In UWB receiver baseband chips, the analog-to-digital converter (ADC) and automatic gain control circuit are crucial modules affecting chip power consumption, area, receiver sensitivity, and dynamic range. Due to the characteristics of UWB signals, such as narrow pulse width, high sampling rate, bursty packet structure, and significant timing differences between preamble and data fields, using a high-resolution, high-sampling-rate ADC, while achieving high quantization accuracy, significantly increases chip area, power consumption, and design complexity, hindering the implementation of low-power, miniaturized UWB terminal chips. Especially in battery-powered portable devices, tag devices, and embedded sensing nodes, the power consumption of the receiver link is often strictly limited; therefore, employing a low-bit quantization structure to reduce ADC complexity becomes a valuable engineering approach.

[0004] Low-bit quantization is typically achieved using one-, two-, or a small number of-bit comparator arrays, which reduces the circuit complexity and power consumption of the ADC. However, this method is highly sensitive to the amplitude of the input signal and the comparison threshold: when the input signal is too weak, the comparator output may not toggle for a long time, resulting in insufficient effective quantization information; when the input signal is too strong, the comparator output is prone to saturation, causing input signals of different amplitudes to be mapped to the same quantization result; when there is amplitude imbalance, DC bias, or asymmetric positive and negative swings in the I / Q signals, the fixed threshold structure may also cause quantization distortion in one path or a branch of a certain polarity. These problems directly weaken the reliability of subsequent UWB digital baseband in synchronization, demodulation, and ranging processing.

[0005] Existing automatic gain control methods commonly used in receivers estimate signal strength based on the average power, root mean square (RMS) value, or peak value of the received signal, and adjust the gain of the variable gain amplifier accordingly. While these methods are applicable to conventional communication receivers, they have shortcomings in low-bit UWB receiver links: First, control methods based on overall power or peak value typically require more sampling points and more complex amplitude estimation circuits, making it difficult to simultaneously meet the convergence speed and hardware complexity requirements of low-power UWB baseband chips. Second, these methods usually only control the amplifier gain, failing to utilize the low-bit comparator's own positive and negative threshold statistics, saturation statistics, and polarity imbalance statistics, making it difficult to solve the problems of insufficient weak signal switching, strong signal saturation, and positive and negative comparison window imbalance in low-bit quantization. Third, in scenarios with strong signal input or close-range reception, simply reducing the gain may not prevent comparator saturation in time; while in weak signal scenarios, simply increasing the gain may introduce noise amplification, and even when the gain has reached its upper limit, it still cannot guarantee effective comparator switching.

[0006] Furthermore, UWB data frames typically include different fields such as a synchronization header, an STS field, a physical layer header, and a data payload. For low-bit UWB receivers, the critical timing requirement is not to repeatedly switch gain or thresholds between different fields, but rather to achieve gain and quantization threshold convergence of the receive link within the preamble, synchronization segment, or a preset training statistical window, and to lock the control word before the arrival of the data field, keeping the comparison threshold and gain stable during the data field. If the gain or comparison threshold is continuously changed during the data field, it will cause low-bit quantization scale drift, which will affect the stability of subsequent synchronization maintenance, demodulation, CIR generation, or ranging processing.

[0007] On the other hand, for low-bit quantization structures implemented using comparators and threshold DACs, setting only a fixed comparison threshold makes it difficult to adapt to received signals under different distances, channel fading, antenna gains, process variations, and input amplitudes. When there is DC bias, comparator misalignment, or asymmetrical positive and negative swings in the I or Q paths, fixed positive and negative thresholds may also lead to a long-term imbalance between the positive and negative comparison outputs, causing the low-bit quantization result to be biased towards one polarity. Pre-configuring fixed gain and fixed thresholds for each scenario requires a complex calibration process and has poor adaptability to changes in the actual environment. If quantization distortion is compensated entirely by software or digital baseband post-processing, the lost low-bit quantization information is difficult to recover if the front-end comparator is already saturated or has not toggled for a long time.

[0008] Therefore, a low-bit UWB receiver baseband control scheme is needed: directly multiplexing the positive and negative threshold statistics of the comparator output, updating the gain, threshold half-width and offset center in a coordinated manner with preset priority, and locking the control word before the data field, thereby simultaneously handling the problems of insufficient weak signal flipping, strong signal saturation and polarity imbalance. Summary of the Invention

[0009] To address the aforementioned technical problems, this invention provides a low-bit quantization gain control circuit and method for UWB receiver baseband chips. This circuit utilizes statistical information from the comparator's own output to collaboratively complete the convergence of variable gain, positive and negative comparison threshold half-width, and I / Q bias center before the data field arrives. It also locks the control word during the data field to improve weak signal detectability, strong signal anti-saturation capability, I / Q DC bias compensation capability, and low-bit quantization stability.

[0010] The present invention provides a low-bit quantization gain control circuit for a UWB receiver baseband chip, comprising: A variable gain amplifier unit is used to receive the I-channel analog baseband signal and the Q-channel analog baseband signal output from the UWB receiver, and to adjust the gain of the I-channel analog baseband signal and the Q-channel analog baseband signal according to the gain control word. An I / Q positive and negative threshold comparator array is used to compare the gain-adjusted I / Q signal with the corresponding positive and negative comparison thresholds respectively, and generate I-channel positive comparison result, I-channel negative comparison result, Q-channel positive comparison result and Q-channel negative comparison result; The low-bit quantization output unit is used to form an I-channel two-bit raw quantization code from the I-channel positive comparison result and the I-channel negative comparison result, and to form a Q-channel two-bit raw quantization code from the Q-channel positive comparison result and the Q-channel negative comparison result, so as to form a low-bit I / Q quantization output containing four comparison bits. A threshold / bias generation circuit is used to generate corresponding positive comparison thresholds and negative comparison thresholds based on the bias center value and threshold half-width value set for the I and Q paths, respectively. The positive comparison threshold is the sum of the bias center value and the threshold half-width value, and the negative comparison threshold is the difference between the bias center value and the threshold half-width value. The threshold half-width value controls the width of the comparison window between the positive and negative comparison thresholds, and the bias center value controls the center position of the comparison window. The comparison counting unit is used to count the number of positive and negative threshold crossings of the four comparison results within a preset statistical window, and to obtain the effective threshold crossing ratio, saturation ratio, and imbalance between the positive and negative comparison results of the same channel based on the number of positive and negative threshold crossings. A state control finite state machine is used to coordinate and schedule the gain control word, threshold half-width control word, and bias center control word according to the statistical results of the comparison counting unit and a preset priority. A gain control register unit is used to store the gain control word and update the gain control word according to the gain adjustment signal; A threshold / bias control register unit is used to store the threshold half-width control word and the bias center control word, and update the corresponding control word according to the threshold half-width adjustment signal and the bias center adjustment signal; A locking control unit is used to lock the gain control word, threshold half-width control word, and bias center control word when the continuous locking condition is met, so that the low-bit quantization output unit outputs low-bit I / Q quantization results with stable gain and threshold during the data field.

[0011] Furthermore, the threshold / bias generation circuit generates positive and negative comparison thresholds in pairs based on the bias center value and the threshold half-width value: , In the formula, This represents the positive comparison threshold for the c-th path within the m-th statistical window; This represents the offset compensation center value of the c-th path within the m-th statistical window; This represents the threshold half-width value of the c-th path within the m-th statistical window; This indicates the mismatch adjustment amount of the c-th positive comparator; , In the formula, This represents the negative comparison threshold for the c-th path within the m-th statistical window; This indicates the mismatch adjustment amount of the c-th negative comparator; when When the threshold decreases, both the positive and negative comparison thresholds shrink synchronously towards the bias center; when As the value increases, both the positive and negative comparison thresholds expand synchronously away from the bias center; when... When the values ​​change, the positive and negative comparison thresholds shift as a whole.

[0012] Furthermore, the comparison counting unit counts: Effective threshold crossing ratio: , And the imbalance of the positive and negative comparison outputs on the same path: , In the formula, This represents the average effective threshold crossing rate of the four comparators within the m-th statistical window; This represents the number of times the positive threshold is exceeded in the c-th path; represents the number of times the negative threshold of the c-th path is exceeded; N represents the statistical window length; the constant 4 represents the four types of comparison results: I-path positive comparison, I-path negative comparison, Q-path positive comparison, and Q-path negative comparison. This represents the imbalance of the c-th positive / negative comparison output within the m-th statistical window; This represents a small constant to prevent the denominator from being zero; The state control finite state machine is based on the average effective threshold crossing ratio. Determine the signal strength based on the aforementioned imbalance. Determine the state of bias imbalance.

[0013] Furthermore, the state control finite state machine includes: Initialization state IDLE, weak signal fast adjustment state LFAST, weak signal slow adjustment state LSLOW, strong signal threshold pull-up state THUP, strong signal gain pull-back state PULL, stepped threshold processing state STEP, and output lock state LOCK. In the initialization state, the circuit loads the initial gain control word, the initial threshold half-width control word, and the initial bias center control word; When the effective threshold ratio is lower than the fast adjustment threshold, the finite state machine enters the LFAST state, and prioritizes increasing the gain of the variable gain amplifier unit with the first gain adjustment step size. When the effective threshold crossing ratio is between the fast adjustment threshold and the weak signal threshold, the finite state machine enters the LSLOW state and adjusts the gain with a second gain adjustment step size, wherein the first gain adjustment step size is larger than the second gain adjustment step size. When the effective threshold crossing ratio is higher than the strong signal threshold and hard saturation is not triggered, the finite state machine enters the THUP state and preferentially increases the threshold half-width. When the threshold half-width reaches the preset upper limit or the saturation ratio is higher than the preset saturation judgment threshold, the finite state machine enters the PULL state and pulls back the gain of the variable gain amplifier unit. When the effective threshold crossing ratio is within the preset effective range, the finite state machine enters the stepped threshold processing state, selects the corresponding threshold half-width step value according to the current gain control word, and performs code-level alignment on the threshold half-width control word and the offset center control word; when K consecutive K values ​​are in the stepped threshold processing state... lock When a statistical window meets the continuous locking condition, or when a preset locking window is reached, the finite state machine enters the locking output state from the stepped threshold processing state, locking each control word.

[0014] Furthermore, in the bias-unbalanced state, the state-controlled finite state machine determines the balance between the positive and negative comparison counts in the same path based on the imbalance amount. Update the offset center value for this path: , In the formula, This represents the updated offset compensation center value for the c-th path; Indicates the offset update step size; This indicates the imbalance of the positive and negative comparison output of the c-th path; and These represent the lower and upper limits of the bias compensation center value, respectively; Represents the amplitude limiting function; When the imbalance is greater than a preset positive imbalance threshold, the bias center value is compensated in the positive direction; when the imbalance is less than a preset negative imbalance threshold, the bias center value is compensated in the negative direction; wherein the preset positive imbalance threshold is greater than zero and the preset negative imbalance threshold is less than zero.

[0015] Furthermore, the continuous locking conditions of the locking control unit include: The effective threshold crossing ratio remains between the preset lower limit and the preset upper limit for several consecutive statistical windows; The saturation ratio is below the saturation threshold for several consecutive statistical windows. The imbalance of each positive and negative comparison result is below the bias imbalance judgment threshold for several consecutive statistical windows. When all the above locking conditions are met, or when the preset locking window of the UWB frame is reached, the locking control unit keeps the current gain control word, threshold half-width control word, and offset center control word unchanged, and maintains the locked state during the data field.

[0016] This invention also provides a low-bit quantization gain control method for a UWB receiver baseband chip, implemented based on the aforementioned low-bit quantization gain control circuit for a UWB receiver baseband chip, comprising the following steps: Step S1: Initialize configuration: Load the initial gain control word, initial threshold half-width control word, initial bias center control word, and decision parameters; Step S2, Variable Gain Amplification: Adjust the gain of the I-channel analog baseband signal and the Q-channel analog baseband signal according to the current gain control word; Step S3, Threshold Generation and Comparison: Based on the current bias center control word and threshold half-width control word, generate I-channel positive comparison threshold, I-channel negative comparison threshold, Q-channel positive comparison threshold, and Q-channel negative comparison threshold respectively; compare the gain-adjusted I / Q signals with the corresponding positive and negative comparison thresholds respectively to generate four comparison results; Step S4, Comparison Counting and State Determination: Within a preset statistical window, count the effective threshold crossing ratio, saturation ratio, and positive-negative comparison imbalance of the four comparison results, and determine the current signal state based on the statistical results; Step S5, Coordinated Scheduling and Adjustment: Based on the determined signal state, coordinately adjust the gain control word, threshold half-width control word, and offset center control word according to the preset priority; repeat steps S2 to S5 in the next statistical window with the updated control word until the locking condition is met. Step S6, Lock Output: When the continuous locking condition is met, lock each control word and output low-bit I / Q quantization results with stable gain and threshold during the data field.

[0017] The beneficial effects of this invention are as follows: 1) This invention achieves UWB received baseband signal quantization through a low-bit comparator, a comparator counter, a state control unit, and a register control structure, reducing the dependence on the high-resolution ADC and its amplitude estimation data path; 2) This invention controls the positive and negative comparison thresholds in pairs by using the threshold half-width parameter, thus avoiding the asymmetry of the positive and negative comparison windows caused by adjusting only one side of the threshold; 3) This invention compensates for I / Q DC bias, comparator offset, or reference voltage deviation by setting a bias center value, thereby reducing the risk of the positive and negative comparison outputs being biased towards one polarity for a long time. 4) This invention coordinates the gain, threshold half-width, and bias center according to clear priorities, which can respectively improve the quantization distortion caused by insufficient switching of weak signals, saturation of comparison of strong signals, and bias imbalance. 5) The present invention completes control word convergence and locking within a preset training statistics window; the duration of the training statistics window is configured by the statistics window length, sampling clock and number of locking windows, so that its end time is earlier than the start time of the data field, thereby reducing the impact of control word transitions in the data field on subsequent synchronization, demodulation, CIR generation or ranging processing. Attached Figure Description

[0018] Figure 1 This is a block diagram of the overall structure of the UWB receiver baseband chip; Figure 2 This is a schematic diagram of a low-bit quantization gain control circuit. Figure 3 This is a schematic diagram showing the connection between the I / Q positive and negative comparators and the threshold / bias DAC; Figure 4 This is a diagram showing the comparison counting window and the counting results; Figure 5 This is the state transition diagram of the state control unit; Figure 6 This is a flowchart of the closed-loop adjustment process for weak signal thresholds; Figure 7 This is a flowchart of strong signal threshold pull-up and gain pull-back; Figure 8 This is a schematic diagram of the step threshold generation; Figure 9 This is a timing diagram of the UWB frame structure and gain / threshold locking. Figure 10 This is an overall flowchart of the method of the present invention; Figure 11This is a comparison chart of the quantization effects of a fixed threshold and the adaptive threshold of this invention; Figure 12 These are the convergence curves of gain and threshold half-width under different input amplitudes, where... Figure 12 (a) represents the convergence process of VGA gain with respect to the statistical window under different input amplitudes. Figure 12 (b) represents the convergence process of the corresponding threshold DAC code with the statistical window. Detailed Implementation

[0019] To make the content of this invention easier to understand, the invention will be further described in detail below with reference to specific embodiments and accompanying drawings. Without departing from the concept of this invention, any equivalent substitutions or modifications made by those skilled in the art to related circuit units, state control logic, threshold numbers, statistical methods, and register configuration methods should fall within the protection scope of this invention.

[0020] Example 1

[0021] This invention provides a low-bit quantization gain control circuit for a UWB receiver baseband chip, the overall position of which is as follows: Figure 1 As shown, this circuit is positioned after the mixer and analog baseband unit and before the digital baseband synchronization / demodulation unit. It is used to perform variable gain amplification, positive and negative threshold comparison, low-bit quantization output, gain closed-loop control, threshold half-width closed-loop control, bias center compensation, and output locking on the I / Q signals output from the analog baseband. The main control interface register is used to configure parameters such as initial gain, initial threshold half-width, initial bias center, effective over-threshold ratio range, saturation judgment threshold, bias balance judgment threshold, and lock window position. The configuration / lock register unit is used to store the locked gain control word, threshold half-width control word, and bias center control word, and writes the locked state back to the main control interface register.

[0022] like Figure 2 As shown, the low-bit quantization gain control circuit of this invention includes an I / Q analog baseband input terminal, a variable gain amplifier unit, an I / Q positive and negative threshold comparator array, a low-bit quantization output unit, a comparator counting unit, a state control finite state machine, a gain control register unit, a threshold / bias control register unit, a threshold / bias generation circuit, and a lock control unit. The upper part is the data path; the I / Q analog baseband signal sequentially passes through the variable gain amplifier unit, the I / Q positive and negative threshold comparator array, and the low-bit quantization output unit before being sent to the digital baseband processing unit. The lower part is the control path; the state control finite state machine generates gain adjustment, threshold half-width adjustment, bias center adjustment, and lock control signals based on the statistical results output by the comparator counting unit. Each control signal is sent to the corresponding register unit or control unit via the control bus.

[0023] The variable gain amplifier unit is used to synchronously amplify or pull back the I-channel and Q-channel analog baseband signals according to the gain control word output by the gain control register unit. This unit can be implemented using a variable gain amplifier, a programmable attenuation / amplification network, a switched-capacitor gain unit, or an equivalent on-chip analog gain control structure. The gain control register unit receives gain update instructions from the state control finite state machine, increases the equivalent gain in weak signal conditions, pulls back the equivalent gain in strong signal or saturation conditions, and maintains the gain control word unchanged after locking.

[0024] An I / Q positive and negative threshold comparator array is used to compare the amplified I / Q signals for positive and negative thresholds. For example... Figure 3 As shown, the comparator array includes an I-channel positive comparator, an I-channel negative comparator, a Q-channel positive comparator, and a Q-channel negative comparator. Each of the four comparators can have an independent input branch and an independent comparison threshold, but the comparison threshold is preferably generated in pairs from the threshold half-width and the bias center value. For any signal c, where c is I or Q, its positive comparison threshold and negative comparison threshold are expressed as follows: , In the formula, This represents the positive comparison threshold for the c-th path; This represents the offset center value of the c-th path; This represents the threshold half-width of the c-th path; This indicates the mismatch adjustment amount of the c-th positive comparator; , In the formula, This represents the negative comparison threshold for the c-th path; This represents the offset center value of the c-th path; This represents the threshold half-width of the c-th path; This represents the mismatch adjustment amount of the c-th negative comparator.

[0025] like Figure 3 As shown, in the implementation using a DAC, B I B Q These are the offset center values ​​for I-path and Q-path, respectively, and A I A Q These are the threshold half-width values ​​for the I-path and Q-path, respectively; , , , These correspond to the DAC outputs of the four positive and negative comparison thresholds, respectively. Figure 3 Mismatch adjustment values ​​not separately indicated can be zero or incorporated into the corresponding DAC code. Therefore, the I-channel positive comparator outputs the comparison bit. I-channel negative comparator output comparison bit Q-channel positive comparator outputs comparison bit Q-channel negative comparator output comparison bit The four comparison bits together constitute the I / Q low-bit quantization result of the low-bit quantization output unit. This structure retains the independent positive and negative threshold channels of each of the four I / Q comparators, while also... and The parameterized control ensures symmetrical adjustment of the positive and negative threshold windows.

[0026] For any path c, the positive comparison bit is 1 when the input signal is greater than the positive comparison threshold, and the negative comparison bit is 1 when the input signal is less than the negative comparison threshold. The positive and negative comparison bits of this path are arranged in the order of [positive comparison bit, negative comparison bit] to form a two-bit raw quantization code: 01 indicates below the negative comparison threshold, 00 indicates between the positive and negative comparison thresholds, 10 indicates above the positive comparison threshold, and 11 is a reserved exception code. Paths I and Q each output a two-bit raw quantization code, forming a total of four comparison bits.

[0027] The threshold / bias generation circuit receives the control word output from the threshold / bias control register and generates positive and negative comparison thresholds for use by the comparator array. In one embodiment, the circuit includes a digital-to-analog converter branch driven by the threshold half-width control word, a digital-to-analog converter branch driven by the bias center control word, and an output buffer branch. The outputs of the two digital-to-analog converter branches are combined by addition or subtraction to form the positive and negative comparison thresholds, respectively. In another embodiment, the circuit includes a reference voltage divider network or a switched capacitor reference network selected by the control word. The threshold half-width is used to control the width of the comparison window, and the bias center is used to control the center position of the comparison window.

[0028] The comparison counting unit is used to count the number of threshold crossings, saturation times, and positive / negative count imbalances of the four comparison bits within a preset statistical window. For example... Figure 4 As shown, within each statistical window, the comparison counting units accumulate... , , and The effective output count is calculated to form an effective threshold ratio. If the effective threshold ratio is lower than the preset lower limit, it indicates that the current signal is weaker than the comparison window; if the effective threshold ratio is higher than the preset upper limit or the saturation ratio is high, it indicates that the current signal is stronger than the comparison window; if the difference between the positive and negative comparison counts of the same channel exceeds the preset bias threshold, it indicates that there is a DC bias, comparator offset, or reference voltage offset causing the center offset of the comparison window.

[0029] The state transition relationships of a state-controlled finite state machine are as follows: Figure 5As shown, the finite state machine includes an initialization state (IDLE), a weak signal fast adjustment state (LFAST), a weak signal slow adjustment state (LSLOW), a strong signal threshold pull-up state (THUP), a strong signal gain pull-back state (PULL), a stepped threshold processing state (STEP), and a locked output state (LOCK). Bias compensation can be implemented as a slow update branch running in parallel with the above states, or as a sub-process within the STEP state. In the initialization state, the circuit loads the initial gain control word, the initial threshold half-width control word, and the initial bias center control word. When the effective threshold crossing ratio is lower than the fast adjustment threshold, the finite state machine enters the LFAST state, prioritizing gain increase with a larger step size; when the effective threshold crossing ratio is between the fast adjustment threshold and the weak signal threshold, the finite state machine enters the LSLOW state, performing fine adjustment with a smaller step size. When the effective threshold crossing ratio is higher than the strong signal threshold and hard saturation is not triggered, the finite state machine enters the THUP state, prioritizing increase of the threshold half-width; when the threshold half-width reaches a preset upper limit or the saturation ratio is higher than a preset saturation judgment threshold, the finite state machine enters the PULL state, pulling back the gain of the variable gain amplifier unit.

[0030] The locking control unit is used to complete the convergence of gain, threshold half-width, and offset center within the preamble, synchronization segment, or preset training statistics window of a UWB frame, and to keep the gain control word, threshold half-width control word, and offset center control word stable before the data field arrives. For example... Figure 9 As shown, the circuit can complete comparison counting, state judgment, gain / threshold / bias update, and stepped threshold processing within the statistical window at the beginning of the UWB frame, and output a lock signal before entering the data field. After locking, the low-bit quantization output unit outputs the I / Q low-bit result under stable gain and threshold conditions, thereby reducing quantization inconsistencies caused by continued gain or threshold jumps within the data field.

[0031] Through the above structure, this embodiment integrates low-bit comparison quantization, threshold / bias DAC control, VGA gain control, comparison counting, and finite state machine inside the UWB receiver baseband chip, enabling the receiver to perform coordinated control of gain, threshold half-width, and bias center based on the statistical information output by the comparator, thereby improving the detectability of weak signals, the anti-saturation capability of strong signals, and the I / Q bias compensation capability.

[0032] Example 2

[0033] This invention provides a low-bit quantization gain control method for a UWB receiver baseband chip. This method can be executed by the low-bit quantization gain control circuit described in Embodiment 1, or by a comparator, counter, register, threshold / bias DAC, and state control logic with the same function. The method includes the following steps:

[0034] Step 1: Initialize configuration; After the UWB receiver baseband chip enters the receive state, the state control unit loads the initial control parameters according to the register configuration. These initial control parameters include initial gain, I-channel initial threshold half-width, Q-channel initial threshold half-width, I-channel initial bias center, Q-channel initial bias center, statistical window length, weak signal determination threshold, strong signal determination threshold, saturation determination threshold, bias balance determination threshold, gain adjustment step size, threshold half-width adjustment step size, bias center adjustment step size, and locking condition.

[0035] Step S2: Variable gain amplification; The result of gain adjustment for the c-th input signal within the m-th statistical window is expressed as: , In the formula, G(m) represents the c-th baseband signal after gain adjustment at the n-th sampling point within the m-th statistical window; G(m) represents the gain used in the m-th statistical window. This represents the c-th analog baseband signal input at the n-th sampling point within the m-th statistical window; c represents the signal channel, with a value of I or Q; n represents the sampling point number within the statistical window; and N represents the number of sampling points contained in each statistical window.

[0036] Step 3: Threshold generation and comparison; This embodiment does not update a single positive or negative threshold in isolation. Instead, it configures the bias center value and threshold half-width for both the I and Q paths, and generates positive and negative comparison thresholds in pairs using the threshold / bias generation circuit. , In the formula, This represents the positive comparison threshold for the c-th path within the m-th statistical window; This represents the offset compensation center value of the c-th path within the m-th statistical window; This represents the threshold half-width value of the c-th path within the m-th statistical window; This indicates the mismatch adjustment amount of the c-th positive comparator; , In the formula, This represents the negative comparison threshold for the c-th path within the m-th statistical window; This indicates the mismatch adjustment amount of the c-th negative comparator.

[0037] From the above formula, it can be seen that when When the threshold decreases, both the positive and negative comparison thresholds shrink synchronously towards the bias center; when As the value increases, both the positive and negative comparison thresholds expand synchronously away from the bias center; when... When the values ​​change, the positive and negative comparison thresholds are shifted as a whole to compensate for the DC bias of the I or Q path.

[0038] The comparator unit compares the gain-adjusted I-channel signal with the I-channel positive comparison threshold and the I-channel negative comparison threshold, respectively, and simultaneously compares the gain-adjusted Q-channel signal with the Q-channel positive comparison threshold and the Q-channel negative comparison threshold, respectively. The positive threshold comparison result is defined as: , In the formula, This represents the output of the c-th positive comparator at the nth sampling point within the m-th statistical window; This represents the c-th baseband signal after gain adjustment.

[0039] The negative threshold comparison result is defined as: , In the formula, This represents the output of the c-th negative comparator at the nth sampling point within the m-th statistical window.

[0040] Step 4: Compare the count with the state determination; The comparison counting unit counts the number of times the threshold is exceeded for both positive and negative values. , In the formula, This represents the number of times the c-th path crosses the positive threshold within the m-th statistical window; N represents the length of the statistical window. , In the formula, This represents the number of times the negative threshold of the c-th path is exceeded within the m-th statistical window; N represents the length of the statistical window.

[0041] Furthermore, by normalizing the number of positive and negative threshold crossings for both the I and Q paths, the effective threshold crossing ratio within the current statistical window is obtained: , In the formula, The value represents the average effective threshold crossing ratio of the four comparators within the m-th statistical window; N represents the length of the statistical window; and the constant 4 represents the four types of comparison results: I-way positive comparison, I-way negative comparison, Q-way positive comparison, and Q-way negative comparison.

[0042] The imbalance of the positive and negative comparison outputs of the same path is defined as: , In the formula, This represents the imbalance of the c-th positive / negative comparison output within the m-th statistical window; This represents a small constant to prevent the denominator from being zero.

[0043] The status control unit reads the output of the comparison counting unit. , saturation ratio and And compare it with a preset threshold. P fast P low and P high The register configuration is written via the main control interface, where P low For weak signal threshold, P high It is a strong signal threshold and satisfies .set up For weak signals, the threshold is adjusted quickly. To be the lower limit of the effective threshold ratio, The upper limit of the effective threshold ratio, and ; when When, it is determined to be a weak signal fast-adjustment state LFAST; when When, it is determined to be a weak signal slow adjustment state LSLOW; when And the saturation criterion was not triggered, and When not approaching the upper limit, it is determined to be a strong signal threshold pull-up state (THUP); when And the saturation criterion is triggered, or When the signal is close to its upper limit, it is determined to be a strong signal gain pull-back state (PULL); when When several consecutive statistical windows are stable, it enters the STEP state; when the preset locking window is reached or the locking conditions are met, it enters the LOCK state.

[0044] The bias compensation criterion is ,in This indicates the threshold for determining bias imbalance. Bias center updates can be performed in parallel with weak signal and strong signal adjustments, or they can be performed in the STEP state. When the signal is in a severely weak signal or severely saturated state, gain and threshold half-width adjustment are performed first, followed by small-step bias center fine-tuning.

[0045] Step 5: Coordinated scheduling and adjustment; In LFAST state, the state control unit uses larger step sizes for rapid adjustment; in LSLOW state, the state control unit uses smaller step sizes for slow adjustment. Weak signal processing employs deterministic prioritization: if... Not achieved If so, then prioritize increasing the gain; if Achieved and Not achieved If so, then reduce the threshold half-width; if Achieved and Achieved If so, the current control word is maintained and the weak signal non-convergence flag is set.

[0046] The formula for gain up adjustment is: , In the formula, Indicates the gain used in the next statistics window; Indicates the maximum allowable gain; Indicates the gain used in the current statistics window; Indicates the gain adjustment step size; This indicates that the smaller value is selected during the operation.

[0047] The formula for lowering the threshold half-width is: , In the formula, This indicates the half-width of the threshold for the c-th path in the next statistical window; Indicates the minimum allowed threshold half-width; This represents the half-width of the threshold for the c-th path in the current statistical window; This indicates the threshold half-width down adjustment step size; This indicates the operation of taking the larger value.

[0048] In THUP mode, the state control unit preferentially increases the threshold half-width, shifting the positive comparison threshold upwards and the negative comparison threshold downwards, thereby expanding the comparison window. In PULL mode, the state control unit pulls back the variable gain, reducing the signal amplitude input to the comparator array. Strong signal processing employs deterministic priority: if... Not achieved If no continuous hard saturation occurs, then the threshold half-width should be increased first; if Achieved Or the saturation ratio continuously exceeds the saturation threshold, and Not achieved Then pull back the gain; if Achieved and Achieved If so, the current control word is maintained and the strong signal saturation flag is set.

[0049] The formula for adjusting the threshold half-width is: , In the formula, This indicates the half-width of the threshold for the c-th path in the next statistical window; Indicates the maximum allowed threshold half-width; This represents the half-width of the threshold for the c-th path in the current statistical window; This indicates the step size for adjusting the threshold half-width.

[0050] The gain pullback formula is: , In the formula, Indicates the gain used in the next statistics window; Indicates the minimum allowable gain; Indicates the gain used in the current statistics window; This indicates the gain pullback step size.

[0051] With the above scheduling rules, the positive and negative comparison thresholds shrink synchronously towards the bias center under weak signal conditions, and expand synchronously away from the bias center under strong signal conditions, thus avoiding the asymmetry problem of positive and negative windows caused by only reducing the negative comparison threshold or only increasing the positive comparison threshold.

[0052] When the imbalance between the positive and negative comparison counts for the same channel exceeds a preset threshold, the state control unit updates the bias center value for that channel. If the positive comparison count is significantly greater than the negative comparison count, it indicates that the center of the comparison window is offset relative to the bias of that signal; if the negative comparison count is significantly greater than the positive comparison count, it indicates that the center of the comparison window is offset in the opposite direction. The state control unit adjusts accordingly. This balances the positive and negative comparison outputs. The bias center update formula is: , In the formula, This represents the updated offset compensation center value for the c-th path; This represents the current offset compensation center value for the c-th path; Indicates the offset update step size; This indicates the imbalance of the positive and negative comparison output of the c-th path; and These represent the lower and upper limits of the bias compensation center value, respectively; This represents the amplitude limiting function.

[0053] In STEP mode, the state control unit selects or fine-tunes the corresponding threshold half-width step value based on the current gain level, and performs DAC code-level alignment on the threshold half-width control word and the bias center control word to make the final control word suitable for on-chip register latching. When the gain has not yet reached its upper limit in a weak signal state, the gain is updated first; only after the gain reaches its upper limit is the threshold half-width reduced. When the threshold half-width has not reached its upper limit and hard saturation has not been triggered in a strong signal state, the threshold half-width is increased first; only when the threshold half-width reaches its upper limit or saturation persists is the gain pulled back. Therefore, boundary processing has clear selection criteria.

[0054] Step 6: Locking and Outputting; When the effective threshold ratio, saturation ratio, and bias imbalance all meet the continuous locking condition for several consecutive statistical windows, or when the preset locking window of the UWB frame has been reached and the data field is about to arrive, the state control unit enters the LOCK state.

[0055] The continuous locking condition can be expressed as: , In the formula, This indicates the lower limit of the effective threshold crossing ratio; Indicates the upper limit of the effective threshold crossing ratio; This represents the effective threshold crossing ratio when backtracking the j-th statistical window; This represents the saturation ratio when backtracking the j-th statistical window; This indicates the saturation threshold. This indicates that the imbalance is output by comparing the positive and negative values ​​of the c-th path in the j-th statistical window backwards. This indicates the threshold for determining bias imbalance. This indicates the number of statistical windows that need to continuously meet the stability condition.

[0056] Once the locking conditions are met, the locking control unit maintains the current gain control word, threshold half-width control word, and bias center control word: , In the formula, Indicates the gain after locking; Indicates the gain when entering the locked state; This represents the threshold half-width of the c-th path after locking; This indicates the threshold half-width of the c-th path when entering the locked state; This represents the c-th bias center value after locking; This represents the c-th bias center value when entering the locked state.

[0057] In the locked state, the low-bit quantization output unit outputs the current comparator output as a stable low-bit I / Q quantization result to the digital baseband processing unit. Through the above steps, this embodiment can complete the convergence and locking of gain, threshold half-width, and bias center before the arrival of the UWB data field, keeping the comparison threshold and gain level stable during the data field. This reduces the insufficiency problem of low-bit quantization receiving structure in weak signal scenarios, the comparison saturation problem in strong signal scenarios, and the polarity imbalance problem caused by I / Q bias, thereby improving the adaptability of the UWB receiving baseband chip under different received signal strengths and different bias conditions.

[0058] To verify the effectiveness of the low-bit quantization gain control circuit and method described in this invention, a discrete-time simulation model of UWB baseband I / Q signals was established. The simulation model processes the I / Q signals according to statistical windows, with a total of 150 statistical windows, each containing 64 sampling points. The input signal amplitude is sequentially set to weak signal segment, medium signal segment, strong signal segment, strong signal recovery segment, and locked data segment, to simulate the input amplitude variations caused by propagation distance, target reflection intensity, antenna attitude, or front-end gain deviation during UWB reception.

[0059] In the simulation, the weak signal segment corresponds to statistical windows 0 to 35, the medium signal segment to statistical windows 36 to 63, the strong signal segment to statistical windows 64 to 95, the strong signal recovery segment to statistical windows 96 to 111, and the locked data segment to statistical windows 112 and beyond. Within each statistical window, the output results of the I-channel positive comparison, I-channel negative comparison, Q-channel positive comparison, and Q-channel negative comparison are statistically analyzed, and the average threshold crossing ratio of the four comparison results is used as the basis for judging whether the gain and threshold half-width are appropriate. The effective threshold crossing ratio range is set from 0.10 to 0.34. When the threshold crossing ratio is below 0.10, it is determined to be a weak signal state; when the threshold crossing ratio is above 0.34 or the saturation ratio is high, it is determined to be a strong signal or a saturation state.

[0060] Three comparison schemes were set up for the simulation. The first was a fixed threshold scheme, where the gain and comparison threshold were fixed, and no adaptive adjustment was performed. The second was a gain-only control scheme, where the comparison threshold remained unchanged, and the VGA gain was adjusted only based on the comparison count results. The third was the scheme of this invention, which simultaneously performed gain control and threshold half-width control, and kept the gain control word, threshold half-width control word, and offset center control word unchanged after reaching a preset locking window. In the simulation, the comparison threshold of the fixed threshold scheme was set to 0.16, the initial threshold half-width of the scheme of this invention was set to 0.18, the threshold half-width adjustment range was 0.055 to 0.46, the initial gain was 1.0, the gain adjustment range was 0.36 to 7.2, and it entered the locking state at the 112th statistical window.

[0061] like Figure 4 As shown, the comparison counting unit can output the effective threshold crossing ratio within a continuous statistical window, reflecting whether the current gain and threshold half-width combination is within the usable range. When the input signal is weak, the comparison output of the fixed threshold scheme remains in a low-flip state for a long time, and the low-bit quantization result contains insufficient information. The present invention can prioritize increasing the VGA gain based on the judgment result that the threshold crossing ratio is lower than the lower limit, and reduce the threshold half-width after the gain reaches the upper limit, so that the positive and negative comparison thresholds shrink synchronously towards the bias center, thereby gradually bringing the comparison output into the effective flipping range. The weak signal threshold closed-loop adjustment process is as follows: Figure 6 As shown.

[0062] When the input signal is strong, the fixed threshold scheme is prone to comparator output saturation, causing the low-bit quantization result to remain close to all positive or all negative for a prolonged period. Gain control alone is insufficient to simultaneously balance the threshold dynamic range and response speed. This invention, upon detecting a strong signal or a high saturation ratio, first performs a threshold half-width pull-up operation, shifting the positive comparison threshold upwards and the negative comparison threshold downwards, thus expanding the comparison window. When the threshold half-width reaches its upper limit or saturation persists, a gain pull-back operation is then performed. Finally, a stepped threshold processing method is used to bring the comparison result back to the lockable operating range. The strong signal threshold pull-up and gain pull-back process is as follows: Figure 7 As shown, the step threshold generation process is as follows: Figure 8 As shown.

[0063] like Figure 9 As shown, in this simulation configuration, the circuit enters a locked state at the 112th statistical window. In actual implementation, the number of available statistical windows is determined by the statistical window length, sampling clock, and allowed training time for convergence; a locking window should be configured so that the locking time is earlier than the start time of the data field in the corresponding frame format. After locking, the circuit maintains the current gain control word, threshold half-width control word, and bias center control word unchanged, ensuring that subsequent low-bit I / Q data is output under stable quantization conditions.

[0064] Figure 10 The overall flow of the method of the present invention is shown. This flow sequentially includes parameter initialization, I / Q gain amplification, positive and negative threshold comparison, statistical threshold overshoot counting, signal state determination, performance of gain / threshold half-width / bias center adjustment, stepped threshold processing, and locking and outputting the low-bit I / Q result. Specifically, under weak signal conditions, the gain is increased or the threshold half-width is decreased; under strong signal conditions, the threshold half-width is increased or the gain is pulled back; and under bias imbalance conditions, the bias center is updated, thereby ensuring that the low-bit quantization result maintains high effectiveness under different input amplitudes and different DC bias conditions.

[0065] Simulation results are as follows Figure 11 and Figure 12 As shown. For weak signal segments, the effective window ratio of the fixed threshold scheme is 0.000, while the effective window ratio of the present invention is increased to 0.778, indicating that the present invention can significantly improve the problem of long-term non-flipping of low-bit comparison output under weak signal conditions. For strong signal segments, the average saturation ratio of the fixed threshold scheme is 0.529, the average saturation ratio of the gain control-only scheme is 0.298, and the average saturation ratio of the present invention is further reduced to 0.183, indicating that the combined adjustment of gain control and threshold half-width control has better anti-saturation capability than gain adjustment alone.

[0066] In the data segment after locking, the effective window ratio of the present invention is 1.000, the gain after locking is approximately -0.89dB, and the threshold DAC code after locking is 34. This result demonstrates that the present invention can obtain a stable gain and threshold combination before the start of the data field and maintain stable low-bit quantization output after locking. For scenarios with I / Q DC bias or comparator misalignment, the present invention can also update the bias center value through the imbalance of positive and negative comparison counts, making the positive and negative comparison outputs tend to be balanced and avoiding long-term unipolar bias in the low-bit quantization result. Therefore, the present invention can balance weak signal detection, strong signal anti-saturation, bias compensation, and output stability after locking in low-bit UWB receiver baseband chips, and can be used for on-chip baseband implementation of UWB receivers.

[0067] The above description is merely a preferred embodiment of the present invention and is not intended to further limit the present invention. All equivalent changes made based on the description and drawings of the present invention are within the protection scope of the present invention.

Claims

1. A low-bit quantization gain control circuit for a UWB receiver baseband chip, characterized in that, include: A variable gain amplifier unit is used to receive the I-channel analog baseband signal and the Q-channel analog baseband signal output from the UWB receiver, and to adjust the gain of the I-channel analog baseband signal and the Q-channel analog baseband signal according to the gain control word. An I / Q positive and negative threshold comparator array is used to compare the gain-adjusted I / Q signal with the corresponding positive comparison threshold and negative comparison threshold, respectively, to generate I-channel positive comparison result, I-channel negative comparison result, Q-channel positive comparison result, and Q-channel negative comparison result; The low-bit quantization output unit is used to form an I-channel two-bit raw quantization code from the I-channel positive comparison result and the I-channel negative comparison result, and to form a Q-channel two-bit raw quantization code from the Q-channel positive comparison result and the Q-channel negative comparison result, so as to form a low-bit I / Q quantization output containing four comparison bits. The threshold / bias generation circuit is used to generate corresponding positive comparison thresholds and negative comparison thresholds based on the bias center value and threshold half-width value set for the I-channel and Q-channel respectively; the threshold half-width value is used to control the width of the comparison window between the positive and negative comparison thresholds, and the bias center value is used to control the center position of the comparison window; The comparison counting unit is used to count the number of positive and negative threshold crossings of the four comparison results within a preset statistical window, and to obtain the effective threshold crossing ratio, saturation ratio, and imbalance between the positive and negative comparison results of the same channel based on the number of positive and negative threshold crossings. A state control finite state machine is used to coordinate and schedule the gain control word, threshold half-width control word, and bias center control word according to the statistical results of the comparison counting unit and a preset priority. A gain control register unit is used to store the gain control word and update the gain control word according to the gain adjustment signal; A threshold / bias control register unit is used to store the threshold half-width control word and the bias center control word, and update the corresponding control word according to the threshold half-width adjustment signal and the bias center adjustment signal; A locking control unit is used to lock the gain control word, threshold half-width control word, and bias center control word when the continuous locking condition is met, so that the low-bit quantization output unit outputs low-bit I / Q quantization results with stable gain and threshold during the data field.

2. The low-bit quantization gain control circuit for a UWB receiver baseband chip according to claim 1, characterized in that, The threshold / bias generation circuit generates corresponding positive and negative comparison thresholds based on the bias center value and the threshold half-width value: ， In the formula, This represents the positive comparison threshold for the c-th path within the m-th statistical window; This represents the offset compensation center value of the c-th path within the m-th statistical window; This represents the threshold half-width value of the c-th path within the m-th statistical window; This indicates the mismatch adjustment amount of the c-th positive comparator; ， In the formula, This represents the negative comparison threshold for the c-th path within the m-th statistical window; This indicates the mismatch adjustment amount of the c-th negative comparator; when When the threshold decreases, both the positive and negative comparison thresholds shrink synchronously towards the bias center; when As the value increases, both the positive and negative comparison thresholds expand synchronously away from the bias center; when... When the change occurs, the positive and negative comparison thresholds shift as a whole.

3. The low-bit quantization gain control circuit for a UWB receiver baseband chip according to claim 2, characterized in that, The comparison unit statistics are as follows: Effective threshold crossing ratio: ， And the imbalance of the positive and negative comparison outputs on the same path: ， In the formula, This represents the average effective threshold crossing rate of the four comparators within the m-th statistical window; This represents the number of times the positive threshold is exceeded in the c-th path; This represents the number of times the negative threshold is exceeded in the c-th path; N represents the statistical window length; the constant 4 represents the comparison results of the four categories; This represents the imbalance of the c-th positive / negative comparison output within the m-th statistical window; This represents a small constant to prevent the denominator from being zero.

4. The low-bit quantization gain control circuit for a UWB receiver baseband chip according to claim 3, characterized in that, The state control finite state machine includes: initialization state, weak signal fast adjustment state, weak signal slow adjustment state, strong signal threshold pull-up state, strong signal gain pull-back state, stepped threshold processing state, and output lockout state. In the initialization state, the circuit loads the initial gain control word, the initial threshold half-width control word, and the initial bias center control word; When the effective threshold ratio is lower than the fast adjustment threshold, the finite state machine enters the weak signal fast adjustment state, and prioritizes increasing the gain of the variable gain amplifier unit with the first gain adjustment step size. When the effective threshold crossing ratio is between the fast adjustment threshold and the weak signal threshold, the finite state machine enters the weak signal slow adjustment state and adjusts the gain with the second gain adjustment step size, wherein the first gain adjustment step size is larger than the second gain adjustment step size. When the effective threshold crossing ratio is higher than the strong signal threshold and hard saturation is not triggered, the finite state machine enters the THUP state and preferentially increases the threshold half-width. When the threshold half-width reaches the preset upper limit or the saturation ratio is higher than the preset saturation judgment threshold, the finite state machine enters the strong signal gain pull-back state, pulling back the gain of the variable gain amplifier unit. When the effective threshold ratio is within the preset effective range, the finite state machine enters the stepped threshold processing state, selects the corresponding threshold half-width step value according to the current gain control word, and performs code-level alignment on the threshold half-width control word and the offset center control word; when the continuous locking condition is met for K_lock consecutive statistical windows since entering the stepped threshold processing state, or when the preset locking window is reached, the finite state machine enters the locked output state from the stepped threshold processing state and locks each control word.

5. A low-bit quantization gain control circuit for a UWB receiver baseband chip according to claim 3, characterized in that, The state-controlled finite state machine, under bias imbalance, determines the imbalance between the positive and negative comparison counts in the same path based on the imbalance amount. Update the offset center value for this path: ， In the formula, This represents the updated offset compensation center value for the c-th path; Indicates the offset update step size; This indicates the imbalance of the positive and negative comparison output of the c-th path; and These represent the lower and upper limits of the bias compensation center value, respectively; Represents the amplitude limiting function; When the imbalance is greater than a preset positive imbalance threshold, the bias center value is compensated in the positive direction; when the imbalance is less than a preset negative imbalance threshold, the bias center value is compensated in the negative direction. The preset positive imbalance threshold is greater than zero, and the preset negative imbalance threshold is less than zero.

6. The low-bit quantization gain control circuit for a UWB receiver baseband chip according to claim 1, characterized in that, The continuous locking conditions of the locking control unit include: The effective threshold crossing ratio remains between the preset lower limit and the preset upper limit for several consecutive statistical windows; The saturation ratio is below the saturation threshold for several consecutive statistical windows. The imbalance of each positive and negative comparison result is below the bias imbalance judgment threshold for several consecutive statistical windows. When all the above locking conditions are met, or when the preset locking window of the UWB frame is reached, the locking control unit keeps the current gain control word, threshold half-width control word, and offset center control word unchanged, and maintains the locked state during the data field.

7. A low-bit quantization gain control method for a UWB receiver baseband chip, characterized in that, The implementation of a low-bit quantization gain control circuit for a UWB receiver baseband chip according to any one of claims 1-6 includes the following steps: Step S1: Initialize configuration: Load the initial gain control word, initial threshold half-width control word, initial bias center control word, and decision parameters; Step S2, Variable Gain Amplification: Adjust the gain of the I-channel analog baseband signal and the Q-channel analog baseband signal according to the current gain control word; Step S3, Threshold Generation and Comparison: Based on the current bias center control word and threshold half-width control word, generate I-channel positive comparison threshold, I-channel negative comparison threshold, Q-channel positive comparison threshold, and Q-channel negative comparison threshold respectively; compare the gain-adjusted I / Q signals with the corresponding positive and negative comparison thresholds respectively to generate four comparison results; Step S4, Comparison Counting and State Determination: Within a preset statistical window, count the effective threshold crossing ratio, saturation ratio, and positive-negative comparison imbalance of the four comparison results, and determine the current signal state based on the statistical results; Step S5, Coordinated Scheduling and Adjustment: Based on the determined signal state, coordinately adjust the gain control word, threshold half-width control word, and offset center control word according to the preset priority; repeat steps S2 to S5 in the next statistical window with the updated control word until the locking condition is met. Step S6, Lock Output: When the continuous locking condition is met, lock each control word and output low-bit I / Q quantization results with stable gain and threshold during the data field.

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