Miniaturized ltcc time delay equalizer

Abstract

The application discloses a miniaturized LTCC time delay equalizer, which comprises an LTCC multilayer substrate, an input port, an output port, a ground shielding layer and lumped elements composed of lumped parameter inductors and capacitors; the LTCC multilayer substrate is internally layered to arrange a port layer, a lumped element layer and the ground shielding layer, and the ground shielding layer is electrically connected with the element ground end through a metallized via. The lumped elements are connected to form a constant resistance type LC time delay compensation network, which comprises a signal main path connected in series between the ports and a series LC ground resonance branch connected between a main path node and the ground shielding layer, and the frequency characteristics of LC reactance can be used to regulate and control the transmission time delay of signals of different frequencies and compensate the in-band group time delay fluctuation of a band-pass filter. The device is small in size, high in integration, good in time delay compensation precision and low in signal loss, and is suitable for miniaturized radio frequency communication and radar systems.

Description

Technical Field

[0001] This invention relates to the field of radio frequency communication technology, and in particular to a miniaturized LTCC delay equalizer. Background Technology

[0002] Delay equalizers are important passive components in radio frequency communication and radar systems. They are used to compensate for group delay differences generated during the transmission of signals of different frequencies, ensuring synchronous signal reception and accurate processing. For example... Figure 1 As shown, in conventional RF front-end links, the in-band group delay ripple of bandpass filters generally exhibits a "flat U-shape". There is a significant difference between the group delay of the sideband and the center frequency within the passband. If no compensation is performed, it will cause signal distortion and directly affect the system transmission quality.

[0003] Existing lumped delay equalizers mostly use discrete inductors and capacitors soldered onto a PCB substrate to achieve delay control through the reactance frequency characteristics of the LC network. This approach has the following drawbacks: a large number of discrete components require significant PCB footprint, making it difficult to reduce the overall device size and adapt to the assembly requirements of miniaturized devices; parasitic parameters are easily introduced during the soldering process, degrading high-frequency signal transmission performance and reducing the accuracy of delay compensation; the assembly process is prone to positional deviations and soldering errors, resulting in poor component parameter consistency and insufficient stability in mass production; furthermore, the discrete structure has low integration, making it difficult to achieve system integration with other RF passive components and failing to meet the integration design requirements of high-density communication modules.

[0004] Overall, existing time delay equalizers suffer from drawbacks such as large size, prominent parasitic parameters, insufficient compensation accuracy, poor assembly consistency, low integration, and weak reliability. Summary of the Invention

[0005] The purpose of this invention is to provide a miniaturized LTCC delay equalizer to solve the aforementioned technical problems in the prior art. The specific technical solution is as follows: A miniaturized LTCC delay equalizer includes an LTCC multilayer substrate, an input port, an output port, a ground shield layer, and a lumped element composed of a lumped parameter inductor and a lumped parameter capacitor. The LTCC multilayer substrate has a port layer, a lumped element layer, and a ground shield layer. The input port and output port are located on the port layer. The lumped parameter inductor and lumped parameter capacitor are integrated on the lumped element layer. The ground shield layer is electrically connected to the ground terminal of the lumped element through a metallized via. The lumped parameter inductor and lumped capacitor are connected to form a constant resistance LC delay compensation network. The delay compensation network includes a main signal path connected in series between the input port and the output port and at least one series LC ground resonant branch connected between a node of the main signal path and the ground shield layer. The main signal path is composed of a parallel inductor and capacitors connected in series on both sides, so as to utilize the characteristic of LC reactance changing with frequency to generate differentiated transmission delays for radio frequency signals of different frequencies, compensate for the group delay fluctuations in the bandpass filter, and flatten the group delay curve of the working passband.

[0006] Furthermore, the grounding shielding layer includes a grounding layer disposed on the bottom layer of the LTCC multilayer substrate and a grounding metal layer disposed on the periphery of the substrate, which together form an electromagnetic shielding structure covering the lumped element layer.

[0007] Furthermore, the grounding shield layer also includes at least one intermediate grounding shield layer, which is disposed between adjacent lumped element layers to achieve interlayer electromagnetic isolation and reduce signal crosstalk.

[0008] Furthermore, the lumped parameter inductor adopts a spiral metal wiring structure, distributed in multiple wiring layers of the lumped element layer, and the layers are electrically connected through metallized vias.

[0009] Furthermore, the lumped-parameter capacitor adopts a metal electrode stacked structure, which is composed of multiple layers of spaced metal electrodes stacked with interlayer ceramic dielectric to form a stable lumped capacitance value.

[0010] Furthermore, the constant resistance LC delay compensation network adopts a Chebyshev topology, which consists of multiple sets of series and parallel inductors and capacitors to broaden the delay compensation range.

[0011] Furthermore, the constant resistance LC delay compensation network is a second-order or higher multi-order topology.

[0012] Furthermore, both the input and output ports adopt a microstrip line structure, which is led out laterally from both sides of the LTCC multilayer substrate for electrical connection with external radio frequency circuits.

[0013] Furthermore, both the input and output ports feature 50Ω impedance-matched bonded gold-plated pad structures to enable low-loss port interconnection.

[0014] Furthermore, the LTCC multilayer substrate uses 9KC ceramic green ceramic material, and the number of substrate layers is 21±n, where n is a non-negative integer.

[0015] The miniaturized LTCC delay equalizer of the present invention has the following advantages: 1. By integrating a constant-resistance LC delay compensation network into an LTCC multilayer substrate, replacing the traditional delay equalization structure built with discrete components, the device size is significantly reduced. By adopting a topology of a main signal path combined with a series LC ground resonant branch, the transmission delay of signals at different frequencies can be precisely controlled by utilizing the frequency characteristics of the LC reactance, and the in-band group delay fluctuation of the bandpass filter can be compensated in reverse, smoothing out the passband group delay. At the same time, relying on the LTCC layered layout and metallized via grounding design, the signal return path is shortened, parasitic parameters and signal loss are reduced, and the device integration and operational reliability are improved, making it suitable for the assembly requirements of miniaturized RF communication and radar systems.

[0016] 2. By setting ground shielding layers on the bottom and periphery of the substrate, a shielding structure is formed that surrounds the internal lumped component layer. On the one hand, it can provide a complete low-impedance ground return path for the internal circuit, shorten the high-frequency signal return distance to reduce transmission loss; on the other hand, it can effectively block the intrusion of external electromagnetic interference, suppress the radiation of internal radio frequency signals outward, reduce crosstalk between devices, and improve the electromagnetic compatibility performance of the overall circuit.

[0017] 3. By adding an intermediate grounding shield layer between adjacent lumped element layers, electromagnetic isolation can be formed for the inductor and capacitor elements arranged in the upper and lower layers, effectively weakening the parasitic coupling effect between layers, avoiding the deviation of element parameters due to interference from the traces of adjacent layers, ensuring the stability of the parameters of each lumped element, thereby improving the control accuracy of the delay compensation network and reducing the impact of signal crosstalk on delay characteristics.

[0018] 4. A lumped-parameter inductor is achieved by using spiral metal wiring and a multi-layer wiring method combined with metallized vias. This extends the conductive path within a limited planar area to obtain the required inductance, making full use of the 3D wiring space of LTCC, compressing the planar area occupied by the inductor, improving the device integration, and ensuring the continuity of the current path, reducing the adverse effects of parasitic parameters on inductor performance.

[0019] 5. A lumped-parameter capacitor is achieved by using a metal electrode stack structure with an LTCC green ceramic layer as the interlayer dielectric. Different capacitance requirements can be flexibly adapted by adjusting the number of stacked electrodes, and stable capacitive parameters can be obtained in a very small volume. Relying on the material properties of ceramic dielectric, the capacitor structure has low temperature drift and high parameter consistency, which can provide accurate and stable capacitance support for LC time delay compensation network, and ensure the repeatability and long-term stability of time delay compensation characteristics.

[0020] 6. A constant-resistance LC time delay compensation network is constructed using Chebyshev topology. Through the combined design of multiple sets of series and parallel inductors and capacitors, its time delay characteristics can better match the group time delay ripple law of the bandpass filter. Under the same component order and device size, a wider time delay compensation range can be achieved. The operating bandwidth of the device can be broadened without significantly increasing the number of components, thereby improving the adaptability and versatility of the solution to filters of different frequency bands.

[0021] 7. By adopting a second-order or higher multi-order topology, the degree of freedom in adjusting the delay curve can be increased, enabling a more precise fit to the group delay ripple pattern of the front-end filter, further improving the accuracy of delay compensation, and making the passband group delay curve of the cascaded filter flatter. In practical applications, the order can be flexibly selected according to the compensation requirements, achieving the optimal balance between compensation accuracy, device size, and manufacturing cost.

[0022] 8. The microstrip line structure with leads on both sides is used as the input and output ports. Its transmission line form is compatible with conventional RF PCB circuits, which can achieve smooth impedance transition and reduce signal reflection caused by impedance abrupt changes at the port. At the same time, the side-lead layout conforms to the conventional assembly form of surface mount devices, is compatible with automated mounting processes, and improves the convenience of engineering applications and assembly efficiency of the device.

[0023] 9. Using 50Ω impedance-matched gold-plated pads as the port structure, matching the standard characteristic impedance of the RF system, can effectively reduce signal reflection at the port and optimize the return loss performance of the device; the gold plating treatment of the pads can improve soldering reliability and oxidation resistance, reduce interconnect contact loss, and enable the device to maintain stable connection performance in harsh environments such as wide temperature and high humidity.

[0024] 10. LTCC multilayer substrates are fabricated using 9KC ceramic green ceramic, with a single-layer green ceramic thickness of 50μm and an adjustable layer number design of 21±n. The 9KC ceramic material has a stable dielectric constant, low dielectric loss, and a wide temperature range, which can ensure the reliability of the device in harsh environments. The adjustable layer design allows for the flexible addition or removal of functional layers according to performance, size and cost requirements, balancing the overall performance of the device and manufacturing cost, and adapting to diverse application scenarios. Attached Figure Description

[0025] Figure 1 This is a group delay curve within the band of an existing bandpass filter.

[0026] Figure 2 This is an overall schematic diagram of the miniaturized LTCC delay equalizer of the present invention.

[0027] Figure 3 This is the delay curve of the miniaturized LTCC delay equalizer group of the present invention.

[0028] Figure 4This invention relates to the miniaturized LTCC delay equalizer and filter synthesis group delay curve.

[0029] Figure 5 This is the circuit schematic of the miniaturized LTCC delay equalizer of the present invention.

[0030] Figure 6 This is a schematic diagram of the layer structure of the miniaturized LTCC delay equalizer of the present invention. Detailed Implementation

[0031] To better understand the purpose, structure, and function of this invention, the miniaturized LTCC delay equalizer of this invention will be described in detail below with reference to the accompanying drawings.

[0032] like Figures 2 to 6 As shown, this invention provides a miniaturized LTCC delay equalizer, which is fabricated using a low-temperature co-fired ceramic multilayer process. The overall package size is only 5.0mm × 2.8mm × 1.0mm. The core consists of an LTCC multilayer substrate, an input port IN, an output port OUT, a ground shield layer, and lumped elements composed of lumped parameter inductors and lumped parameter capacitors. Inside the LTCC multilayer substrate, a layered functional partitioning layout is adopted, with a port layer, a lumped element layer, and a ground shield layer arranged sequentially. In this embodiment, in the C00 to C20 layer arrangement from bottom to top, the port layer is located on the C07 layer, the inductors of the lumped element layer are distributed on the C04, C06, and C19 layers, the capacitors are distributed on the C01, C11, C12, C13, and C14 layers, and the ground shield layer is correspondingly located in the outer area of ​​the C00, C07, and C19 layers. The input port IN and output port OUT are located on the port layer. All lumped parameter inductors and lumped parameter capacitors are built into the lumped element layer. The ground shield layer is connected to the ground terminal of each lumped element through metallized vias to form a reliable electrical connection.

[0033] It should be emphasized that the lumped parameter inductors and lumped parameter capacitors connected according to a specific topology form a constant resistance LC delay compensation network. This network includes a main signal path connected in series between the input port and the output port, and at least one series LC ground resonant branch. The main signal path includes a first inductor L1 connected in parallel between the input port IN and the output port OUT, and a first capacitor C1 and a second capacitor C2 connected in series. The first capacitor C1 is connected between the input port and the intermediate node, and the second capacitor C2 is connected between the intermediate node and the output port. The series LC ground resonant branch is formed by the second inductor L2 and the third capacitor C3 connected in series. Its upper end is connected to the intermediate node between the first capacitor C1 and the second capacitor C2, and its lower end is connected to the ground shielding layer. This utilizes the characteristic of LC reactance changing with frequency to generate differentiated transmission delays for radio frequency signals of different frequencies, compensates for the group delay fluctuations in the bandpass filter, and flattens the group delay curve of the working passband.

[0034] The working mechanism of this delay equalizer is based on the frequency dispersion characteristics of LC reactance and the impedance matching characteristics of a constant resistance network. After the RF signal is fed into the delay compensation network inside the substrate from the input port IN, most of the energy is transmitted along the main signal path. A portion flows directly to the output port OUT via the first inductor L1, and another portion flows to the output port OUT via the first capacitor C1, the intermediate node, and the second capacitor C2, together completing the main signal transmission. A small portion of the energy enters the ground resonant branch formed by the second inductor L2 and the third capacitor C3 connected in series through the intermediate node, forming a resonant energy storage structure. Since the inductive reactance of the inductor increases linearly with increasing signal frequency, while the capacitive reactance of the capacitor decreases with increasing signal frequency, the combined reactance exhibited by the two in series at different frequency points varies significantly. This results in different equivalent electrical lengths corresponding to different frequency components of the signal in the resonant circuit, leading to differences in energy residence time, ultimately manifesting as a regular change in transmission delay with frequency. By precisely designing the parameters of each inductor and capacitor, the group delay curve of this network can exhibit a "flat n-shaped" characteristic that complements the front-end bandpass filter—a higher delay at the center frequency of the passband and lower delays at the side frequencies. This precisely offsets the inherent "flat U-shaped" group delay fluctuation of the bandpass filter, making the overall group delay curve of the cascaded link flatter and ensuring synchronous transmission and reception of signals at different frequencies. Simultaneously, the constant-impedance topology can optimize the matching of the standard characteristic impedance of the ports, achieving delay control while maintaining stable port impedance across the entire passband. This effectively suppresses signal reflection at the ports, balancing delay compensation performance and signal transmission efficiency.

[0035] In the specific layer structure design, the grounding shielding layer includes a grounding layer located at the bottom of the LTCC multilayer substrate and a grounding metal layer arranged around the perimeter of the substrate. The two are connected by a side metallization structure to form a semi-enclosed electromagnetic shielding structure that covers the internal lumped component layer. This layout provides a complete low-impedance ground return path for the internal circuits, effectively shortening the return distance of high-frequency signals and reducing transmission losses and signal crosstalk. On the other hand, it effectively blocks the influence of external electromagnetic interference on the internal delay network, while suppressing the outward radiation of internal RF signals, reducing crosstalk between devices, and improving the overall electromagnetic compatibility performance of the circuit.

[0036] Preferably, the grounding shield layer may further include at least one intermediate grounding shield layer, which is disposed between adjacent lumped element layers. For multi-layered inductor and capacitor elements, parasitic coupling between layers can affect the accuracy of element parameters, thereby interfering with the accuracy of time delay compensation. After adding an intermediate grounding shield layer, physical and electromagnetic dual isolation can be formed between the upper and lower layers of elements, significantly weakening the parasitic coupling effect between layers, further reducing signal crosstalk, ensuring the parameter stability of each layer of lumped elements, and improving the accuracy of time delay compensation.

[0037] In this embodiment, both the first inductor L1 and the second inductor L2 adopt a spiral metal wiring structure. Depending on the inductance design requirements, they can be distributed across multiple wiring layers in the lumped component layer. The spiral traces on the upper and lower layers are electrically connected via metallized vias. Spiral wiring can achieve longer conductor paths within a limited planar area, thereby realizing a larger inductance and fully utilizing the planar wiring capabilities of the LTCC process. Furthermore, using a multi-layer stacking method can further compress the planar space occupied by the inductor, improving the device's integration density. Simultaneously, the interlayer transition with metallized vias ensures the continuity of the inductor current path and reduces the impact of parasitic parameters on inductor performance.

[0038] The first capacitor C1, the second capacitor C2, and the third capacitor C3 all employ a multilayer metal electrode structure, consisting of multiple layers of spaced-apart metal electrodes and ceramic dielectrics between the layers. The ceramic dielectric is the LTCC green ceramic layer itself. This multilayer capacitor structure leverages the advantages of LTCC's multilayer process, allowing for flexible adjustment of capacitance values ​​by stacking electrode layers, achieving the desired capacitance parameters within a very small volume. Simultaneously, the stable material properties of the ceramic dielectric result in capacitors with low temperature drift and high consistency, providing accurate and stable capacitive parameters for the LC time delay compensation network, ensuring the repeatability and long-term stability of the time delay compensation characteristics.

[0039] In terms of circuit topology selection, the constant-resistance LC delay compensation network adopts a Chebyshev topology, which consists of multiple sets of inductors and capacitors connected in series and parallel. The delay characteristics of the Chebyshev topology can better match the group delay ripple characteristics of bandpass filters, achieving a wider delay compensation range with the same component order, while keeping the in-band delay ripple within the design range. Compared to conventional simple LC networks, this topology can broaden the operating bandwidth of the device without significantly increasing the number of components, adapting to the filter compensation requirements of more frequency bands and improving the versatility of the solution.

[0040] Furthermore, this constant-resistance LC delay compensation network can employ second-order or higher multi-order topologies. As the topology order increases, the adjustable degrees of freedom of the delay curve increase, enabling a more precise fit to the group delay ripple shape of the front-end filter, thereby improving the accuracy of delay compensation and making the group delay curve within the operating passband flatter. In practical applications, the topology order can be flexibly selected based on the group delay ripple amplitude and bandwidth requirements of the target filter, achieving a balance between compensation accuracy, device size, and manufacturing cost.

[0041] The input port IN and output port OUT employ a microstrip line structure, extending horizontally from both sides of the LTCC multilayer substrate to form lateral signal interfaces. The microstrip line structure is compatible with transmission line configurations on conventional RF PCBs, enabling smooth impedance transitions and facilitating soldering and interconnection between the device and external RF circuits. The side-outlet layout also conforms to standard surface mount device assembly methods, adapting to automated mounting processes and enhancing the ease of engineering applications.

[0042] In the detailed design of the ports, the input port (IN) and output port (OUT) adopt a 50Ω impedance-matched gold-plated pad structure, which is a bonded interconnect design. 50Ω is the standard characteristic impedance of RF communication systems. By optimizing the microstrip line width, thickness, and surrounding grounding layout, precise impedance matching is achieved, which can effectively reduce signal reflection at the port and ensure the return loss performance of the device. The gold plating treatment on the pad surface can improve soldering reliability and oxidation resistance, reduce interconnect contact loss, and enable the device to maintain stable connection performance in harsh environments such as wide temperature range and high humidity.

[0043] In this embodiment, the LTCC multilayer substrate is made by laminating 9KC ceramic green ceramics and then co-firing them at low temperature. The 9KC ceramic green ceramics are LTCC glass-ceramic green blanks with a relative permittivity of approximately 7.3. The thickness of a single green ceramic layer is 50μm, and the overall number of layers on the substrate is designed to be 21±n, where n is an adjustable non-negative integer. 9K ceramic materials have a stable dielectric constant and low dielectric loss, and the device can operate in a temperature range of -55℃ to 125℃, ensuring the reliability of the device in harsh environments. The layered design of approximately 21 layers allows for the reasonable allocation of functional layers such as ports, components, and grounding, balancing integration and process feasibility. The adjustable number of layers allows for flexible addition or removal of component layers or shielding layers according to actual performance indicators, size requirements, and cost targets, balancing the device's size, electrical performance, and manufacturing cost, and adapting to different application scenarios.

[0044] Through the combination of the aforementioned multi-layered structure and circuit topology, the delay equalizer in this embodiment achieves stable and accurate group delay compensation while realizing miniaturized packaging. Within the operating frequency band of 1.545GHz to 2.295GHz, it achieves insertion loss ≤1.0dB, return loss ≤-20dB, and a delay compensation difference ≤0.5ns within any 250MHz range in the in-band. This device also supports system integration with other passive RF devices such as RF front-end filters, further simplifying the overall circuit layout and reducing module footprint. It can be widely used in various miniaturized RF communication and radar systems.

[0045] The terms “above,” “below,” and “within” as used above include the number itself; the terms “exceeding” and “excluding” do not include the number itself.

[0046] The present invention has been further described above with reference to specific embodiments. However, it should be understood that the specific descriptions herein should not be construed as limiting the substance and scope of the present invention. Various modifications made to the above embodiments by those skilled in the art after reading this specification are all within the scope of protection of the present invention. The various specific technical features described in the above embodiments can be combined in any suitable manner without contradiction. To avoid unnecessary repetition, the embodiments of the present invention will not further describe various possible combinations.

[0047] If the embodiments of the present invention involve directional indicators (such as up, down, left, right, front, back, etc.), the directional indicators are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicators will also change accordingly.

Claims

1. A miniaturized LTCC delay equalizer, characterized in that, The device includes an LTCC multilayer substrate, an input port, an output port, a ground shield layer, and a lumped element composed of lumped parameter inductors and lumped parameter capacitors. The LTCC multilayer substrate has a port layer, a lumped element layer, and a ground shield layer. The input port and output port are located on the port layer. The lumped parameter inductors and lumped parameter capacitors are integrated on the lumped element layer. The ground shield layer is electrically connected to the ground terminal of the lumped element through metallized vias. The lumped parameter inductors and lumped parameter capacitors are connected to form a constant-resistance LC delay compensation network. The delay compensation network includes a main signal path connected in series between the input port and the output port, and at least one series LC ground resonant branch connecting a node of the main signal path to the ground shield layer. The main signal path is composed of parallel-connected inductors and capacitors connected in series on both sides. This utilizes the characteristic of LC reactance varying with frequency to generate differentiated transmission delays for radio frequency signals of different frequencies, compensating for group delay fluctuations within the bandpass filter and flattening the group delay curve of the operating passband.

2. The miniaturized LTCC delay equalizer according to claim 1, characterized in that, The grounding shielding layer includes a grounding layer disposed on the bottom layer of the LTCC multilayer substrate and a grounding metal layer disposed on the periphery of the substrate, which together form an electromagnetic shielding structure covering the lumped element layer.

3. The miniaturized LTCC delay equalizer according to claim 2, characterized in that, The grounding shield layer also includes at least one intermediate grounding shield layer, which is disposed between adjacent lumped element layers to achieve interlayer electromagnetic isolation and reduce signal crosstalk.

4. The miniaturized LTCC delay equalizer according to claim 1, characterized in that, The lumped parameter inductor adopts a spiral metal wiring structure and is distributed in multiple wiring layers of the lumped element layer, with the layers electrically connected through metallized vias.

5. The miniaturized LTCC delay equalizer according to claim 1, characterized in that, The lumped-parameter capacitor adopts a metal electrode stacked structure, which is composed of multiple layers of spaced metal electrodes stacked with interlayer ceramic dielectric to form a stable lumped capacitance value.

6. The miniaturized LTCC delay equalizer according to claim 1, characterized in that, The constant resistance LC time delay compensation network adopts a Chebyshev topology and is composed of multiple sets of series and parallel inductors and capacitors to broaden the time delay compensation range.

7. The miniaturized LTCC delay equalizer according to claim 6, characterized in that, The constant resistance LC delay compensation network is a second-order or higher multi-order topology.

8. The miniaturized LTCC delay equalizer according to claim 1, characterized in that, Both the input and output ports adopt a microstrip line structure, which is led out laterally from both sides of the LTCC multilayer substrate for electrical connection with external radio frequency circuits.

9. The miniaturized LTCC delay equalizer according to claim 8, characterized in that, Both the input and output ports feature 50Ω impedance-matched bonded gold-plated pad structures to achieve low-loss port interconnection.

10. The miniaturized LTCC delay equalizer according to any one of claims 1 to 9, characterized in that, The LTCC multilayer substrate is made of 9KC ceramic green ceramic material, and the number of substrate layers is 21±n, where n is a non-negative integer.

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