Frequency and pulse width combined control method and unit, and pulse signal generation device

Abstract

This application provides a frequency and pulse width joint control method and unit, as well as a pulse signal generation device, relating to the field of signal processing technology. In this application, firstly, an ideal frequency and an ideal pulse width are obtained; secondly, under the joint constraints of the ideal frequency and ideal pulse width, a target frequency, a target frequency division coefficient, a target pulse width point count, and a target period point count are determined respectively. The target frequency is used to generate a programmable clock signal, the target frequency division coefficient is used to divide the programmable clock signal to obtain a reconstructed sampling clock signal, and the reconstructed sampling clock signal, the target pulse width point count, and the target period point count are used to generate a target digital pulse sequence. The target digital pulse sequence is then processed through analog circuitry to form a target pulse signal whose frequency and pulse width match the ideal frequency and ideal pulse width. Based on the above, the problem of relatively low control accuracy in pulse signal generation in existing technologies can be improved.

Description

Technical Field

[0001] This application relates to the field of signal processing technology, and more specifically, to a method and unit for joint frequency and pulse width control, and a pulse signal generation device. Background Technology

[0002] In the fields of nuclear power, nuclear measurement, nuclear instrument calibration, and detector signal simulation, a widely adopted nuclear pulse generation scheme is an FPGA (Field-Programmable Gate Array) counter scheme based on a fixed sampling clock. This scheme typically involves a control unit, an FPGA, a high-speed digital-to-analog converter (DAC), and analog conditioning circuitry. Its core working principle is as follows: using a fixed high-frequency sampling clock fs (e.g., 200MHz), the control unit calculates the number of sampling points (i.e., the number of period points N) and the number of high-level duration points (i.e., the number of pulse width points M) within one pulse cycle based on the user-defined target nuclear pulse frequency fp and target pulse width W. The calculation formulas are as follows: N = round(fs / fp), M = round(W·fs). Where round() is the floor function.

[0003] Subsequently, the FPGA's internal counter counts in each sampling clock cycle. When the count value is less than M, the DAC outputs a corresponding high-level code value; when the count value is greater than or equal to M and less than N, a low-level code value is output. This cycle generates a digital pulse sequence with a period of N / fs and a pulse width of M / fs. This sequence is then converted into an analog signal by the DAC and finally output as the desired core pulse through analog amplification, attenuation, or filtering circuits. This scheme has a relatively simple structure and can achieve basic adjustment of frequency, pulse width, and amplitude. Therefore, it has been used in various core pulse generation or signal simulation devices.

[0004] In other words, the control unit mentioned above controls the generation of pulse signals based on a fixed high-frequency sampling clock and a determined number of period points and pulse width points. As a result, the control unit has relatively low control accuracy in generating pulse signals. Summary of the Invention

[0005] In view of this, the purpose of this application is to provide a frequency and pulse width joint control method and unit, as well as a pulse signal generation device, to improve the problem of relatively low control accuracy of pulse signal generation in the prior art.

[0006] To achieve the above objectives, this application adopts the following technical solution: A method for joint frequency and pulse width control, comprising: Obtain the ideal frequency and ideal pulse width; Under the joint constraints of the ideal frequency and the ideal pulse width, the target frequency, target frequency division coefficient, target pulse width points, and target period points are determined respectively. The target frequency is used to generate a programmable clock signal, the target frequency division coefficient is used to divide the programmable clock signal to obtain a reconstructed sampling clock signal, the reconstructed sampling clock signal, the target pulse width points, and the target period points are used to generate a target digital pulse sequence, and the target digital pulse sequence is used to undergo analog processing to form a target pulse signal whose frequency and pulse width match the ideal frequency and the ideal pulse width.

[0007] In a preferred embodiment of this application, in the above-described frequency and pulse width joint control method, the step of determining the target frequency, target frequency division coefficient, target pulse width points, and target period points under the joint constraints of the ideal frequency and the ideal pulse width includes: Based on the combined frequency-pulse-width error corresponding to the ideal frequency and the ideal pulse width, and / or the duty cycle error corresponding to the target duty cycle determined based on the ideal frequency and the ideal pulse width, the target frequency, target frequency division coefficient, target pulse width points, and target period points are determined respectively.

[0008] In a preferred embodiment of this application, in the above-described frequency and pulse width joint control method, the step of determining the target frequency, target frequency division coefficient, target pulse width points, and target period points based on the frequency-pulse width joint error corresponding to the ideal frequency and the ideal pulse width and / or the duty cycle error corresponding to the target duty cycle determined based on the ideal frequency and the ideal pulse width as constraints includes: Based on the ideal frequency and the ideal pulse width, the target duty cycle is determined, and multiple first candidate combinations are determined. Each first candidate combination includes a first candidate pulse width point number and a first candidate cycle point number. Each first candidate pulse width point number is an integer, and each first candidate cycle point number is an integer. For each first candidate combination, the first candidate duty cycle corresponding to the first candidate combination is determined based on the number of first candidate pulse width points and the number of first candidate period points included in the first candidate combination. Based on the duty cycle error between the first candidate duty cycle and the target duty cycle for each first candidate combination, a first candidate combination that matches the target duty cycle is determined from the plurality of first candidate combinations, and the number of first candidate pulse width points and the number of first candidate cycle points included in the first candidate combination are determined as the target number of pulse width points and the target number of cycle points. Based on the number of first candidate period points included in the first candidate combination that matches the target duty cycle and the ideal frequency, the ideal sampling clock frequency is determined. Based on the ideal sampling clock frequency, the predetermined output frequency range and resolution, and the predetermined candidate frequency division coefficient range, the target frequency and target frequency division coefficient are determined.

[0009] In a preferred embodiment of this application, in the above-described frequency and pulse width joint control method, the step of determining the target frequency, target frequency division coefficient, target pulse width points, and target period points based on the frequency-pulse width joint error corresponding to the ideal frequency and the ideal pulse width and / or the duty cycle error corresponding to the target duty cycle determined based on the ideal frequency and the ideal pulse width as constraints includes: Based on the ideal frequency and the predetermined actual sampling clock range, a range of candidate period points is determined, wherein each second candidate period point in the range of candidate period points is an integer; The ideal sampling clock frequency corresponding to each of the second candidate period points is determined respectively; The candidate frequency division coefficient range is determined, and each second candidate combination is determined based on the candidate frequency division coefficient range and each second candidate period point, wherein each second candidate combination includes a second candidate frequency division coefficient belonging to the candidate frequency division coefficient range and a second candidate period point, and each second candidate frequency division coefficient is an integer; For each of the second candidate combinations, based on the ideal sampling clock frequency corresponding to the second candidate frequency division coefficient and the number of second candidate period points included in the second candidate combination, the ideal frequency of the synthesizer corresponding to the second candidate combination is determined. Furthermore, based on a predetermined output frequency range and resolution, the synthesizer output frequency that best matches the ideal frequency of the synthesizer is determined. Based on the synthesizer output frequency and the second candidate frequency division coefficient, the candidate sampling clock frequency is determined. Based on the candidate sampling clock frequency and the number of second candidate period points, the actual frequency corresponding to the second candidate combination is determined. Based on the actual frequency and the ideal frequency, the relative frequency error of the second candidate combination is determined. Based on the candidate sampling clock frequency and the ideal pulse width, the number of second candidate pulse width points corresponding to the second candidate combination is determined. Based on the number of second candidate pulse width points and the candidate sampling clock frequency, the actual pulse width corresponding to the second candidate combination is determined. Based on the actual pulse width and the ideal pulse width, the relative pulse width error of the second candidate combination is determined. Based on the relative frequency error and relative pulse width error of each second candidate combination, the second candidate combination that meets the target condition is determined. Based on the actual frequency corresponding to the second candidate combination that meets the target conditions, the second candidate frequency division coefficient, the number of second candidate pulse width points, and the number of second candidate period points, the target frequency, target frequency division coefficient, target number of pulse width points, and target number of period points are determined.

[0010] In a preferred embodiment of this application, in the above-described frequency and pulse width joint control method, the step of determining the second candidate combination that satisfies the target condition based on the relative frequency error and relative pulse width error of each second candidate combination includes: A target screening mode is determined, wherein the target screening mode belongs to frequency priority mode, pulse width priority mode or frequency-pulse width combined mode. In the frequency priority mode, the relative frequency error is more important than the relative pulse width error. In the pulse width priority mode, the relative pulse width error is more important than the relative frequency error. Based on the relative frequency error and relative pulse width error of each second candidate combination, second candidate combinations that meet the target conditions of the target selection mode are determined according to the target selection mode.

[0011] In a preferred embodiment of this application, in the above-described frequency and pulse width joint control method, the step of determining the second candidate combination that satisfies the target conditions of the target screening mode based on the relative frequency error and relative pulse width error of each second candidate combination, according to the target screening mode, includes: When the target screening mode is a frequency priority mode, each second candidate combination with a relative frequency error less than the frequency error threshold is determined, and among each second candidate combination with a relative frequency error less than the frequency error threshold, the second candidate combination with the smallest relative pulse width error is determined, and this second candidate combination is determined as the second candidate combination that satisfies the target condition. When the target screening mode is a pulse width priority mode, each second candidate combination with a relative pulse width error less than the pulse width error threshold is determined, and among each second candidate combination with a relative pulse width error less than the pulse width error threshold, the second candidate combination with the smallest relative frequency error is determined, and this second candidate combination is determined as the second candidate combination that satisfies the target condition. When the target screening mode belongs to the frequency pulse width synthesis mode, the frequency pulse width synthesis error corresponding to each second candidate combination is determined based on the relative frequency error and relative pulse width error of each second candidate combination, and the second candidate combination with the smallest frequency pulse width synthesis error is determined as the second candidate combination that satisfies the target condition.

[0012] In a preferred embodiment of this application, in the above-described frequency and pulse width joint control method, the steps of determining the frequency and pulse width combined error corresponding to each second candidate combination based on the relative frequency error and relative pulse width error of each second candidate combination when the target screening mode belongs to the frequency and pulse width combined mode, and determining the second candidate combination with the smallest frequency and pulse width combined error as the second candidate combination that satisfies the target condition, include: When the target screening mode belongs to the frequency pulse width synthesis mode, for each second candidate combination, the frequency pulse width synthesis error corresponding to the second candidate combination is obtained by weighted summation based on the relative frequency error and relative pulse width error of the candidate combination, combined with the period jitter of the sampling clock source, the total lock time of the clock link, the amplitude flatness error of the analog link. The second candidate combination with the smallest corresponding frequency pulse width synthesis error is determined as the second candidate combination that satisfies the target condition.

[0013] In a preferred embodiment of this application, in the above-described frequency and pulse width joint control method, the step of determining the target frequency, target frequency division coefficient, target pulse width points, and target period points based on the frequency-pulse width joint error corresponding to the ideal frequency and the ideal pulse width and / or the duty cycle error corresponding to the target duty cycle determined based on the ideal frequency and the ideal pulse width as constraints includes: Based on the ideal frequency and the ideal pulse width, the target duty cycle is determined, and multiple first candidate combinations are determined. Each first candidate combination includes a first candidate pulse width point number and a first candidate cycle point number. Each first candidate pulse width point number is an integer, and each first candidate cycle point number is an integer. For each first candidate combination, the first candidate duty cycle corresponding to the first candidate combination is determined based on the number of first candidate pulse width points and the number of first candidate period points included in the first candidate combination. Based on the duty cycle error between the first candidate duty cycle corresponding to each first candidate combination and the target duty cycle, a plurality of first candidate combinations that match the target duty cycle are determined from the plurality of first candidate combinations; For each of the multiple first candidate combinations that match the target duty cycle, the corresponding ideal sampling clock frequency is determined based on the number of first candidate period points in the first candidate combination. The number of first candidate period points is used as the number of third candidate period points to be combined with each third candidate frequency division coefficient in the predetermined range of candidate frequency division coefficients to form each third candidate combination. For each of the third candidate combinations, based on the ideal sampling clock frequency corresponding to the third candidate frequency division coefficient and the number of third candidate period points included in the third candidate combination, the ideal frequency of the synthesizer corresponding to the third candidate combination is determined. Furthermore, based on a predetermined output frequency range and resolution, the synthesizer output frequency that best matches the ideal frequency of the synthesizer is determined. Based on the synthesizer output frequency and the third candidate frequency division coefficient, the candidate sampling clock frequency is determined. Based on the candidate sampling clock frequency and the number of third candidate period points, the actual frequency corresponding to the third candidate combination is determined. Based on the actual frequency and the ideal frequency, the relative frequency error of the third candidate combination is determined. Based on the candidate sampling clock frequency and the ideal pulse width, the number of third candidate pulse width points corresponding to the third candidate combination is determined. Based on the number of third candidate pulse width points and the candidate sampling clock frequency, the actual pulse width corresponding to the third candidate combination is determined. Finally, based on the actual pulse width and the ideal pulse width, the relative pulse width error of the third candidate combination is determined. Based on the relative frequency error and relative pulse width error of each of the third candidate combinations, a third candidate combination that meets the target condition is determined. Based on the actual frequency corresponding to the third candidate combination that meets the target conditions, the included third candidate frequency division coefficient, the corresponding number of third candidate pulse width points, and the included third candidate period points, the target frequency, target frequency division coefficient, target number of pulse width points, and target number of period points are determined.

[0014] Based on the above, this application also provides a frequency and pulse width joint control unit for executing the above-described frequency and pulse width joint control method to determine the target frequency, target frequency division coefficient, target pulse width points, and target period points of the target pulse signal to be generated.

[0015] Based on the above, this application also provides a pulse signal generating device, comprising: The aforementioned frequency and pulse width joint control unit is used to execute the frequency and pulse width joint control method to determine the target frequency, target frequency division coefficient, target pulse width points, and target period points of the target pulse signal to be generated; A clock frequency synthesizer is used to generate a corresponding programmable clock signal based on the target frequency; The phase-locked loop in the field-programmable gate array is used to perform frequency division processing on the programmable clock signal based on the target frequency division coefficient to obtain a reconstructed sampling clock signal; The kernel pulse generation unit in the field-programmable gate array is used to generate a target digital pulse sequence based on the reconstructed sampling clock signal, the target pulse width points, and the target period points. The target digital pulse sequence is then processed by analog to form the target pulse signal.

[0016] This application provides a frequency and pulse width joint control method and unit, as well as a pulse signal generation device, relating to the field of signal processing technology. In this application, firstly, an ideal frequency and an ideal pulse width are obtained; secondly, under the joint constraints of the ideal frequency and ideal pulse width, a target frequency, a target frequency division coefficient, a target pulse width point count, and a target period point count are determined respectively. The target frequency is used to generate a programmable clock signal, the target frequency division coefficient is used to perform frequency division processing on the programmable clock signal to obtain a reconstructed sampling clock signal, the reconstructed sampling clock signal, the target pulse width point count, and the target period point count are used to generate a target digital pulse sequence, and the target digital pulse sequence is used to undergo analog processing to form a target pulse signal whose frequency and pulse width match the ideal frequency and ideal pulse width. Based on the above, on the one hand, since the target digital pulse sequence is formed based on the reconstructed sampling clock signal, and the reconstructed sampling clock signal is generated based on the target frequency and target division coefficient determined under the joint constraints of ideal frequency and ideal pulse width, it can improve the matching degree between the reconstructed sampling clock signal and the actual clock requirements to a certain extent. This makes it easier to match the actual clock requirements in terms of clock frequency compared to the scheme that uses the inherent high-frequency sampling clock frequency in the existing technology. On the other hand, since the determination of the target frequency, target division coefficient, target pulse width points and target period points is based on the joint constraints of ideal frequency and ideal pulse width, it is easier to achieve the high comprehensive accuracy requirements of frequency and pulse width. In other words, in the process of pulse signal generation, by determining the parameters with relatively higher accuracy (i.e., target frequency, target division coefficient, target pulse width points and target period points), higher precision control can be achieved. Attached Figure Description

[0017] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings.

[0018] Figure 1 This is a flowchart illustrating the frequency and pulse width joint control method provided in an embodiment of this application.

[0019] Figure 2 This is a schematic diagram illustrating the process of determining parameters based on duty cycle error, as provided in an embodiment of this application.

[0020] Figure 3 This is a schematic diagram illustrating the parameter determination process based on the frequency-pulse-width joint error, as provided in an embodiment of this application.

[0021] Figure 4 This is a block diagram of a pulse signal generating device provided in an embodiment of this application.

[0022] Figure 5This is a schematic diagram of the glitch-free switching process provided in an embodiment of this application.

[0023] Figure 6 A comparison chart of the fixed sampling clock and the reconfigurable sampling time base output target pulse width of 37.5ns provided in the embodiments of this application. Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely represents selected embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0025] Before formally describing the frequency and pulse width joint control method, unit, and pulse signal generation device provided in the embodiments of this application, it should be noted that, as described in the background art, the technical problem to be solved by the embodiments of this application is that, for the control of pulse signal generation, since the control unit is based on a fixed high-frequency sampling clock and separately determined number of period points and pulse width points, there is a problem that the control accuracy of the control unit in pulse signal generation is relatively low. It should be further explained that, through long-term research and analysis by the inventors of this application, it has been found that under a fixed sampling clock, since the number of period points and pulse width points are both discrete values ​​after rounding, the resulting quantization error cannot be eliminated, leading to inherent deviations between the frequency and pulse width of the output signal and the target frequency and pulse width. Furthermore, under a fixed sampling clock, there is a mutually restrictive relationship between frequency accuracy and pulse width accuracy: improving frequency accuracy requires a higher sampling clock frequency, but this is limited by the maximum sampling rate of the DAC and the timing constraints of the FPGA; while reducing the sampling clock frequency is beneficial to improving pulse width resolution, it deteriorates frequency accuracy. This contradiction makes it difficult for a single fixed clock to simultaneously meet the dual high-precision requirements of frequency and pulse width. Especially in scenarios such as nuclear instrument calibration, it is necessary to output accurate frequency (for count rate calibration) and accurate pulse width (for discrimination threshold testing) at the same time, which is difficult to achieve with a fixed sampling clock scheme.

[0026] In view of the research findings on the aforementioned technical problems, and the long-term research of the inventors of this application, a technical concept completely different from the prior art (i.e., using a fixed high-frequency sampling clock) has been creatively proposed. Specifically, under the joint constraints of ideal frequency and ideal pulse width, the target frequency, target frequency division coefficient, target pulse width points, and target period points are determined respectively. In this technical concept, the sampling clock is reconstructed, thus no longer relying on a fixed high-frequency sampling clock. This effectively improves the problem of relatively low control accuracy in the prior art due to reliance on a fixed high-frequency sampling clock for pulse signal generation control. Therefore, with improved control accuracy, the accuracy of the generated pulse signal can be improved.

[0027] Based on this, and in accordance with the above-mentioned technical concept, embodiments of this application provide a frequency and pulse width joint control method and unit, and a pulse signal generation device. Furthermore, to fully explain the frequency and pulse width joint control method and unit, and the pulse signal generation device, the frequency and pulse width joint control method, the frequency and pulse width joint control unit, and the pulse signal generation device are explained accordingly below, ensuring clarity for each part.

[0028] like Figure 1 As shown, this application provides a method for joint frequency and pulse width control. The following will describe... Figure 1 The specific process shown will be explained in detail.

[0029] Step S110: Obtain the ideal frequency and ideal pulse width.

[0030] In this embodiment, the ideal frequency and ideal pulse width can be obtained. It should be noted that the ideal frequency and ideal pulse width can be the frequency and pulse width of the target pulse signal to be generated, and can be obtained by parsing data sent from a host computer. In this embodiment, the frequency and pulse width joint control method can be executed by a frequency and pulse width joint control unit. For example, the frequency and pulse width joint control unit can be connected to a host computer, and can include a processor and a memory. The processor executes the computer program in the memory to implement the frequency and pulse width joint control method. Furthermore, in some embodiments, parameters such as amplitude, polarity, and / or phase can also be obtained. These parameters can participate in subsequent processing, such as analog processing.

[0031] Step S120: Under the joint constraints of the ideal frequency and the ideal pulse width, the target frequency, the target frequency division coefficient, the target pulse width points, and the target period points are determined respectively.

[0032] In this embodiment, after obtaining the ideal frequency and the ideal pulse width, the target frequency, target division coefficient, target pulse width points, and target period points can be determined under the joint constraints of the ideal frequency and the ideal pulse width. The target frequency is used to generate a programmable clock signal, the target division coefficient is used to divide the programmable clock signal to obtain a reconstructed sampling clock signal, and the reconstructed sampling clock signal, the target pulse width points, and the target period points are used to generate a target digital pulse sequence. The target digital pulse sequence is used to undergo analog processing to form a target pulse signal whose frequency and pulse width match the ideal frequency and the ideal pulse width. Exemplarily, the processor in the frequency and pulse width joint control unit can determine the target frequency, target division coefficient, target pulse width points, and target period points under the joint constraints of the ideal frequency and the ideal pulse width. Additionally, in some embodiments, the frequency and pulse width joint control unit can also be connected to a clock frequency synthesizer and a field-programmable gate array (FPGA). Thus, after determining the target frequency, target division factor, target pulse width points, and target period points, the frequency and pulse width joint control unit can send the target frequency to the clock frequency synthesizer, enabling the clock frequency synthesizer to generate a corresponding programmable clock signal based on the target frequency. Furthermore, the frequency and pulse width joint control unit can send the target division factor to the field-programmable gate array (FPGA), allowing the phase-locked loop (PLL) in the FPGA to perform frequency division processing on the programmable clock signal based on the target division factor to obtain a reconstructed sampling clock signal. Additionally, the frequency and pulse width joint control unit can also send the target pulse width points and the target period points to the FPGA, enabling the core pulse generation unit in the FPGA to generate a target digital pulse sequence based on the reconstructed sampling clock signal, the target pulse width points, and the target period points. This target digital pulse sequence, after analog processing, can form the target pulse signal. For example, it can be converted to an analog signal via a DAC, and finally, through analog amplification, attenuation, and / or filtering circuits, the required core pulse, i.e., the target pulse signal, is output.

[0033] It should be noted that the above-mentioned hardware devices (such as the frequency and pulse width joint control unit, the clock frequency synthesizer, and the field programmable gate array) are only examples. In other embodiments, other devices can also be used as long as they have the corresponding functions.

[0034] Based on the above, on the one hand, since the target digital pulse sequence is formed based on the reconstructed sampling clock signal, and the reconstructed sampling clock signal is generated based on the target frequency and target division coefficient determined under the joint constraints of ideal frequency and ideal pulse width, it can improve the matching degree between the reconstructed sampling clock signal and the actual clock requirements to a certain extent. This makes it easier to match the actual clock requirements in terms of clock frequency compared to the scheme that uses the inherent high-frequency sampling clock frequency in the existing technology. On the other hand, since the determination of the target frequency, target division coefficient, target pulse width points and target period points is based on the joint constraints of ideal frequency and ideal pulse width, it is easier to achieve the high comprehensive accuracy requirements of frequency and pulse width. In other words, in the process of pulse signal generation, by determining the parameters with relatively higher accuracy (i.e., target frequency, target division coefficient, target pulse width points and target period points), higher precision control can be achieved.

[0035] In other words, the above method first obtains the user's desired ideal frequency and ideal pulse width. Then, under the joint constraint of these two parameters, a set of parameters is determined by solving for the target frequency, target frequency division coefficient, target pulse width points, and target period points. The target frequency is used to generate a programmable clock signal, which serves as the basis for all subsequent clocks. The target frequency division coefficient is used to divide this programmable clock signal to obtain a reconstructed sampling clock signal. This reconstructed sampling clock signal, together with the target pulse width points and target period points, is used to generate a target digital pulse sequence. This digital pulse sequence is then processed by simulation to ultimately form a target pulse signal whose frequency and pulse width match the ideal frequency and ideal pulse width. It can be understood that this embodiment no longer treats the sampling clock as a fixed constraint, but rather as an optimization variable that can be derived from the target parameters, thus fundamentally overcoming the inherent defects of a fixed time base.

[0036] It is understood that in step S120 above, the specific methods for determining the target frequency, target frequency division coefficient, target pulse width points, and target period points are not restricted and can be selected according to actual needs. For example, the specific method for the joint constraint of the ideal frequency and the ideal pulse width can be selected according to actual application needs.

[0037] For example, in an alternative implementation, considering that pulse generation generally requires high precision in the frequency and pulse width of the generated pulse, and may also require high precision in the duty cycle of the generated pulse, step S120 above can further include the following steps to determine the target frequency, target frequency division coefficient, target pulse width points, and target period points: Using the combined frequency-pulse-width error corresponding to the ideal frequency and the ideal pulse width, and / or the duty cycle error corresponding to the target duty cycle determined based on the ideal frequency and the ideal pulse width, as constraints, the target frequency, target frequency division factor, target pulse width points, and target period points are determined respectively. In other words, in practical applications, there can be multiple ways to determine the above four parameters. For example, one method is to use the combined frequency-pulse-width error corresponding to the ideal frequency and the ideal pulse width as a constraint, or to use the duty cycle error corresponding to the target duty cycle determined based on the ideal frequency and the ideal pulse width as a constraint, or to use both errors as constraints to determine the target frequency, target frequency division factor, target pulse width points, and target period points respectively. The combined frequency-pulse-width error mentioned here refers to a measure that comprehensively considers both frequency error and pulse width error, while the duty cycle error refers to the deviation between the actual duty cycle and the target duty cycle.

[0038] It is understood that, in the above steps, the specific methods for determining the target frequency, target frequency division coefficient, target pulse width points, and target period points based on the frequency-pulse width joint error and / or duty cycle error are not limited. For example, in the embodiments of this application, the following four methods are used to illustrate this: in the first alternative embodiment, the duty cycle error corresponding to the target duty cycle determined based on the ideal frequency and ideal pulse width is used as the constraint basis; in the second alternative embodiment, the frequency-pulse width joint error corresponding to the ideal frequency and ideal pulse width is used as the constraint basis; and in the third and fourth alternative embodiments, the frequency-pulse width joint error and duty cycle error are used as the constraint basis (the specific constraint processes are different).

[0039] In the first alternative implementation, combined with Figure 2 The specific process of determining the target frequency, target frequency division coefficient, target pulse width points, and target period points can be as follows: steps S121a, S121b, S121c, S121d, and S121e.

[0040] Step S121a: Based on the ideal frequency and the ideal pulse width, determine the target duty cycle and identify multiple first candidate combinations.

[0041] In this embodiment, a target duty cycle (e.g., D = W·fp, where D is the target duty cycle, W is the ideal pulse width, and fp is the ideal frequency) can be determined based on the ideal frequency and the ideal pulse width, and multiple first candidate combinations can be identified. Each first candidate combination includes a first candidate pulse width point count and a first candidate cycle point count, where each first candidate pulse width point count and each first candidate cycle point count are integers. It should be noted that in one application scenario, the first candidate combinations can be randomly and arbitrarily determined, i.e., each first candidate pulse width point count and each first candidate cycle point count are randomly and arbitrarily determined. In another application scenario, to improve efficiency and avoid wasting computational resources, constraints can be imposed on the first candidate pulse width point count and the first candidate cycle point count. Specifically, constraints can be imposed based on the corresponding hardware devices, such as N not exceeding the FPGA counter range, M not less than the minimum pulse width point count, MN not less than the minimum low-level point count, etc., where N is the first candidate cycle point count and M is the first candidate pulse width point count.

[0042] Step S121b: For each first candidate combination, determine the first candidate duty cycle corresponding to the first candidate combination based on the number of first candidate pulse width points and the number of first candidate period points included in the first candidate combination.

[0043] In the embodiments of this application, after determining the first candidate combination, for each first candidate combination, the first candidate duty cycle corresponding to the first candidate combination can be determined based on the number of first candidate pulse width points and the number of first candidate cycle points included in the first candidate combination, such as first candidate duty cycle = number of first candidate pulse width points / number of first candidate cycle points, i.e., M / N.

[0044] Step S121c: Based on the duty cycle error between the first candidate duty cycle and the target duty cycle for each first candidate combination, determine a first candidate combination that matches the target duty cycle among the plurality of first candidate combinations, and determine the number of first candidate pulse width points and the number of first candidate cycle points included in the first candidate combination as the target number of pulse width points and the target number of cycle points.

[0045] In this embodiment of the application, after obtaining the first candidate duty cycle, based on the duty cycle error between the first candidate duty cycle corresponding to each first candidate combination and the target duty cycle (such as calculating the difference between the first candidate duty cycle and the target duty cycle as the corresponding duty cycle error), a first candidate combination that matches the target duty cycle can be determined among the plurality of first candidate combinations (such as the first candidate combination with the smallest duty cycle error). The number of first candidate pulse width points and the number of first candidate cycle points included in the first candidate combination are determined as the target number of pulse width points and the target number of cycle points. That is, the integer pair (M, N) that minimizes the difference between M / N and D is searched first, thus obtaining the target number of pulse width points and the target number of cycle points.

[0046] Step S121d: Based on the number of first candidate period points included in the first candidate combination that matches the target duty cycle and the ideal frequency, determine the ideal sampling clock frequency.

[0047] In this embodiment of the application, after obtaining the first candidate combination that matches the target duty cycle, the ideal sampling clock frequency can be determined based on the number of first candidate period points included in the first candidate combination that matches the target duty cycle and the ideal frequency. For example, the ideal sampling clock frequency = the number of first candidate period points * the ideal frequency, i.e. =N·fp, where This is the ideal sampling clock frequency.

[0048] Step S121e: Based on the ideal sampling clock frequency, the predetermined output frequency range and resolution, and the predetermined candidate frequency division coefficient range, the target frequency and target frequency division coefficient are determined. For example, the difference between the actual sampling clock frequency determined by the target frequency and the target frequency division coefficient and the ideal sampling clock frequency is minimized. The candidate frequency division coefficient range is determined based on the input frequency range, output frequency range, and VCO frequency range of the phase-locked loop.

[0049] In this embodiment, after obtaining the ideal sampling clock frequency, the target frequency and target frequency division coefficient can be determined based on the ideal sampling clock frequency, a predetermined output frequency range and resolution, and a predetermined candidate frequency division coefficient range. That is, the target frequency and target frequency division coefficient are determined when the frequency meets the output frequency range and resolution, and the frequency division coefficient meets the candidate frequency division coefficient range, so that the actual sampling clock frequency determined based on the target frequency and target frequency division coefficient (e.g., ...) is obtained. / Q, where This is the actual sampling clock frequency. The difference between the target frequency (where Q is the target frequency division factor) and the ideal sampling clock frequency is minimized.

[0050] It should be noted that the output frequency range and resolution, as well as the candidate division factor range, can be determined based on the specific hardware. For example, the output frequency range and resolution can be determined based on the clock frequency synthesizer, and the candidate division factor range can be determined based on the phase-locked loop (PLL) in the field-programmable gate array (FPGA). Furthermore, the determined actual sampling clock frequency can be constrained by a DAC or analog link, meaning it cannot exceed the allowable range of the corresponding devices.

[0051] In other words, in one specific implementation, the target duty cycle can be calculated first based on the ideal frequency and ideal pulse width. Then, multiple first candidate combinations are enumerated, each containing an integer number of first candidate pulse width points and an integer number of first candidate cycle points. For each first candidate combination, the corresponding first candidate duty cycle can be calculated based on its number of first candidate pulse width points and first candidate cycle points. Next, the duty cycle error between each first candidate duty cycle and the target duty cycle is compared, and the first candidate combination that best matches the target duty cycle is selected. The number of first candidate pulse width points and the number of first candidate cycle points in this combination are then determined as the target pulse width points and target cycle points, respectively. Then, based on the number of first candidate cycle points in the selected first candidate combination and the ideal frequency, the ideal sampling clock frequency can be calculated. Finally, based on this ideal sampling clock frequency, a predetermined output frequency range and resolution, and a predetermined range of candidate frequency division coefficients, the target frequency and target frequency division coefficients are determined. This approach essentially transforms the joint accuracy problem of frequency and pulse width into a collaborative approximation problem of the target duty cycle through rational number approximation, which is beneficial for simultaneously optimizing the two time parameters.

[0052] In a second alternative implementation, combined with Figure 3 The specific process of determining the target frequency, target frequency division coefficient, target pulse width points, and target period points can be as follows: steps S122a, S122b, S122c, S122d, S122e, and S122f.

[0053] Step S122a: Based on the ideal frequency and the predetermined actual sampling clock range, determine the range of candidate period points. Exemplarily, the output frequency range and resolution are determined based on the output range and resolution of the clock frequency synthesizer.

[0054] In this embodiment, the range of candidate period points can be determined based on the ideal frequency and a predetermined actual sampling clock range. Each second candidate period point in the range of candidate period points is an integer. For example, the range of candidate period points can be determined based on the following calculation method: Where N is the number of the second candidate periodic points, [fs，min f s，max [Indicates the actual sampling clock range] This is the ideal frequency. Furthermore, f s，min The value f is determined by the minimum number of pulse points, the minimum refresh requirement, and the lower limit of PLL (phase-locked loop) operation. s，max The maximum sampling rate of the DAC, the timing convergence capability of the FPGA, the range of the VCO (voltage-controlled oscillator) in the PLL, and the analog link bandwidth are jointly determined. The specific determination process can be referred to the relevant existing technologies, which will not be elaborated here.

[0055] Step S122b: Determine the ideal sampling clock frequency corresponding to each of the second candidate period points.

[0056] In this embodiment of the application, after obtaining the range of candidate period points, the ideal sampling clock frequency corresponding to the second candidate period point in each range of candidate period points can be determined, such as... =N· ,in, Let N be the ideal sampling clock frequency, and N be the number of second candidate period points. This is the ideal frequency.

[0057] Step S122c: Determine the range of candidate frequency division coefficients, and, based on the range of candidate frequency division coefficients and the number of period points of each second candidate, determine each second candidate combination.

[0058] In this embodiment, the range of candidate frequency division coefficients can also be determined (based on the hardware parameters of the PLL (Phase-Locked Loop)). For example, the lower limit of the actual sampling clock range is determined by the minimum number of pulse points, the minimum refresh requirement, and the lower limit of the PLL reference input frequency; the upper limit of the actual sampling clock range is determined by the maximum sampling rate of the digital-to-analog converter, the timing convergence capability of the FPGA, the range of the PLL VCO, and the analog link bandwidth. Thus, after obtaining the range of candidate period points, each second candidate combination, such as (N, Q), can be determined based on the range of candidate frequency division coefficients and each second candidate period point, where N represents the second candidate period point and Q represents the second candidate frequency division coefficient. Each second candidate combination includes a second candidate frequency division coefficient belonging to the range of candidate frequency division coefficients and a second candidate period point, and each second candidate frequency division coefficient is an integer.

[0059] Step S122d: For each second candidate combination, based on the ideal sampling clock frequency corresponding to the second candidate frequency division coefficient and the number of second candidate period points included in the second candidate combination, determine the ideal synthesizer frequency corresponding to the second candidate combination; and based on a predetermined output frequency range and resolution, determine the synthesizer output frequency that best matches the ideal synthesizer frequency; and based on the synthesizer output frequency and the second candidate frequency division coefficient, determine the candidate sampling clock frequency; and based on the candidate sampling clock frequency and the number of second candidate period points, determine the actual frequency corresponding to the second candidate combination; and based on the actual frequency and the ideal frequency, determine the relative frequency error of the second candidate combination; and based on the candidate sampling clock frequency and the ideal pulse width, determine the number of second candidate pulse width points corresponding to the second candidate combination; and based on the number of second candidate pulse width points and the candidate sampling clock frequency, determine the actual pulse width corresponding to the second candidate combination; and based on the actual pulse width and the ideal pulse width, determine the relative pulse width error of the second candidate combination.

[0060] In this embodiment of the application, after determining the second candidate combination, for each second candidate combination, the ideal sampling clock frequency corresponding to the second candidate combination can be determined based on the second candidate frequency division coefficients included in the second candidate combination and the ideal sampling clock frequency corresponding to the number of second candidate period points included in the second candidate combination. = · ,in, For the ideal frequency of the synthesizer, The second candidate frequency division coefficient, Given the ideal sampling clock frequency, and based on a predetermined output frequency range and resolution (which can be determined according to the range and resolution of the clock frequency synthesizer's output frequency), determine the synthesizer output frequency that best matches the ideal frequency of the synthesizer (i.e., select the closest one). Actual configurable output values The candidate sampling clock frequency (i.e., the most matching synthesizer output frequency) is determined based on the synthesizer output frequency and the second candidate frequency division coefficient. = / Q, where Given the candidate sampling clock frequency and Q as the second candidate frequency division coefficient, and based on the candidate sampling clock frequency and the number of period points of the second candidate, determine the actual frequency (e.g., f) corresponding to the second candidate combination. out = / N, where (the actual frequency), and, based on the actual frequency and the ideal frequency, determine the relative frequency error of the second candidate combination (e.g., the actual frequency). ,in, (for relative frequency error), and based on the candidate sampling clock frequency and the ideal pulse width, determine the number of second candidate pulse width points corresponding to the second candidate combination (e.g., M=round(W· ), where M is the number of second candidate pulse width points, W is the ideal pulse width, and round() is the rounding function), and, based on the number of second candidate pulse width points and the candidate sampling clock frequency, the actual pulse width corresponding to the second candidate combination is determined (e.g., =M / ,in, The actual pulse width (i.e., the pulse width that can actually be output based on the number of pulse width points in the second candidate and the sampling clock frequency of the candidate), and the relative pulse width error of the second candidate combination (e.g., based on the actual pulse width and the ideal pulse width) are determined. ,in, (This refers to the relative pulse width error).

[0061] Step S122e: Based on the relative frequency error and relative pulse width error of each second candidate combination, determine the second candidate combination that meets the target conditions. For example, the target conditions are set based on the relative frequency error and the relative pulse width error. Candidate combination filtering conditions: 1. The number of cycle points does not exceed the FPGA counter bit width; 2. The number of pulse width points is not less than the minimum number of high-level points; 3. The difference between the number of cycle points and the number of pulse width points is not less than the minimum number of low-level points; 4. The sampling clock does not exceed the allowable range of the digital-to-analog converter, FPGA, or analog link; 5. The PLL input frequency or VCO frequency does not exceed its operating range; 6. The programmable clock signal frequency does not exceed the clock frequency synthesizer output range; 7. The estimated jitter or lock time does not exceed the system's allowable threshold.

[0062] In this embodiment, after obtaining the relative frequency error and the relative pulse width error, a second candidate combination that satisfies the target condition can be determined based on the relative frequency error and the relative pulse width error of each second candidate combination. That is, the target condition is related to the relative frequency error and the relative pulse width error; that is, the corresponding errors satisfy the conditions set according to the accuracy requirements.

[0063] Step S122f: Based on the actual frequency corresponding to the second candidate combination that meets the target conditions, the second candidate frequency division coefficient, the number of second candidate pulse width points, and the number of second candidate period points, determine the target frequency, target frequency division coefficient, target number of pulse width points, and target number of period points.

[0064] In this embodiment of the application, after determining the second candidate combination that meets the target conditions, the target frequency, target frequency division coefficient, target pulse width point, and target period point can be determined based on the actual frequency corresponding to the second candidate combination that meets the target conditions, the second candidate frequency division coefficient, the corresponding number of second candidate pulse width points, and the number of second candidate period points. For example, the actual frequency corresponding to the second candidate combination that meets the target conditions is taken as the target frequency, the second candidate frequency division coefficient included in the second candidate combination that meets the target conditions is taken as the target frequency division coefficient, the number of second candidate pulse width points corresponding to the second candidate combination that meets the target conditions is taken as the target pulse width point, and the number of second candidate period points included in the second candidate combination that meets the target conditions is taken as the target period point.

[0065] In other words, in one specific implementation, a range of candidate period points is first determined based on the ideal frequency and a predetermined actual sampling clock range, where each second candidate period point is an integer. Then, the ideal sampling clock frequency corresponding to each second candidate period point is determined. Simultaneously, a range of candidate frequency division coefficients is determined, and each integer frequency division coefficient within this range is paired with each second candidate period point to form multiple second candidate combinations. Each combination contains one second candidate frequency division coefficient and one second candidate period point. For each second candidate combination, firstly, the ideal synthesizer frequency corresponding to the combination is calculated based on the ideal sampling clock frequency corresponding to the second candidate frequency division coefficient and the number of second candidate period points. Then, based on the predetermined output frequency range and resolution, the synthesizer output frequency that best matches the ideal synthesizer frequency is found. Next, the candidate sampling clock frequency is calculated based on the synthesizer output frequency and the second candidate frequency division coefficient. Then, based on the candidate sampling clock frequency and the number of second candidate period points, the actual frequency corresponding to the combination is calculated, and the relative frequency error is determined based on the difference between the actual frequency and the ideal frequency. Simultaneously, based on the candidate sampling clock frequency and the ideal pulse width, the number of second candidate pulse width points corresponding to the combination is determined, and the actual pulse width is calculated based on the number of second candidate pulse width points and the candidate sampling clock frequency. The relative pulse width error is determined based on the difference between the actual pulse width and the ideal pulse width. After obtaining the relative frequency error and relative pulse width error of all second candidate combinations, second candidate combinations that meet the preset target conditions are selected. Finally, based on the actual frequency corresponding to the second candidate combination that meets the conditions, the included second candidate frequency division coefficients, the corresponding number of second candidate pulse width points, and the included number of second candidate period points, the target frequency, target frequency division coefficients, target number of pulse width points, and target number of period points are determined respectively. This enumeration and constraint filtering method systematically searches the entire hardware-allowed time base space and can find the optimal configuration for the current target parameters.

[0066] It is understood that the specific method for determining the second candidate combination that meets the target conditions in step S122e above is not limited. For example, in an alternative implementation, in order to make the determined second candidate combination more compatible with actual needs, step S122e above may further include steps e1 and e2, wherein the specific contents of each step are as follows.

[0067] Step e1: Determine the target filtering mode.

[0068] In this embodiment, a target filtering mode can be determined first. For example, it can be determined based on user selection or other data analysis results. The target filtering mode can be a frequency-priority mode, a pulse-width-priority mode, or a frequency-pulse-width combined mode. In the frequency-priority mode, the relative frequency error is more important than the relative pulse-width error, such as prioritizing frequency accuracy requirements. In the pulse-width-priority mode, the relative pulse-width error is more important than the relative frequency error, such as prioritizing pulse-width accuracy requirements. Furthermore, the frequency-pulse-width combined mode can achieve a balance between frequency accuracy requirements and pulse-width accuracy requirements.

[0069] Step e2: Based on the relative frequency error and relative pulse width error of each second candidate combination, determine the second candidate combination that meets the target conditions of the target screening mode according to the target screening mode.

[0070] In this embodiment of the application, after determining the target screening mode, the second candidate combination that satisfies the target conditions of the target screening mode can be determined based on the relative frequency error and relative pulse width error of each second candidate combination.

[0071] In other words, during the enumeration and filtering process described above, the determination of the target conditions can further rely on a target screening mode. This target screening mode can be a frequency-first mode, a pulse-width-first mode, or a frequency-pulse-width combined mode. In the frequency-first mode, the relative frequency error is more important than the relative pulse-width error, i.e., frequency accuracy is prioritized; in the pulse-width-first mode, the opposite is true; while in the frequency-pulse-width combined mode, the importance of both needs to be considered, and a comprehensive score can be used to determine the outcome. Specifically, after determining the target screening mode, for each second candidate combination, its satisfaction with the target conditions can be determined according to the requirements of that mode.

[0072] It is understood that the process of determining the second candidate combination according to the target screening pattern in step e2 above is not limited. For example, in an alternative implementation, step e2 above may specifically include the following: Firstly, when the target screening mode is a frequency priority mode, each second candidate combination whose relative frequency error is less than the frequency error threshold (which can be set according to actual accuracy requirements, without specific limitations here, and can be an acceptable upper limit of error set in engineering practice) can be determined. In each second candidate combination whose relative frequency error is less than the frequency error threshold, the second candidate combination with the smallest relative pulse width error is determined, and this second candidate combination is determined as the second candidate combination that satisfies the target condition. Secondly, when the target screening mode is a pulse width priority mode, each second candidate combination whose relative pulse width error is less than the pulse width error threshold (which can be set according to actual accuracy requirements, without specific limitation here, and can be an acceptable upper limit of error set in engineering practice) can be determined. In each second candidate combination whose relative pulse width error is less than the pulse width error threshold, the second candidate combination with the smallest relative frequency error is determined and the second candidate combination is determined as the second candidate combination that satisfies the target condition. Thirdly, when the target screening mode belongs to the frequency pulse width synthesis mode, the frequency pulse width synthesis error corresponding to each second candidate combination can be determined based on the relative frequency error and relative pulse width error of each second candidate combination, and the second candidate combination with the smallest frequency pulse width synthesis error can be determined as the second candidate combination that satisfies the target condition.

[0073] In other words, when the target selection mode is frequency-priority mode, all second candidate combinations with relative frequency errors less than a certain frequency error threshold are first identified. Then, the combination with the smallest relative pulse width error is selected from these combinations and determined as the combination that meets the target condition. When the target selection mode is pulse width-priority mode, all second candidate combinations with relative pulse width errors less than a certain pulse width error threshold are first identified, and then the combination with the smallest relative frequency error is selected. When the target selection mode is frequency-pulse width combined mode, a frequency-pulse width combined error needs to be calculated for each second candidate combination based on its relative frequency error and relative pulse width error. Then, the combination with the smallest combined error is determined as the combination that meets the target condition.

[0074] It should be noted that for scenarios with higher frequency accuracy requirements, such as count rate verification, the frequency-priority mode can be used. For scenarios with higher sensitivity to pulse width accuracy, such as discrimination threshold testing, the pulse width-priority mode can be used. For scenarios that require comprehensive consideration of multiple accuracy requirements, the frequency-pulse width combined mode can be used.

[0075] Additionally, it should be noted that if no second candidate combination exists in the selected mode (e.g., no solution under a strict error threshold), the corresponding threshold can be relaxed or the approximate solution with the highest score (e.g., the smallest comprehensive error in the frequency pulse width synthesis mode) can be returned, and the actually achievable frequency f should be explicitly returned to the host computer. out Pulse width W out And the error between it and the target value. This decision-making mechanism gives the device a clear "information" capability, solving the problems of vague parameter settings and unknown actual output error in traditional generators. It enables testers to clearly understand the best possible output under the current hardware limitations and to judge whether the test tolerance requirements are met based on the returned error information.

[0076] It is understandable that, in the above steps, the specific process for determining the second candidate combination that meets the target conditions for the frequency pulse width synthesis mode is not limited, that is, the specific method for determining the frequency pulse width synthesis error under the frequency pulse width synthesis mode is not limited. For example, in an alternative implementation, the relative frequency error and the relative pulse width error can be directly summed to obtain the corresponding frequency pulse width synthesis error. Alternatively, in another alternative implementation, to meet greater engineering accuracy requirements, the second candidate combination that meets the target conditions can be further determined based on the following steps: First, when the target screening mode belongs to the frequency pulse width synthesis mode, for each second candidate combination, the frequency pulse width synthesis error corresponding to the second candidate combination can be obtained by weighted summation based on the relative frequency error and relative pulse width error of the candidate combination, combined with the period jitter of the sampling clock source, the total lock time of the clock link, and the amplitude flatness error of the analog link. The amplitude flatness error is the deviation between the actual output amplitude and the ideal output amplitude of the analog link. Secondly, the second candidate combination with the smallest corresponding frequency pulse width synthesis error can be determined as the second candidate combination that satisfies the target condition.

[0077] It should be noted that the specific method for determining the frequency pulse width synthesis error can be as follows: ; in, For frequency pulse width combined error, , , , , These are weighting coefficients set according to the application scenario. This is the relative frequency error. This is the relative pulse width error. RMS period jitter is the sampling clock frequency. RMS period jitter is an inherent performance metric of the sampling clock source. To normalize the reference time, the ideal period corresponding to the ideal pulse width or the ideal frequency can be used. For example, when focusing on pulse width accuracy, the ideal pulse width is used; when focusing on frequency accuracy, the ideal period is used. This can be the lock time for the clock frequency synthesizer and PLL, i.e., the total lock time of the clock link. The maximum allowed lock time, To simulate link amplitude flatness error, such as ,in, The amplitude compensation coefficient (measured amplitude / ideal amplitude, or its reciprocal) is obtained from the compensation table. When the value is 1, it indicates no amplitude distortion. The further the deviation from 1, the greater the amplitude error. It should be noted that the amplitude response may vary with signal frequency, pulse width, output level, and load impedance. Therefore, the amplitude flatness error needs to be included in the scoring function to balance time accuracy and amplitude accuracy, avoiding the selection of a clock configuration with extremely high time accuracy but severe amplitude distortion, which would result in the output signal amplitude not meeting requirements. Additionally, This refers to the output level. This refers to the load impedance.

[0078] In other words, in frequency pulse width synthesis mode, more engineering factors can be introduced when calculating the frequency pulse width synthesis error. Specifically, for each second candidate combination, in addition to considering its relative frequency error and relative pulse width error, factors such as the period jitter of the sampling clock source, the total lock time of the clock link, and the amplitude flatness error of the analog link can be combined. These factors are then weighted and summed to obtain the frequency pulse width synthesis error corresponding to the combination. The resulting comprehensive score can more comprehensively reflect the performance trade-offs in actual engineering. For example, in scenarios requiring rapid parameter switching, the weight of lock time can be increased; in scenarios with high signal purity requirements, the jitter weight can be increased to optimize the low-jitter clock configuration. Finally, the second candidate combination with the smallest synthesis error is determined as the combination that meets the target conditions.

[0079] In a third alternative implementation, the specific process of determining the target frequency, target frequency division coefficient, target pulse width points, and target period points can be as follows: steps S123a, S123b, S123c, S123d, S123e, S123f, and S123g.

[0080] Step S123a: Based on the ideal frequency and the ideal pulse width, determine the target duty cycle and identify multiple first candidate combinations.

[0081] In this embodiment, based on the ideal frequency and the ideal pulse width, a target duty cycle is determined, and multiple first candidate combinations are identified. Each first candidate combination includes a first candidate pulse width point count and a first candidate cycle point count, where each first candidate pulse width point count and each first candidate cycle point count are integers. Refer to the preceding explanation of step S121a.

[0082] Step S123b: For each first candidate combination, determine the first candidate duty cycle corresponding to the first candidate combination based on the number of first candidate pulse width points and the number of first candidate period points included in the first candidate combination.

[0083] In this embodiment of the application, after determining the first candidate combination, for each first candidate combination, the first candidate duty cycle corresponding to the first candidate combination can be determined based on the number of first candidate pulse width points and the number of first candidate period points included in the first candidate combination. Refer to the preceding explanation of step S121b for further details.

[0084] Step S123c: Based on the duty cycle error between the first candidate duty cycle corresponding to each first candidate combination and the target duty cycle, determine a plurality of first candidate combinations that match the target duty cycle from among the plurality of first candidate combinations.

[0085] In this embodiment, after obtaining the first candidate duty cycle, based on the duty cycle error between the first candidate duty cycle corresponding to each first candidate combination and the target duty cycle, multiple first candidate combinations matching the target duty cycle can be determined from the multiple first candidate combinations. For example, a specified number of first candidate combinations with the smallest duty cycle error can be determined as first candidate combinations matching the target duty cycle. Alternatively, each first candidate combination with a duty cycle error less than a set threshold can be determined as a first candidate combination matching the target duty cycle. The specified number and set threshold can be configured according to actual application scenarios and requirements. For example, when the accuracy requirement for the duty cycle is high, the specified number and set threshold can be set to smaller values.

[0086] Step S123d: For each of the multiple first candidate combinations that match the target duty cycle, the corresponding ideal sampling clock frequency is determined based on the number of first candidate period points in the first candidate combination. The number of first candidate period points is used as the number of third candidate period points to be combined with each of the third candidate frequency division coefficients in the predetermined candidate frequency division coefficient range to form each third candidate combination.

[0087] In this embodiment of the application, after determining a plurality of first candidate combinations that match the target duty cycle, for each of the plurality of first candidate combinations that match the target duty cycle, the corresponding ideal sampling clock frequency can be determined based on the number of first candidate period points in the first candidate combination (refer to the relevant explanation of step S122b above, which will not be repeated here), and the number of first candidate period points is used as the number of third candidate period points to be combined with each of the third candidate frequency division coefficients in the predetermined candidate frequency division coefficient range to form each third candidate combination.

[0088] Step S123e: For each of the third candidate combinations, based on the ideal sampling clock frequency corresponding to the third candidate frequency division coefficient and the number of third candidate period points included in the third candidate combination, determine the ideal synthesizer frequency corresponding to the third candidate combination; and based on a predetermined output frequency range and resolution, determine the synthesizer output frequency that best matches the ideal synthesizer frequency; and based on the synthesizer output frequency and the third candidate frequency division coefficient, determine the candidate sampling clock frequency; and based on the candidate sampling clock frequency and the number of third candidate period points, determine the actual frequency corresponding to the third candidate combination; and based on the actual frequency and the ideal frequency, determine the relative frequency error of the third candidate combination; and based on the candidate sampling clock frequency and the ideal pulse width, determine the number of third candidate pulse width points corresponding to the third candidate combination; and based on the number of third candidate pulse width points and the candidate sampling clock frequency, determine the actual pulse width corresponding to the third candidate combination; and based on the actual pulse width and the ideal pulse width, determine the relative pulse width error of the third candidate combination.

[0089] In this embodiment of the application, after forming each third candidate combination, for each third candidate combination, the ideal frequency of the synthesizer corresponding to the third candidate combination can be determined based on the ideal sampling clock frequency corresponding to the third candidate frequency division coefficient and the number of third candidate period points included in the third candidate combination. Furthermore, based on a predetermined output frequency range and resolution, the synthesizer output frequency that best matches the ideal frequency of the synthesizer can be determined. Based on the synthesizer output frequency and the third candidate frequency division coefficient, the candidate sampling clock frequency can be determined. Based on the candidate sampling clock frequency and the number of third candidate period points, the actual frequency corresponding to the third candidate combination can be determined. Based on the actual frequency and the ideal frequency, the relative frequency error of the third candidate combination can be determined. Based on the candidate sampling clock frequency and the ideal pulse width, the number of third candidate pulse width points corresponding to the third candidate combination can be determined. Based on the number of third candidate pulse width points and the candidate sampling clock frequency, the actual pulse width corresponding to the third candidate combination can be determined. Finally, based on the actual pulse width and the ideal pulse width, the relative pulse width error of the third candidate combination can be determined. Please refer to the explanation of step S122d above.

[0090] Step S123f: Based on the relative frequency error and relative pulse width error of each of the third candidate combinations, determine the third candidate combination that satisfies the target condition.

[0091] In this embodiment, after obtaining the relative frequency error and relative pulse width error, a third candidate combination that satisfies the target condition can be determined based on the relative frequency error and relative pulse width error of each of the third candidate combinations. Refer to the preceding explanation of step S122e.

[0092] Step S123g: Based on the actual frequency corresponding to the third candidate combination that meets the target conditions, the third candidate frequency division coefficient, the corresponding number of third candidate pulse width points, and the number of third candidate period points, determine the target frequency, target frequency division coefficient, target number of pulse width points, and target number of period points.

[0093] In this embodiment, after determining the third candidate combination that satisfies the target conditions, the target frequency, target frequency division coefficient, target pulse width point number, and target period point number can be determined based on the actual frequency corresponding to the third candidate combination that satisfies the target conditions, the included third candidate frequency division coefficient, the corresponding third candidate pulse width point number, and the included third candidate period point number. Refer to the preceding explanation of step S122f ​​for further details.

[0094] In other words, this method first determines the target duty cycle based on the ideal frequency and ideal pulse width, and enumerates multiple first candidate combinations. Then, it filters out multiple first candidate combinations that match the target duty cycle based on the duty cycle error, instead of just one. Next, for each of these matched first candidate combinations, the number of first candidate cycle points is used as the number of third candidate cycle points, and paired with each third candidate frequency divider coefficient in the candidate frequency divider coefficient range to form multiple third candidate combinations. Then, for each third candidate combination, following steps similar to the aforementioned enumeration and filtering method, the synthesizer ideal frequency, synthesizer output frequency, candidate sampling clock frequency, actual frequency, relative frequency error, number of third candidate pulse width points, actual pulse width, and relative pulse width error are calculated sequentially. Finally, based on the relative frequency error and relative pulse width error of each third candidate combination, the third candidate combination that meets the target conditions is determined. Finally, based on the actual frequency corresponding to the third candidate combination that meets the conditions, the included third candidate frequency division coefficient, the corresponding number of third candidate pulse width points, and the included third candidate period points, the target frequency, target frequency division coefficient, target number of pulse width points, and target number of period points are determined respectively. This method first narrows down the candidate range by approximating the duty cycle, and then performs fine enumeration and filtering, balancing efficiency and accuracy.

[0095] In a fourth alternative implementation, the specific process of determining the target frequency, target frequency division coefficient, target pulse width points, and target period points can be as follows: steps S124a, S124b, S124c, S124d, S124e, and S124f.

[0096] Step S124a: Based on the ideal frequency and the predetermined actual sampling clock range, determine the range of candidate period points.

[0097] In this embodiment, the range of candidate period points can be determined based on the ideal frequency and a predetermined actual sampling clock range. Refer to the preceding explanation of step S122a.

[0098] Step S124b: Determine the ideal sampling clock frequency corresponding to each of the second candidate period points.

[0099] In this embodiment, after obtaining the range of candidate period points, the ideal sampling clock frequency corresponding to the second candidate period point in each range of candidate period points can be determined. Refer to the preceding explanation of step S122b.

[0100] Step S124c: Determine the range of candidate frequency division coefficients, and, based on the range of candidate frequency division coefficients and the number of period points of each second candidate, determine each second candidate combination.

[0101] In this embodiment, a range of candidate frequency division coefficients can also be determined. Thus, after obtaining the range of candidate period points, each second candidate combination can be determined based on the range of candidate frequency division coefficients and the number of each second candidate period point. Refer to the preceding explanation of step S122c.

[0102] Step S124d: For each of the second candidate combinations, based on the ideal sampling clock frequency corresponding to the second candidate frequency division coefficient and the number of second candidate period points included in the second candidate combination, determine the ideal synthesizer frequency corresponding to the second candidate combination; and, based on a predetermined output frequency range and resolution, determine the synthesizer output frequency that best matches the ideal synthesizer frequency; and, based on the synthesizer output frequency and the second candidate frequency division coefficient, determine the candidate sampling clock frequency; and, based on the candidate sampling clock frequency and the number of second candidate period points, determine the actual frequency corresponding to the second candidate combination; and, based on the actual frequency and the ideal frequency... The relative frequency error of the second candidate combination is determined, and the number of second candidate pulse width points corresponding to the second candidate combination is determined based on the candidate sampling clock frequency and the ideal pulse width. Based on the number of second candidate pulse width points and the candidate sampling clock frequency, the actual pulse width corresponding to the second candidate combination is determined. Based on the actual pulse width and the ideal pulse width, the relative pulse width error of the second candidate combination is determined. Based on the number of second candidate pulse width points and the number of second candidate period points, the second candidate duty cycle is determined. The difference between the second candidate duty cycle and the target duty cycle determined based on the ideal frequency and the ideal pulse width is calculated to obtain the duty cycle error of the second candidate combination.

[0103] In this embodiment, after determining the second candidate combination, for each second candidate combination, the ideal frequency of the synthesizer corresponding to the second candidate combination can be determined based on the ideal sampling clock frequency corresponding to the second candidate frequency division coefficient and the number of second candidate period points included in the second candidate combination. Furthermore, based on a predetermined output frequency range and resolution, the synthesizer output frequency that best matches the ideal frequency of the synthesizer can be determined. Based on the synthesizer output frequency and the second candidate frequency division coefficient, the candidate sampling clock frequency can be determined. Based on the candidate sampling clock frequency and the number of second candidate period points, the actual frequency corresponding to the second candidate combination can be determined. Based on the actual frequency and the ideal frequency, the relative frequency error of the second candidate combination can be determined. Based on the candidate sampling clock frequency and the ideal pulse width, the number of second candidate pulse width points corresponding to the second candidate combination can be determined. Based on the number of second candidate pulse width points and the candidate sampling clock frequency, the actual pulse width corresponding to the second candidate combination can be determined. Finally, based on the actual pulse width and the ideal pulse width, the relative pulse width error of the second candidate combination can be determined. The aforementioned processing procedure can be referred to the explanation of step S122d above. Based on this, a second candidate duty cycle can be determined based on the number of second candidate pulse width points and the number of second candidate period points. Furthermore, the difference between this second candidate duty cycle and the target duty cycle determined based on the ideal frequency and the ideal pulse width is calculated to obtain the duty cycle error.

[0104] Step S124e: Based on the relative frequency error, relative pulse width error, and duty cycle error of each second candidate combination, determine the second candidate combination that meets the target conditions.

[0105] In this embodiment, after obtaining the relative frequency error, relative pulse width error, and duty cycle error, a second candidate combination that meets the target condition can be determined based on the relative frequency error, relative pulse width error, and duty cycle error of each second candidate combination. That is, the target condition is related to the relative frequency error, the relative pulse width error, and the duty cycle error; that is, the corresponding errors satisfy the conditions set according to the accuracy requirements. For example, a weighted sum of the relative frequency error, the relative pulse width error, and the duty cycle error can be calculated to obtain the comprehensive error. Alternatively, based on the relative frequency error, the relative pulse width error, and the duty cycle error, the period jitter of the sampling clock source, the total lock time of the clock link, and the amplitude flatness error of the analog link can be further integrated to obtain the comprehensive error. Thus, the second candidate combination with the smallest comprehensive error can be selected as the second candidate combination that meets the target condition.

[0106] Step S124f: Based on the actual frequency corresponding to the second candidate combination that meets the target conditions, the second candidate frequency division coefficient, the number of second candidate pulse width points, and the number of second candidate period points, determine the target frequency, target frequency division coefficient, target number of pulse width points, and target number of period points.

[0107] In this embodiment of the application, after determining the second candidate combination that meets the target conditions, the target frequency, target frequency division coefficient, target pulse width point and target period point can be determined based on the actual frequency corresponding to the second candidate combination that meets the target conditions, the second candidate frequency division coefficient, the corresponding second candidate pulse width point and the second candidate period point.

[0108] This application also provides a frequency and pulse width joint control unit, which can be used to execute the above-described frequency and pulse width joint control method to determine the target frequency, target frequency division coefficient, target pulse width points, and target period points of the target pulse signal to be generated. In some embodiments, the frequency and pulse width joint control unit may include a processor and a memory. The processor can be used to execute a computer program in the memory to obtain an ideal frequency and an ideal pulse width, and under the joint constraints of the ideal frequency and the ideal pulse width, determine the target frequency, target frequency division coefficient, target pulse width points, and target period points, respectively.

[0109] Combination Figure 4 This application also provides a pulse signal generation device, which may include a frequency and pulse width joint control unit, a clock frequency synthesizer and a field-programmable gate array, wherein the field-programmable gate array may include a phase-locked loop and a core pulse generation unit.

[0110] In detail, the frequency and pulse width joint control unit can be used to execute the above-described frequency and pulse width joint control method to determine the target frequency, target frequency division coefficient, target pulse width points, and target period points of the target pulse signal to be generated. The clock frequency synthesizer can be used to generate a corresponding programmable clock signal based on the target frequency. The phase-locked loop in the field-programmable gate array can be used to perform frequency division processing on the programmable clock signal based on the target frequency division coefficient to obtain a reconstructed sampling clock signal. The kernel pulse generation unit in the field-programmable gate array can be used to generate a target digital pulse sequence based on the reconstructed sampling clock signal, the target pulse width points, and the target period points. The target digital pulse sequence is then processed by analog to form the target pulse signal.

[0111] It is understood that, in some embodiments, the pulse signal generating device may further include a digital-to-analog converter and an analog processing circuit. In this way, the digital-to-analog converter can be used to convert the target digital pulse sequence into an analog signal, and the analog processing circuit can be used to amplify, attenuate, and / or filter the analog signal to form the target pulse signal.

[0112] It is understood that the specific method by which the nuclear pulse generation unit generates the target digital pulse sequence based on the reconstructed sampling clock signal, the target pulse width points, and the target period points is not limited and can be selected and configured according to actual needs.

[0113] For example, in an alternative implementation, the nuclear pulse generation unit receives parameters written by the frequency and pulse width joint control unit via a bus interface and stores them in a set of registers, the mapping relationship of which is shown in the table below:

[0114] Wherein, the number of period points N = HighLen + LowLen. By independently setting the number of high and low level points (HighLen, LowLen) and the corresponding output code values ​​(HighValue, LowValue), rectangular pulses with arbitrary duty cycles can be flexibly generated, and the pulse polarity can be defined by configuring the high and low level code values. In addition, n and m refer to the most significant bit numbers of the corresponding registers.

[0115] Alternatively, in an alternative implementation, the FPGA internally uses a free-running synchronous counter, sample_cnt, which operates on a pulse refresh clock (typically synchronized with the DAC sampling clock). Incrementing on each rising edge of (from the same source) when sample_cnt reaches N. At time 1, it returns to zero in the next clock cycle, thus forming a cycle with a period of N clock cycles.

[0116] To generate a pulse, the current counting position needs to be compared with the high-level length. Considering phase shift, first, the phase-adjusted position pos is calculated: ; in, This refers to the position of the synchronous counter within one pulse cycle at the current moment. It refers to the amount of phase shift. This refers to the modulo operation, used to convert... Mapped to the range [0, N-1].

[0117] The output logic is: when When, output Corresponding code value; otherwise output The corresponding code value. That is, the counter inside the FPGA counts in each sampling clock cycle. When the count value is less than the number of pulse width points, the DAC is controlled to output the corresponding high-level code value; when the count value is greater than or equal to the number of pulse width points but less than the number of cycle points, a low-level code value is output.

[0118] To ensure timing convergence at high sampling clock frequencies, the comparison and output logic described above is typically implemented using a pipelined architecture. For example, the first stage latches the counter and register values, the second stage calculates and compares the output (pos), and the third stage stores the final DAC output data. This pipelined design ensures timing convergence at higher sampling clock frequencies. This helps maintain stable output timing under reconfigurable sampling clocks. The output data is strictly synchronized with the clock and sent to the DAC.

[0119] Alternatively, in an alternative implementation, for multi-channel output, each channel has an independent phase offset register (PhaseOffset), but multiple channels share the same time base. This mechanism uses the same global counter, sample_cnt. Each channel calculates its own pos based on its own PhaseOffset, thus generating a synchronization pulse with a fixed phase difference. This mechanism leverages the deterministic nature of digital synchronization to help overcome the effects of inconsistencies in delays between analog channels. This provides a synchronization basis for multi-channel test scenarios requiring strict timing relationships. It is suitable for multi-channel test scenarios requiring strict timing relationships.

[0120] Alternatively, in an alternative implementation, the FPGA can integrate a DDS phase accumulator or a waveform RAM lookup table unit to generate arbitrary waveforms such as exponential, double-exponential, and sine waves. The core pulse generation unit and the outputs of these waveform generation units are connected to the DAC data input via a multiplexer. This multiplexing structure allows the same high-precision reconfigurable time base and DAC analog link to serve multiple core pulse waveform outputs, improving the device's versatility and cost-effectiveness. Waveform switching can be configured via a shadow register and performed at the synchronization commit point.

[0121] Alternatively, in an alternative implementation, for the time base reconfiguration mechanism of the clock frequency synthesizer and the PLL in the FPGA, the physical implementation of the reconfigurable sampling time base depends on the coordinated operation of the clock frequency synthesizer and the PLL inside the FPGA.

[0122] In an alternative implementation, a clock frequency synthesizer supporting high-resolution fractional division can be used. This synthesizer receives configuration from the frequency and pulse width control unit via a serial interface and can output a programmable clock signal with a frequency range of kHz to hundreds of MHz and a resolution up to 1 Hz. This clock frequency synthesizer not only provides a reference clock source, but also serves as the first-stage execution unit for "time base reconstruction." Its output frequency... It is one of the direct output targets of the joint solution algorithm, which means that its operating frequency is dynamically adjusted according to the needs of the nuclear pulse, rather than being fixed.

[0123] In an alternative implementation, the PLL inside the FPGA receives the clock output from the clock frequency synthesizer. As its reference input, the frequency and pulse width joint control unit configures the multiplication / division coefficients of the PLL based on the solution results. In a typical embodiment, the PLL is configured in integer division mode, that is, the output clock is divided by 1 / Q (Q is a positive integer) of the input clock. Therefore, the output clock of the PLL is the final DAC sampling clock. = / Q. PLL can also generate with Other clocks of the same origin but with adjustable phase are used for internal logic synchronization within the FPGA.

[0124] This two-level architecture of "external frequency synthesizer + FPGA PLL" constitutes a flexible, reconfigurable time base generation link. Its technical advantage lies in achieving this through joint adjustment. Q and Q can generate the required sampling clock over a wide continuous frequency range. This breaks through the limitations of a single fixed clock or the limited input range of the PLL inside the FPGA, providing ample hardware implementation space for the joint solution algorithm.

[0125] In an alternative implementation, when the ideal sampling clock frequency obtained by joint solution is lower than the lower limit of the reference input frequency of the phase-locked loop (PLL) in the field-programmable gate array (FPGA), the target frequency division factor is greater than 1. The PLL then performs frequency division processing on the programmable clock signal to reduce it to near the ideal sampling clock frequency. For example, if the lower limit of the PLL's reference input frequency is 19MHz, the target frequency is 500kHz, and the target pulse width is 400ns, then the ideal sampling clock frequency is 5MHz (10 period points, 2 pulse width points, with no quantization error in both frequency and pulse width). Since this is lower than the lower limit, the clock frequency synthesizer is configured to output 20MHz, and the PLL frequency division factor is configured to 4, resulting in a 5MHz reconstructed sampling clock signal. Correspondingly, without frequency division, constrained by the lower limit of the reference input, the sampling clock must be increased to at least 19MHz, requiring 40 period points, a sampling clock of 20MHz, and 8 pulse width points to achieve the same zero quantization error (the number of period points and pulse width points are increased to four times). It can be seen that by using the two-stage time base reconstruction link, even when the sampling clock frequency is lower than the lower limit of the PLL reference input, it is still possible to generate a reconstructed sampling clock that meets the zero quantization error requirement of the target parameters with a lower sampling clock frequency and fewer period points and pulse width points, thus breaking through the limitations of a single frequency synthesizer and the lower limit of the PLL reference input.

[0126] The joint solution process for the above example is as follows: Based on the ideal frequency of 500kHz and the predetermined actual sampling clock range, determine the range of candidate period points, and take one candidate period point N=10 to determine the corresponding ideal sampling clock frequency. =N· =5MHz; determine the candidate frequency division coefficient range, and based on the candidate frequency division coefficient range and the number of candidate period points, form multiple second candidate combinations (N,Q); for each second candidate combination, based on the frequency division coefficients included in the combination and the ideal sampling clock frequency corresponding to the number of period points included in the combination, determine the ideal synthesizer frequency corresponding to the combination. =Q·f s For example, Q=1, 2, 3, and 4 correspond to 5MHz, 10MHz, 15MHz, and 20MHz, respectively. The synthesizer output frequency corresponding to Q=1, 2, and 3 is lower than the lower limit of the PLL's reference input frequency of 19MHz, thus failing to meet the hardware constraint and being filtered out. The synthesizer output frequency of 20MHz corresponding to Q=4 is within the reference input frequency range of the PLL and the output frequency range of the clock frequency synthesizer. Based on the synthesizer output frequency of 20MHz corresponding to Q=4 and the division factor of 4, the candidate sampling clock frequency is determined. =20MHz / 4=5MHz; Based on the candidate sampling clock frequency and the number of candidate period points, determine the actual output frequency f.out =5MHz / 10=500kHz, relative frequency error is zero; based on this candidate sampling clock frequency and ideal pulse width 400ns, the number of candidate pulse width points is determined as M=round(400ns×5MHz)=2, and the actual output pulse width W is determined. out =2 / 5MHz=400ns, relative pulse width error is zero; and, to verify the feasibility of the phase-locked loop: with a reference input of 20MHz multiplied to VCO=600MHz and an output frequency division coefficient C=600MHz / 5MHz=120, both are within the VCO frequency range and output frequency division range of the phase-locked loop. Therefore, the target frequency is determined to be 20MHz, the target frequency division coefficient is 4, the target pulse width points are 2, and the target period points are 10.

[0127] The phase-locked loop (PLL) frequency division plays a role in the scenario as follows: (i) When the required sampling clock frequency is lower than the lower limit of the reference input frequency of the PLL (or the lowest programmable output frequency of the clock frequency synthesizer, whichever is higher), the clock frequency synthesizer outputs a programmable clock signal that is not lower than the lower limit, and the required sampling clock is obtained by frequency division by the PLL; (ii) Frequency division refines the absolute frequency step of the reconstructed sampling clock signal, so that the sampling clock frequency that cannot be directly hit by the clock frequency synthesizer can be accurately obtained; (iii) The PLL can generate a clock that is of the same origin as the reconstructed sampling clock signal and has an adjustable phase, for multi-channel synchronization.

[0128] Alternatively, in an alternative implementation, to meet the output requirements of a large dynamic range and high precision of the nuclear pulse amplitude, a systematic amplitude control scheme combining digital code values, analog ranges, and software compensation can be adopted.

[0129] Specifically, the HighValue and LowValue outputs from the FPGA are digital code values ​​directly written into the DAC. For a 14-bit DAC, the code value range is typically 0~16383, with a median of around 8192. For positive polarity pulses, the high-level code value is greater than the median, and the low-level value is equal to the median; the opposite is true for negative polarity pulses.

[0130] Alternatively, in an alternative implementation, the analog processing circuitry includes multiple programmable gain / attenuation links, such as: attenuation level (x0.1), no gain level (x1), 5x amplification level (x5), and 10x amplification level (x10). A frequency and pulse width joint control unit automatically selects the appropriate level based on the target amplitude to ensure the DAC operates in the region of optimal linearity and covers an output range from millivolts to tens of volts. Level switching can be achieved via FPGA control of analog switches, relays, or programmable gain amplifiers.

[0131] Alternatively, in an alternative implementation, due to gain errors and zero drift in devices such as DACs and operational amplifiers, a set of KB calibration parameters is stored for each channel and each analog range: ; Among them, A set The amplitude is set (calculated based on DAC code value and gear theory). The actual measured amplitude is represented by K, which is the gain calibration coefficient, and B, which is the offset calibration coefficient. After calibration, the control software performs an inverse calculation based on the target amplitude A. target Calculate the required setting value A set =(A target B) / K, then converted to DAC code value. This eliminates systematic errors caused by the inherent bias of analog devices.

[0132] In an alternative implementation, the amplitude response of the nuclear pulse output link may vary with signal frequency, pulse width, output level, and load impedance. Based on this, a multi-dimensional calibration compensation table is established. This table is created through precise measurements during factory or periodic calibration and stores the amplitude compensation coefficients C(f, W, gear, load) under different combinations of dimensions.

[0133]

[0134] During operation, the frequency and pulse width joint control unit determines the corresponding compensation coefficient C based on the current actual output frequency f, pulse width W, gear setting, and load impedance through table lookup or interpolation. The final code value written to the DAC is calculated using the following formula: Codedac=F(A,gear,K,B,C(f,W,gear,load)); Where F is the amplitude-to-code value conversion function that includes KB calibration, and it can be a linear function, which can be any relevant existing function. Additionally, A can refer to the desired setpoint A. set This calibration and compensation method systematically solves the complex problem of amplitude accuracy varying with signal time and load conditions, achieving high-precision end-to-end amplitude output over a wide range of parameters, thus meeting the stringent requirements of nuclear instrument calibration. Calibration parameters and compensation coefficients can be stored in non-volatile memory.

[0135] Alternatively, in an alternative implementation, to prevent abnormal pulse output when changing frequency, pulse width, amplitude, or clock configuration, a glitch-free switching process can be employed, such as... Figure 5 As shown.

[0136] Among them, through Figure 5The glitch-free switching procedure shown ensures that no abnormal pulses or voltage glitches are generated when switching output parameters. This procedure follows the principle of "silence first, preparation then synchronous switching." For example, its core steps are as follows: Entering safe mode: Upon receiving a new parameter command, the output enters the output protection mode, forcing the output to a safe intermediate level or shutting down the output to isolate the impact of subsequent internal operations on the output; Parallel preloading and hardware reconfiguration: Under the premise of output silence, two tasks are executed in parallel: (i) Parameter pre-calculation and temporary storage: New parameters (such as new clock configuration, number of period points, number of pulse width points, DAC code value, etc.) are calculated and written to the shadow parameter register without affecting the currently running active parameters; (ii) Dynamic reconfiguration of hardware links: The clock frequency synthesizer and the PLL in the FPGA are configured or selected in sequence to generate a new sampling clock. In addition, the stability of all clock links can be waited for by two judgment nodes: "Is the frequency synthesizer stable?" and "Is the PLL locked?". Analog link stabilization wait: After the digital clock stabilizes, it will check "Analog range and filter stabilization?" to ensure that the analog processing circuit (such as amplifier, attenuator, filter, etc.) has completed the switching and reached a stable working state; Synchronization triggers atomic commit: Once all new clocks and analog links are ready, a critical synchronization moment is awaited: "Reaching a cycle boundary or silent window?". This condition ensures that the switching action aligns with the natural cycle boundary of the current output pulse. When the moment arrives, a "one-time update of the working register" is performed, atomically and synchronously committing the shadow parameters to the active register. Subsequently, the output gating is released, and the target kernel pulse is immediately output based on a completely new, fully synchronized parameter set.

[0137] In other words, this process integrates the complex parameter switching process involving multiple hardware modules into a deterministic, glitch-free atomic operation through four major mechanisms: output protection, shadow register, hardware stable waiting, and period boundary synchronization. This fundamentally ensures the output security and signal integrity during dynamic parameter switching.

[0138] Alternatively, in an alternative implementation, when parameter switching is required, the frequency and pulse width joint control unit first activates "output gating." This operation forces the DAC's input data to a safe intermediate code value (such as the code value 8192 corresponding to zero), or directly disables the output enable of subsequent analog processing circuits. This ensures that no uncontrollable voltage jumps or half-cycle pulses occur at the output during internal parameter reconstruction.

[0139] Alternatively, in an alternative implementation, shadow registers are set within the FPGA for all runtime parameters (such as HighLen, LowLen, HighValue, LowValue, and waveform selection registers). The frequency and pulse width joint control unit can write the calculated new parameters into these shadow registers without affecting the currently active register. This achieves parameter preloading, decoupling parameter updates from output timing.

[0140] Alternatively, in an alternative implementation, the frequency and pulse width joint control unit configures the clock frequency synthesizer to a new frequency via I2C. Then, the frequency division factor Q of the PLL in the FPGA is reconfigured. After configuration, the frequency and pulse width joint control unit must wait for two key states: (i) the lock indicator of the clock frequency synthesizer (such as the Lock Detect signal) is valid, indicating that its output has stabilized; (ii) the lock signal of the PLL inside the FPGA is valid, indicating that the new sampling clock... Stable. This waiting mechanism avoids outputting while the clock is unlocked, thus eliminating output jitter or errors caused by clock instability.

[0141] Alternatively, in an alternative implementation, after all new clocks have stabilized, the frequency and pulse width joint control unit waits for a critical timing point: the end of the current pulse output cycle. That is, when the FPGA's internal counter `sample_cnt` reaches zero, a state machine automatically triggers a "commit" operation. At this moment, all contents of the shadow register are atomically and synchronously copied to the corresponding active register. Simultaneously, the output gating is deactivated.

[0142] Alternatively, in an alternative implementation, starting from the next clock cycle, the FPGA will generate pulses based on the new sampling clock, new cycle points, and pulse width points. Since the switching occurs at the cycle boundary and all relevant parameters take effect synchronously, this effectively prevents the generation of incomplete pulses, pulses with abnormal widths, or intermediate state glitches. For multi-channel applications, this synchronous submission mechanism also ensures that all channels switch to the new parameters at the same time, maintaining synchronization between channels.

[0143] In an alternative implementation, the solution provided in this application is primarily optimized for periodic rectangular nuclear pulses (or gated pulses with a defined threshold width). By extending the waveform generation unit of the FPGA, various waveforms common in nuclear detection fields can be supported: Trapezoidal pulse: can be achieved by controlling the number of rising edges, plateau periods, and falling edges, as well as the slope; Exponential decay pulse and double exponential pulse: Waveform data can be stored in the RAM lookup table inside the FPGA, read out by address under the sampling clock drive, and output through DAC. Its time base can also be driven by the reconfigurable clock of this technology to ensure the accuracy of waveform time parameters. Half-sine pulse: can be implemented as a lookup table for special waveforms; Random interval pulse sequence: can be used for dead time testing. Pulse intervals are generated by a pseudo-random algorithm, and the generation time of each pulse is controlled by the high-precision time base of this device.

[0144] This approach highlights the core advantage of the solution, which lies in the precise control of time parameters (period, pulse width, interval), while the waveform shape can be flexibly expanded through different data generation methods, enabling the device to maintain high time accuracy while also possessing good versatility.

[0145] In other words, by introducing the core concept of "reconfigurable sampling time base" and combining it with joint solution algorithms, system-level amplitude compensation, and glitch-free switching mechanisms, high-precision coordinated control and stable output of key parameters such as core pulse frequency, pulse width, and amplitude are achieved on a general-purpose hardware platform. This fundamentally solves the inherent technical defects of fixed sampling clock schemes, as detailed below: (i) Significantly reduce or even eliminate inherent quantization errors in frequency and pulse width: In traditional fixed-time-base schemes (such as 200MHz), the pulse width and period are forcibly mapped to a fixed 5ns time grid, resulting in unavoidable quantization errors. This scheme uses the sampling clock as an optimization variable driven by the target parameters, adaptively selecting the most suitable sampling period for each set of target parameters. This transforms the source of time parameter error from passive rounding of the fixed grid to optimal approximation of the target-driven adaptive grid. Under the hardware constraints of an external frequency synthesizer output of 0-200MHz and 1Hz resolution, and a PLL in the FPGA with a frequency divider of 1, the theoretical derivation is performed using a 1MHz target frequency as an example: In frequency-priority mode, for integer nanosecond target pulse widths from 5ns to 995ns, the average absolute error of the pulse width can be reduced from approximately 1.2ns in the fixed-time-base scheme to approximately 0.031ns, with a median error of approximately 0.0155ns. Specifically, for a target pulse width of 7ns, the error decreased from 2ns (28.57%) to approximately 0.0070ns (0.10%), an improvement of approximately 286 times; for 47ns, the error decreased from 2ns (4.26%) to approximately 0.0201ns (0.043%), an improvement of approximately 99 times; and for 37.5ns, zero quantization error at the digital level can be achieved. Figure 6 As shown, Figure 6 The left side shows the target pulse output of 37.5ns with a fixed sampling clock. It can be seen that the actual output pulse width is 35ns or 40ns with a fixed 200MHz clock, with an error of 2.5ns. Figure 6 The right side shows the target pulse diagram for the reconfigurable sampling time base output of 37.5ns, which can achieve an accurate output of 37.5ns. Simultaneously, by prioritizing the search for... / f p (and Figure 6 In this context, fs and fp have the same meaning. Additionally, Figure 6 In this context, Tclk (referring to the sampling clock) is configured as an integer, which allows for zero error in the output cycle in many cases (e.g., ...). Figure 6 The target pulse width overlaps with the actual pulse width. This fundamentally solves the contradiction that the two parameters cannot be set accurately at the same time under a fixed time base, and meets the test scenarios in nuclear instrument calibration where both the count rate (frequency) and the discrimination threshold (pulse width) have high precision requirements.

[0146] (II) Achieving sub-nanosecond-level time parameter control accuracy with high cost-effectiveness: Traditional techniques require a significant increase in sampling clock frequency (e.g., to 1GHz to achieve 1ns steps) to reduce the fixed sampling period (e.g., 5ns). This necessitates the use of higher-speed DACs and FPGAs, and presents significant challenges in analog link design. This solution does not pursue an absolutely smaller fixed sampling period. Instead, it selects a sampling clock that minimizes the residual mapping of the target parameters through algorithms and secondary clock reconstruction. For example, to accurately generate a 1MHz / 37.5ns pulse, an 80MHz sampling clock (period of 12.5ns) can be selected. At this point, the number of pulse width points M=3, achieving an accurate output of 37.5ns. This means that by utilizing a DAC and FPGA platform in the hundreds of MHz range and through time base reconstruction in this solution, pulse width accuracy that traditional techniques might require GHz-level sampling rates can be achieved. This significantly reduces the dependence on the extreme performance of hardware and achieves higher time parameter accuracy at a given cost, demonstrating excellent cost-effectiveness.

[0147] (iii) Clear feasibility decisions and error information feedback: When ideal frequency and ideal pulse width cannot be precisely met simultaneously, traditional techniques typically implicitly round the output, leaving the user unaware of the actual error. This solution, through three operating modes—frequency-first, pulse width-first, and comprehensive optimization—along with a candidate solution scoring and screening process, empowers the device with decision-making capabilities. The frequency and pulse width joint control unit not only outputs the optimal achievable configuration but also simultaneously returns the actual output frequency, pulse width, and residual error relative to the ideal value. This allows testers to clearly understand the best possible output and its accuracy boundaries under current hardware limitations. Based on this error information, they can determine the validity of the test or adjust the test strategy, thus improving the reliability and authority of the entire verification process.

[0148] (iv) Achieve high-quality amplitude output and overcome analog link errors: By combining "DAC digital code value + automatic analog amplification / attenuation range selection + KB linear calibration + multi-dimensional calibration and compensation table for frequency / pulse width / range / load," the system systematically corrects the end-to-end error from digital setting to analog output. KB linear calibration eliminates inherent gain and offset errors of the devices; the multi-range design ensures the DAC operates in its optimal linear region, covering a wide amplitude range from mV to tens of V; and the compensation based on the multi-dimensional calibration table specifically addresses the challenge of analog link amplitude response varying with signal frequency and pulse width, a problem that simple DAC code value control cannot solve. Through this system-level amplitude compensation, this solution maintains high accuracy and consistency of end-to-end amplitude output under different time parameters and load conditions, meeting the stringent requirements of nuclear instruments for precise signal amplitude calibration.

[0149] (v) No glitches or abnormal pulse output during parameter switching: In fields such as nuclear power and nuclear measurement, voltage spikes or abnormally large pulses generated during parameter switching may cause malfunctions or damage to the equipment under test. This solution ensures that the switching of all key parameters (clock, point count, code value, waveform) occurs synchronously at the end of a complete cycle of an output pulse through a complete process of "output gating (security code) → shadow register preloading → clock reconfiguration and lockout waiting → cycle boundary synchronous submission". This eliminates half-cycle pulses, pulse width distortion, or intermediate state spikes caused by asynchronous parameter updates, making the output clean and stable before and after switching, which greatly improves the reliability and safety in dynamic applications such as automated testing and parameter scanning.

[0150] (vi) High-precision multi-channel synchronization and phase offset control: By leveraging the homogeneity of the reconfigurable time base and the determinism of the digital counter within the FPGA, a precise synchronization mechanism is provided for multi-channel output. Each channel shares the same high-precision sampling clock and global counter, and the relative delay between channels is set only through an independent digital phase offset register. This method overcomes the drawback of inconsistent delays between analog channels and can achieve nanosecond-level precision, repeatable programmable multi-channel synchronous or phase difference output. This is crucial for nuclear pulse test scenarios that require strict synchronous triggering of multiple channels or simulation of specific spatial distributions.

[0151] (vii) Good waveform scalability: Precise control of signal timing parameters can be easily extended to other waveforms. Based on the same set of reconfigurable sampling time base, DAC and analog link, by adding a waveform lookup table or DDS kernel inside the FPGA, various typical nuclear detector waveforms such as exponential, double exponential, trapezoidal and half sine can be generated while maintaining high time base accuracy. This maximizes the reuse of the hardware platform, making the device not only a high-precision rectangular pulse generator, but also a general-purpose, high-precision nuclear signal simulation source, thus expanding its application range and value.

[0152] In summary, the frequency and pulse width joint control method, unit, and pulse signal generation device provided in this application relate to the field of signal processing technology. In this application, firstly, an ideal frequency and an ideal pulse width are obtained; secondly, under the joint constraints of the ideal frequency and ideal pulse width, a target frequency, a target frequency division coefficient, a target pulse width point count, and a target period point count are determined respectively. The target frequency is used to generate a programmable clock signal, the target frequency division coefficient is used to perform frequency division processing on the programmable clock signal to obtain a reconstructed sampling clock signal, the reconstructed sampling clock signal, the target pulse width point count, and the target period point count are used to generate a target digital pulse sequence, and the target digital pulse sequence is used to undergo analog processing to form a target pulse signal whose frequency and pulse width match the ideal frequency and ideal pulse width. Based on the above, on the one hand, since the target digital pulse sequence is formed based on the reconstructed sampling clock signal, and the reconstructed sampling clock signal is generated based on the target frequency and target division coefficient determined under the joint constraints of ideal frequency and ideal pulse width, it can improve the matching degree between the reconstructed sampling clock signal and the actual clock requirements to a certain extent. This makes it easier to match the actual clock requirements in terms of clock frequency compared to the scheme that uses the inherent high-frequency sampling clock frequency in the existing technology. On the other hand, since the determination of the target frequency, target division coefficient, target pulse width points and target period points is based on the joint constraints of ideal frequency and ideal pulse width, it is easier to achieve the high comprehensive accuracy requirements of frequency and pulse width. In other words, in the process of pulse signal generation, by determining the parameters with relatively higher accuracy (i.e., target frequency, target division coefficient, target pulse width points and target period points), higher precision control can be achieved.

[0153] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A method for joint frequency and pulse width control, characterized in that, include: Obtain the ideal frequency and ideal pulse width; Under the joint constraints of the ideal frequency and the ideal pulse width, the target frequency, target frequency division coefficient, target pulse width points, and target period points are determined respectively. The target frequency is used to generate a programmable clock signal, the target frequency division coefficient is used to divide the programmable clock signal to obtain a reconstructed sampling clock signal, the reconstructed sampling clock signal, the target pulse width points, and the target period points are used to generate a target digital pulse sequence, and the target digital pulse sequence is used to undergo analog processing to form a target pulse signal whose frequency and pulse width match the ideal frequency and the ideal pulse width.

2. The frequency and pulse width joint control method according to claim 1, characterized in that, The steps of determining the target frequency, target frequency division coefficient, target pulse width points, and target period points under the joint constraints of the ideal frequency and the ideal pulse width include: Based on the combined frequency-pulse-width error corresponding to the ideal frequency and the ideal pulse width, and / or the duty cycle error corresponding to the target duty cycle determined based on the ideal frequency and the ideal pulse width, the target frequency, target frequency division coefficient, target pulse width points, and target period points are determined respectively.

3. The frequency and pulse width joint control method according to claim 2, characterized in that, The step of determining the target frequency, target frequency division coefficient, target pulse width points, and target period points based on the joint error of frequency and pulse width corresponding to the ideal frequency and the ideal pulse width, and / or the duty cycle error corresponding to the target duty cycle determined based on the ideal frequency and the ideal pulse width, respectively, includes: Based on the ideal frequency and the ideal pulse width, the target duty cycle is determined, and multiple first candidate combinations are determined. Each first candidate combination includes a first candidate pulse width point number and a first candidate cycle point number. Each first candidate pulse width point number is an integer, and each first candidate cycle point number is an integer. For each first candidate combination, the first candidate duty cycle corresponding to the first candidate combination is determined based on the number of first candidate pulse width points and the number of first candidate period points included in the first candidate combination. Based on the duty cycle error between the first candidate duty cycle and the target duty cycle for each first candidate combination, a first candidate combination that matches the target duty cycle is determined from the plurality of first candidate combinations, and the number of first candidate pulse width points and the number of first candidate cycle points included in the first candidate combination are determined as the target number of pulse width points and the target number of cycle points. Based on the number of first candidate period points included in the first candidate combination that matches the target duty cycle and the ideal frequency, the ideal sampling clock frequency is determined. Based on the ideal sampling clock frequency, the predetermined output frequency range and resolution, and the predetermined candidate frequency division coefficient range, the target frequency and target frequency division coefficient are determined.

4. The frequency and pulse width joint control method according to claim 2, characterized in that, The step of determining the target frequency, target frequency division coefficient, target pulse width points, and target period points based on the joint error of frequency and pulse width corresponding to the ideal frequency and the ideal pulse width, and / or the duty cycle error corresponding to the target duty cycle determined based on the ideal frequency and the ideal pulse width, respectively, includes: Based on the ideal frequency and the predetermined actual sampling clock range, a range of candidate period points is determined, wherein each second candidate period point in the range of candidate period points is an integer; The ideal sampling clock frequency corresponding to each of the second candidate period points is determined respectively; The candidate frequency division coefficient range is determined, and each second candidate combination is determined based on the candidate frequency division coefficient range and each second candidate period point, wherein each second candidate combination includes a second candidate frequency division coefficient belonging to the candidate frequency division coefficient range and a second candidate period point, and each second candidate frequency division coefficient is an integer; For each of the second candidate combinations, based on the ideal sampling clock frequency corresponding to the second candidate frequency division coefficient and the number of second candidate period points included in the second candidate combination, the ideal frequency of the synthesizer corresponding to the second candidate combination is determined. Furthermore, based on a predetermined output frequency range and resolution, the synthesizer output frequency that best matches the ideal frequency of the synthesizer is determined. Based on the synthesizer output frequency and the second candidate frequency division coefficient, the candidate sampling clock frequency is determined. Based on the candidate sampling clock frequency and the number of second candidate period points, the actual frequency corresponding to the second candidate combination is determined. Based on the actual frequency and the ideal frequency, the relative frequency error of the second candidate combination is determined. Based on the candidate sampling clock frequency and the ideal pulse width, the number of second candidate pulse width points corresponding to the second candidate combination is determined. Based on the number of second candidate pulse width points and the candidate sampling clock frequency, the actual pulse width corresponding to the second candidate combination is determined. Based on the actual pulse width and the ideal pulse width, the relative pulse width error of the second candidate combination is determined. Based on the relative frequency error and relative pulse width error of each second candidate combination, the second candidate combination that meets the target condition is determined. Based on the actual frequency corresponding to the second candidate combination that meets the target conditions, the second candidate frequency division coefficient, the number of second candidate pulse width points, and the number of second candidate period points, the target frequency, target frequency division coefficient, target number of pulse width points, and target number of period points are determined.

5. The frequency and pulse width joint control method according to claim 4, characterized in that, The step of determining the second candidate combination that satisfies the target condition based on the relative frequency error and relative pulse width error of each second candidate combination includes: A target screening mode is determined, wherein the target screening mode belongs to frequency priority mode, pulse width priority mode or frequency-pulse width combined mode. In the frequency priority mode, the relative frequency error is more important than the relative pulse width error. In the pulse width priority mode, the relative pulse width error is more important than the relative frequency error. Based on the relative frequency error and relative pulse width error of each second candidate combination, second candidate combinations that meet the target conditions of the target selection mode are determined according to the target selection mode.

6. The frequency and pulse width joint control method according to claim 5, characterized in that, The step of determining the second candidate combination that meets the target conditions of the target screening mode based on the relative frequency error and relative pulse width error of each second candidate combination, according to the target screening mode, includes: When the target screening mode is a frequency priority mode, each second candidate combination with a relative frequency error less than the frequency error threshold is determined, and among each second candidate combination with a relative frequency error less than the frequency error threshold, the second candidate combination with the smallest relative pulse width error is determined, and this second candidate combination is determined as the second candidate combination that satisfies the target condition. When the target screening mode is a pulse width priority mode, each second candidate combination with a relative pulse width error less than the pulse width error threshold is determined, and among each second candidate combination with a relative pulse width error less than the pulse width error threshold, the second candidate combination with the smallest relative frequency error is determined, and this second candidate combination is determined as the second candidate combination that satisfies the target condition. When the target screening mode belongs to the frequency pulse width synthesis mode, the frequency pulse width synthesis error corresponding to each second candidate combination is determined based on the relative frequency error and relative pulse width error of each second candidate combination, and the second candidate combination with the smallest frequency pulse width synthesis error is determined as the second candidate combination that satisfies the target condition.

7. The frequency and pulse width joint control method according to claim 6, characterized in that, When the target screening mode belongs to the frequency pulse width synthesis mode, the steps of determining the frequency pulse width synthesis error corresponding to each second candidate combination based on the relative frequency error and relative pulse width error of each second candidate combination, and determining the second candidate combination with the smallest frequency pulse width synthesis error as the second candidate combination that satisfies the target condition, include: When the target screening mode belongs to the frequency pulse width synthesis mode, for each second candidate combination, the frequency pulse width synthesis error corresponding to the second candidate combination is obtained by weighted summation based on the relative frequency error and relative pulse width error of the candidate combination, combined with the period jitter of the sampling clock source, the total lock time of the clock link, the amplitude flatness error of the analog link. The second candidate combination with the smallest corresponding frequency pulse width synthesis error is determined as the second candidate combination that satisfies the target condition.

8. The frequency and pulse width joint control method according to claim 2, characterized in that, The step of determining the target frequency, target frequency division coefficient, target pulse width points, and target period points based on the joint error of frequency and pulse width corresponding to the ideal frequency and the ideal pulse width, and / or the duty cycle error corresponding to the target duty cycle determined based on the ideal frequency and the ideal pulse width, respectively, includes: Based on the ideal frequency and the ideal pulse width, the target duty cycle is determined, and multiple first candidate combinations are determined. Each first candidate combination includes a first candidate pulse width point number and a first candidate cycle point number. Each first candidate pulse width point number is an integer, and each first candidate cycle point number is an integer. For each first candidate combination, the first candidate duty cycle corresponding to the first candidate combination is determined based on the number of first candidate pulse width points and the number of first candidate period points included in the first candidate combination. Based on the duty cycle error between the first candidate duty cycle corresponding to each first candidate combination and the target duty cycle, a plurality of first candidate combinations that match the target duty cycle are determined from the plurality of first candidate combinations; For each of the multiple first candidate combinations that match the target duty cycle, the corresponding ideal sampling clock frequency is determined based on the number of first candidate period points in the first candidate combination. The number of first candidate period points is used as the number of third candidate period points to be combined with each third candidate frequency division coefficient in the predetermined range of candidate frequency division coefficients to form each third candidate combination. For each of the third candidate combinations, based on the ideal sampling clock frequency corresponding to the third candidate frequency division coefficient and the number of third candidate period points included in the third candidate combination, the ideal frequency of the synthesizer corresponding to the third candidate combination is determined. Furthermore, based on a predetermined output frequency range and resolution, the synthesizer output frequency that best matches the ideal frequency of the synthesizer is determined. Based on the synthesizer output frequency and the third candidate frequency division coefficient, the candidate sampling clock frequency is determined. Based on the candidate sampling clock frequency and the number of third candidate period points, the actual frequency corresponding to the third candidate combination is determined. Based on the actual frequency and the ideal frequency, the relative frequency error of the third candidate combination is determined. Based on the candidate sampling clock frequency and the ideal pulse width, the number of third candidate pulse width points corresponding to the third candidate combination is determined. Based on the number of third candidate pulse width points and the candidate sampling clock frequency, the actual pulse width corresponding to the third candidate combination is determined. Finally, based on the actual pulse width and the ideal pulse width, the relative pulse width error of the third candidate combination is determined. Based on the relative frequency error and relative pulse width error of each of the third candidate combinations, a third candidate combination that meets the target condition is determined. Based on the actual frequency corresponding to the third candidate combination that meets the target conditions, the included third candidate frequency division coefficient, the corresponding number of third candidate pulse width points, and the included third candidate period points, the target frequency, target frequency division coefficient, target number of pulse width points, and target number of period points are determined.

9. A frequency and pulse width combined control unit, characterized in that, The method is used to execute the frequency and pulse width joint control method according to any one of claims 1-8, so as to determine the target frequency, target frequency division coefficient, target pulse width points and target period points of the target pulse signal to be generated.

10. A pulse signal generating device, characterized in that, The pulse signal generating device includes: The frequency and pulse width joint control unit of claim 9 is used to execute the frequency and pulse width joint control method to determine the target frequency, target frequency division coefficient, target pulse width points and target period points of the target pulse signal to be generated; A clock frequency synthesizer is used to generate a corresponding programmable clock signal based on the target frequency; The phase-locked loop in the field-programmable gate array is used to perform frequency division processing on the programmable clock signal based on the target frequency division coefficient to obtain a reconstructed sampling clock signal; The kernel pulse generation unit in the field-programmable gate array is used to generate a target digital pulse sequence based on the reconstructed sampling clock signal, the target pulse width points, and the target period points. The target digital pulse sequence is then processed by analog to form the target pulse signal.

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