Tri-state detection circuit and method

Abstract

This invention discloses a three-state detection circuit and method, belonging to the field of electronic circuit control technology. The three-state detection circuit includes a POR detection module that detects the input voltage and outputs a detection signal to a voltage comparator for comparison to obtain a POR signal; a USID acceleration module that provides an initial potential to the USID port to accelerate voltage establishment; a USID detection module that detects the USID port and outputs a USID detection signal to a current comparison unit to obtain the corresponding USID status signal; and a current reference module that provides bias current to the POR detection module and the current comparison unit. The POR signal controls the operating states of the USID acceleration module, the USID detection module, and the current reference module. This not only achieves a high degree of integration between POR and USID functions but also utilizes the POR signal to accelerate the processing of the USID port, meeting system timing requirements.

Description

Technical Field

[0001] This invention relates to the field of electronic circuit control technology, and in particular to a three-state detection circuit and method. Background Technology

[0002] The USID (Unique Slave ID) in a chip is an address identifier used to uniquely identify a device. It is widely used in MIPI RFFE (RF Front-End) interface communication, especially playing a crucial role in RF front-end modules (such as antenna tuners, RF switches, and power amplifiers). When multiple slave devices share the same bus (such as the MIPI RFFE bus), the USID is used to distinguish different chips or functional modules. By setting different USIDs, the master device can independently access each slave device, avoiding communication conflicts.

[0003] POR (Power-On Reset) is a crucial protection mechanism in a chip. Its core function is to provide a digital reset signal when the power is on, resetting each node within the chip to ensure that the chip starts operating from a deterministic and safe state, preventing system abnormalities caused by power instability or initialization errors.

[0004] In the 5G era, the timing design of the USID and POR ports of power amplifier (PA) chips is crucial for achieving high-speed, high-reliability communication. It requires the USID and POR signal timing to coordinate with power management and system clocks to meet the stringent latency, synchronization accuracy, and reliability requirements of 5G networks. Meanwhile, to reduce chip heat dissipation and extend battery life, standby power consumption has become one of the chip's key performance indicators.

[0005] Currently, among the existing three-state detection technologies, the voltage establishment methods for the high-impedance state of the USID port include resistor voltage division, diode-connected transistor voltage division, and current mirror voltage division. When the USID port is floating, the reference voltage of the USID port is determined by a voltage divider circuit. When the USID port has a large parasitic capacitance, the establishment time of the reference voltage increases.

[0006] It should be noted that the information disclosed in the background section of this invention is intended only to enhance the understanding of the general background of this invention, and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention

[0007] The purpose of this invention is to provide a three-state detection circuit and method to solve the problem that three-state detection circuits are difficult to balance setup speed and static power consumption.

[0008] To solve the above-mentioned technical problems, the present invention provides a three-state detection circuit and method, comprising:

[0009] The POR detection module is used to detect the input voltage, and outputs the detection signal to the voltage comparator for comparison to obtain the POR signal indicating the power-on status of the system.

[0010] The USID acceleration module is connected to the USID port at one end and is used to provide an initial potential to the USID port to accelerate voltage establishment.

[0011] The USID detection module is connected to the USID port at one end for detecting the USID port, and outputs the USID detection signal to the current comparison unit at the other end to obtain the corresponding USID status signal.

[0012] A current reference module is used to provide bias current to the POR detection module and the current comparison unit; wherein, the POR signal controls the operating state of the USID acceleration module, the USID detection module and the current reference module.

[0013] Optionally, it also includes a latching module, which receives the POR signal and the USID status signal and latches and outputs a POR latching signal and a status latching signal. The POR latching signal controls the USID acceleration module to shut down after the system power is established. The latching module also outputs an enable signal at the enable terminal based on the POR signal to control the USID detection module and the current reference module to shut down after a predetermined time after the system power is established.

[0014] Optionally, the USID acceleration module includes a second resistor, a third resistor, a second control switch, and a third control switch. The first end of the second resistor is connected to the input voltage, and the second end is connected to the first end of the second control switch. The second end of the second control switch is connected to the USID port and the first end of the third control switch. The first end of the third resistor is connected to the second end of the third control switch, and the second end is grounded. The control terminals of both the second and third control switches are connected to the POR latch signal.

[0015] Optionally, the USID detection module includes pull-up resistors and pull-down resistors for performing voltage divider detection on the USID port, wherein the resistance values ​​of the pull-up resistors and the pull-down resistors are both greater than the resistance values ​​of the second resistor and the third resistor, in order to ensure the accuracy of voltage divider detection when the driving capability of the USID port is weak or parasitic resistance exists.

[0016] Optionally, the USID acceleration module includes a 21st MOS transistor, a 22nd MOS transistor, a second control switch, and a third control switch. The input terminal of the 21st MOS transistor is connected to the input voltage, and its output terminal is connected to the first terminal of the second control switch. The second terminal of the second control switch is connected to the USID port and the first terminal of the third control switch. The input terminal of the 22nd MOS transistor is connected to the second terminal of the third control switch, and its output terminal is grounded. The control terminals of both the 21st and 22nd MOS transistors are connected to the current reference module to obtain the corresponding bias current. The control terminals of both the second and third control switches are connected to the POR latch signal.

[0017] Optionally, the USID detection module includes a fourth resistor, a fifth resistor, a fourth control switch, and a fifth control switch. The first end of the fourth resistor is connected to the input voltage, and the second end is connected to the first end of the fourth control switch. The second end of the fourth control switch is connected to the USID port and the first end of the fifth control switch. The second end of the fourth control switch also outputs the USID detection signal. The first end of the fifth resistor is connected to the second end of the fifth control switch, and the second end is grounded.

[0018] Optionally, the USID detection module includes a nineteenth MOSFET, a twentieth MOSFET, a fourth control switch, and a fifth control switch. The input terminal of the nineteenth MOSFET is connected to the input voltage. The output terminal of the nineteenth MOSFET is connected to the control terminal and connected to the first terminal of the fourth control switch. The second terminal of the fourth control switch is connected to the USID port and the first terminal of the fifth control switch. The second terminal of the fifth control switch is connected to the control terminal of the twentieth MOSFET and the input terminal of the twentieth MOSFET. The output terminal of the twentieth MOSFET is grounded.

[0019] Optionally, the control terminals of the fourth control switch and the fifth control switch are both connected to the enable terminal of the latch module.

[0020] Optionally, it also includes an AND gate, wherein the first input terminal of the AND gate is connected to the enable terminal of the latch module, the second input terminal is connected to the POR latch signal, and the control terminals of the fourth control switch and the fifth control switch are both connected to the output terminal of the AND gate.

[0021] Optionally, the current reference module includes a startup circuit and a core circuit. The startup circuit is used to drive the current reference module away from the degenerate bias point when the input voltage is powered on, and automatically shuts down after startup. The output terminal of the startup circuit is connected to the bias terminal of the core circuit. The core circuit has a first control terminal and a second control terminal for outputting bias current. The enable terminal of the latch module is used to control the operating state of the startup circuit and the core circuit.

[0022] Optionally, the current reference module includes an initial MOSFET, a first MOSFET, a second MOSFET, a third MOSFET, a fourth MOSFET, a fifth MOSFET, a sixth MOSFET, an initial control switch, a first resistor, and a first control switch. The input terminals of the initial MOSFET, the third MOSFET, and the fourth MOSFET are all connected to the input voltage. The control terminal of the initial MOSFET is grounded. The output terminal of the initial MOSFET is connected to the input terminals of the first MOSFET and the control terminals of the second MOSFET. The output terminal of the third MOSFET, the control terminals of the third MOSFET and the fourth MOSFET, the first terminal of the initial control switch, and the input terminal of the fifth MOSFET are all connected to the input voltage. The first control terminal is connected to the first control terminal. The second terminal of the initial control switch is connected to the input terminal of the second MOS transistor. The output terminal of the fourth MOS transistor, the first terminal of the first resistor, the control terminal of the first MOS transistor, the control terminal of the sixth MOS transistor, and the first terminal of the first control switch are all connected to and connected to the second control terminal. The second terminal of the first resistor is connected to the control terminal of the fifth MOS transistor and the input terminal of the sixth MOS transistor. The output terminals of the second MOS transistor, the fifth MOS transistor, the first MOS transistor, the sixth MOS transistor, and the second terminal of the first control switch are all grounded. The control terminals of the initial control switch and the first control switch are both connected to the enable terminal of the latch module.

[0023] Optionally, the POR detection module includes an eleventh MOSFET, a twelfth MOSFET, an initial capacitor, and a sixth control switch. The control terminal of the eleventh MOSFET is connected to the first control terminal. The input terminal of the eleventh MOSFET is connected to the input voltage, and the output terminal is connected to the input terminal of the twelfth MOSFET. The output terminal of the twelfth MOSFET is connected to the control terminal of the twelfth MOSFET, the first terminal of the initial capacitor, and the first terminal of the sixth control switch to output the detection signal. The second terminal of the initial capacitor and the second terminal of the sixth control switch are grounded. The control terminal of the sixth control switch is connected to the enable terminal of the latch module.

[0024] Optionally, the voltage comparator is a Schmitt trigger.

[0025] Optionally, the voltage comparator includes a thirteenth MOSFET, a fourteenth MOSFET, a fifteenth MOSFET, a sixteenth MOSFET, a seventeenth MOSFET, an eighteenth MOSFET, a second inverter, a third inverter, and a fourth inverter. The control terminals of the thirteenth MOSFET, the fourteenth MOSFET, the sixteenth MOSFET, and the seventeenth MOSFET are all connected to and connected to the detection signal. The input terminals of the thirteenth MOSFET and the eighteenth MOSFET are connected to the input voltage. The output terminal of the thirteenth MOSFET, the input terminal of the fourteenth MOSFET, and the input terminal of the fifteenth MOSFET are all connected to the detection signal. The fourteenth MOS transistor is connected to the input of the sixteenth MOS transistor, the control terminal of the fifteenth MOS transistor, the control terminal of the eighteenth MOS transistor, and the input of the second inverter. The output of the sixteenth MOS transistor is connected to the output of the eighteenth MOS transistor and the input of the seventeenth MOS transistor. The outputs of the fifteenth MOS transistor and the seventeenth MOS transistor are both grounded. The output of the second inverter is connected to the input of the third inverter. The output of the third inverter is connected to the input of the fourth inverter. The output of the fourth inverter outputs the POR signal.

[0026] Optionally, the voltage comparator includes a fifth inverter and a sixth inverter. The input terminal of the fifth inverter is connected to the detection signal, the output terminal of the fifth inverter is connected to the input terminal of the sixth inverter, and the output terminal of the sixth inverter outputs the POR signal.

[0027] Optionally, the current comparison unit includes a first current comparator and a second current comparator. The USID status signal includes an initial status signal and a first status signal. The first current comparator includes a seventh MOSFET and an eighth MOSFET. The control terminal of the seventh MOSFET is connected to the first control terminal. The input terminal of the seventh MOSFET is connected to the input voltage. The input terminal of the eighth MOSFET is connected to the output terminal of the seventh MOSFET and outputs the initial status signal. The control terminal of the eighth MOSFET is connected to the USID detection signal, and its output terminal is grounded.

[0028] Optionally, the second current comparator includes a ninth MOSFET and a tenth MOSFET. The input terminal of the ninth MOSFET is connected to the input voltage, and its control terminal is connected to the USID detection signal. The input terminal of the tenth MOSFET and the output terminal of the ninth MOSFET are both connected to and output the first status signal. The control terminal of the tenth MOSFET is connected to the second control terminal, and its output terminal is grounded.

[0029] Optionally, the latch module includes a first delay, an SR latch, an initial TG transmission gate, a first TG transmission gate, a seventh control switch, an eighth control switch, a first D flip-flop, a second D flip-flop, a third D flip-flop, a first OR gate, a second OR gate, a third OR gate, a second delay, and a first inverter. The input terminal of the first delay, the data input terminal of the first D flip-flop, and the first input terminal of the first OR gate are all connected to the POR signal. The output terminal of the first delay is connected to the set terminal of the SR latch, and the reset terminal of the SR latch is grounded. The original code output terminal of the SR latch is connected to the clock input terminals of the first D flip-flop, the second D flip-flop, and the third D flip-flop, and the input terminal of the second delay. The output terminal of the second delay is connected to the input terminal of the first inverter. The output terminal of the first inverter outputs the enable signal. The second input of the first OR gate... The first OR gate is connected to the original code output of the first D flip-flop, and the first OR gate outputs the POR latch signal. The input of the first TG transmission gate is connected to the first state signal. The output of the first TG transmission gate is connected to the first terminal of the eighth control switch, the data input of the second D flip-flop, and the first input of the second OR gate. The second terminal of the eighth control switch is grounded. The second input of the second OR gate is connected to the original code output of the second D flip-flop, and the output of the second OR gate outputs the first state latch signal. The input of the initial TG transmission gate is connected to the initial state signal. The output of the initial TG transmission gate is connected to the first terminal of the seventh control switch, the data input of the third D flip-flop, and the first input of the third OR gate. The second terminal of the seventh control switch is grounded. The second terminal of the second OR gate is connected to the original code output of the third D flip-flop, and the output of the second OR gate outputs the initial state latch signal.

[0030] A three-state detection method, comprising:

[0031] After the system is powered on, the current reference module starts working, providing bias current to the POR detection module and the current comparison unit. At the same time, the USID acceleration module is turned on to quickly establish the initial potential of the USID port.

[0032] The input voltage is detected, and the output detection signal is compared with the voltage comparator to obtain the POR signal indicating the power-on status of the system.

[0033] After the system power is established, the USID port is detected and the USID detection signal is output to the current comparison unit to obtain the corresponding USID status signal.

[0034] After the system power supply is established, under the control of the POR signal, the detection of the USID port is stopped, and the USID acceleration module and the current reference module are turned off.

[0035] Optionally, after the system power is established, the USID acceleration module is turned off. After a first delay, the latching module is turned on to latch the USID status signal and the POR signal. After a second delay, the latching module outputs an enable signal at the enable terminal based on the POR signal and the USID status signal, which is used to turn off the current reference module and stop detecting the USID port after a predetermined time has elapsed since the system power was established, thereby reducing power consumption.

[0036] Optionally, the resistance of the USID acceleration module is less than that of the USID detection module, thereby enabling acceleration to form an initial potential; the USID detection module performs voltage division detection on the USID port through pull-up and pull-down resistors with resistance values ​​greater than the acceleration resistor in the USID acceleration module, thereby accurately reflecting the external connection status of the USID port.

[0037] The tri-state detection circuit provided by this invention includes: a POR detection module for detecting the input voltage and outputting a detection signal to a voltage comparator for comparison to obtain a POR signal indicating the system power-on status; a USID acceleration module, one end connected to the USID port, for providing an initial potential to the USID port to accelerate voltage establishment; a USID detection module, one end connected to the USID port, for detecting the USID port, and the other end outputting a USID detection signal to a current comparison unit to obtain a corresponding USID status signal; and a current reference module for providing bias current to the POR detection module and the current comparison unit. The POR signal controls the operating states of the USID acceleration module, the USID detection module, and the current reference module. The POR function is implemented using a common current source, achieving a high degree of integration between POR and USID functions. The output POR signal is used for system reset, ensuring the reliability of circuit startup after power-on. Furthermore, the POR signal is used to accelerate the USID port, enabling rapid establishment of a reference voltage even with a large capacitor or weak drive at the USID port, thus meeting system timing requirements. Under the control of the POR signal, the relevant functional modules can be shut down after the system power is established, which can achieve zero static power consumption. This function can reduce the difficulty of chip heat dissipation and extend the system battery life.

[0038] The three-state detection method and the three-state detection circuit provided by this invention belong to the same inventive concept. Therefore, the three-state detection method provided by this invention has at least all the advantages of the three-state detection circuit provided by this invention, which will not be repeated here. Attached Figure Description

[0039] Those skilled in the art will understand that the accompanying drawings are provided to better understand the invention and do not constitute any limitation on the scope of the invention. Wherein:

[0040] Figure 1 This is a circuit block diagram of an embodiment of the present invention;

[0041] Figure 2 This is a circuit block diagram of another embodiment of the present invention;

[0042] Figure 3 This is a data flow diagram of an embodiment of the present invention;

[0043] Figure 4 This is a circuit schematic diagram of an embodiment of the present invention;

[0044] Figure 5 This is a circuit schematic diagram of the latch module of the present invention;

[0045] Figure 6 This is the signal timing diagram of the latch module of the present invention when USID is low;

[0046] Figure 7 This is a circuit diagram of the voltage comparator of the present invention;

[0047] Figure 8 This is a timing diagram of the operation of each module in the three-state detection circuit after power-on;

[0048] Figure 9 This is another circuit schematic diagram of the USID acceleration module of the present invention;

[0049] Figure 10 This is another circuit schematic diagram of the USID detection module of the present invention;

[0050] Figure 11 This is another circuit diagram of the voltage comparator of the present invention;

[0051] Figure 12 This is a circuit diagram of yet another embodiment of the present invention;

[0052] Figure 13 yes Figure 12 Timing diagram of the corresponding modules in the circuit.

[0053] In the attached image:

[0054] 1-USID acceleration module; 2-USID detection module; 3-current reference module; 4-POR detection module; 5-voltage comparator; 6-first current comparator; 7-second current comparator; 8-latch module.

[0055] M0 - Initial MOSFET; M1 - First MOSFET; M2 - Second MOSFET; M3 - Third MOSFET; M4 - Fourth MOSFET; M5 - Fifth MOSFET; M6 - Sixth MOSFET; M7 - Seventh MOSFET; M8 - Eighth MOSFET; M9 - Ninth MOSFET; M10 - Tenth MOSFET; M11 - Eleventh MOSFET; M12 - Twelfth MOSFET; M13 - Thirteenth MOSFET; M14 - Fourteenth MOSFET; M15 - Fifteenth MOSFET; M16 - Sixteenth MOSFET; M17 - Seventeenth MOSFET; M18 - Eighteenth MOSFET; M19 - Nineteenth MOSFET; M20 - Twentieth MOSFET; M21 - Twenty-first MOSFET; M22 - Twenty-second MOSFET.

[0056] C0 - Initial capacitor; S0 - Initial control switch; S1 - First control switch; S2 - Second control switch; S3 - Third control switch; S4 - Fourth control switch; S5 - Fifth control switch; S6 - Sixth control switch; S7 - Seventh control switch; S8 - Eighth control switch; R1 - First resistor; R2 - Second resistor; R3 - Third resistor; R4 - Fourth resistor; R5 - Fifth resistor; D1 - First D flip-flop; D2 - Second D flip-flop; D3 - Third D flip-flop; Delay1 - First delay unit; Delay2 - Second delay unit; SR latch1 - SR latch; INV1 - First inverter; INV2 - Second inverter; INV3 - Third inverter; INV4 - Fourth inverter; INV5 - Fifth inverter; INV6 - Sixth inverter; TG0 - Initial TG transmission gate; TG1 - First TG transmission gate; AND - AND gate; OR1 - First OR gate; OR2 - Second OR gate; OR3 - Third OR gate. Detailed Implementation

[0057] To make the objectives, advantages, and features of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to facilitate and clarify the explanation of the embodiments of this invention. Furthermore, the structures shown in the drawings are often part of the actual structures. In particular, different figures may emphasize different aspects and may sometimes use different scales.

[0058] As used in this invention, the singular forms “a,” “an,” and “the” include plural objects; the term “or” is generally used to mean “and / or”; the term “a number” is generally used to mean “at least one”; and the term “at least two” is generally used to mean “two or more”. Furthermore, the terms “first,” “second,” and “third” are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as “first,” “second,” or “third” may explicitly or implicitly include one or at least two of that feature. “One end” and “the other end,” as well as “proximal end” and “distal end,” generally refer to two corresponding parts, including not only endpoints. The terms “installed,” “connected,” and “joined” should be interpreted broadly, for example, as a fixed connection, a detachable connection, or an integral part; a mechanical connection or an electrical connection; a direct connection or an indirect connection through an intermediate medium; or a connection within two elements or an interaction between two elements. Furthermore, as used in this invention, the phrase "one element is disposed on another element" generally only indicates that there is a connection, coupling, cooperation, or transmission relationship between the two elements, and the connection, coupling, cooperation, or transmission between the two elements can be direct or indirect through an intermediate element. It should not be construed as indicating or implying a spatial positional relationship between the two elements, i.e., one element can be located arbitrarily inside, outside, above, below, or to one side of the other element, unless otherwise explicitly stated. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0059] Research has found that the voltage establishment method of the USID port in the high impedance state is essentially to determine the reference voltage of the USID port through a voltage divider circuit. When the USID port has a large parasitic capacitance, the establishment time of the reference voltage increases. However, if the establishment speed is to be accelerated, conventional methods will increase the static power consumption.

[0060] Based on this, the core idea of ​​this invention is to implement the POR function using a common current source, achieving a high degree of integration between the POR and USID functions. The output POR signal is used for system reset, ensuring the reliability of circuit startup after power-on. Furthermore, the POR signal is used to accelerate the processing of the USID port, enabling the rapid establishment of a reference voltage even with a large capacitor or weak drive at the USID port, thus meeting system timing requirements. Simultaneously, the circuit incorporates a latching function, achieving zero static power consumption. This function reduces chip heat dissipation difficulty and extends system battery life.

[0061] For details, please refer to Figures 1-13 This is a schematic diagram of an embodiment of the present invention. Figure 1As shown, a three-state detection circuit includes:

[0062] POR detection module 4 is used to detect the input voltage VIO and output the detection signal POR_det to the voltage comparator 5 for comparison to obtain the POR signal POR indicating the power-on status of the system.

[0063] USID acceleration module 1, one end of which is connected to the USID port USID, is used to provide an initial potential to the USID port and accelerate voltage establishment;

[0064] USID detection module 2 has one end connected to the USID port USID for detecting the USID port, and the other end outputs the USID detection signal USID_det to the current comparison unit to obtain the corresponding USID status signal.

[0065] The current reference module 3 is used to provide bias current to the POR detection module 4 and the current comparison unit; wherein, the POR signal controls the working state of the USID acceleration module 1, the USID detection module 2 and the current reference module 3.

[0066] This disclosure provides a USID tri-state detection circuit with static power consumption integrated acceleration function. A current reference module 3 generates a bias current, which is provided to the POR detection module 4 and the current comparison unit. The POR detection module 4 detects the input voltage VIO and outputs a detection signal POR_det, which is then passed through a voltage comparator 5 to obtain the POR signal. The POR signal simultaneously controls the operating state of the USID acceleration module 1. The USID acceleration module 1, USID detection module 2, and current comparison unit are used for USID port status determination. During the initialization phase, the USID acceleration module 1 quickly provides an initial potential to the USID port. After the POR signal is established, it stops working, and the USID detection module 2 performs precise detection on the USID port, outputting the USID detection signal USID_det to the current comparison unit to obtain the USID status signal UID<1:0>.

[0067] Furthermore, the POR signal provided by the POR detection module 4 can acquire the current system power-up status. Therefore, the POR signal can control the on / off state of the USID acceleration module 1, USID detection module 2, and current reference module 3. Both the POR detection module 4 and the current comparison unit are driven by the bias current provided by the current reference module 3. The on / off state of the current reference module 3 directly affects the on / off state of the POR detection module 4 and the current comparison unit. The POR signal output by the POR detection module 4 can directly or indirectly control the operating state of the modules in the three-state detection circuit, achieving closed-loop feedback and enabling zero static power consumption. Specifically, after the system power is on, the POR signal obtained by the POR detection module 4 accelerates the voltage establishment of the USID acceleration module 1. After the system power is on, the POR signal controls the shutdown of the USID acceleration module 1, USID detection module 2, and current reference module 3, thereby controlling the shutdown of the POR detection module 4 and the current comparison unit. Additionally, the POR signal can control the immediate shutdown or the shutdown of the USID acceleration module 1, USID detection module 2, and current reference module 3 after a predetermined delay.

[0068] For example, the aforementioned core module can be paired with latch module 8 to achieve zero static power consumption. The latch module latches the stabilized UID signal and POR signal, and then shuts down the tri-state detection circuit, thereby achieving zero static power consumption. The latch module 8 receives the POR signal and the USID status signal and latches and outputs a POR latch signal POR_Latch and a status latch signal. The POR latch signal POR_Latch controls the USID acceleration module 1 to shut down immediately after the system power is established. The latch module 8 also outputs an enable signal EN at the enable terminal based on the POR signal to control the USID detection module 2 and the current reference module 3 to shut down after a predetermined period of time after the system power is established.

[0069] This solution achieves the following: Figure 2 As shown, the POR signal and USID status signal output from the voltage comparator 5 and the current comparator unit are fed into the latch module 8. The latch module 8 outputs the POR latch signal POR_Latch and the status latch signal UID_Latch<1:0>, indicating the system power-on status and the USID port status. After the system is operating stably, the USID detection module 2 and the current reference module 3 are shut down to achieve zero static power consumption. Under the control of the POR signal, the current reference module 3 is shut down, thus stopping the supply of bias current to the current comparator and the POR detection module 4.

[0070] In order to enable those skilled in the art to easily understand the three-state detection circuit and method in the embodiments of the present invention, the following will further describe the three-state detection circuit and method proposed in the present invention in conjunction with the circuit structure of each module in the circuit block diagram.

[0071] Example 1

[0072] Please refer to Figure 2 This embodiment provides a USID tri-state detection circuit with zero static power consumption and integrated acceleration function, including a USID acceleration module 1, a USID detection module 2, a voltage comparator 5, a current reference module 3, and a POR detection module 4. The USID acceleration module 1 accelerates the establishment time of the reference voltage when the USID port is in a high-impedance state. The USID detection module and comparator are used to determine the USID port state and output a USID state signal, i.e., a UID signal. The current reference module 3 provides bias current to the current comparison unit and the POR detection module 4. The POR detection module 4 is used for system power-on detection. Its output POR signal is used not only for system reset indication but also for processing indications of USID acceleration, USID detection, the current reference module 3, and the latch module 8. Under the control of the POR signal, when the current reference module 3 is turned off, it stops providing bias current to the current comparison unit and the POR detection module 4, thus turning off the current comparison unit and the POR detection module 4 and achieving zero static power consumption.

[0073] The current comparison unit includes a first current comparator 6 and a second current comparator 7, and the USID status signal UID<1:0> includes the initial status signal UID. <0> and the first state signal UID <1> The signal OUT0 output by the first current comparator 6 is also the initial state signal UID. <0> The signal OUT1 output by the second current comparator 7 is also the first state signal UID. <1> .

[0074] The current reference module 3 generates three bias currents: first, second, and third bias currents, which are provided to the POR detection module 4, the first current comparator 6, and the second current comparator 7. The POR detection module 4 detects the input voltage VIO and outputs a detection signal POR_det. After passing through the voltage comparator 5, the POR signal is obtained and input to the latch module 8. The POR signal also controls the working state of the USID acceleration module 1. The USID acceleration module 1, USID detection module 2, first current comparator 6, and second current comparator 7 are used for USID port status judgment. During the initialization phase, the USID acceleration module 1 quickly provides an initial potential to the USID port. After the POR signal is established, it stops working. The USID detection module 2 performs accurate detection on the USID port and outputs a detection signal USID_det to the first current comparator 6 and the second current comparator 7 to obtain the first output signal OUT1 and the initial output signal OUT0, which are then passed to the latch module 8. The latch module 8 outputs the POR latch signal POR_Latch and the status latch signal UID_Latch<1:0> to indicate the system power-on status and the USID port status. After the system is working stably, it shuts down the USID detection module 2 and the current reference module 3 to achieve zero static power consumption.

[0075] The current reference module 3 includes a startup circuit and a core circuit. The startup circuit drives the current reference module 3 away from the degenerate bias point when the input voltage is powered on, and automatically shuts down after startup. The output terminal of the startup circuit is connected to the bias terminal of the core circuit. The core circuit has a first control terminal and a second control terminal for outputting a bias current. The enable terminal of the latch module 8 is used to control the operating state of the startup circuit and the core circuit. The core circuit has at least one current mirror structure for outputting the bias current.

[0076] like Figure 4As shown, the current reference module 3 includes an initial MOSFET M0, a first MOSFET M1, a second MOSFET M2, a third MOSFET M3, a fourth MOSFET M4, a fifth MOSFET M5, a sixth MOSFET M6, an initial control switch S0, a first resistor R1, and a first control switch S1. The input terminals of the initial MOSFET M0, the third MOSFET M3, and the fourth MOSFET M4 are all connected to the input voltage VIO. The control terminal of the initial MOSFET M0 is grounded. The output terminal of the initial MOSFET M0 is connected to the input terminal of the first MOSFET M1 and the control terminal of the second MOSFET M2. The output terminal of the third MOSFET M3, the control terminal of the third MOSFET M3, the control terminal of the fourth MOSFET M4, the first terminal of the initial control switch S0, and the fifth MOSFET M6 are all connected to the input voltage VIO. The input terminals of the first control terminal are connected together and output to the first control terminal. The second terminal of the initial control switch S0 is connected to the input terminal of the second MOS transistor M2. The output terminal of the fourth MOS transistor M4, the first terminal of the first resistor R1, the control terminal of the first MOS transistor M1, the control terminal of the sixth MOS transistor M6, and the first terminal of the first control switch S1 are connected together and output to the second control terminal. The second terminal of the first resistor R1 is connected to the control terminal of the fifth MOS transistor M5 and the input terminal of the sixth MOS transistor M6. The output terminals of the second MOS transistor M2, the fifth MOS transistor M5, the first MOS transistor M1, the sixth MOS transistor M6, and the second terminal of the first control switch S1 are all grounded. The control terminals of the initial control switch S0 and the first control switch S1 are both connected to the enable terminal of the latch module 8.

[0077] The initial MOSFET M0, first MOSFET M1, and second MOSFET M2 form the startup circuit. The third MOSFET M3, fourth MOSFET M4, fifth MOSFET M5, sixth MOSFET M6, initial control switch S0, first resistor R1, and first control switch S1 constitute the core circuit. The first control terminal outputs the first bias current and the second bias current to the first current comparator 6 and the POR detection module 4, respectively. The initial MOSFET M0, third MOSFET M3, and fourth MOSFET M4 are PMOS transistors, while the first MOSFET M1, second MOSFET M2, fifth MOSFET M5, and sixth MOSFET M6 are NMOS transistors. The third MOSFET M3 and fourth MOSFET M4 form a proportional current mirror pair. When the enable terminal of the latch module 8 outputs a high level, the initial control switch S0 closes and the first control switch S1 opens; when it outputs a low level, the initial control switch S0 opens and the first control switch S1 closes.

[0078] When the enable terminal of latch module 8 outputs a high level, i.e., EN=1, the initial control switch S0 is closed and the first control switch S1 is open, the circuit operates normally, and the output terminals of the third MOSFET M3 and the fourth MOSFET M4 provide the third current I3 and the fourth current I4, as follows:

[0079]

[0080] In the above formula, VGS5 and VGS6 represent the gate-source voltages of the fifth MOSFET M5 and the sixth MOSFET M6, respectively, and R1 also represents the resistance value of the first resistor R1. The initial MOSFET M0, the first MOSFET M1, and the second MOSFET M2 form the startup circuit of the current reference module 3, operating only during the startup phase. When no current flows through the third MOSFET M3 and the fourth MOSFET M4, no current flows through the first MOSFET M1 either. Since the initial MOSFET M0 is normally on, the gate voltage of the second MOSFET M2 is pulled high, and the second MOSFET M2 conducts, thus providing startup current for the third MOSFET M3 and the fourth MOSFET M4. After the current reference module 3 is working normally, current flows through the first MOSFET M1, pulling down the gate voltage of the second MOSFET M2, turning off the second MOSFET M2, and no longer providing startup current for the third MOSFET M3 and the fourth MOSFET M4. When the enable terminal of the latch module 8 outputs a low level, i.e., EN=0, the initial control switch S0 is open, the first control switch S1 is closed, the current reference module 3 is turned off, and there is no power consumption.

[0081] In one implementation, the USID acceleration module 1, the USID detection module 2, the first current comparator 6, and the second current comparator 7 identify the USID port status and output a first output signal OUT1 and an initial output signal OUT0 to describe the USID port status.

[0082] Specifically, the USID acceleration module 1 includes a second resistor R2, a third resistor R3, a second control switch S2, and a third control switch S3. The first end of the second resistor R2 is connected to the input voltage VIO, and the second end is connected to the first end of the second control switch S2. The second end of the second control switch S2 is connected to the USID port and the first end of the third control switch S3. The first end of the third resistor R3 is connected to the second end of the third control switch S3, and the second end is grounded. The control terminals of the second control switch S2 and the third control switch S3 are both connected to the POR latch signal POR_Latch.

[0083] The second resistor R2 and the third resistor R3 are small-value resistors. When the POR latch signal POR_Latch is low, the second control switch S2 and the third control switch S3 are closed. The USID port is connected to the power supply and ground respectively through small resistors. When USID is in a high-impedance state, by adjusting the ratio and value of the second resistor R2 and the third resistor R3, even if there is a large parasitic capacitance in the USID port, the USID node potential can be quickly established to the initial level. When the POR latch signal POR_Latch is high, the second control switch S2 and the third control switch S3 are open, and this module does not work.

[0084] In one embodiment, the USID detection module 2 includes a pull-up resistor and a pull-down resistor for performing voltage divider detection on the USID port, wherein the resistance values ​​of the pull-up resistor and the pull-down resistor are both greater than the resistance values ​​of the second resistor R2 and the third resistor R3, in order to ensure the accuracy of voltage divider detection when the driving capability of the USID port is weak or parasitic resistance exists.

[0085] Specifically, the USID detection module 2 includes a fourth resistor R4, a fifth resistor R5, a fourth control switch S4, and a fifth control switch S5. The first terminal of the fourth resistor R4 is connected to the input voltage VIO, and the second terminal is connected to the first terminal of the fourth control switch S4. The second terminal of the fourth control switch S4 is connected to the USID port and the first terminal of the fifth control switch S5. The second terminal of the fourth control switch S4 also outputs the USID detection signal USID_det. The first terminal of the fifth resistor R5 is connected to the second terminal of the fifth control switch S5, and the second terminal is grounded. The fourth resistor R4 and the fifth resistor R5 are pull-up and pull-down resistors, respectively.

[0086] In this embodiment, the control terminals of the fourth control switch S4 and the fifth control switch S5 are both connected to the enable terminal of the latch module 8.

[0087] Even better, the fourth resistor R4 and the fifth resistor R5 are larger value resistors, which can avoid the influence of the voltage division value when the driving force of the USID port is weak or the parasitic resistance is large, thus ensuring the accuracy of the detection result. The USID detection signal USID_det is transmitted to the first current comparator 6 and the second current comparator 7. When the enable signal EN output by the enable terminal of the latch module 8 is high, the fourth control switch S4 and the fifth control switch S5 are closed, and the module works. When the enable signal EN output by the enable terminal of the latch module 8 is low, the fourth control switch S4 and the fifth control switch S5 are open, and the module no longer performs detection processing on the USID port. There is no static power consumption at the USID port and the power supply terminal.

[0088] The current comparison unit includes a first current comparator 6 and a second current comparator 7. The USID status signal includes an initial status signal OUT0 and a first status signal OUT1. The first current comparator 6 includes a seventh MOSFET M7 and an eighth MOSFET M8. The control terminal of the seventh MOSFET M7 is connected to the first control terminal, and the input terminal of the seventh MOSFET M7 is connected to the input voltage VIO. The input terminal of the eighth MOSFET M8 is connected to the output terminal of the seventh MOSFET M7 and outputs the initial status signal OUT0. The control terminal of the eighth MOSFET M8 is connected to the USID detection signal, and its output terminal is grounded. The second current comparator 7 includes a ninth MOSFET M9 and a tenth MOSFET M10. The input terminal of the ninth MOSFET M9 is connected to the input voltage VIO, and its control terminal is connected to the USID detection signal. The input terminal of the tenth MOSFET M10 and the output terminal of the ninth MOSFET M9 are both connected to and output the first status signal OUT1. The control terminal of the tenth MOSFET M10 is connected to the second control terminal, and its output terminal is grounded.

[0089] The seventh MOSFET M7 and the ninth MOSFET M9 are PMOS transistors, and the eighth MOSFET M8 and the tenth MOSFET M10 are NMOS transistors. The control terminal of the seventh MOSFET M7 is connected to the output terminal of the third MOSFET M3 in the current reference module 3. The control terminal of the tenth MOSFET M10 is connected to the control terminal of the sixth MOSFET M6 in the current reference module 3. The control terminals of the eighth MOSFET M8 and the ninth MOSFET M9 are both connected to the second terminal of the fourth control switch S4.

[0090] USID acceleration module 1 operates until the POR signal is established, while USID detection module 2 operates for a period of time after the POR signal is established. The former accelerates the establishment of the initial potential of the USID port, while the latter performs more precise detection of the USID port, thereby quickly and accurately outputting the USID detection signal USID_det to meet the system timing requirements. In the first current comparator 6, the eighth MOS transistor M8 converts the input USID detection signal USID_det into a current, which is compared with the first bias current provided by the current reference module 3 to obtain the initial output signal OUT0. The first current comparator 6 and the second current comparator 7 operate on the same principle, obtaining the first output signal OUT1. The USID port status and OUT0-1 output results are shown in Table 1 below.

[0091] Table 1 Truth Table of DVS Trigger Sampling Circuit

[0092] Serial Number USID port status OUT1 OUT0 1 high level 0 0 2 low level 1 1 3 High resistance state 1 0

[0093] Furthermore, the POR detection module 4 and voltage comparator 5 monitor the input voltage VIO and output a POR signal to indicate the power-on status of the system.

[0094] Specifically, the POR detection module 4 includes an eleventh MOSFET M11, a twelfth MOSFET M12, an initial capacitor C0, and a sixth control switch S6. The control terminal of the eleventh MOSFET M11 is connected to the first control terminal. The input terminal of the eleventh MOSFET M11 is connected to the input voltage VIO, and the output terminal is connected to the input terminal of the twelfth MOSFET M12. The output terminal of the twelfth MOSFET M12 is connected to the control terminal of the twelfth MOSFET M12, the first terminal of the initial capacitor C0, and the first terminal of the sixth control switch S6, and outputs the detection signal POR_det. The second terminal of the initial capacitor C0 and the second terminal of the sixth control switch S6 are grounded. The control terminal of the sixth control switch S6 is connected to the enable terminal of the latch module 8.

[0095] Both the eleventh MOSFET M11 and the twelfth MOSFET M12 are PMOS transistors. The control terminal of the eleventh MOSFET M11 is connected to the output terminal of the third MOSFET M3. In the POR detection module 4, the twelfth MOSFET M12 is used to set the charging threshold. When the input voltage VIO is higher than the predetermined threshold, the eleventh MOSFET M11 enters the saturation region and begins to charge the initial capacitor C0 with a constant current. The predetermined threshold is Vgs12 + Vds11, where Vgs12 represents the gate-source voltage of the twelfth MOSFET M12 and Vds11 represents the drain-source voltage of the eleventh MOSFET M11. In one embodiment, the voltage comparator 5 is a Schmitt trigger.

[0096] When the voltage on the initial capacitor C0 rises to the Schmitt trigger's rising threshold, the output POR signal jumps to a high level, and the USID acceleration module 1 shuts down. When the enable terminal of the latch module 8 outputs a high level, i.e., EN=1, the sixth control switch S6 is open, and the POR detection module 4 operates normally; when the enable terminal of the latch module 8 outputs a low level, i.e., EN=0, the sixth control switch S6 is closed, the POR detection module 4 outputs the detection signal POR_det signal, which is pulled down to a low level, and the voltage comparator 5 also outputs a low POR signal.

[0097] The latch module 8 latches the input signals and outputs an enable signal EN at the enable terminal. The latch module 8 has three input signals (POR signal), a first output signal (OUT1), and an initial output signal (OUT0), and outputs four logic signals: the enable signal EN and three latch signals (POR_Latch and UID_Latch<1:0>). The enable signal EN controls the operating state of the current reference module 3 and the USID detection module 2. After a period of time following the latch signal's readiness, the enable signal EN goes low, shutting down the current reference module 3 and the USID detection module 2, achieving zero static power consumption.

[0098] like Figure 5As shown, the latch module 8 includes a first delay unit Delay1, an SR latch SR latch1, an initial TG transmission gate TG0, a first TG transmission gate TG1, a seventh control switch S7, an eighth control switch S8, a first D flip-flop D1, a second D flip-flop D2, a third D flip-flop D3, a first OR gate OR1, a second OR gate OR2, a third OR gate OR3, a second delay unit Delay2, and a first inverter INV1. The input terminal of the first delay unit Delay1, the data input terminal of the first D flip-flop D1, and the first input terminal of the first OR gate OR1 are all connected to the POR signal. The output terminal of the first delay unit Delay1 is connected to the set terminal of the SR latch SR latch1. The reset terminal of the SR latch SR latch1 is grounded. The original code output of latch1 is connected to the clock input of the first D flip-flop D1, the clock input of the second D flip-flop D2, the clock input of the third D flip-flop D2, and the input of the second delay unit Delay2. The output of the second delay unit Delay2 is connected to the input of the first inverter INV1. The output of the first inverter INV1 outputs the enable signal EN. The second input of the first OR gate OR1 is connected to the original code output of the first D flip-flop D1. The first OR gate OR1 outputs the POR latch signal POR_Latch. The input of the first TG transmission gate TG1 is connected to the first state signal OUT1. The output of the first TG transmission gate TG1 is connected to the first terminal of the eighth control switch S8, the data input of the second D flip-flop D2, and the first input of the second OR gate OR2. The second terminal of the eighth control switch S8 is grounded. The second input of the second OR gate OR2 is connected to the original code output of the second D flip-flop D2. The output of the second OR gate OR2 outputs the first state latch signal UID_Latch. <1> The input of the initial TG transmission gate TG0 is connected to the initial state signal OUT0. The output of the initial TG transmission gate TG0 is connected to the first terminal of the seventh control switch S7, the data input terminal of the third D flip-flop D3, and the first input terminal of the third OR gate OR3. The second terminal of the seventh control switch S7 is grounded. The second terminal of the second OR gate OR2 is connected to the original code output terminal of the third D flip-flop D3. The output of the second OR gate OR2 outputs the initial state latch signal UID_Latch. <0> The two control terminals of the initial TG transmission gate TG0 are connected to the input and output terminals of the first inverter INV1, respectively, to obtain the corresponding enable inverting signal ENB and enable signal EN. Similarly, the two control terminals of the first TG transmission gate TG1 are also connected to the input and output terminals of the first inverter INV1, respectively.The seventh control switch S7 and the eighth control switch S8 are open when the initial TG transmission gate TG0 and the first TG transmission gate TG1 are turned on, and closed and turned on otherwise.

[0099] When the enable signal EN=1, the initial TG transmission gate TG0 and the first TG transmission gate TG1 are turned on, and the seventh control switch S7 and the eighth control switch S8 are turned off. The input signal POR, the first output signal OUT1 and the initial output signal OUT0 are directly connected to the corresponding D flip-flop input terminals as latched signals. At the same time, they are transmitted to the output POR latch signal POR_Latch and the status latch signal UID_Latch<1:0> through the first OR gate OR1, the second OR gate OR2 and the third OR gate OR3. The purpose is to output real-time signals before the latch signals Q1, Q2 and Q3 are established. Q1, Q2 and Q3 represent the data output from the original code output terminals of the first D flip-flop D1, the second D flip-flop D2 and the third D flip-flop D3, respectively. After the POR signal is established, after a delay of T1 by the first delay unit Delay1, the output POR delay signal POR_delay is established. The SR latch1 outputs the rising edge signal of the clock signal CLK. The clock signal CLK serves as the trigger signal for the first D flip-flop D1, the second D flip-flop D2, and the third D flip-flop D3, latching the values ​​of the currently input first output signal OUT1, the initial output signal OUT0, and the POR signal into Q1, Q2, and Q3. After the rising edge of the clock signal CLK is delayed by T2 by the second delay unit Delay2, the output enable signal EN is cleared. The initial TG transmission gate TG0 and the first TG transmission gate TG1 are opened, and the seventh control switch S7 and the eighth control switch S8 are closed. As mentioned earlier, when the enable signal EN=0, the POR signal is also cleared. Therefore, the first input terminals of the first OR gate OR1, the second OR gate OR2, and the third OR gate OR3 are also... Figure 5 As shown, all input terminals 'a' are low, and the output POR latch signal POR_Latch and status latch signal UID_Latch<1:0> are entirely determined by latch signals Q1, Q2, and Q3. The internal signal timing diagram of latch module 8 is shown below. Figure 6 As shown, the USID port is in a low-level state at this time, and the output state latch signals UID_Latch<1:0> are all in a high-level state.

[0100] like Figure 7As shown, one embodiment of voltage comparator 5 includes a thirteenth MOSFET M13, a fourteenth MOSFET M14, a fifteenth MOSFET M15, a sixteenth MOSFET M16, a seventeenth MOSFET M17, an eighteenth MOSFET M18, a second inverter INV2, a third inverter INV3, and a fourth inverter INV4. The control terminals of the thirteenth MOSFET M13, the fourteenth MOSFET M14, the sixteenth MOSFET M16, and the seventeenth MOSFET M17 are all connected to the detection signal POR_det. The input terminals of the thirteenth MOSFET M13 and the eighteenth MOSFET M18 are connected to the input voltage VIO. The output terminal of the thirteenth MOSFET M13 and the input terminal of the fourteenth MOSFET M14 are connected to the detection signal POR_det. The input terminal of the fifteenth MOSFET M15 is connected. The output terminal of the fourteenth MOSFET M14 is connected to the input terminal of the sixteenth MOSFET M16, the control terminal of the fifteenth MOSFET M15, the control terminal of the eighteenth MOSFET M18, and the input terminal of the second inverter INV2. The output terminal of the sixteenth MOSFET M16 is connected to the output terminal of the eighteenth MOSFET M18 and the input terminal of the seventeenth MOSFET M17. The output terminals of the fifteenth MOSFET M15 and the seventeenth MOSFET M17 are both grounded. The output terminal of the second inverter INV2 is connected to the input terminal of the third inverter INV3. The output terminal of the third inverter INV3 is connected to the input terminal of the fourth inverter INV4. The output terminal of the fourth inverter INV4 outputs the POR signal.

[0101] The thirteenth MOSFET M13, the fourteenth MOSFET M14, and the fifteenth MOSFET M15 are all PMOS transistors, while the sixteenth MOSFET M16, the seventeenth MOSFET M17, and the eighteenth MOSFET M18 are all NMOS transistors. In this embodiment, when the detection signal POR_det progresses from 0 to VIO, it reaches the upper threshold VT. R At this time, the POR signal exhibits a rising edge transition. At the upper threshold VT... R At this point, the sixteenth MOSFET M16 is in a critical conduction state:

[0102]

[0103]

[0104]

[0105] Among them, V th16 V th17 V th18This represents the threshold voltage of the sixteenth MOSFET M16, the seventeenth MOSFET M17, and the eighteenth MOSFET M18. ds17 I ds18 Let M17 and M18 represent the drain-source currents of the seventeenth MOSFET and the eighteenth MOSFET, respectively. The threshold values ​​of all MOSFETs are approximated as equal and denoted as... ,Right now:

[0106]

[0107] Combining the above equations, we get:

[0108]

[0109]

[0110] Therefore, by adjusting the width-to-length ratio of the seventeenth MOSFET M17 and the eighteenth MOSFET M18, the POR rising-to-turn threshold can be set.

[0111] The timing relationship of each module after the system is powered on is as follows: Figure 8 As shown, the slashed square indicates that the module is in working state. After the system is powered on, the input voltage VIO starts to rise, and the current reference module 3 starts working. Before the POR detection module 4 outputs a signal, the USID acceleration module 1 works and plays a leading role, accelerating the establishment of the USID port voltage. When the input voltage VIO rises to the flip threshold, the voltage comparator 5 outputs a POR signal, the USID acceleration module 1 is turned off, and only the USID detection module 2 performs accurate detection of the USID port. After a delay of T1, the latch module 8 works, latching the current signal. After latching, a delay of T2 is performed to turn off the current reference module 3 and the USID detection module 2, achieving zero static power consumption. The output POR latch signal POR_Latch and the status latch signal UID_Latch<1:0> can always maintain the state before latching. It should be noted that the USID detection module 2 cannot be turned off during the T2 time period, otherwise it will affect the latching result. Figure 8 It can be seen that this embodiment consumes more power and has a faster detection speed during the startup phase.

[0112]

Example 2

[0113] In this embodiment, the high-resistance resistor in the USID acceleration module 1 can also be replaced with a current mirror structure, such as... Figure 9As shown, the USID acceleration module 1 includes a 21st MOSFET M21, a 22nd MOSFET M22, a second control switch S2, and a third control switch S3. The input terminal of the 21st MOSFET M21 is connected to the input voltage VIO, and the output terminal is connected to the first terminal of the second control switch S2. The second terminal of the second control switch S2 is connected to the USID port and the first terminal of the third control switch S3. The input terminal of the 22nd MOSFET M22 is connected to the second terminal of the third control switch S3, and the output terminal is grounded. The control terminals of the 21st MOSFET M21 and the 22nd MOSFET M22 are both connected to the current reference module 3 to obtain the corresponding bias current. The control terminals of the second control switch S2 and the third control switch S3 are both connected to the POR latch signal.

[0114] The solution in this embodiment can reduce the circuit area, and the current mirror structure can reuse the bias current generated by the current reference module 3.

[0115] For example, the 21st MOSFET M21 is a PMOS transistor, and the 22nd MOSFET M22 is an NMOS transistor. Understandably, the gates of the 21st MOSFET M21 and the 22nd MOSFET M22 are respectively connected to the current reference module 3 to obtain the corresponding fourth bias current and fifth bias current, forming a current mirror structure. Taking the current reference module 3 provided in Embodiment 1 as an example: the gate of the 21st MOSFET M21 is connected to the gate of the 3rd MOSFET M3 to obtain the fourth bias current; the 21st MOSFET M21 and the 3rd MOSFET M3 constitute a current mirror structure. The gate of the 22nd MOSFET M22 is connected to the gate of the 6th MOSFET M6 to obtain the fifth bias current; the 22nd MOSFET M22 and the 6th MOSFET M6 form another current mirror structure.

[0116]

Example 3

[0117] like Figure 10As shown, the high-resistance resistor in the USID detection module 2 in this embodiment can also be replaced with a diode-connected MOSFET to reduce the circuit area. The USID detection module 2 includes a nineteenth MOSFET M19, a twentieth MOSFET M20, a fourth control switch S4, and a fifth control switch S5. The input terminal of the nineteenth MOSFET M19 is connected to the input voltage VIO. The output terminal of the nineteenth MOSFET M19 is connected to the control terminal and to the first terminal of the fourth control switch S4. The second terminal of the fourth control switch S4 is connected to the USID port and the first terminal of the fifth control switch S5. The second terminal of the fifth control switch S5 is connected to the control terminal and the input terminal of the twentieth MOSFET M20. The output terminal of the twentieth MOSFET M20 is grounded. The USID acceleration module 1, current reference module 3, POR detection module 4, voltage comparator 5, first current comparator 6, second current comparator 7, and latch module 8 in this embodiment are the same as in embodiment 1, and their working principles are the same, so they will not be described again here.

[0118]

Example 4

[0119] like Figure 11 As shown, the voltage comparator 5 in this embodiment can also use two inverters without a hysteresis threshold. Specifically, the voltage comparator 5 includes a fifth inverter INV5 and a sixth inverter INV6. The input terminal of the fifth inverter INV5 is connected to the detection signal POR_det, and the output terminal of the fifth inverter INV5 is connected to the input terminal of the sixth inverter INV6. The output terminal of the sixth inverter INV6 outputs the POR signal. The USID acceleration module 1, USID detection module 2, current reference module 3, POR detection module 4, first current comparator 6, second current comparator 7, and latch module 8 in this embodiment are the same as in embodiment 1, and their working principles are the same, so they will not be described again here.

[0120] Example 5

[0121] like Figure 13 As shown in the timing diagram, in this embodiment, the USID detection module 2 starts working from time period T1 after the POR signal is established and continues until the hold phase. During this process, the USID detection module 2 continues to work during the latching phase of the latching module 8 to ensure the latching result. In this embodiment, the USID detection module 2 can also be enabled by both the POR latch signal POR_Latch and the enable signal EN.

[0122] For example Figure 12As shown, it also includes an AND gate, the first input of which is connected to the enable terminal of the latch module 8, and the second input is connected to the POR latch signal POR_Latch. The control terminals of the fourth control switch S4 and the fifth control switch S5 are both connected to the output terminal of the AND gate. Figure 12 The corresponding timing shown indicates that the USID detection module 2 only operates after the POR is established and before the hold phase. In this embodiment, the USID acceleration module 1, USID detection module 2, current reference module 3, POR detection module 4, voltage comparator 5, first current comparator 6, second current comparator 7, and latch module 8 are all the same as in Embodiment 1, and their operating principles are the same; therefore, they will not be described again here. Compared to Embodiment 1, this embodiment... Figure 13 The proposed solution consumes less power during the startup phase.

[0123] Example 6

[0124] Based on the same technical concept, this embodiment provides a three-state detection method, including:

[0125] After the system is powered on, the current reference module 3 starts working, providing bias current to the POR detection module 4 and the current comparison unit. At the same time, the USID acceleration module 1 is turned on to quickly establish the initial potential of the USID port.

[0126] The input voltage VIO is detected, and the output detection signal POR_det is compared with the voltage comparator 5 to obtain the POR signal indicating the power-on status of the system.

[0127] After the system power is established, the USID port is detected and the USID detection signal is output to the current comparison unit to obtain the corresponding USID status signal.

[0128] After the system power supply is established, under the control of the POR signal, the detection of the USID port is stopped, and the USID acceleration module 1 and the current reference module 3 are turned off.

[0129] After the system power is established, the USID acceleration module 1 is turned off. After a first delay, the latch module 8 is turned on to latch the USID status signal and the POR signal. After a second delay, the latch module 8 outputs an enable signal at the enable terminal based on the POR signal and the USID status signal. This signal is used to turn off the current reference module 3 and stop detecting the USID port after a predetermined time has elapsed since the system power was established, thereby reducing power consumption.

[0130] Current reference module 3 generates a bias current, which is provided to POR detection module 4 and current comparison unit. POR detection module 4 detects the input voltage VIO and outputs a detection signal POR_det. After passing through voltage comparator 5, the POR signal is obtained, which simultaneously controls the operating state of USID acceleration module 1. USID acceleration module 1, USID detection module 2, and current comparison unit are used for USID port status determination. During the initialization phase, USID acceleration module 1 quickly provides an initial potential to the USID port. After the POR signal is established, it stops working, and USID detection module 2 performs precise detection on the USID port, outputting the USID detection signal USID_det to the current comparison unit to obtain the USID status signal UID<1:0>. Furthermore, the POR signal provided by the POR detection module 4 can acquire the current system power-up status. Therefore, the POR signal can control the on / off state of the USID acceleration module 1, USID detection module 2, and current reference module 3. Both the POR detection module 4 and the current comparison unit are driven by the bias current provided by the current reference module 3. The on / off state of the current reference module 3 directly affects the on / off state of the POR detection module 4 and the current comparison unit. The POR signal output by the POR detection module 4 can directly or indirectly control the operating state of the modules in the three-state detection circuit, achieving closed-loop feedback and enabling zero static power consumption. Specifically, after the system power is on, the POR signal obtained by the POR detection module 4 accelerates the voltage establishment of the USID acceleration module 1. After the system power is on, the POR signal controls the shutdown of the USID acceleration module 1, USID detection module 2, and current reference module 3, thereby controlling the shutdown of the POR detection module 4 and the current comparison unit. Additionally, the POR signal can control the immediate shutdown or the shutdown of the USID acceleration module 1, USID detection module 2, and current reference module 3 after a predetermined delay.

[0131] In one embodiment, a latch module 8 is also used to latch the POR signal and the USID status signal UID<1:0> and output a POR latch signal POR_Latch and a status latch signal UID_Latch<1:0>. The POR latch signal POR_Latch controls the USID acceleration module 1 to stop working immediately after the system power is established. The latch module 8 also outputs an enable signal at the enable terminal based on the POR signal and the USID status signal UID<1:0>, which is used to shut down the current reference module 3 and stop detecting the USID port after a predetermined time after the system power is established. The POR signal and USID status signal output from the voltage comparator 5 and the current comparator unit are input to the latch module 8. The latch module 8 outputs the POR latch signal POR_Latch and the status latch signal UID_Latch<1:0> to indicate the system power-on status and the USID port status. After the system is operating stably, the USID detection module 2 and the current reference module 3 are shut down to achieve zero static power consumption. When the current reference module 3 is turned off under the control of the POR signal, it stops providing bias current to the current comparator and the POR detection module 4.

[0132] like Figure 3 As shown, the core principle of this disclosure is to use the built-in POR detection signal to determine the system's power-on state and sequentially perform acceleration, detection, and latching operations on the USID port. Before the POR signal is established, the USID acceleration module 1 is turned on; after the POR signal is established, the USID acceleration module 1 is turned off, and the USID detection module 2 performs precise detection of the USID node state; after obtaining the USID detection result, the latching module 8 latches the detection result and turns off the USID detection module 2. The startup timing logic of the USID acceleration module 1, USID detection module 2, and latching module 8 is independent of the system and relies only on the built-in POR circuit in the design. This can effectively improve the establishment speed when the USID node is in a high-impedance state, and after obtaining the detection information POR_det, the signal is latched and the USID detection module is turned off, achieving zero static power consumption.

[0133] The current comparison unit includes a first current comparator 6 and a second current comparator 7, and the USID status signal UID<1:0> includes the initial status signal UID. <0> and the first state signal UID <1> The signal OUT0 output by the first current comparator 6 is also the initial state signal UID. <0> The signal OUT1 output by the second current comparator 7 is also the first state signal UID. <1> The current reference module 3 includes a startup circuit and a core circuit. The startup circuit drives the current reference module 3 away from the degenerate bias point when the input voltage is powered on, and automatically shuts down after startup. The output terminal of the startup circuit is connected to the bias terminal of the core circuit. The core circuit has a first control terminal and a second control terminal for outputting bias current. The enable terminal of the latch module 8 is used to control the operating state of the startup circuit and the core circuit. The core circuit has at least one current mirror structure for providing bias current.

[0134] The current reference module 3 generates three bias currents: first, second, and third bias currents, which are provided to the POR detection module 4, the first current comparator 6, and the second current comparator 7. The POR detection module 4 detects the input voltage VIO and outputs a detection signal POR_det. After passing through the voltage comparator 5, the POR signal is obtained and input to the latch module 8. The POR signal also controls the working state of the USID acceleration module 1. The USID acceleration module 1, USID detection module 2, first current comparator 6, and second current comparator 7 are used for USID port status judgment. During the initialization phase, the USID acceleration module 1 quickly provides an initial potential to the USID port. After the POR signal is established, it stops working, and the USID detection module 2 performs accurate detection on the USID port, outputting a detection signal USID_det to the first current comparator 6 and the second current comparator 7 to obtain the first output signal OUT1 and the initial output signal OUT0, which are then passed to the latch module 8. The latch module 8 outputs the POR latch signal POR_Latch and the status latch signal UID_Latch<1:0>, indicating the system power-on status and the USID port status. After the system is operating stably, it shuts down the USID detection module 2 and the current reference module 3, achieving zero static power consumption. In this embodiment, the USID acceleration module 1, USID detection module 2, current reference module 3, POR detection module 4, voltage comparator 5, first current comparator 6, second current comparator 7, and latch module 8 can be selected from the module schemes disclosed in embodiments one to five, and the corresponding circuits and working principles will not be described in detail here.

[0135] More preferably, the resistance of the USID acceleration module 1 is less than the resistance of the USID detection module 2, thereby enabling acceleration to form an initial potential; the USID detection module 2 performs voltage division detection on the USID port through pull-up and pull-down resistors with resistance values ​​greater than the acceleration resistor in the USID acceleration module 1, thereby accurately reflecting the external connection status of the USID port.

[0136] This disclosure provides a USID tri-state detection circuit and method with integrated static power consumption acceleration function. It uses a common current source to implement the POR function, achieving a high degree of integration between POR and USID functions. The output POR signal is used for system reset, ensuring reliable circuit startup after power-on. Furthermore, the POR signal is used to accelerate the processing of the USID port, enabling rapid establishment of a reference voltage even with a large capacitor or weak drive at the USID port, thus meeting system timing requirements. Under the control of the POR signal, relevant functional modules shut down after system power-on, achieving zero static power consumption. This function reduces chip heat dissipation difficulty and extends system battery life.

[0137] It should be noted that although the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the present invention. For any person skilled in the art, many possible variations and modifications can be made to the technical solutions of the present invention based on the disclosed technical content, or equivalent embodiments can be modified accordingly, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the present invention shall still fall within the scope of protection of the present invention.

[0138] The above description is only a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the present invention.

Claims

1. A three-state detection circuit, characterized in that, include: The POR detection module is used to detect the input voltage, and outputs the detection signal to the voltage comparator for comparison to obtain the POR signal indicating the power-on status of the system. The USID acceleration module is connected to the USID port at one end and is used to provide an initial potential to the USID port to accelerate voltage establishment. The USID detection module is connected to the USID port at one end for detecting the USID port, and outputs the USID detection signal to the current comparison unit at the other end to obtain the corresponding USID status signal. A current reference module is used to provide bias current to the POR detection module and the current comparison unit; wherein, the POR signal controls the operating state of the USID acceleration module, the USID detection module and the current reference module.

2. The three-state detection circuit according to claim 1, characterized in that, It also includes a latching module, which receives the POR signal and the USID status signal and latches and outputs a POR latching signal and a status latching signal. The POR latching signal controls the USID acceleration module to shut down after the system power is established. The latching module also outputs an enable signal at the enable terminal based on the POR signal to control the USID detection module and the current reference module to shut down after a predetermined time after the system power is established.

3. The three-state detection circuit according to claim 2, characterized in that, The USID acceleration module includes a second resistor, a third resistor, a second control switch, and a third control switch. The first end of the second resistor is connected to the input voltage, and the second end is connected to the first end of the second control switch. The second end of the second control switch is connected to the USID port and the first end of the third control switch. The first end of the third resistor is connected to the second end of the third control switch, and the second end is grounded. The control terminals of the second and third control switches are both connected to the POR latch signal.

4. The three-state detection circuit according to claim 2, characterized in that, The USID acceleration module includes a 21st MOSFET, a 22nd MOSFET, a second control switch, and a third control switch. The input terminal of the 21st MOSFET is connected to the input voltage, and its output terminal is connected to the first terminal of the second control switch. The second terminal of the second control switch is connected to the USID port and the first terminal of the third control switch. The input terminal of the 22nd MOSFET is connected to the second terminal of the third control switch, and its output terminal is grounded. The control terminals of both the 21st and 22nd MOSFETs are connected to the current reference module to obtain the corresponding bias current. The control terminals of both the second and third control switches are connected to the POR latch signal.

5. The three-state detection circuit according to claim 3, characterized in that, The USID detection module includes pull-up resistors and pull-down resistors for performing voltage divider detection on the USID port. The resistance values ​​of the pull-up resistor and the pull-down resistor are both greater than the resistance values ​​of the second resistor and the third resistor, which is used to ensure the accuracy of voltage divider detection when the driving capability of the USID port is weak or parasitic resistance exists.

6. The three-state detection circuit according to claim 2, characterized in that, The USID detection module includes a fourth resistor, a fifth resistor, a fourth control switch, and a fifth control switch. The first end of the fourth resistor is connected to the input voltage, and the second end is connected to the first end of the fourth control switch. The second end of the fourth control switch is connected to the USID port and the first end of the fifth control switch. The second end of the fourth control switch also outputs the USID detection signal. The first end of the fifth resistor is connected to the second end of the fifth control switch, and the second end is grounded.

7. The three-state detection circuit according to claim 2, characterized in that, The USID detection module includes a nineteenth MOSFET, a twentieth MOSFET, a fourth control switch, and a fifth control switch. The input terminal of the nineteenth MOSFET is connected to the input voltage. The output terminal of the nineteenth MOSFET is connected to the control terminal and connected to the first terminal of the fourth control switch. The second terminal of the fourth control switch is connected to the USID port and the first terminal of the fifth control switch. The second terminal of the fifth control switch is connected to the control terminal of the twentieth MOSFET and the input terminal of the twentieth MOSFET. The output terminal of the twentieth MOSFET is grounded.

8. The three-state detection circuit according to any one of claims 6 and 7, characterized in that, The control terminals of the fourth and fifth control switches are both connected to the enable terminal of the latch module.

9. The three-state detection circuit according to any one of claims 6 and 7, characterized in that, It also includes an AND gate, the first input terminal of which is connected to the enable terminal of the latch module, the second input terminal of which is connected to the POR latch signal, and the control terminals of the fourth control switch and the fifth control switch are both connected to the output terminal of the AND gate.

10. The three-state detection circuit according to claim 2, characterized in that, The current reference module includes a startup circuit and a core circuit. The startup circuit is used to drive the current reference module away from the degenerate bias point when the input voltage is powered on, and automatically shuts down after startup. The output terminal of the startup circuit is connected to the bias terminal of the core circuit. The core circuit has a first control terminal and a second control terminal for outputting bias current. The enable terminal of the latch module is used to control the working state of the startup circuit and the core circuit.

11. The three-state detection circuit according to claim 10, characterized in that, The current reference module includes an initial MOSFET, a first MOSFET, a second MOSFET, a third MOSFET, a fourth MOSFET, a fifth MOSFET, a sixth MOSFET, an initial control switch, a first resistor, and a first control switch. The input terminals of the initial MOSFET, the third MOSFET, and the fourth MOSFET are all connected to the input voltage. The control terminal of the initial MOSFET is grounded. The output terminal of the initial MOSFET is connected to the input terminals of the first MOSFET and the control terminals of the second MOSFET. The output terminal of the third MOSFET, the control terminal of the third MOSFET, the control terminal of the fourth MOSFET, the first terminal of the initial control switch, and the input terminal of the fifth MOSFET are all connected to the input voltage. The first control terminal is described above. The second terminal of the initial control switch is connected to the input terminal of the second MOS transistor. The output terminal of the fourth MOS transistor, the first terminal of the first resistor, the control terminal of the first MOS transistor, the control terminal of the sixth MOS transistor, and the first terminal of the first control switch are all connected to the second control terminal. The second terminal of the first resistor is connected to the control terminal of the fifth MOS transistor and the input terminal of the sixth MOS transistor. The output terminals of the second MOS transistor, the fifth MOS transistor, the first MOS transistor, the sixth MOS transistor, and the second terminal of the first control switch are all grounded. The control terminals of the initial control switch and the first control switch are both connected to the enable terminal of the latch module.

12. The three-state detection circuit according to claim 10, characterized in that, The POR detection module includes an eleventh MOSFET, a twelfth MOSFET, an initial capacitor, and a sixth control switch. The control terminal of the eleventh MOSFET is connected to the first control terminal. The input terminal of the eleventh MOSFET is connected to the input voltage, and the output terminal is connected to the input terminal of the twelfth MOSFET. The output terminal of the twelfth MOSFET is connected to the control terminal of the twelfth MOSFET, the first terminal of the initial capacitor, and the first terminal of the sixth control switch to output the detection signal. The second terminal of the initial capacitor and the second terminal of the sixth control switch are grounded. The control terminal of the sixth control switch is connected to the enable terminal of the latch module.

13. The three-state detection circuit according to claim 1, characterized in that, The voltage comparator is a Schmitt trigger.

14. The three-state detection circuit according to claim 1, characterized in that, The voltage comparator includes a thirteenth MOSFET, a fourteenth MOSFET, a fifteenth MOSFET, a sixteenth MOSFET, a seventeenth MOSFET, an eighteenth MOSFET, a second inverter, a third inverter, and a fourth inverter. The control terminals of the thirteenth MOSFET, the fourteenth MOSFET, the sixteenth MOSFET, and the seventeenth MOSFET are all connected to the detection signal. The input terminals of the thirteenth MOSFET and the eighteenth MOSFET are connected to the input voltage. The output terminal of the thirteenth MOSFET is connected to the input terminals of the fourteenth MOSFET and the fifteenth MOSFET. The output terminal of the fourteenth MOS transistor, the input terminal of the sixteenth MOS transistor, the control terminal of the fifteenth MOS transistor, the control terminal of the eighteenth MOS transistor, and the input terminal of the second inverter are all connected together. The output terminal of the sixteenth MOS transistor, the output terminal of the eighteenth MOS transistor, and the input terminal of the seventeenth MOS transistor are connected together. The output terminals of the fifteenth MOS transistor and the seventeenth MOS transistor are both grounded. The output terminal of the second inverter is connected to the input terminal of the third inverter. The output terminal of the third inverter is connected to the input terminal of the fourth inverter. The output terminal of the fourth inverter outputs the POR signal.

15. The three-state detection circuit according to claim 1, characterized in that, The voltage comparator includes a fifth inverter and a sixth inverter. The input terminal of the fifth inverter is connected to the detection signal, the output terminal of the fifth inverter is connected to the input terminal of the sixth inverter, and the output terminal of the sixth inverter outputs the POR signal.

16. The three-state detection circuit according to claim 10, characterized in that, The current comparison unit includes a first current comparator and a second current comparator. The USID status signal includes an initial status signal and a first status signal. The first current comparator includes a seventh MOSFET and an eighth MOSFET. The control terminal of the seventh MOSFET is connected to the first control terminal. The input terminal of the seventh MOSFET is connected to the input voltage. The input terminal of the eighth MOSFET is connected to the output terminal of the seventh MOSFET and outputs the initial status signal. The control terminal of the eighth MOSFET is connected to the USID detection signal, and its output terminal is grounded. The second current comparator includes a ninth MOSFET and a tenth MOSFET. The input terminal of the ninth MOSFET is connected to the input voltage, and its control terminal is connected to the USID detection signal. The input terminal of the tenth MOSFET and the output terminal of the ninth MOSFET are both connected to and output the first status signal. The control terminal of the tenth MOSFET is connected to the second control terminal, and its output terminal is grounded.

17. The three-state detection circuit according to claim 10, characterized in that, The latch module includes a first delay, an SR latch, an initial TG transmission gate, a first TG transmission gate, a seventh control switch, an eighth control switch, a first D flip-flop, a second D flip-flop, a third D flip-flop, a first OR gate, a second OR gate, a third OR gate, a second delay, and a first inverter. The input of the first delay, the data input of the first D flip-flop, and the first input of the first OR gate are all connected to the POR signal. The output of the first delay is connected to the set input of the SR latch, and the reset input of the SR latch is grounded. The original code output of the SR latch is connected to the clock inputs of the first D flip-flop, the second D flip-flop, and the third D flip-flop, and the input of the second delay. The output of the second delay is connected to the input of the first inverter. The output of the first inverter outputs the enable signal. The second input of the first OR gate and... The original code output of the first D flip-flop is connected, the first OR gate outputs the POR latch signal, the input of the first TG transmission gate is connected to the first state signal, the output of the first TG transmission gate is connected to the first terminal of the eighth control switch, the data input of the second D flip-flop, and the first input of the second OR gate, the second terminal of the eighth control switch is grounded, the second input of the second OR gate is connected to the original code output of the second D flip-flop, and the output of the second OR gate outputs the first state latch signal; the input of the initial TG transmission gate is connected to the initial state signal, the output of the initial TG transmission gate is connected to the first terminal of the seventh control switch, the data input of the third D flip-flop, and the first input of the third OR gate, the second terminal of the seventh control switch is grounded, the second terminal of the second OR gate is connected to the original code output of the third D flip-flop, and the output of the second OR gate outputs the initial state latch signal.

18. A three-state detection method, characterized in that, include: After the system is powered on, the current reference module starts working, providing bias current to the POR detection module and the current comparison unit. At the same time, the USID acceleration module is turned on to quickly establish the initial potential of the USID port. The input voltage is detected, and the output detection signal is compared with the voltage comparator to obtain the POR signal indicating the power-on status of the system. After the system power is established, the USID port is detected and the USID detection signal is output to the current comparison unit to obtain the corresponding USID status signal. After the system power supply is established, under the control of the POR signal, the detection of the USID port is stopped, and the USID acceleration module and the current reference module are turned off.

19. The three-state detection method according to claim 18, characterized in that, After the system power is established, the USID acceleration module is turned off. After a first delay, the latching module is turned on to latch the USID status signal and the POR signal. After a second delay, the latching module outputs an enable signal at the enable terminal based on the POR signal and the USID status signal. This signal is used to turn off the current reference module and stop detecting the USID port after a predetermined period of time after the system power is established, thereby reducing power consumption.

20. The three-state detection method according to claim 18, characterized in that, The resistance of the USID acceleration module is less than that of the USID detection module, thereby enabling acceleration to form an initial potential. The USID detection module performs voltage division detection on the USID port using pull-up and pull-down resistors with resistance values ​​greater than the acceleration resistor in the USID acceleration module, thereby accurately reflecting the external connection status of the USID port.

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