Resistor-capacitor type double-edge multi-phase interpolator and working method thereof

Abstract

The application provides a kind of based on resistance capacitance type double edge multi-phase interpolator and its working method, comprising: phase selector circuit controls the gate end phase of M C And M D In different passageways in multi-phase interpolator by input binary digital code, so as to change the size of resistance value in the path of charging and discharging load capacitor, utilize the different of charging and discharging speed of capacitor by different resistance capacitance time constant, realize accurate phase interpolation.Voltage keeper circuit accelerates the speed of charging and discharging of phase interpolator output node V PI To VDD and GND by positive feedback mechanism, ensure that the interpolator output can be fully charged and discharged to VDD or GND, so as to solve the non-linear problem caused by different initial voltage of phase interpolator charging and discharging under different input binary digital code, realize high-speed high linearity phase interpolation.Multiple phase interpolator circuit generates the required interpolation phase according to the gate end input phase of different tubes M C And tube M D ​

Description

Technical Field

[0001] This invention relates to the field of multiphase interpolator technology, specifically to a resistor-capacitor type double-edge multiphase interpolator and its operating method. Background Technology

[0002] Existing phase interpolator design methods can be categorized based on the basic unit used into current mirror type phase interpolators, inverter type phase interpolators, and resistor-capacitor type phase interpolators. Specifically:

[0003] Current mirror phase interpolator:

[0004] The paper R. Kreienkamp, ​​U. Langmann, C. Zimmermann, T. Aoyama and H. Siedhoff, "A10-gb / s CMOS clock and data recovery circuit with an analog phase interpolator," in IEEE Journal of Solid-State Circuits, vol.40, no.3, pp.736-743, March 2005, discloses the use of a current mirror as the basic interpolation structure. Although this type of interpolator can provide high-precision phase interpolation, it results in high power consumption due to its large static power consumption. Furthermore, the output signal generated by the current mirror interpolator has a small amplitude, requiring conversion by a power-intensive CML-to-CMOS signal converter before it can be used normally, further increasing the system's power consumption and complexity.

[0005] Inverter-type phase interpolator:

[0006] The paper J.-.Chae et al., "266–2133MHz phase shifter using all-digital delay-locked loop and triangular-modulated phase interpolator for LPDDR4X interface," in Electronics Letters, vol.53, no.12, pp.766-768, 2017, discloses the use of inverters as the basic interpolation unit. Although inverter-type interpolators are simple in structure and low in cost, their performance is significantly affected by factors such as manufacturing process, power supply voltage, and temperature. This makes it difficult for inverter-type interpolators to achieve high linearity and stable output, thus limiting their widespread application in high-linearity applications.

[0007] Resistive-capacitive phase interpolator:

[0008] The reference A. Jakobsson, A. Serban and S. Gong, "A Low-Noise RC-Based Phase Interpolator in 16-nm CMOS," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 66, no. 1, pp. 1-5, Jan. 2019, describes how, to prevent a DC path from VDD to GND, the MOSFET M... C and M D The gate signal is switched between the two input phase clocks. However, frequent gate signal switching introduces a switching delay, which degrades the linearity of the phase interpolator. Furthermore, this design does not account for phase errors caused by output swing errors in a dual-edge phase interpolator, which limits the output linearity of the interpolator. Therefore, this design is more suitable for applications with low linearity requirements and low operating frequencies, but cannot meet the performance requirements of applications with high linearity and high speed requirements.

[0009] The reference AKMishra, Y.Li, P.Agarwal and S.Shekhar, "A 9b-Linear 14GHz Integrating-Mode Phase Interpolator in 5nm FinFET Process," 2022 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 2022, pp.1-3, while similar to this design, differs significantly in several key aspects. First, the linear charge-discharge characteristics proposed in that reference only hold true in high-frequency applications. At lower operating frequencies (e.g., below 1GHz), the capacitor's charge-discharge process occurs exponentially between power and ground, thus disrupting its linearity. Second, compared to the M in this application... S Pipe connected to Ф IN1 (This signal switches between GND and VDD over time) Unlike the M in this document, S The transistor is connected to the static control word. Therefore, when the output phase is fixed, M... SThe gate voltage of the transistor remains constant, resulting in a quiescent current flowing from VDD to GND during the rising and falling edge switching process. These two characteristics limit the circuit proposed in this paper to applications only at higher frequencies. At low frequencies, its linearity performance will significantly decrease due to the exponential charge-discharge characteristics and the influence of the quiescent current. Furthermore, compared to the voltage holder used in this application to address the voltage-to-phase error conversion problem, this paper fails to effectively solve this problem. Summary of the Invention

[0010] To address the shortcomings of existing technologies, the purpose of this invention is to provide a resistor-capacitor type double-edge multi-phase interpolator and its operating method.

[0011] According to the present invention, a resistor-capacitor type double-edge multi-phase interpolator is provided, comprising: a phase selector circuit, a multi-phase interpolator circuit, and a voltage holder circuit;

[0012] The phase selector circuit controls the M in different paths of the multi-phase interpolator through the input binary digital code. C and M D The gate phase is changed, thereby altering the resistance value in the charging and discharging path of the load capacitor. By utilizing the different charging and discharging speeds of the capacitor with different resistance and capacitance time constants, phase interpolation is achieved.

[0013] The voltage holding circuit accelerates the output node V of the multi-phase interpolator through a positive feedback mechanism. PI The charging and discharging speed to VDD and GND enables the multi-phase interpolator output to be fully charged and discharged to VDD or GND, thereby achieving phase interpolation;

[0014] The multi-phase interpolator circuit is based on different transistors M in the multi-phase interpolator circuit. C and pipe M D The gate input phase is used to generate the required interpolated phase.

[0015] Preferably, the phase selector circuit includes a binary code to thermometer code circuit and 2n multiplexer circuits;

[0016] The binary code to thermometer code circuit is used to process the input binary code. When the binary code is incremented by 1, the number of 1s in the output thermometer code also increases accordingly.

[0017] Each multiplexer circuit includes two tri-state gates.

[0018] Preferably, the on / off state of the tri-state gate is controlled by a thermometer code;

[0019] The inputs of the two tri-state gates are respectively Ф IN1 and ФIN2 When the corresponding temperature code bit of the control tri-state gate is 1, the output terminal selects Ф. IN2 When the corresponding thermometer code bit is 0, the output terminal selects Ф. IN1 .

[0020] Preferably, the multi-phase interpolator circuit includes n charging / discharging paths and n discharging paths, and each path includes a transistor M. C Pipe M D Pipe M S and charging / discharging resistor R PI ;

[0021] The tube M C and pipe M D Used to control the opening and closing of the charging and discharging path;

[0022] The tube M S Used to block the DC path from VDD to GND, located in the charging and discharging path of the multi-phase interpolator circuit;

[0023] The charging and discharging resistor R PI Used to implement linear interpolation.

[0024] Preferably, the tube M C and pipe M D The gate phase can be determined by the two tri-state gate inputs Ф in the phase selector. IN1 and Ф IN2 Switch between them.

[0025] Preferably, when there are nm tubes M C and pipe M D The gate terminal is connected to Ф IN1 The remaining m gate terminals are connected to Ф IN2 At that time, the output phase of the multi-phase interpolator is generated by linear weighting.

[0026] Preferably, the voltage holding circuit includes positive feedback inverters INV1 and INV2, and MOSFETs M1 and M2;

[0027] The inverters INV1 and INV2 are connected end to end to form a positive feedback loop;

[0028] The MOSFETs M1 and M2 are used to block the DC path from the multiphase interpolator to the voltage holder.

[0029] Preferably, when the output voltage V of the multi-phase interpolator PI The conversion threshold voltage V of inverter INV1 is reached. THAfter a delay from two inverters, inverter INV2 will output a current in the same direction as the charging and discharging of the multi-phase interpolator, driving the load capacitor C. PI Perform charging and discharging until V PI It is charged and discharged to VDD or GND.

[0030] A method for operating a resistor-capacitor type double-edge multi-phase interpolator according to the present invention includes:

[0031] The phase selector circuit controls the transistor M in different paths of the multi-phase interpolator through the input binary digital code. C and pipe M D The gate phase is changed, thereby altering the resistance value in the charging and discharging path of the load capacitor. By utilizing the different charging and discharging speeds of the capacitor with different resistance and capacitance time constants, phase interpolation is achieved.

[0032] The voltage holding circuit accelerates the output node V of the phase interpolator through a positive feedback mechanism. PI Charge and discharge to V DD The speed of GND is used to ensure that the interpolator output can be fully charged and discharged to VDD or GND to achieve phase difference;

[0033] The multi-phase interpolator circuit is based on different transistors M in the multi-phase interpolator circuit. C and pipe M D The gate input phase is used to generate the required interpolated phase.

[0034] Preferably, when the phase interpolator outputs node voltage V PI When the multi-phase interpolator has been pre-discharged to the GND state, its operation includes the following steps:

[0035] Step S1: When Ф IN1 When the falling edge arrives, there are a total of nm charging paths through P. CHR <1> To P CHR <n-m>For load capacitor C PI During the charging process, V PI With time constant R PI *C PI The rate of exponential charging to VDD is / (nm), at which point V PI The voltage formula is as follows:

[0036]

[0037] In the formula, Ф IN1 V represents the input signal of the first tri-state gate in the phase selector circuit. PI R represents the output voltage of the multi-phase interpolator. PI This represents the charging and discharging resistor in the multi-phase interpolator circuit, and Δt represents the input signal Ф. IN1 Compared to Ф IN2 The lead time, t represents time, and VDD represents the power supply voltage;

[0038] Step S2: When Ф IN2 When the falling edge arrives, there are n charging paths through P. CHR <1> To P CHR <n>For load capacitor C PI During the charging process, V PI With time constant R PI *C PI The rate of charge / n is exponentially increased to VDD, at which point V... PI The voltage formula is:

[0039]

[0040] In the formula, Ф IN2 This represents the input signal of the second tri-state gate in the phase selector circuit;

[0041] According to formulas (1) and (2), we obtain the result from Ф IN1 The time delay after the falling edge arrives is as follows:

[0042]

[0043] In the formula, V TH This represents the threshold voltage of the next stage inverter. The first half before the plus sign is a fixed delay, and the second half of the delay increases linearly with the increase of m, thereby achieving linear interpolation of the output rising edge.

[0044] Step S3: When Ф IN1 When the rising edge arrives, there are a total of (nm) discharge paths through P. DIS <1> To P DIS <n-m>For load capacitor C PI During the discharge, V PI With time constant R PI *C PI The exponential discharge to GND occurs at a rate of / (nm), at which point V PI The voltage is:

[0045]

[0046] Step S4: When Ф IN2 When the falling edge arrives, there are n charging paths through P. CHR <1> To P CHR <n>For load capacitor C PI During the charging process, V PI With time constant R PI *C PI The rate of charge / n is exponentially increased to VDD, at which point V PI The voltage is:

[0047]

[0048] According to formulas (4) and (5), we obtain the result from Ф IN1 The time delay after the rising edge arrives is:

[0049]

[0050] In formula (6), the first part of the plus sign is a fixed delay, and the second part of the delay increases linearly with the increase of m, thereby realizing linear interpolation of the output falling edge.

[0051] The voltage holder operates by including a charging process and a discharging process;

[0052] The charging process includes: when the multi-phase interpolator adjusts the output node voltage V PI During charging, V PI Gradually charge from GND to the conversion threshold voltage V of inverter INV1. TH When V PI Reaching V TH At this time, inverter INV1 outputs GND, driving inverter INV2 to output V. DD This accelerates the adjustment of the output node voltage V of the multi-phase interpolator. PI The charging process ensures that the output node voltage quickly reaches the predetermined voltage;

[0053] The discharge process includes: when the multi-phase interpolator adjusts the output node voltage V PI During discharge, V PI From V DD Gradually discharge to the switching threshold voltage V of inverter INV1 TH When V PI Reduce to V TH At that time, inverter INV1 outputs V DD This drives the inverter INV2 to output GND, thereby accelerating the output node voltage V of the multi-phase interpolator. PI The discharge speed ensures that the output node voltage drops rapidly to ground level.

[0054] Compared with the prior art, the present invention has the following beneficial effects:

[0055] 1. This invention effectively isolates the DC current from VDD to GND by connecting a MOS transistor (MS) with a gate terminal connected in series in the charging and discharging path, thereby eliminating the phase switching delay, significantly improving the linearity of the interpolator, and reducing the complexity of circuit design.

[0056] 2. The positive feedback characteristic of the voltage holder of the present invention ensures that the multi-phase interpolator can be fully charged and discharged to the power supply or ground, thereby significantly reducing the phase nonlinearity caused by swing error and greatly improving the working speed and linearity of the interpolator. Attached Figure Description

[0057] Other features, objects, and advantages of the present invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0058] Figure 1 This is a schematic diagram of the resistor-capacitor type double-edge multi-phase interpolator of the present invention.

[0059] Figure 2 This is a schematic diagram illustrating the working principle of the phase interpolator in an embodiment of the present invention. Detailed Implementation

[0060] The present invention will now be described in detail with reference to specific embodiments. These embodiments will help those skilled in the art to further understand the present invention, but do not limit the invention in any way. It should be noted that those skilled in the art can make several changes and improvements without departing from the concept of the present invention. These all fall within the protection scope of the present invention.

[0061] This invention proposes a high-speed, high-linearity, double-edge multi-phase interpolator structure. This interpolator performs phase interpolation by utilizing the exponential charging and discharging characteristics of a resistor-capacitor circuit, and achieves multi-phase interpolation output by controlling the value of the series resistor along the charging and discharging path of the load capacitor.

[0062] According to the present invention, a resistor-capacitor type double-edge multi-phase interpolator is provided, such as... Figure 1 As shown, it includes: a phase selector circuit, a multi-phase interpolator circuit, and a voltage holder circuit. The phase selector circuit controls the M in different paths of the multi-phase interpolator through an input binary digital code. C and M D The gate phase is adjusted to change the resistance value in the charging and discharging path of the load capacitor. By utilizing the different charging and discharging speeds of the capacitor with different resistance and capacitance time constants, accurate phase interpolation is achieved. The voltage holding circuit then accelerates the output node V of the phase interpolator through a positive feedback mechanism. PI The charging and discharging speed to VDD and GND ensures that the interpolator output can be fully charged and discharged to VDD or GND, thus solving the nonlinearity problem caused by different initial charging and discharging voltages of the phase interpolator under different input binary digital codes, achieving high-speed and high-linearity phase interpolation. The multi-phase interpolator circuit includes n charging / discharging paths and n discharging paths, with each path consisting of a transistor M... C Pipe M D Pipe M S Charge / discharge resistor R PI .

[0063] The phase selector circuit includes a binary code to thermometer code conversion circuit and 2n multiplexer circuits. The binary code to thermometer code conversion circuit processes the input binary code; as the binary code increments by 1, the number of 1s in the output thermometer code also increases. Each multiplexer circuit includes two tri-state gates, whose on / off states are controlled by the thermometer code. The inputs of the two tri-state gates are Ф... IN1 and Ф IN2 When the corresponding temperature code bit of the control tri-state gate is 1, the output terminal selects Ф. IN2 When the corresponding thermometer code bit is 0, the output terminal selects Ф. IN1 This setting enables precise phase selection based on thermometer code control.

[0064] The multi-phase interpolator circuit contains n charge / discharge paths (P CHR <1> -P CHR <n>), n discharge paths (P DIS <1> -P DIS <n>), the tube M in each path C and pipe M D Used to control the opening and closing of the charging and discharging path, tube M S The charging / discharging resistor R is used to block the DC path from VDD to GND. PI Used to achieve linear interpolation. The tube M C and pipe M D The gate phase can be determined from the two tri-state gate inputs Ф in the phase selector. IN1 and Ф IN2 Switching between them. When there are (nm) tubes M C and pipe M D The gate terminal is connected to Ф IN1 The remaining m gate terminals are connected to Ф IN2 At this time, the output phase of the multi-phase interpolator is generated through a linear weighting method. The multi-phase interpolator can adjust the phase according to different M... C and M D The gate input phase is used to accurately generate the required interpolated phase. This is achieved by adding a MOSFET M to the charging and discharging path of the resistor-capacitor interpolator circuit to block the DC path from VDD to GND. S This simplifies the structure of the dual-edge multi-bit resistor-capacitor interpolator. This design effectively avoids the problem of M... C Pipe and M D The frequent switching of the phase at the gate reduces the switching time and improves the overall response speed of the phase interpolator. Simultaneously, this simplified structure reduces circuit complexity, lowers nonlinearity errors during phase interpolation, and further improves the linearity of phase interpolation.

[0065] The voltage holding circuit includes positive feedback inverters INV1 and INV2, and MOSFETs M1 and M2 to block the DC path from VDD to GND. Inverters INV1 and INV2 are connected end-to-end to form a positive feedback loop. MOSFETs M1 and M2 block the DC path from the phase interpolator to the voltage holding circuit, thus ensuring the normal operation of the voltage holding circuit. When the output voltage V of the multi-phase interpolator... PI The conversion threshold voltage V of inverter INV1 is reached. TH After a delay from two inverters, inverter INV2 will output a current in the same direction as the charging and discharging of the multi-phase interpolator, driving the load capacitor C. PI Perform charging and discharging until V PI The voltage is charged and discharged to VDD or GND to ensure that the interpolator's output voltage eventually stabilizes at the desired supply voltage or ground voltage. The voltage at the phase interpolator output node V is maintained by a voltage hold circuit. PI By employing positive feedback charging and discharging, the phase error problem caused by insufficient charging and discharging in resistive-capacitive interpolators is resolved. This design effectively eliminates nonlinearity caused by incomplete charging and discharging, significantly improving the linearity of phase interpolation. Simultaneously, the positive feedback mechanism of the voltage holder accelerates the charging and discharging speed of the phase interpolator's load node voltage, thereby greatly improving the phase interpolator's response speed and further widening its operating frequency range, enabling it to meet high linearity requirements at higher frequencies.

[0066] The dual-edge multi-phase interpolator of this invention can be widely used in applications requiring high phase interpolation speed and linearity, such as phase-locked loops (PLLs) and clock data recovery (CDR). In these applications, the input signal includes a two-phase clock and a binary digital code. Based on the input binary digital code value, the system can select and output interpolation results for different phases, thereby achieving precise phase adjustment.

[0067] According to the present invention, a method for operating a resistive-capacitive double-edge multi-phase interpolator is provided, such as... Figure 2 As shown, it includes: a phase selector circuit that controls M in different paths of the multi-phase interpolator through an input binary digital code. C and M D The gate phase is adjusted to change the resistance value in the charging and discharging path of the load capacitor. By utilizing the different charging and discharging speeds of the capacitor with different resistance and capacitance time constants, accurate phase interpolation is achieved. The voltage holding circuit then accelerates the output node V of the phase interpolator through a positive feedback mechanism. PI The charging and discharging speed to VDD and GND ensures that the interpolator output can be fully charged and discharged to VDD or GND to achieve phase difference.

[0068] Taking a 4-bit double-edge multi-phase interpolator as an example, the working process of the phase selector is described in detail below:

[0069] When the input binary code is 4'b0000, the binary-to-thermometer code circuit outputs 16'h0000. At this time, all M... C All pipes are connected to Ф IN1 When the input binary code is 4'b1000, the binary-to-thermometer code circuit outputs 16'h00FF. At this time, the 8 M... C Pipe connection to Ф IN2 8 M's remaining C Pipe connection to Ф IN1 When the input binary code is 4'b1111, the binary-to-thermometer code circuit outputs 16'hEFFF. At this time, 15 M... C Pipe connection to Ф IN2 Only 1 M C Pipe connection to Ф IN1 In this way, the phase selector can precisely adjust the phase interpolation result according to different input digital codes.

[0070] Combined with appendix Figure 2 The working process of the multi-phase interpolator is described in detail below:

[0071] Assume the input signal Ф IN1 Compared to Ф IN2 It has a lead of Δt, and before this, the phase interpolator output node voltage V PI It has been pre-discharged to GND state:

[0072] Step 1: When Ф IN1 When the falling edge arrives, there are a total of nm charging paths through P. CHR <1> To P CHR <n-m>For load capacitor C PI Charging is underway. During this process, V... PI With time constant R PI *C PI The rate of exponential charging to VDD is / (nm). V PI The voltage can be expressed as:

[0073]

[0074] In the formula, VDD represents the power supply voltage.

[0075] Step 2: When Ф IN2 When the falling edge arrives, there are n charging paths through P. CHR <1> To P CHR <n>For load capacitor C PI Charging is underway. During this process, V... PI With time constant R PI *C PI The rate of charge / n is exponentially charged to VDD. V PI The voltage can be expressed as:

[0076]

[0077] Assume the threshold voltage of the next stage inverter is V TH According to formulas (1) and (2), we can obtain the value from Ф IN1 The time delay after the falling edge arrives is:

[0078]

[0079] Among them, the first half of formula (3), that is With a fixed delay, the second half, i.e. The delay increases linearly with the increase of m, thus achieving linear interpolation of the output rising edge.

[0080] Step 3: When Ф IN1 When the rising edge arrives, there are a total of (nm) discharge paths through P. DIS <1> To P DIS <n-m>For load capacitor C PI Discharge occurs. During this process, V PI With time constant R PI *C PI Discharge to GND at a rate of / (nm). V PI The voltage can be expressed as:

[0081]

[0082] Step 4: When Ф IN2 When the falling edge arrives, there are n charging paths through P. CHR <1> To P CHR <n>For load capacitor C PI Charging is underway. During this process, V... PI With time constant R PI *C PI The rate of charge / n is exponentially charged to VDD. V PI The voltage can be expressed as:

[0083]

[0084] Assume the threshold voltage of the next stage inverter is V TH According to formulas (4) and (5), we can obtain the value from Ф IN1 The time delay after the rising edge arrives is:

[0085]

[0086] Among them, the first half of formula (6), that is With a fixed delay, the second half, i.e. The delay increases linearly with the increase of m, thus achieving linear interpolation of the output falling edge.

[0087] According to formulas (3) and (6), when the initial voltage state of the output node of the phase interpolator is VDD or GND, the number of m can be changed by changing the input binary digital code of the phase selector, thereby achieving accurate rising and falling edge phase interpolation.

[0088] The working process of the voltage holder is described in detail below:

[0089] The operation of a voltage holder consists of two main parts: a charging process and a discharging process. The charging process includes: when the multi-phase interpolator adjusts the output node voltage V... PI During charging, V PI Gradually charge from GND to V TH V TH This is the switching threshold voltage of the inverter INV1 in the voltage holder. When V PI Reaching V TH At this time, inverter INV1 outputs GND, driving inverter INV2 to output VDD. The output of INV2 further accelerates the voltage change at the output node of the multi-phase interpolator, V. PI The charging process ensures that the output node quickly and stably reaches the predetermined voltage. The discharging process includes: when the multi-phase interpolator adjusts the output node voltage V... PI During discharge, V PI Gradually discharge from VDD to the switching threshold voltage V of inverter INV1. TH When V PI Reduce to V TH At this time, inverter INV1 outputs VDD, driving inverter INV2 to output GND, thereby accelerating the output node voltage V of the multi-phase interpolator. PI The discharge rate ensures that the voltage drops rapidly to ground level.

[0090] In high-speed, high-linearity applications, the voltage hold ensures that the output node voltage of the multi-phase interpolator can be fully charged and discharged to VDD and GND. During each rising-edge and falling-edge interpolation process, the charging and discharging of the output voltage always begins from VDD or GND, and the initial charging and discharging voltage is independent of the input digital code. This design effectively avoids the nonlinear transformation from amplitude to phase, thus significantly improving the interpolation linearity of the phase interpolator. On the other hand, the positive feedback mechanism of the voltage hold accelerates the charging and discharging speed of the interpolator's output node voltage to VDD or GND, further improving the response speed and operating frequency of the phase interpolator, enabling it to operate stably at higher frequencies. Therefore, the voltage hold not only optimizes the linearity of the phase interpolator but also significantly increases its maximum operating frequency.

[0091] Those skilled in the art will understand that, besides implementing the system and its various devices, modules, and units provided by this invention in the form of purely computer-readable program code, the same functions can be achieved entirely through logical programming of the method steps, making the system and its various devices, modules, and units of this invention function in the form of logic gates, switches, application-specific integrated circuits, programmable logic controllers, and embedded microcontrollers. Therefore, the system and its various devices, modules, and units provided by this invention can be considered as a hardware component, and the devices, modules, and units included therein for implementing various functions can also be considered as structures within the hardware component; alternatively, the devices, modules, and units for implementing various functions can be considered as both software modules implementing the method and structures within the hardware component.

[0092] Specific embodiments of the present invention have been described above. It should be understood that the present invention is not limited to the specific embodiments described above, and those skilled in the art can make various changes or modifications within the scope of the claims, which do not affect the essence of the present invention. Unless otherwise specified, the embodiments and features described in this application can be arbitrarily combined with each other.< / n> < / n> < / n> < / n> < / n> < / n>

Claims

1. A resistor-capacitor type double-edge multi-phase interpolator, characterized in that, include: Phase selector circuit, multi-phase interpolator circuit, and voltage holder circuit; The phase selector circuit controls the M in different paths of the multi-phase interpolator through the input binary digital code. C and M D The gate phase is changed, thereby altering the resistance value in the charging and discharging path of the load capacitor. By utilizing the different charging and discharging speeds of the capacitor with different resistance and capacitance time constants, phase interpolation is achieved. The voltage holding circuit accelerates the output node V of the multi-phase interpolator through a positive feedback mechanism. PI The charging and discharging speed to VDD and GND enables the multi-phase interpolator output to be fully charged and discharged to VDD or GND, thereby achieving phase interpolation; The multi-phase interpolator circuit is based on different transistors M in the multi-phase interpolator circuit. C and pipe M D The gate input phase is used to generate the required interpolated phase.

2. The resistor-capacitor type double-edge multi-phase interpolator according to claim 1, characterized in that, The phase selector circuit includes a binary code to thermometer code circuit and 2n multiplexer circuits; The binary code to thermometer code circuit is used to process the input binary code. When the binary code is incremented by 1, the number of 1s in the output thermometer code also increases accordingly. Each multiplexer circuit includes two tri-state gates.

3. The resistor-capacitor type double-edge multi-phase interpolator according to claim 2, characterized in that, The on / off state of the three-state gate is controlled by a thermometer code; The inputs of the two tri-state gates are respectively Ф IN1 and Ф IN2 When the corresponding temperature code bit of the control tri-state gate is 1, the output terminal selects Ф. IN2 When the corresponding thermometer code bit is 0, the output terminal selects Ф. IN1 .

4. The resistor-capacitor type double-edge multi-phase interpolator according to claim 1, characterized in that, The multi-phase interpolator circuit includes n charge / discharge paths and n discharge paths, each path comprising a transistor M. C Pipe M D Pipe M S and charging / discharging resistor R PI ; The tube M C and pipe M D Used to control the opening and closing of the charging and discharging path; The tube M S Used to block the DC path from VDD to GND, located in the charging and discharging path of the multi-phase interpolator circuit; The charging and discharging resistor R PI Used to implement linear interpolation.

5. The resistor-capacitor type double-edge multi-phase interpolator according to claim 4, characterized in that, The tube M C and pipe M D The gate phase can be determined by the two tri-state gate inputs Ф in the phase selector. IN1 and Ф IN2 Switch between them.

6. The resistor-capacitor type double-edge multi-phase interpolator according to claim 4, characterized in that, When there are nm tubes M respectively C and pipe M D The gate terminal is connected to Ф IN1 The remaining m gate terminals are connected to Ф IN2 At that time, the output phase of the multi-phase interpolator is generated by linear weighting.

7. The resistor-capacitor type double-edge multi-phase interpolator according to claim 1, characterized in that, The voltage holding circuit includes positive feedback inverters INV1 and INV2, and MOSFETs M1 and M2; The inverters INV1 and INV2 are connected end to end to form a positive feedback loop; The MOSFETs M1 and M2 are used to block the DC path from the multiphase interpolator to the voltage holder.

8. The resistor-capacitor type double-edge multi-phase interpolator according to claim 7, characterized in that, When the output voltage V of the multiphase interpolator PI The conversion threshold voltage V of inverter INV1 is reached. TH After a delay from two inverters, inverter INV2 will output a current in the same direction as the charging and discharging of the multi-phase interpolator, driving the load capacitor C. PI Perform charging and discharging until V PI It is charged and discharged to VDD or GND.

9. A method for operating a resistive-capacitive double-edge multi-phase interpolator, characterized in that, include: The phase selector circuit controls the transistor M in different paths of the multi-phase interpolator through the input binary digital code. C and pipe M D The gate phase is changed, thereby altering the resistance value in the charging and discharging path of the load capacitor. By utilizing the different charging and discharging speeds of the capacitor with different resistance and capacitance time constants, phase interpolation is achieved. The voltage holding circuit accelerates the output node V of the phase interpolator through a positive feedback mechanism. PI Charge and discharge to V DD The speed of GND is used to ensure that the interpolator output can be fully charged and discharged to VDD or GND to achieve phase difference; The multi-phase interpolator circuit is based on different transistors M in the multi-phase interpolator circuit. C and pipe M D The gate input phase is used to generate the required interpolated phase.

10. The resistor-capacitor type double-edge multi-phase interpolator according to claim 9, characterized in that, When the phase interpolator outputs node voltage V PI When the multi-phase interpolator has been pre-discharged to the GND state, its operation includes the following steps: Step S1: When Ф IN1 When the falling edge arrives, there are a total of nm charging paths through P. CHR <1> To P CHR <n-m>For load capacitor C PI During the charging process, V PI With time constant R PI *C PI The rate of exponential charging to VDD is / (nm), at which point V PI The voltage formula is as follows: In the formula, Ф IN1 V represents the input signal of the first tri-state gate in the phase selector circuit. PI R represents the output voltage of the multi-phase interpolator. PI This represents the charging and discharging resistor in the multi-phase interpolator circuit, and Δt represents the input signal Ф. IN1 Compared to Ф IN2 The lead time is t, where t represents time and VDD represents the power supply voltage. Step S2: When Ф IN2 When the falling edge arrives, there are n charging paths through P. CHR <1> To P CHR <n>For load capacitor C PI During the charging process, V PI With time constant R PI *C PI The rate of charge / n is exponentially increased to VDD, at which point V... PI The voltage formula is:< / n> In the formula, Ф IN2 This represents the input signal of the second tri-state gate in the phase selector circuit; According to formulas (1) and (2), we obtain the result from Ф IN1 The time delay after the falling edge arrives is as follows: In the formula, V TH This represents the threshold voltage of the next stage inverter. The first half before the plus sign is a fixed delay, and the second half of the delay increases linearly with the increase of m, thereby achieving linear interpolation of the output rising edge. Step S3: When Ф IN1 When the rising edge arrives, there are a total of (nm) discharge paths through P. DIS <1> To P DIS <n-m>For load capacitor C PI During the discharge, V PI With time constant R PI *C PI The exponential discharge to GND occurs at a rate of / (nm), at which point V PI The voltage is: Step S4: When Ф IN2 When the falling edge arrives, there are n charging paths through P. CHR <1> To P CHR <n>For load capacitor C PI During the charging process, V PI With time constant R PI *C PI The rate of charge / n is exponentially increased to VDD, at which point V PI The voltage is:< / n> According to formulas (4) and (5), we obtain the result from Ф IN1 The time delay after the rising edge arrives is: In formula (6), the first part of the plus sign is a fixed delay, and the second part of the delay increases linearly with the increase of m, thereby realizing linear interpolation of the output falling edge. The voltage holder operates by including a charging process and a discharging process; The charging process includes: when the multi-phase interpolator adjusts the output node voltage V PI During charging, V PI Gradually charge from GND to the conversion threshold voltage V of inverter INV1. TH When V PI Reaching V TH At this time, inverter INV1 outputs GND, driving inverter INV2 to output V. DD This accelerates the adjustment of the output node voltage V of the multi-phase interpolator. PI The charging process ensures that the output node voltage quickly reaches the predetermined voltage; The discharge process includes: when the multi-phase interpolator adjusts the output node voltage V PI During discharge, V PI From V DD Gradually discharge to the switching threshold voltage V of inverter INV1 TH When V PI Reduce to V TH At that time, inverter INV1 outputs V DD This drives the inverter INV2 to output GND, thereby accelerating the output node voltage V of the multi-phase interpolator. PI The discharge speed ensures that the output node voltage drops rapidly to ground level.

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