A method and system for delay adjustment in semiconductor devices

Abstract

This invention relates to semiconductor devices, specifically to a delay adjustment method and system applied to semiconductor devices. The method includes: S100, providing a delay management circuit with a two-level adjustment mode, the two-level adjustment mode including: a first-level adjustment mode that only activates the internal delay adjustment module, and a second-level adjustment mode that activates both the internal and external delay adjustment modules; S102, selecting a temperature determination mechanism based on the power supply voltage; S103, identifying the current operating temperature; S104, determining whether the operating temperature is greater than or equal to a first set temperature; if the result of S104 is yes, it is recommended to switch or maintain the delay management circuit in the second-level adjustment mode; if the result of S104 is no, it is recommended to switch or maintain the delay management circuit in the first-level adjustment mode. This invention provides a delay adjustment scheme that achieves relatively uniform control of delay errors.

Description

Technical Field

[0001] This invention relates to the field of time delay adjustment methods for semiconductor circuits, specifically to a time delay adjustment method and system applied to semiconductor devices. Background Technology

[0002] Against the backdrop of rapid AI development, technologies such as die-to-die and optical interconnects are advancing rapidly. Converting parallel data into serial data requires a multiplexer (MUX) circuit, such as a 2:1 or 4:1 selector. However, the output load capacitance of the selector is often quite large, resulting in insufficient bandwidth for the MUX output signal and introducing significant inter-symbol interference (ISI). To address the ISI problem, a dual-feedback equalizer is often connected after the MUX to mitigate its effects.

[0003] Common dual-feedback equalizers such as Figure 1 As shown. From Figure 1 As can be seen, two branches need to be set up in the feedback equalizer for signal processing, and this separate processing mode is prone to introducing time delay problems.

[0004] Therefore, there is an urgent need for a solution to alleviate the latency problem in dual-feedback equalizers. Summary of the Invention

[0005] The purpose of this invention is to provide a delay adjustment method for semiconductor devices, which partially solves or alleviates the above-mentioned deficiencies in the prior art and can reduce or mitigate the impact of delay problems on dual feedback equalizers.

[0006] To solve the aforementioned technical problems, the present invention specifically adopts the following technical solution: This invention provides a time delay adjustment method for semiconductor devices, comprising the following steps: S100 provides a delay management circuit with a two-stage adjustment mode, which includes: The main circuit is equipped with inverter I and inverter II; The first branch, and the input and output terminals of the first branch are respectively located at the output terminal of inverter II and between inverter I and inverter II. The first branch is provided with a first phase adjustment unit and a first adjustable delay buffer. The second branch has its input and output terminals located before the output terminal of inverter II and the input terminal of inverter I, respectively; the second branch is provided with a second phase adjustment unit and a gain-controllable inverter in sequence. A multi-phase clock generator is connected to a first phase adjustment unit and a second phase adjustment unit to form an internal time delay adjustment module in the time delay management circuit, and an external time delay adjustment module is also provided after the output node of the time delay management circuit. Correspondingly, the two-level adjustment mode includes: a first-level adjustment mode that only enables the internal delay adjustment module, and a second-level adjustment mode that enables both the internal delay adjustment module and the external delay adjustment module. S102, selects the temperature determination mechanism based on the power supply voltage; Specifically, when the power supply voltage is greater than or equal to a first voltage threshold, a first determination mechanism is selected. Correspondingly, the first determination mechanism includes: S103 identifies the current operating temperature; S104, determine whether the operating temperature is greater than or equal to the first set temperature; If so, it is recommended to switch or maintain the delay management circuit in the secondary adjustment mode; If not, it is recommended to switch or maintain the delay management circuit in the first-level adjustment mode.

[0007] In some embodiments, the steps further include: If the power supply voltage is less than or equal to the set second voltage threshold, the second determination mechanism is selected. Correspondingly, the second determination mechanism includes: S103 identifies the current operating temperature; S105, determine whether the operating temperature is greater than or equal to the second set temperature; If so, it is recommended to switch or maintain the delay management circuit in the first-level adjustment mode; If not, it is recommended to switch or maintain the delay management circuit in the secondary adjustment mode.

[0008] In some embodiments, the first voltage threshold or the second voltage threshold has a default input value.

[0009] In some embodiments, the steps include: The first voltage threshold or the second voltage threshold is selected based on the degree of fluctuation of the power supply voltage.

[0010] In some embodiments, the greater the fluctuation, the larger the first voltage threshold, or the smaller the second voltage threshold.

[0011] In some embodiments, it also includes: S106, Identify the current load size of the delay management circuit; S107, Update the power supply voltage according to the load size.

[0012] In some embodiments, the larger the load, the lower the recommended power supply voltage.

[0013] In some embodiments, the longer the idle time of the time delay management circuit under a set duty cycle, the smaller the load size.

[0014] The present invention also provides a time delay adjustment system for semiconductor devices, comprising: A time delay management circuit with a two-stage adjustment mode includes: The main circuit is equipped with inverter I and inverter II; The first branch, and the input and output terminals of the first branch are respectively located at the output terminal of inverter II and between inverter I and inverter II. The first branch is provided with a first phase adjustment unit and a first adjustable delay buffer. The second branch has its input and output terminals located before the output terminal of inverter II and the input terminal of inverter I, respectively; the second branch is provided with a second phase adjustment unit and a gain-controllable inverter in sequence. A multi-phase clock generator is connected to a first phase adjustment unit and a second phase adjustment unit to form an internal time delay adjustment module in the time delay management circuit, and an external time delay adjustment module is also provided after the output node of the time delay management circuit. The two-level adjustment mode includes: a first-level adjustment mode that only enables the internal delay adjustment module, and a second-level adjustment mode that enables both the internal delay adjustment module and the external delay adjustment module. The mechanism selection module is used to select a temperature determination mechanism based on the power supply voltage; wherein, when the power supply voltage is greater than or equal to a first voltage threshold, the first determination mechanism is selected. Correspondingly, the system includes: a temperature recognition module for recognizing the current operating temperature; The first temperature determination module is used to determine whether the operating temperature is greater than or equal to the first set temperature. If so, it is recommended to switch or maintain the delay management circuit in the secondary adjustment mode; If not, it is recommended to switch or maintain the delay management circuit in the first-level adjustment mode.

[0015] In some embodiments, the mechanism selection module is further configured to select a second determination mechanism when the power supply voltage is less than or equal to a set second voltage threshold. The second temperature determination module determines whether the working temperature is greater than or equal to the second set temperature. If so, it is recommended to switch or maintain the delay management circuit in the first-level adjustment mode; If not, it is recommended to switch or maintain the delay management circuit in the secondary adjustment mode.

[0016] Beneficial technical effects: This invention provides a time delay management circuit with a two-stage adjustment mode, and its two-stage adjustment mode can reduce the fluctuation of time delay error to a certain extent.

[0017] It should be noted that the purpose of this application is not to measure or limit the specific size of the latency with absolute precision, but to find or determine the stage where the latency problem is most prominent or rapidly escalates, so as to identify the scenarios most likely to have severe latency and to perform secondary adjustments for these most challenging scenarios.

[0018] In response, the applicant noted that the latency issue is affected by many factors, especially voltage and temperature. Furthermore, the degree of influence of temperature and voltage can vary significantly across different temperature ranges, and there may even be different temperature-based decision-making logics.

[0019] To reduce or mitigate the conflict in temperature judgment under different logics and to reasonably assess the overall impact of temperature on latency, this application introduces a prediction of the dominant influence mode of power supply voltage on temperature (that is, to select a first or second discrimination mechanism) to simplify the temperature judgment logic through scenario segmentation.

[0020] This application uses the power supply voltage to divide temperature into the following different logical judgment scenarios: When the power supply voltage (VDD) is high, the higher voltage provides a stronger external driving force for the transistor to turn on. Therefore, the carrier mobility at this point will affect the time delay; if the carrier mobility is too slow, the time delay will increase.

[0021] For example, when the power supply voltage is low, the external driving force available to turn on the transistor is relatively small. Therefore, if the transistor's turn-on threshold (i.e., threshold voltage) is high at this time, it will lead to a larger time delay. Conversely, if the temperature is high at this time, the time delay may be reduced because the threshold voltage decreases.

[0022] From another perspective, this application eliminates temperature interference factors by classifying power supply voltage magnitude (such as reducing one of the factors, i.e., reducing or minimizing the impact of changes in carrier velocity or threshold voltage at temperature on the final result). This makes the single logical judgment reasonable (i.e. it can fit the scenario, and the logic will not be too simple due to the elimination of interference factors, and will not fail to reflect global changes).

[0023] Furthermore, it should be noted that in order to more reliably separate (or distinguish) the two interfering factors of temperature (i.e., carrier migration velocity and threshold voltage level), the first voltage threshold and the second voltage threshold can be made to have a certain width between them. That is, the first discrimination mechanism should be executed in the scenario of significantly high voltage, and the second discrimination mechanism should be executed in the scenario of significantly low voltage, so as to avoid or reduce the error that may be caused by executing a single discrimination mechanism in the fuzzy range. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. In all the drawings, similar elements or parts are generally identified by similar reference numerals. The elements or parts in the drawings are not necessarily drawn to scale. Obviously, the drawings described below are some embodiments of the present invention, and those skilled in the art can obtain other drawings based on these drawings without any creative effort.

[0025] Figure 1 This is a schematic diagram of the circuit architecture of an exemplary dual-feedback equalizer in the prior art; Figure 2 This is a schematic diagram of the circuit architecture of a dual-feedback equalizer with a time delay adjustment module in an exemplary embodiment of the present invention. Figure 3 This is a schematic diagram of the circuit architecture of a dual-feedback equalizer with internal and external time delay adjustment modules in an exemplary embodiment of the present invention. Figure 4 This is a schematic diagram of the circuit architecture of the external delay adjustment module in an exemplary embodiment of the present invention; Figure 5 This is a schematic diagram of the waveform of a clock signal in an exemplary embodiment; Figure 6 This is a schematic diagram of the waveform of a data signal in an exemplary embodiment; Figure 7 This is a schematic diagram of the method flow in an exemplary embodiment of the present invention.

[0026] Summary of reference numerals in the attached diagram: 1. Inverter I; 2. Inverter II; 3. First phase adjustment unit; 4. First adjustable delay buffer; 5. Second phase adjustment unit; 6. Gain-controllable inverter; 7. Output node; 8. Second multi-phase clock generator; 9. Third phase adjustment unit; 10. Second gain adjustment unit; 11. Fourth phase adjustment unit; 12. Second adjustable delay buffer; 13. Multi-phase clock generator; 101. Rising edge; 102. Falling edge; 103. High level region; 104. Low level region; 200. External delay adjustment module. Detailed Implementation

[0027] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0028] In this document, suffixes such as "module," "part," or "unit" used to denote elements are used only for the purpose of illustrative purposes and have no specific meaning in themselves. Therefore, "module," "part," or "unit" may be used interchangeably.

[0029] In this document, the terms "upper," "lower," "inner," "outer," "front," "rear," "one end," and "the other end," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the present invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the present invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0030] In this document, unless otherwise explicitly specified and limited, the terms "installed," "equipped with," "connected," etc., should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, a direct connection, or an indirect connection through an intermediate medium; it can be a connection within two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0031] In this document, "and / or" includes any and all combinations of one or more of the listed related items.

[0032] In this article, "multiple" means two or more, that is, it includes two, three, four, five, etc.

[0033] As used in this specification, the term "about" typically means + / -5% of the value, more typically + / -4% of the value, more typically + / -3% of the value, more typically + / -2% of the value, even more typically + / -1% of the value, and even more typically + / -0.5% of the value.

[0034] In this specification, certain embodiments may be disclosed in a range-bound format. It should be understood that this "range-bound" description is merely for convenience and brevity and should not be construed as a rigid limitation on the disclosed range. Therefore, the description of a range should be considered as having specifically disclosed all possible subranges and the individual numerical values ​​within those ranges. For example, a description of the range 1-6 should be considered as having specifically disclosed subranges such as from 1 to 3, from 1 to 4, from 1 to 5, from 2 to 4, from 2 to 6, from 3 to 6, etc., and the individual numbers within those ranges, such as 1, 2, 3, 4, 5, and 6. This rule applies regardless of the breadth of the range.

[0035] INV: An inverter (also known as a NOT gate) is one of the most basic units in digital logic circuits. Its core function is to perform a logical NOT operation—when the input is high (logic "1"), the output is low (logic "0"); when the input is low (logic "0"), the output is high (logic "1"), meaning the output signal is always out of phase with the input signal.

[0036] DLL: Delay-Locked Loop, is a circuit used to generate precise clock phase or delay, and is a type of clock management technology.

[0037] Typically, a DLL architecture is a negative feedback control loop, consisting of the following main modules: a phase detector (PD), used to compare the phase difference between the reference clock (input clock) and the delayed clock signal; a loop filter, used to smooth the phase difference signal output by the phase detector; and a voltage-controlled delay line (VCDL), used to adjust the delay amount according to the control voltage, thereby changing the phase delay of the output clock relative to the input clock.

[0038] See Figure 1 The diagram illustrates an example of a dual-feedback equalizer architecture in the prior art. The input inverter (INV0), the first inverter (INV1), and the second inverter (INV2) form a first feedback loop, while the first inverter (INV1), the third inverter (INV3), and the fourth inverter (INV4) form a second feedback loop. The first and second feedback loops converge at the output. The first and second feedback loops are used to independently process the data signal and the clock signal, respectively.

[0039] However, the applicant noted that the presence of INV in the circuit design easily introduces delay. Especially in this dual feedback path, the input inverter (INV0) and the first inverter (INV1) are located on the main path of the entire circuit and are the first / second stage of the entire circuit. Therefore, their delay directly affects the core timing parameters of the system (such as period, phase, setup / hold time).

[0040] To facilitate understanding of the technical problem this application aims to solve, the specific workflow of the aforementioned feedback loop is explained here: The circuit's input terminal is connected to an input electrical signal Vi, which records both data signals and clock signals. These two signals are prone to errors due to time delays during the transition process.

[0041] In response, this application provides a latency feedback adjustment method to optimize and adjust latency issues on the backbone path.

[0042] See Figure 2 As shown, the present invention first provides a delay management circuit (equivalent to a dual feedback equalization circuit) applied to semiconductor devices, which includes: The main path is provided with inverter I1 (e.g., INV0) and inverter II2 (e.g., INV1) sequentially along the direction from the input end to the output end. The first branch, and the input terminal of the first branch is located at the output terminal of the inverter II2 (such as INV1), and the output terminal of the first branch is located between inverter I1 and inverter II2. The first branch is provided with a first phase adjustment unit 3 and a first adjustable delay buffer 4. The second branch has its input terminal located at the output terminal of inverter II2, and its output terminal located before the input terminal of inverter I1; the second branch is sequentially provided with a second phase adjustment unit 5 and a gain controllable inverter 6. The inverter II2, the first phase adjustment unit 3 and the first adjustable delay buffer 4 form a first feedback loop, while the inverter I1, the inverter II2, the second phase adjustment unit 5 and the gain controllable inverter 6 form a second feedback loop. The first feedback loop and the second feedback loop output electrical signals to the outside through the output node. A multi-phase clock generator 13 is connected to the first and second phase adjustment units respectively to form a delay adjustment module inside the feedback equalizer.

[0043] Preferably, in some embodiments, the adjustable delay buffer may refer to a circuit unit composed of two inverters. That is to say, in this embodiment, the dual feedback equalization circuit can adopt a connection structure similar to that in the prior art, the difference being that this application introduces a delay adjustment design inside and outside the feedback circuit.

[0044] Typically, the multi-phase clock generator 13 specifically includes: The delay-locked module (DLL, also known as a delay-locked loop) and the clock selector, specifically the output of the clock selector is connected to two different phase adjustment units.

[0045] Specifically, the workflow of delay control in this embodiment is as follows: First, the external input electrical signals include: data signals and clock signals. The data signals record the transmitted information data, while the clock signals are used to define the time data for sampling the data signals, that is, they define the time point for sampling the data signals.

[0046] However, during data transmission, the data signal and clock signal may experience signal quality degradation. For example, ideally, the data signal is in its most stable or highest quality state at the sampling time defined by the clock signal. However, if quality deteriorates (such as due to time delays between the two), the final acquired signal will also deteriorate.

[0047] See Figure 5 As shown, Figure 5 This is a waveform illustration of a clock signal, where the horizontal axis represents time and the vertical axis represents voltage levels (specifically indicated by 0 or 1). The instantaneous transition from low level (0V) to high level (VDDH) in this square wave is called the rising edge 101. Rising edge 101 marks the moment when the data signal is sampled. In other words, the clock signal is used to define the sampling time and period for sampling the data signal.

[0048] Figure 6 The waveform of the data signal is shown, with the horizontal axis representing time and the vertical axis representing voltage levels. The waveform includes a rising edge (101) and a falling edge (102), which are considered the data transition region. The remaining moments are considered the stable data region, such as the high-level region (103) and the low-level region (104). The purpose of the clock signal is to position the sampling time within the stable data region. However, due to deviations during transmission, the preset sampling time of the clock signal may not fall within the stable data region.

[0049] It should be noted that, Figure 5 , Figure 6 The voltage levels are represented by logic numbers 0 or 1. Figure 5 , Figure 6 Only one example waveform data is shown.

[0050] In other words, the applicant noticed that Figure 1 The original purpose of the line was to solve the ISI problem, but due to the delay problem of its two branches, the data sampling will become unstable.

[0051] Therefore, in order to ensure that the clock signal falls back into the stable data region, this invention will first introduce clock selection technology into the feedback equalizer to achieve this goal. Specifically, the clock selection technology can be DLL technology.

[0052] The following is merely an illustrative description of the application of DLL technology within a feedback equalizer: First, the delay adjustment module includes: (1) A multi-phase clock generator, which may specifically include: A DLL (Delay-Locked Loop) is used to select the locked phase to generate multiple clock copies with different delay sizes; A clock selector is used to select the appropriate clock copy from multiple clock copies; wherein, the clock selector is a type of multiplexer (MUX) that can select one output from multiple phase clocks based on an external control signal (or a lockout state from within a DLL).

[0053] (2) DFF (such as D flip-flop), which is used to receive a selected clock copy and sample data according to the clock copy; Specifically, DFF samples the data signal according to the selected clock signal (i.e., a selected clock copy) to obtain sampled data.

[0054] Specifically, the quality of the sampled data can be judged, and then the clock signal or gain coefficient can be selected based on the data quality.

[0055] The DLL's inputs include a reference clock signal, which is used to output multiple clock copies. These copies are delayed versions of the reference clock signal, such as clk_0°, clk_90°, clk_180°, and clk_270°. The reference clock signal can be directly taken from the clock signal recorded in the input electrical signal.

[0056] For example, a DLL can generate multiple delayed versions of a reference clock signal, i.e., different clock replicas, via voltage-controlled delay lines, with each replica's delay being an integer fraction of the reference clock period (e.g., 1 / 4, 1 / 2, or 3 / 4 of the period). In other words, multiple replica signals can be viewed as shifts of the same periodic signal along the time axis. Therefore, the reference clock signal and the different clock replicas are all electrical signals to be transmitted (i.e., having the same waveform), differing only in their respective signal start times.

[0057] (3) Gain adjustment unit, used to receive the gain adjustment signal and select to update or maintain the current gain according to the current gain adjustment signal.

[0058] In this embodiment, the gain adjustment unit is preferably set only in the data path.

[0059] Specifically, the clock selector aims to ensure that the final clock signal sampling point falls within the stable data region, while skipping the transition region.

[0060] Therefore, the selection logic of the clock selector can be: At least two corresponding sampling results are obtained based on at least two clock replicas. If the difference between the two data sampling results is less than a set threshold (i.e., the two sampling results are very close), then the clock replica is considered to meet the sampling requirements. Either one can be selected as the chosen clock signal. This is equivalent to selecting the phase difference between the clock signal and the data signal.

[0061] It is important to understand that in the transmission of electrical signals, data is recorded using a 01 method. That is, when the voltage value is greater than the discrimination threshold, it is stored as 1, and otherwise it is stored as 0.

[0062] And, as Figure 4 As shown, it is important to note that in order to ensure that the clock signal and the data signal have the same phase difference, a clock selector will provide a unified time reference and provide selected time copies to the data signal and the clock signal respectively, so as to ensure that the two maintain the same phase difference as much as possible, that is, to achieve phase locking.

[0063] For example, one can first select a corresponding time copy for the clock signal, and then generate a synchronized time copy for the data signal based on the selected time copy, i.e., a unified time reference line, to lock the phase difference.

[0064] Furthermore, after resolving the time difference issue, the next step will be to address the gain adjustment problem along the data path.

[0065] As mentioned earlier, the data recording rule for the data signal is a 0 / 1 data format. Specifically, when the voltage value is greater than the discrimination threshold, it is stored as a signal value of 1; otherwise, it is stored as 0. Furthermore, in this embodiment, to resist noise interference, the voltage value needs to be as much greater or less than the discrimination threshold as possible to improve the accuracy of 0 / 1 discrimination.

[0066] For example, due to signal noise, assuming the noise level is approximately 0.05V, and the threshold for judgment is 0.6V, if the actual signal voltage is 0.6V, and there is a negative noise of -0.05V superimposed on it, the voltage value will be incorrectly recorded as 0.55V, leading to a misjudgment of 0. Therefore, to reduce the risk of misjudgment, the voltage value can be amplified through gain adjustment.

[0067] The voltage value corresponding to a signal value of 1 should be as much higher as possible than the discrimination threshold, and the voltage value corresponding to a signal value of 0 should be as much lower than the discrimination threshold, leaving sufficient noise margin in between to improve the system's noise immunity and reduce the bit error rate.

[0068] Specifically, the process of judging the quality of sampled data and adjusting the gain based on the numerical quality includes: Sampling data is collected based on the clock signal, and the sampling data is a set of 0s and 1s. The actual proportion of 0s or 1s in a statistical data set; Calculate the difference between the actual ratio and the standard ratio (usually set at 50%); The gain adjustment signal is generated based on the difference, such as increasing the gain signal, decreasing the gain signal, or maintaining the gain signal.

[0069] For example, if the difference is greater than a set first threshold, the gain is decreased; if the difference is less than a set second threshold, the gain is increased; otherwise, it is recommended to maintain the current gain. The second threshold is less than the first threshold. In this paper, the execution flow of the "recommendation" can be understood as generating an executable control signal.

[0070] For example, a specific scenario will be used to illustrate the gain adjustment scheme: In most high-speed communication systems, the input electrical signal is typically encoded to ensure that the number of 1s and 0s at the end is statistically nearly equal. Therefore, when the error is small, the ratio of 0s to 1s should be close to 50%. Thus, the standard ratio is also set at 50%.

[0071] At this point, when the calculated actual proportion of 1 is 60%, the difference is 10%, which is greater than 2% (i.e., greater than the first threshold). Since there are too many 1s, the signal amplitude may be too high, and it is recommended to reduce the gain. When the calculated actual proportion of 1 is 40%, the difference is -10%, which is less than -2% (i.e., less than the second threshold). Since there are too few 1s, the signal amplitude may be too low, and it is recommended to increase the gain. When the actual proportion of 1 is 50%, it falls between the first and second thresholds; therefore, the current gain can be kept unchanged.

[0072] It should be noted that, in order to cope with the complex operating conditions of the chip (such as frequent or large fluctuations in ambient temperature), a two-level delay processing module (or delay adjustment module) is designed in this embodiment.

[0073] The two-stage delay processing module includes: a delay processing module (also known as an internal delay adjustment module) located within the dual-feedback equalizer, and a delay processing module (also known as an external delay adjustment module) located at the rear end of the dual-feedback equalizer. The external delay adjustment module 200 is used to further delay the output electrical signal after it has been processed by the internal delay adjustment module (i.e., after being processed by the internal delay adjustment module), such as... Figure 3 As shown.

[0074] It is understandable that the external delay adjustment module can adopt the same or similar circuit architecture as the internal delay adjustment module, that is, the clock signal is selected first, and then the gain is adjusted.

[0075] For example, the external delay adjustment module includes: After the dual feedback equalizer (specifically after output node 7), a multi-phase clock generator, a DFF, a gain adjustment unit, and an adjustable delay buffer are sequentially arranged. The reference clock signal in the multi-phase clock generator is preferably a clock signal selected / generated after processing by an external delay adjustment module.

[0076] Specifically, such as Figure 4 As shown, it includes: a second multi-phase clock generator 8, which is also connected to two separate external branches. The first external branch (corresponding to the data path) is sequentially provided with a third phase adjustment unit 9 and a second gain adjustment unit 10, and the second external branch is sequentially provided with a fourth phase adjustment unit 11 and a second adjustable delay buffer 12.

[0077] For example, the third phase adjustment unit 9 of the first external branch is used to receive a clock copy selected for the data signal and transmit the data signal according to the clock copy, and the second gain adjustment unit 10 determines whether gain adjustment is needed based on the sampling result of the current data signal. The fourth phase adjustment unit 11 of the second external branch is used to receive a time copy selected for the clock signal and, through the second adjustable delay buffer 12, is used to execute which clock signal is allowed to pass.

[0078] In other words, the purpose of an adjustable delay buffer is to limit the passage of the next clock signal at a single moment, so as to avoid signal confusion and collision in the path.

[0079] Similarly, the external and internal delay adjustment modules in this application can directly use the clock selection technology in the prior art, and this invention does not limit them.

[0080] Below, the present invention provides a method for dynamically switching adjustment modes for a delay management circuit that combines internal and external delay adjustment modules. This method includes: S100 provides a delay management circuit with a two-stage adjustment mode, wherein the delay management circuit includes: The main path is provided with inverter I1 (e.g., INV0) and inverter II2 (e.g., INV1) sequentially along the direction from the input end to the output end. The first branch has an input terminal located at the output terminal of inverter II2, and the output terminal of the first branch is located between inverter I1 and inverter II2. The first branch is provided with a first phase adjustment unit 3 and a first adjustable delay buffer 4 (i.e., BUF0). The second branch has its input terminal located at the output terminal of inverter II2, and its output terminal located before the input terminal of inverter I1; the second branch is sequentially provided with a second phase adjustment unit 5 and a gain controllable inverter 6 (such as INV3). The inverter II2, the first phase adjustment unit 3 and the first adjustable delay buffer 4 form a first feedback loop, while the inverter I1, the inverter II2, the second phase adjustment unit 5 and the gain controllable inverter 6 form a second feedback loop. The first feedback loop and the second feedback loop output electrical signals to the outside through the output node 7. The input electrical signal includes a data signal and a clock signal, and the data signal and the clock signal are processed through the first feedback loop and the second feedback loop, respectively. The first multi-phase clock generator has its input terminals connected between inverter I1 and inverter II2, and between inverter II2 and output node 7, respectively. Furthermore, the output of the first multi-phase clock generator is connected to the first phase adjustment unit 3 and the second phase adjustment unit 5 respectively, so as to output different clock replica signals through the same time reference, thereby realizing phase difference locking between the data signal and the clock signal. The first phase clock generator is used to perform the first time delay adjustment on the input electrical signal. The time delay management circuit further includes an external time delay adjustment module 200 disposed after the output node 7, and the external time delay adjustment module is used to perform a second time delay adjustment on the output electrical signal; The two-stage adjustment mode includes: a first-stage adjustment mode, in which the external time delay adjustment module is kept off. That is, only the input electrical signal is subject to the first time delay adjustment; and a second-stage adjustment mode, in which the external time delay adjustment module is kept on. That is, in the second-stage adjustment mode, the input electrical signal is subject to the first time delay adjustment, while the output electrical signal is subject to the second time delay adjustment.

[0081] like Figure 7 As shown, in step S101, the power supply voltage of the external power source is acquired. This external power supply voltage is used to provide the input electrical signal. S102, selects the temperature determination mechanism based on the power supply voltage; Specifically, when the power supply voltage is greater than the set first voltage threshold (corresponding to a high voltage scenario), the first determination mechanism is selected; The first determination mechanism includes: S103 identifies the current operating temperature; Specifically, the operating temperature can be the operating temperature of the chip in which the circuit is located.

[0082] Alternatively, the operating temperature can be the measured ambient temperature.

[0083] S104, determine whether the working temperature is greater than or equal to the first set temperature (i.e., the temperature can be considered too high at this time). If the result of S104 is yes, it is recommended to switch or maintain the delay management circuit in the secondary adjustment mode; If the result of S104 is negative, it is recommended to switch or maintain the delay management circuit in the first-level adjustment mode.

[0084] In other words, in this embodiment, when the power supply is at a high voltage, it is assumed that the mapping relationship between temperature and time delay is that the higher the temperature, the more serious the time delay problem may be, such as the larger the time delay deviation and the greater the difficulty in solving the time delay problem.

[0085] In this embodiment, when the current operating temperature is very high and exceeds the high temperature warning line (i.e., exceeds the first set temperature), a two-level adjustment mode is adopted, that is, both the inner and outer time delay adjustment modules of the dual feedback equalizer are activated. When the operating temperature does not exceed the high temperature warning line, in order to reduce energy consumption, a first-level adjustment mode can be adopted, that is, the external time delay adjustment module is turned off.

[0086] In some embodiments, S102 includes: When the power supply voltage is less than the set second voltage threshold (corresponding to a low voltage scenario, the second voltage threshold should be less than the first voltage threshold), the second determination mechanism is selected (under this determination mechanism, the higher the temperature, the lower the possible delay).

[0087] Correspondingly, the second determination mechanism includes: S103 identifies the current operating temperature; S105, determine whether the working temperature is greater than or equal to the second set temperature (i.e., the temperature can be considered too high at this time). If the result of S105 is yes, it is recommended to switch or maintain the delay management circuit in the first-level adjustment mode. If the result of S105 is negative, it is recommended to switch or maintain the delay management circuit in the secondary adjustment mode.

[0088] In this embodiment, temperature and latency are considered to be nearly negatively correlated; that is, the higher the temperature, the smaller the latency problem is considered to be, and in this case, it is possible to choose not to enable the external latency adjustment module. Conversely, the lower the temperature, the more severe the latency problem may be, and in this case, it is recommended to enable the secondary adjustment mode to cope with more complex latency adjustment tasks.

[0089] Understandably, due to the use of different discrimination mechanisms, the criteria for judging high and low temperatures can be differentiated in different scenarios. For example, in high-temperature scenarios, for semiconductor chips used in commercial applications, the first set temperature can be set to approximately 85°C, while the second set temperature can be set to approximately 25°C. That is, when the temperature exceeds 85°C, the effect of mobility may cause significant changes, thus requiring a secondary adjustment module. When the temperature is below approximately 25°C, the threshold voltage may be very high, which significantly increases the difficulty of transistor switching and the switching time. When the temperature is higher, the threshold voltage is lower, and below a certain threshold range, transistor switching becomes very easy. At this point, even if the temperature gradually increases, the resulting deviation in switching time is relatively weak, and the impact on latency is relatively small.

[0090] For example, in this embodiment, the second set temperature is lower than the first set temperature.

[0091] It is worth noting that the purpose of this application is not to measure or limit the specific size of the latency with absolute precision, but to find or determine the stage where the latency problem is most prominent or rapidly escalates, so as to identify the scenarios most prone to severe latency and to perform secondary adjustments for these most challenging scenarios.

[0092] In other words, in this embodiment, the goal is not to pursue absolute uniformity of delay error in all scenarios (i.e., to ensure that the error must be consistent under all operating conditions), but to ensure relative consistency of the final output delay error as much as possible under approximate operating conditions.

[0093] Specifically, the core technical concept of this application is not to pursue an absolute value of latency approaching zero, but to strive for high consistency in latency under different operating conditions (such as temperature and voltage variations), minimizing deviations or fluctuations. In other words, this application pursues relative consistency. This pursuit of relative consistency is significant in scenarios requiring precise synchronization, such as clock tree allocation, high-speed data conversion, and memory interface communication. In these scenarios, latency fluctuations can lead to system timing errors, data sampling errors, or signal distortion. Even if the absolute latency is slightly larger (but needs to be kept within the redundancy range of the system design), it is acceptable as long as it remains within a relatively stable data range (e.g., it can be tolerated, or it can be compensated for through subsequent system design).

[0094] To facilitate understanding of the technical concept of the time delay adjustment scheme in this application, its application principle will be explained from another perspective below: In the context of time delay issues in digital circuits, the applicant argues that the primary cause stems from deviations in the switching times of transistors within inverters (or logic gates). These deviations result in a delay in the signal's transition from input to output, rather than an instantaneous process. Consequently, faster switching times lead to relatively smaller delays, while longer switching times, especially since different inverters are prone to timing discrepancies, exacerbate the delay problem. Furthermore, the difficulty in addressing these issues (such as selecting a clock replica signal and choosing a gain coefficient) makes time delay management challenging.

[0095] Furthermore, the applicant noted that time delay is affected by multiple factors, particularly voltage and temperature. For example, temperature affects carrier mobility. Increased temperature tends to intensify lattice vibrations, thus increasing the resistance to carrier (electron / hole) movement, resulting in decreased mobility. Therefore, increased temperature tends to slow transistor switching speeds, leading to increased time delay (i.e., considering only carrier mobility interference, higher temperatures result in greater time delay). On the other hand, increased temperature can also lower the built-in potential of semiconductor materials, which reduces the threshold voltage required to turn on the transistor, making it easier to turn it on. This reduced difficulty in turning on the transistor helps reduce time delay deviation (i.e., considering only threshold voltage interference, higher temperatures result in smaller time delay).

[0096] In order to reduce or mitigate the conflict in temperature judgment under different logics and to reasonably assess the overall impact of temperature on latency, this application introduces a prediction of the dominant influence mode of power supply voltage on temperature (that is, to select the first or second discrimination mechanism) to simplify the temperature judgment logic through scenario segmentation.

[0097] Specifically, this application uses the power supply voltage to divide temperature into the following different logical judgment scenarios: When the power supply voltage (VDD) is high, the higher voltage provides a stronger external driving force for the transistor to turn on. Therefore, the carrier mobility at this point will affect the time delay; if the carrier mobility is too slow, the time delay will increase.

[0098] For example, when the power supply voltage is low, the external driving force available to turn on the transistor is relatively small. Therefore, if the transistor's turn-on threshold (i.e., threshold voltage) is high at this time, it will lead to a larger time delay. Conversely, if the temperature is high at this time, the time delay may be reduced because the threshold voltage decreases.

[0099] From another perspective, this embodiment eliminates temperature interference factors by classifying the power supply voltage (such as reducing one of the factors, i.e., reducing or minimizing the impact of changes in carrier velocity or threshold voltage at temperature on the final result). This makes the single logical judgment reasonable (i.e., it can fit the scenario, and the logic will not be too simple due to the elimination of interference factors, and will not fail to reflect global changes).

[0100] Furthermore, it should be noted that in order to more reliably separate (or distinguish) the two interfering factors of temperature (i.e., carrier migration velocity and threshold voltage level), the first voltage threshold and the second voltage threshold can be made to have a certain width between them. That is, the first discrimination mechanism should be executed in the scenario of significantly high voltage, and the second discrimination mechanism should be executed in the scenario of significantly low voltage, so as to avoid or reduce the error that may be caused by executing a single discrimination mechanism in the fuzzy range.

[0101] In other words, whether in high-voltage or low-voltage scenarios, carrier velocity and threshold voltage will be affected by temperature. However, this application chooses the most influential interference factor as the primary criterion for judging the magnitude of time delay deviation. The intermediate voltage range acts as a buffer and isolation to avoid abrupt or disjointed changes in direct reverse switching of logic.

[0102] For example, in some embodiments, the value range of the intermediate voltage range is approximately between 0.7V and 0.9V. Accordingly, the first voltage threshold can be approximately between 0.85V and 1.0V, and the second voltage threshold can be approximately between 0.6V and 0.75V.

[0103] It should be noted that the specific boundary values ​​of this intermediate voltage range (defined as (second voltage threshold, first voltage threshold)) can be dynamically adjusted by the performance or operational stability of the initial circuit design. Therefore, this invention does not limit its specific values.

[0104] For example, in some embodiments, the step of updating the value of the intermediate voltage range (such as at least one boundary, such as a first or second voltage threshold) includes: The value should be selected based on the degree of fluctuation in the power supply voltage.

[0105] Specifically, the smaller the fluctuation, the smaller the width of the intermediate voltage can be. When the fluctuation is high, the intermediate voltage range can be appropriately increased.

[0106] Specifically, in some embodiments, when the power supply voltage fluctuates significantly (e.g., load transients cause severe voltage jitter), or when the circuit has extremely high stability requirements for logic switching (misjudgment or oscillation at interval boundaries is not allowed), it is necessary to amplify the intermediate voltage range. Therefore, the larger the buffer, the less likely the two logics are to interfere with each other due to minor voltage fluctuations, resulting in a more stable system.

[0107] The degree of fluctuation can be the difference between the maximum and minimum voltage values ​​among multiple power supply voltage values ​​obtained under a set measurement period. Alternatively, it can be the average of the differences between multiple adjacent voltage values.

[0108] For example, in some embodiments, when the power supply voltage is exactly in the middle voltage range, the relationship between the final delay error and temperature can be monitored. If the delay error becomes more affected by temperature changes—for example, if the temperature rises significantly and the error also increases significantly—then it is recommended to activate the secondary adjustment mode. Conversely, if the temperature change is small and its impact on the delay error is also small, then it is recommended to activate the primary adjustment mode.

[0109] It should be noted that the differentiated management mode based on voltage level in this application is particularly suitable for circuit systems configured with power management strategies. For example, in a power management strategy, the voltage of the external power supply is dynamically adjusted for energy saving. For instance, the voltage is actively reduced to save power consumption under low load, and then restored to a high voltage under high load to meet performance requirements.

[0110] Specifically, in such Figure 3 In the circuit shown, the specific load size can be determined by the idle state of the circuit within a set period. For example, the more idle states there are, the smaller the load is.

[0111] In other words, this application is particularly suitable for scenarios where the power supply voltage does not fluctuate too frequently in a short period of time. For example, in power management strategies, when the voltage is reduced under low load due to energy-saving management, the power supply voltage is often maintained at a relatively uniform low level for a certain period of time. Therefore, a relatively uniform temperature judgment mechanism can also be maintained during this period of time, without frequent jumps.

[0112] Furthermore, in this embodiment, if the voltage value fluctuates too frequently and the amplitude is too large, it is necessary to restrictively activate the temperature determination mechanism. At this time, the user can manually select whether to activate the first-level adjustment mode or the second-level adjustment mode.

[0113] Specifically, in this embodiment, the following steps are also included: Identify the degree of voltage fluctuation under a set period; When the voltage fluctuation is less than the set threshold, S102-S104 are allowed to be executed. Otherwise, the user can manually select the first-level regulation mode or the second-level regulation mode.

[0114] In other words, this application will implement a single temperature determination mechanism in a relatively fixed scenario, thereby reducing the additional deviations that may occur under a single temperature determination mechanism.

[0115] Furthermore, in some embodiments, in the two-level adjustment mode, in order to simplify management, a fixed adjustment ratio is set for the inner and outer delay adjustment modules. For example, it is preferable to use the inner delay adjustment module for large-scale coarse adjustment (or play the main adjustment role), while the outer delay adjustment module for small-scale fine adjustment (or play the supplementary adjustment role).

[0116] For example, an internal delay adjustment module can be used to adjust approximately 80% to 90% of the delay deviation, while an external delay adjustment module can be used to adjust approximately 10% to 20% of the delay deviation.

[0117] It is worth noting that another core difference in the technical concept of this application is that, instead of pursuing a refined modification of the time delay adjustment module (such as a specific clock selection circuit) as in conventional thinking, it introduces voltage and temperature judgment mechanisms to dynamically manage the dual time delay adjustment module, based on the existing circuit design of the time delay adjustment module as much as possible, thereby reducing the impact of time delay deviation on system stability while controlling energy consumption.

[0118] Therefore, in this application, the specific connection settings of the delay adjustment modules, such as clock selectors and DFF devices, can all adopt existing solutions, and this invention does not limit them.

[0119] The present invention also provides a time delay adjustment system for semiconductor devices, comprising: A time delay management circuit with a two-stage adjustment mode includes: The main circuit is equipped with inverter I and inverter II; The first branch, and the input and output terminals of the first branch are respectively located at the output terminal of inverter II and between inverter I and inverter II. The first branch is provided with a first phase adjustment unit and a first adjustable delay buffer. The second branch has its input and output terminals located before the output terminal of inverter II and the input terminal of inverter I, respectively; the second branch is provided with a second phase adjustment unit and a gain-controllable inverter in sequence. A multi-phase clock generator is connected to a first phase adjustment unit and a second phase adjustment unit to form an internal time delay adjustment module in the time delay management circuit, and an external time delay adjustment module is also provided after the output node of the time delay management circuit. The two-level adjustment mode includes: a first-level adjustment mode that only enables the internal delay adjustment module, and a second-level adjustment mode that enables both the internal delay adjustment module and the external delay adjustment module. The mechanism selection module is used to select a temperature determination mechanism based on the power supply voltage; wherein, when the power supply voltage is greater than or equal to a first voltage threshold, the first determination mechanism is selected. Correspondingly, the system includes: a temperature recognition module for recognizing the current operating temperature; The first temperature determination module is used to determine whether the operating temperature is greater than or equal to the first set temperature. If so, it is recommended to switch or maintain the delay management circuit in the secondary adjustment mode; If not, it is recommended to switch or maintain the delay management circuit in the first-level adjustment mode.

[0120] In some embodiments, the mechanism selection module is further configured to select a second determination mechanism when the power supply voltage is less than or equal to a set second voltage threshold. The second temperature determination module determines whether the working temperature is greater than or equal to the second set temperature. If so, it is recommended to switch or maintain the delay management circuit in the first-level adjustment mode; If not, it is recommended to switch or maintain the delay management circuit in the secondary adjustment mode.

[0121] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0122] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a computer terminal (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of the present invention.

[0123] The embodiments of the present invention have been described above with reference to the accompanying drawings. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of the present invention without departing from the spirit and scope of the claims. All of these forms are within the protection scope of the present invention.

Claims

1. A time delay adjustment method applied to semiconductor devices, characterized in that, Including the following steps: S100 provides a delay management circuit with a two-stage adjustment mode, which includes: The main circuit is equipped with inverter I (1) and inverter II (2); The first branch, and the input and output terminals of the first branch are respectively located at the output terminal of the inverter II (2) and between the inverter I (1) and the inverter II (2). The first branch is provided with a first phase adjustment unit (3) and a first adjustable delay buffer (4). The second branch, and the input and output terminals of the second branch are respectively located before the output terminal of the inverter II (2) and the input terminal of the inverter I (1); the second branch is provided with a second phase adjustment unit (5) and a gain controllable inverter (6) in sequence. A multi-phase clock generator is connected to a first phase adjustment unit (3) and a second phase adjustment unit (5) to form an internal time delay adjustment module in the time delay management circuit, and an external time delay adjustment module (200) is provided after the output node (7) of the time delay management circuit. Correspondingly, the two-level adjustment mode includes: a first-level adjustment mode that only enables the internal delay adjustment module, and a second-level adjustment mode that enables both the internal delay adjustment module and the external delay adjustment module. S102, selects the temperature determination mechanism based on the power supply voltage; Specifically, when the power supply voltage is greater than or equal to a first voltage threshold, a first determination mechanism is selected. Correspondingly, the first determination mechanism includes: S103 identifies the current operating temperature; S104, determine whether the operating temperature is greater than or equal to the first set temperature; If so, the delay management circuit will be switched to or maintained in the secondary adjustment mode; If not, the delay management circuit will be switched to or maintained in the first-level adjustment mode.

2. The method according to claim 1, characterized in that, It also includes the following steps: If the power supply voltage is less than or equal to the set second voltage threshold, the second determination mechanism is selected. Correspondingly, the second determination mechanism includes: S103 identifies the current operating temperature; S105, determine whether the operating temperature is greater than or equal to the second set temperature; If so, the delay management circuit will be switched to or maintained in the first-level adjustment mode; If not, the delay management circuit will be switched to or maintained in the secondary adjustment mode.

3. The method according to claim 2, characterized in that, The first voltage threshold or the second voltage threshold has a default input value.

4. The method according to claim 3, characterized in that, Including the following steps: The first voltage threshold or the second voltage threshold is selected based on the degree of fluctuation of the power supply voltage.

5. The method according to claim 4, characterized in that, The greater the fluctuation, the higher the first voltage threshold, or the lower the second voltage threshold.

6. The method according to claim 1, characterized in that, Also includes: S106, Identify the current load size of the delay management circuit; S107, Update the power supply voltage according to the load size.

7. The method according to claim 6, characterized in that, The larger the load, the lower the recommended power supply voltage.

8. The method according to claim 6, characterized in that, The longer the idle time of the delay management circuit under the set working cycle, the smaller the load size.

9. A time delay adjustment system applied to semiconductor devices, characterized in that, include: A time delay management circuit with a two-stage adjustment mode includes: The main circuit is equipped with inverter I (1) and inverter II (2); The first branch, and the input and output terminals of the first branch are respectively located at the output terminal of the inverter II (2) and between the inverter I (1) and the inverter II (2). The first branch is provided with a first phase adjustment unit (3) and a first adjustable delay buffer (4). The second branch, and the input and output terminals of the second branch are respectively located before the output terminal of the inverter II (2) and the input terminal of the inverter I (1); the second branch is provided with a second phase adjustment unit (5) and a gain controllable inverter (6) in sequence. A multi-phase clock generator is connected to a first phase adjustment unit (3) and a second phase adjustment unit (5) to form an internal time delay adjustment module in the time delay management circuit. An external time delay adjustment module is also provided after the output node of the time delay management circuit. The two-level adjustment mode includes: a first-level adjustment mode that only enables the internal delay adjustment module, and a second-level adjustment mode that enables both the internal delay adjustment module and the external delay adjustment module. The mechanism selection module is used to select a temperature determination mechanism based on the power supply voltage; wherein, when the power supply voltage is greater than or equal to a first voltage threshold, the first determination mechanism is selected. Correspondingly, the system includes: a temperature recognition module for recognizing the current operating temperature; The first temperature determination module is used to determine whether the operating temperature is greater than or equal to the first set temperature. If so, the delay management circuit will be switched to or maintained in the secondary adjustment mode; If not, the delay management circuit will be switched to or maintained in the first-level adjustment mode.

10. The system according to claim 9, characterized in that, The mechanism selection module is also used to select a second determination mechanism when the power supply voltage is less than or equal to a set second voltage threshold. The second temperature determination module determines whether the working temperature is greater than or equal to the second set temperature. If so, the delay management circuit will be switched to or maintained in the first-level adjustment mode; If not, the delay management circuit will be switched to or maintained in the secondary adjustment mode.

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