High speed comparator with low misalignment voltage
Patent Information
- Application Number
- CN202611273503.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-08-21
- Publication Date
- 2026-09-22
AI Technical Summary
然而，输入差分对管的尺寸增加不可避免地引入了较大的节点寄生电容；同时，受限于比较器整体增益，在相同输入差分电压下，输出节点的压摆率（Slew Rate）受到约束，对节点电容进行充放电的有效电流仍显不足，导致该传统结构在高频开关应用中的响应速度难以满足系统需求
1、由于本发明的低失调电压的高速比较器的全差分运输放大电路的两个输入差分对管与对应负载电阻之间均串联有放大管，放大管的沟道类型与输入差分对管的沟道类型一致，且放大管沟道宽长比小于对应的输入差分对管的沟道宽长比，放大管的下方有电流源一。该结构构成了折叠式共源共栅（Cascode）放大级：一方面，它显著提升了单级增益；另一方面，通过将高频极点推向更高频率，有效降低了输出节点的等效寄生电容，从而大幅优化了第一级的瞬态响应特性，提升了比较器的响应速度，使得本方案的高速比较器的响应速度可满足高频开关的需求。
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Abstract
Description
Technical Field
[0001] This invention relates to the field of comparator technology, specifically a high-speed comparator with low offset voltage. Background Technology
[0002] As the switching frequency of DC-DC converters continues to increase, comparators with low offset voltage and high-speed response characteristics have become particularly critical, with typical applications including inductor current zero-crossing detection.
[0003] The circuit structure of a traditional low offset voltage high speed comparator is as follows: Figure 1 As shown, a two-stage architecture of "first-stage fully differential op-amp + second-stage transconductance amplifier" is typically used. The first-stage fully differential op-amp amplifies the differential input voltage and transmits the differential output voltage to the second-stage transconductance amplifier. The second stage rapidly charges and discharges the parasitic capacitance of the output node through the current difference between the PMOS and NMOS transistors in the output stage, and then generates the final logic level after being shaped by two stages of inverters. To reduce the input offset voltage, traditional low-offset voltage high-speed comparators use a resistive load in the first-stage fully differential op-amp and introduce a resistor in the second-stage transconductance amplifier to improve gain. However, the increased size of the input differential pair transistors inevitably introduces a larger node parasitic capacitance; at the same time, limited by the overall comparator gain, the slew rate of the output node is constrained under the same input differential voltage, and the effective current for charging and discharging the node capacitance is still insufficient, making it difficult for this traditional structure to meet the system requirements in high-frequency switching applications. Summary of the Invention
[0004] The technical problem to be solved by the present invention is to provide a high-speed comparator with low offset voltage. The high-speed comparator has a fast response speed and can be applied to high-frequency switching.
[0005] To solve the above problems, the following technical solutions are provided: The low offset voltage high-speed comparator of the present invention includes a fully differential transport amplifier circuit and a transconductance amplifier; the fully differential transport amplifier circuit is adapted to the transconductance amplifier, the fully differential transport amplifier circuit is used to amplify the input voltage to form a differential output voltage, and the transconductance amplifier is used to form a logic level based on the differential output voltage; characterized in that, an amplifying transistor is connected in series between each of the two input differential pairs of transistors in the fully differential transport amplifier circuit and the corresponding load resistor, the channel type of the amplifying transistor is the same as the channel type of the input differential pairs of transistors, and the channel width-to-length ratio of the amplifying transistor is smaller than the channel width-to-length ratio of the corresponding input differential pairs of transistors; a current source is located below the amplifying transistor.
[0006] In this configuration, a source follower is connected between the amplifying transistor and the corresponding load resistor. A load transistor is connected in series between the upper end of the source follower and the power supply VCC. The gate and drain of the load transistor are shorted together. A current source is located below the load transistor.
[0007] There are two fully differential transport amplifier circuits, each with an amplifying transistor and a source follower. The channel width of the input differential pair transistors in the second fully differential transport amplifier circuit is smaller than that in the first fully differential transport amplifier circuit. The output voltage of the first fully differential transport amplifier circuit is the external input VIN+ and VIN-. The first fully differential transport amplifier circuit amplifies VIN+ and VIN- to obtain VO1- and VO1+, which are used as the output voltage of the second fully differential transport amplifier circuit. The second fully differential transport amplifier circuit amplifies VO1- and VO1+ to obtain VO2+ and VO2-, which are used as the differential output voltage input to the transconductance amplifier.
[0008] The amplifying tube is the output branch tube of a current mirror circuit with a current source IB1 on the reference branch, which replicates the current of the current source IB1 to form current source one.
[0009] A current transistor is connected in series between the lower end of the source follower and GND. The current transistor is the output branch transistor of the current mirror circuit with current source IB2 on the reference branch, and the current of current source IB2 is replicated to form current source two.
[0010] The channel type of the source follower is opposite to that of the input differential pair transistor, the channel type of the load transistor is opposite to that of the source follower, and the channel type of the current transistor is the same as that of the source follower.
[0011] The reference branch of the current mirror circuit with current source IB1 contains NMOS transistor MN1. The drain of NMOS transistor MN1 is connected to the power supply VCC through the current source IB1, and the source of NMOS transistor MN1 is grounded.
[0012] The reference branch of the current mirror circuit with current source IB2 contains NMOS transistor MN2. The drain of NMOS transistor MN2 is connected to the power supply VCC through the current source IB2, and the source of NMOS transistor MN2 is grounded.
[0013] The output terminal VO of the transconductance amplifier is converted into the output terminal VOUT of a high-speed comparator through two stages of inverters.
[0014] The above approach has the following advantages: 1. In the fully differential transport amplifier circuit of the low offset voltage high-speed comparator of this invention, an amplifying transistor is connected in series between each of the two input differential pairs and their corresponding load resistors. The channel type of the amplifying transistor is the same as that of the input differential pairs, and the aspect ratio of the amplifying transistor's channel is smaller than that of the corresponding input differential pairs. A current source is located below the amplifying transistor. This structure constitutes a folded cascode amplifier stage: on the one hand, it significantly improves the single-stage gain; on the other hand, by pushing the high-frequency poles to higher frequencies, it effectively reduces the equivalent parasitic capacitance of the output node, thereby greatly optimizing the transient response characteristics of the first stage and improving the comparator's response speed. This allows the response speed of the high-speed comparator in this solution to meet the requirements of high-frequency switching.
[0015] 2. This solution sets a source follower on the first fully differential operational amplifier to perform level conversion and amplitude compression of the high-swing differential voltage, thereby providing more suitable driving conditions for the subsequent stages.
[0016] 3. This scheme uses a second fully differential operational amplifier, and the input differential pair of the second fully differential operational amplifier can use shorter channel devices, thereby obtaining higher transconductance and bandwidth.
[0017] 4. This solution introduces another source follower between the second fully differential op-amp to improve the driving capability and transient response of the transconductance amplifier input pair. Attached Figure Description
[0018] Figure 1 This is a schematic diagram of the comparator structure in the background technology. Figure 2A This is a schematic diagram of the low offset voltage high-speed comparator of the present invention (including a first-stage fully differential operational amplifier, a second-stage source follower, a third-stage fully differential operational amplifier + a fourth-stage source follower). Figure 2B This is a schematic diagram of the low offset voltage high-speed comparator of the present invention (including the fifth stage transconductance amplifier). Figure 3 This is a DC sweep simulation result of the high-speed comparator with low offset voltage in the embodiment; Figure 4 This is a Monte Carlo simulation result of the high-speed comparator with low offset voltage in the embodiment; Figure 5 This is a simulation result of the transient response of the high-speed comparator with low offset voltage in the embodiment, with a voltage change slope of 0.01V / ms at VIN+. Figure 6 This is a simulation result of the transient response of the high-speed comparator with low offset voltage in the embodiment, with a voltage change slope of 0.1V / ms at VIN+. Figure 7This is a simulation result of the transient response of the high-speed comparator with low offset voltage in the embodiment, where the slope of the VIN+ voltage change is 1V / ms. Detailed Implementation
[0019] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.
[0020] like Figure 2A and Figure 2B As shown, the low offset voltage high-speed comparator of the present invention includes a fully differential transport amplifier circuit and a transconductance amplifier. The fully differential transport amplifier circuit is adapted to the transconductance amplifier. The fully differential transport amplifier circuit is used to amplify the input voltage to form a differential output voltage, and the transconductance amplifier is used to form a logic level based on the differential output voltage. An amplifying transistor is connected in series between each of the two input differential transistor pairs and their corresponding load resistors. The channel type of the amplifying transistor is the same as that of the input differential transistor pair, and the channel width-to-length ratio of the amplifying transistor is smaller than that of the corresponding input differential transistor pair. A current source is located below the amplifying transistor. A source follower is connected between each amplifying transistor and its corresponding load resistor. A load transistor is connected in series between the upper end of the source follower and the power supply VCC. The gate and drain of the load transistor are shorted. A second current source is located below the load transistor. There are two fully differential transport amplifier circuits. Each circuit has an amplifying transistor and a source follower. In the second fully differential transport amplifier circuit, the channel width of the input differential pair is smaller than that in the first circuit. The first fully differential transport amplifier circuit receives external inputs VIN+ and VIN-. It amplifies VIN+ and VIN- to obtain VO1- and VO1+, which are then used as the input voltage for the second circuit. The second fully differential transport amplifier circuit amplifies VO1- and VO1+ to obtain VO2+ and VO2-, which are the differential output voltages input to the transconductance amplifier.
[0021] Specifically, the first fully differential transport amplifier circuit and its corresponding source follower form a first-stage fully differential op-amp + a second-stage source follower; the second fully differential transport amplifier circuit and its corresponding source follower form a third-stage fully differential op-amp + a fourth-stage source follower; and the transconductance amplifier forms a fifth-stage transconductance amplifier. To significantly improve the comparator's response speed while maintaining low input offset voltage characteristics, a pair of smaller MOSFETs of the same type can be added between the input differential pair transistors and the load resistor of the first-stage fully differential op-amp. This structure constitutes a folded cascode amplifier stage: on the one hand, it significantly improves the single-stage gain; on the other hand, by pushing the high-frequency poles to higher frequencies, it effectively reduces the equivalent parasitic capacitance of the output node, thereby greatly optimizing the transient response characteristics of the first stage. In the first-stage fully differential op-amp, a large-value load resistor is usually used to achieve high voltage gain; however, an excessively large differential output voltage will weaken the driving capability of the subsequent differential pair, thus limiting the overall response speed of the comparator. To address this, the present invention inserts a source follower after the first stage to perform level conversion and amplitude compression on the high-swing differential voltage, thereby providing more suitable driving conditions for subsequent stages. The intrinsic gain of a resistively loaded fully differential op-amp is limited; simultaneously, to suppress input offset voltage, the first-stage differential pair typically uses a long channel length, which inevitably increases node parasitic capacitance and further limits the gain and bandwidth of this stage. Therefore, while allowing for a moderate sacrifice in response delay, a third-stage fully differential op-amp is added after the second-stage source follower. Its input differential pair can use shorter channel devices to achieve higher transconductance and bandwidth. Finally, another source follower is introduced between the third-stage fully differential op-amp and the final stage transconductance amplifier to improve the driving capability and transient response of the transconductance amplifier's input pair. In summary, the improved comparator presents a five-stage cascaded architecture: "fully differential op-amp → source follower → fully differential op-amp → source follower → transconductance amplifier".
[0022] like Figure 2AAs shown, in this embodiment, the first-stage fully differential operational amplifier includes PMOS transistors MP1, MP2, MP3, and MP4. PMOS transistors MP1 and MP2 are the differential pair of the first-stage fully differential operational amplifier, while PMOS transistors MP3 and MP4 are amplifying transistors. The second-stage source follower includes NMOS transistors MN3 and MN4, and the load transistors are PMOS transistors MP5 and MP6. The sources of PMOS transistors MP1 and MP2 are both connected to the power supply VCC through current source IB3. Power supply VCC and current source IB3 are the driving sources of the first-stage fully differential operational amplifier. The gate of PMOS transistor MP1 is connected to the external input power supply VIN+, and the gate of PMOS transistor MP2 is connected to the external input power supply VIN-. The drain of PMOS transistor MP1 is connected to the source of PMOS transistor MP3. The drain of PMOS transistor MP3 is connected to the gate of NMOS transistor MN3 and one end of the load resistor R1. Current source one is located between the drain of PMOS transistor MP3 and the load resistor R1, and the other end of the load resistor R1 is grounded. The drain of PMOS transistor MP2 is connected to the source of PMOS transistor MP4. The drain of PMOS transistor MP4 is connected to the gate of NMOS transistor MN4 and one end of the load resistor R2. Current source one is located between the drain of PMOS transistor MP4 and the load resistor R2, and the other end of the load resistor R2 is connected to GND. The drain of NMOS transistor MN3 is connected to the drain and gate of PMOS transistor MP5. The source of PMOS transistor MP5 is connected to the power supply VCC. Current source two is located between the source of NMOS transistor MN3 and GND. The source of NMOS transistor MN3 outputs VO1-. The drain of NMOS transistor MN4 is connected to the drain and gate of PMOS transistor MP6. The source of PMOS transistor MP6 is connected to the power supply VCC. Current source two is located between the source of NMOS transistor MN4 and GND. The source of NMOS transistor MN4 outputs VO1+.
[0023] like Figure 2AAs shown, in this embodiment, the third-stage fully differential operational amplifier includes PMOS transistors MP7, MP8, MP9, and MP10. PMOS transistors MP7 and MP8 are the differential pair transistors of the third-stage fully differential operational amplifier, while PMOS transistors MP9 and MP10 are amplifying transistors. The fourth-stage source follower includes NMOS transistors MN7 and MN8, and the load transistors are PMOS transistors MP11 and MP12. The sources of PMOS transistors MP7 and MP8 are both connected to the power supply VCC through current source IB4. The power supply VCC and current source IB4 are the driving sources of the third-stage fully differential operational amplifier. The gate of PMOS transistor MP7 is connected to VO1+, and the gate of PMOS transistor MP8 is connected to VO1-. The drain of PMOS transistor MP7 is connected to the source of PMOS transistor MP9. The drain of PMOS transistor MP9 is connected to the gate of NMOS transistor MN7 and one end of load resistor R3. Current source one is located between the drain of PMOS transistor MP9 and load resistor R3, and the other end of load resistor R3 is connected to GND. The source of NMOS transistor MN7 outputs VO2-. The drain of PMOS transistor MP8 is connected to the source of PMOS transistor MP10. The drain of PMOS transistor MP10 is connected to the gate of NMOS transistor MN8 and one end of load resistor R4. Current source one is located between the drain of PMOS transistor MP10 and load resistor R4, and the other end of load resistor R4 is connected to GND. The source of NMOS transistor MN8 outputs VO+. The drain of NMOS transistor MN7 is connected to the drain and gate of PMOS transistor MP11. The source of PMOS transistor MP11 is connected to power supply VCC. Power source two is located between the source of NMOS transistor MN7 and GND. The drain of NMOS transistor MN8 is connected to the drain and gate of PMOS transistor MP12. The source of PMOS transistor MP12 is connected to power supply VCC. Power supply source 2 is located between the source of NMOS transistor MN8 and GND.
[0024] like Figure 2A and Figure 2BAs shown, in this embodiment, the fifth-stage transconductance amplifier includes PMOS transistors MP13, MP14, MN11, MN12, MN13, and MN14. The gate of PMOS transistor MP13 is connected to VO2-, and the gate of PMOS transistor MP14 is connected to VO2+. The sources of PMOS transistors MP13 and MP14 are connected to power supply VCC via power supply IB5. The drain of PMOS transistor MP13 is connected to the gate of NMOS transistor MN11, the drain of NMOS transistor MN12, and one end of resistor R5, while the other end of resistor R5 is connected to the gate of NMOS transistor MN12. The source of NMOS transistor MN12 is connected to GND. The drain of NMOS transistor MN11 is connected to the drain and gate of PMOS transistor MP15, the source of PMOS transistor MP15 is connected to VCC, and the source of NMOS transistor MN11 is grounded. The drain of PMOS transistor MP14 is connected to the gate of NMOS transistor MN14, the drain of NMOS transistor MN13, and one end of resistor R6. The other end of resistor R6 is connected to the gate of NMOS transistor MN13. The gate of NMOS transistor MN13 is connected to the gate of NMOS transistor MN12. The source of NMOS transistor MN13 is connected to GND. The drain of NMOS transistor MN14 is connected to the drain and gate of PMOS transistor MP16. The source of PMOS transistor MP16 is connected to VCC, the source of NMOS transistor MN14 is grounded, and the gate of PMOS transistor MP16 is connected to the gate of PMOS transistor MP15. The drain of NMOS transistor MN14 is the output terminal VO of the fifth-stage transconductance amplifier (i.e., the transconductance amplifier).
[0025] In some possible embodiments, the amplifying transistor is the output branch transistor of a current mirror circuit with current source IB1 on the reference branch, and the current of current source IB1 is replicated to form current source one. A current transistor is connected in series between the lower end of the source follower and GND. This current transistor is the output branch transistor of a current mirror circuit with current source IB2 on the reference branch, and the current of current source IB2 is replicated to form current source two.
[0026] Specifically, such as Figure 2A and Figure 2BAs shown, the reference branch of the current mirror circuit with current source IB1 contains an NMOS transistor MN1. The drain of NMOS transistor MN1 is connected to the power supply VCC through current source IB1, and the source of NMOS transistor MN1 is connected to GND. The gates of PMOS transistors MP3, MP4, MP9, and MP10 are all connected to the gate of NMOS transistor MN1, thus forming the output branches of the current mirror circuit with current source IB1. Current source one is formed between PMOS transistor MP3 and load resistor R1, PMOS transistor MP4 and load resistor R2, PMOS transistor MP9 and load resistor R3, and PMOS transistor MP10 and load resistor R4. The reference branch of the current mirror circuit with current source IB2 contains an NMOS transistor MN2. The drain of NMOS transistor MN2 is connected to the power supply VCC through current source IB2, the source of NMOS transistor MN2 is connected to GND, and the gate and drain of NMOS transistor MN2 are connected. NMOS transistors MN5, MN6, MN9, and MN10 are all current-carrying transistors. The gates of NMOS transistors MN5, MN6, MN9, and MN10 are all connected to the gate of NMOS transistor MN2. The drain of NMOS transistor MN5 is connected to the source of NMOS transistor MN3, and the source of NMOS transistor MN5 is grounded. NMOS transistor MN5 acts as the output branch of a current mirror circuit with current source IB2, replicating the current from current source IB2 between the source of NMOS transistor MN3 and GND, forming current source two. The drain of NMOS transistor MN6 is connected to the source of NMOS transistor MN4, and the source of NMOS transistor MN6 is grounded. NMOS transistor MN6 acts as the output branch of a current mirror circuit with current source IB2, replicating the current from current source IB2 between the source of NMOS transistor MN4 and GND, forming current source two. The drain of NMOS transistor MN9 is connected to the source of NMOS transistor MN7. The source of NMOS transistor MN9 is grounded. NMOS transistor MN9 acts as the output branch of a current mirror circuit with current source IB2, replicating the current from current source IB2 between the source of NMOS transistor MN7 and GND, forming current source two. The drain of NMOS transistor MN10 is connected to the source of NMOS transistor MN8. The source of NMOS transistor MN10 is grounded. NMOS transistor MN10 acts as the output branch of a current mirror circuit with current source IB2, replicating the current from current source IB2 between the source of NMOS transistor MN8 and GND, forming current source two.
[0027] In some possible embodiments, the channel type of the source follower is opposite to that of the input differential pair transistor, the channel type of the load transistor is opposite to that of the source follower, and the channel type of the current transistor is the same as that of the source follower.
[0028] In some possible embodiments, the output VO of the transconductance amplifier is formed into the output VOUT of a high-speed comparator through two stages of inverters.
[0029] Taking Dongbu's 0.18µm BCD process as an example, this embodiment demonstrates the construction of a low offset voltage high-speed comparator circuit. With VCC set to 5V and VIN- to 600mV, DC sweep simulation was performed by changing the VIN+ voltage. The results show a threshold voltage of 599.985mV and an input offset voltage of 15mV. Figure 3 As shown.
[0030] After completing the DC sweep simulation, a Monte Carlo simulation of the comparator's threshold voltage was performed. The results showed that the standard deviation of the offset voltage was 990 mV. Figure 4 As shown.
[0031] Transient response simulations were performed with the slope of the VIN+ voltage change set to 0.01V / ms, 0.1V / ms, and 1V / ms, respectively. The results show that the switching delays of the output logic level are 11.9ns, 9.0ns, and 10.6ns, respectively. Figure 5 , Figure 6 and Figure 7 As shown.
[0032] The high-speed comparator in this solution presents a five-stage cascaded architecture of "fully differential op-amp → source follower → fully differential op-amp → source follower → transconductance amplifier", which reduces offset voltage and improves response speed, and can be applied to high-frequency DC-DC converters.
[0033] The above description is merely an embodiment of this application and is not intended to limit the scope of protection of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application. It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.
[0034] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.
[0035] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
Claims
1. A high-speed comparator with low offset voltage, comprising a fully differential transport amplifier circuit and a transconductance amplifier; wherein the fully differential transport amplifier circuit is adapted to the transconductance amplifier, the fully differential transport amplifier circuit is used to amplify the input voltage to form a differential output voltage, and the transconductance amplifier is used to form a logic level based on the differential output voltage; characterized in that, The fully differential transport amplifier circuit has an amplifying transistor connected in series between each of the two input differential pairs and the corresponding load resistor. The channel type of the amplifying transistor is the same as that of the input differential pairs, and the width-to-length ratio of the amplifying transistor's channel is smaller than that of the corresponding input differential pairs. There is a current source below the amplifying transistor.
2. The high-speed comparator with low offset voltage as described in claim 1, characterized in that, Each amplifier tube is connected to a source follower between itself and its corresponding load resistor. A load tube is connected in series between the upper end of the source follower and the power supply VCC. The gate and drain of the load tube are shorted together. There is a second current source below the load tube.
3. The high-speed comparator with low offset voltage as described in claim 2, characterized in that, There are two fully differential transport amplifier circuits, each with an amplifying transistor and a source follower. The channel width of the input differential pair transistors in the second fully differential transport amplifier circuit is smaller than that in the first fully differential transport amplifier circuit. The output voltage of the first fully differential transport amplifier circuit is the external input VIN+ and VIN-. The first fully differential transport amplifier circuit amplifies VIN+ and VIN- to obtain VO1- and VO1+, which are used as the output voltage of the second fully differential transport amplifier circuit. The second fully differential transport amplifier circuit amplifies VO1- and VO1+ to obtain VO2+ and VO2-, which are used as the differential output voltage input to the transconductance amplifier.
4. The high-speed comparator with low offset voltage as described in claim 1, characterized in that, The amplifying tube is the output branch tube of a current mirror circuit with a current source IB1 on the reference branch, which replicates the current of the current source IB1 to form current source one.
5. The high-speed comparator with low offset voltage as described in claim 2, characterized in that, A current transistor is connected in series between the lower end of the source follower and GND. The current transistor is the output branch transistor of the current mirror circuit with current source IB2 on the reference branch, and the current of current source IB2 is replicated to form current source two.
6. The high-speed comparator with low offset voltage as described in claim 5, characterized in that, The channel type of the source follower is opposite to that of the input differential pair transistor, the channel type of the load transistor is opposite to that of the source follower, and the channel type of the current transistor is the same as that of the source follower.
7. The high-speed comparator with low offset voltage as described in claim 4, characterized in that, The reference branch of the current mirror circuit with current source IB1 contains NMOS transistor MN1. The drain of NMOS transistor MN1 is connected to the power supply VCC through the current source IB1, and the source of NMOS transistor MN1 is grounded.
8. The high-speed comparator with low offset voltage as described in claim 5, characterized in that, The reference branch of the current mirror circuit with current source IB2 contains NMOS transistor MN2. The drain of NMOS transistor MN2 is connected to the power supply VCC through the current source IB2, and the source of NMOS transistor MN2 is grounded.
9. The high-speed comparator with low offset voltage as described in claim 1, characterized in that, The output terminal VO of the transconductance amplifier is converted into the output terminal VOUT of a high-speed comparator through two stages of inverters.