A radio frequency switch matrix control method, system, device and storage medium

Abstract

This application relates to a radio frequency (RF) switch matrix control method, system, device, and storage medium, belonging to the field of RF control technology. The method includes: acquiring a target link set, which contains at least one target link, each target link including an input port and an output port; performing conflict detection on the target link set to determine if any two target links have the same input port or the same output port; if so, terminating the switching operation and outputting fault information; if not, sending a global shutdown signal to all switch chips in the RF switch matrix; while maintaining the global shutdown signal, generating channel selection signals for the switch chips associated with each target link, and synchronously sending turn-on signals to all associated switch chips to simultaneously turn on all target links, thus completing the switching operation. This application effectively avoids the risk of signal conflicts and instrument damage caused by contention for multiple command ports.

Description

Technical Field

[0001] This application relates to the field of radio frequency control technology, and in particular to a radio frequency switch matrix control method, system, device and storage medium. Background Technology

[0002] In RF test systems, RF switch matrices are used to selectively switch multiple input signals to multiple outputs, thereby establishing a routing connection between the signal source and the device under test. Traditional RF switch matrix control methods typically involve a host computer issuing path configuration commands, which are then parsed by an embedded controller to directly rewrite the address lines of the switch chip, completing the channel switching.

[0003] In practical testing applications, the host computer often needs to issue multiple channel switching commands simultaneously, such as switching multiple test channels to achieve parallel testing. When multiple commands involve the same input port or the same output port, multiple signals may simultaneously compete for the same port resource, causing signal crosstalk and even damaging precision RF instruments such as spectrum analyzers and signal generators. However, existing control logic typically parses and executes multiple switching commands one by one until it reaches the conflicting port, at which point it discovers that the resource is already occupied. By then, a signal conflict has already occurred, and the system can only report an error after the conflict occurs, unable to prevent damage. Therefore, the risk of instrument damage due to signal conflict is high, and this needs to be improved. Summary of the Invention

[0004] In order to avoid signal conflicts and instrument damage risks caused by contention for multiple command ports without increasing hardware costs, this application provides a radio frequency switch matrix control method, system, device and storage medium.

[0005] In a first aspect, this application provides a radio frequency switch matrix control method, including: Obtain a set of target links, which includes at least one target link for which a radio frequency signal transmission path needs to be established, and each target link includes an input port and an output port; Conflict detection is performed on the target link set to determine whether any two target links have the same input port or the same output port; If so, it indicates a conflict, and the switching operation of all target links in the target link set is terminated and fault information is output; If not, a switching operation is performed, which includes: sending a global shutdown signal to all switch chips in the RF switch matrix; generating channel selection signals for each switch chip associated with the target link while maintaining the global shutdown signal; and after all channel selection signals for the switch chips associated with the target link are generated, synchronously sending a conduction signal to all the associated switch chips to enable all the target links to conduct simultaneously, thus completing the switching operation.

[0006] By adopting the above technical solution, the problem of signal crosstalk and instrument damage is avoided by detecting whether there are the same input ports or the same output ports in the target link set before switching. If there is a conflict, all switching will be terminated and fault information will be output. If there is no conflict, the problem of instantaneous multi-channel conduction and temporary illegal paths during the switching process is eliminated by the three-step timing sequence of first global shutdown, then generating channel selection signal and finally synchronous conduction.

[0007] Optionally, after the switching operation is completed, the method further includes: After the switching operation is completed, the status feedback signal of each of the relevant switching chips is obtained. The status feedback signal is used to characterize the actual on / off state of each channel inside the switching chip. Also, the presence of radio frequency signals at the input and output ports of each target link is detected. Based on the status feedback signal, determine whether the actual on / off state of each of the related switch chips is consistent with the conduction state corresponding to the channel selection signal, and determine whether each of the target links is actually conducting based on the detection result of the radio frequency signal; If both of the above judgments are true, then the switching is considered normal; If any of the above judgments is negative, a fault is considered to have occurred, and the fault level is determined based on the preset fault classification and handling strategy, and the corresponding handling operation is performed according to the fault level.

[0008] By adopting the above technical solution, after the switching is completed, the actual on / off status of the internal channel is verified by reading the status feedback signal of the switch chip. At the same time, the presence of radio frequency signals at both ends of the target link is detected to verify whether the actual signal transmission is completed. Only when both verifications pass is the switching considered normal. If either fails, it is handled in stages. This solves the problem of address latching errors caused by electromagnetic interference under open-loop control, which prevents the detection of abnormalities.

[0009] Optionally, the step of maintaining the global shutdown signal refers to sending a global shutdown signal to all switch chips in the RF switch matrix, waiting for a preset first maintenance period, and then performing the step of generating channel selection signals for each switch chip associated with each target link. Furthermore, after all the channel selection signals of the switch chips related to the target link are generated, the conduction signal is sent synchronously to all the related switch chips after waiting for a preset second maintenance period.

[0010] By adopting the above technical solution, by limiting the global shutdown signal to be maintained for a first duration before generating the channel selection signal, and by requiring the channel selection signal to be maintained for a second duration before sending the turn-on signal, complete shutdown time and address stabilization time are provided for each switch chip, thus standardizing the timing parameters and making it compatible with different models of switch chips.

[0011] Optionally, after the switching operation is completed, the method further includes: The actual response delay data of each of the relevant switching chips in this switching operation is obtained. The actual response delay data is the time length from sending the conduction signal to obtaining the status feedback signal and determining conduction. The response delay change trend of each of the relevant switching chips is generated based on the historical actual response delay data of each of the relevant switching chips; When the response delay change trend of any of the related switching chips meets the preset first adjustment condition, the first maintenance period of the corresponding switching chip is increased; When the response delay change trend of any of the related switching chips meets the preset second adjustment condition, the second maintenance period of the corresponding switching chip is increased.

[0012] By adopting the above technical solution, the response delay of each switch chip from sending the conduction signal to the status feedback confirmation of conduction during each switching is recorded, and the response delay trend of each switch chip as the number of uses is generated. When the trend meets the adjustment conditions, the maintenance period of the corresponding switch chip is increased, so that the timing parameters increase adaptively with the aging degree of the switch, thus solving the problem that fixed timing parameters cannot adapt to the degradation of response delay after long-term use of the switch.

[0013] Optionally, generating channel selection signals for the switching chips associated with each of the target links includes: Obtain the latest historical actual response delay data of each switching chip in each candidate path corresponding to each target link. The candidate path is a complete sequence of switching chips and channels at each level that need to be passed from the input port to the output port of the target link. Each candidate path corresponds to a delay set consisting of the response delay data of each level of switching chips on the path. Based on the delay set corresponding to each candidate path, calculate the comprehensive evaluation value of the response delay for each candidate path. Based on the comprehensive evaluation value of the response delay of each candidate path, a target path is selected from the candidate paths of each target link; Based on the target path of each target link, channel selection signals for the switching chips associated with each target link are generated respectively.

[0014] By adopting the above technical solution, the latest response delay data of each switching chip on multiple candidate paths of each target link is obtained, the comprehensive delay evaluation value of each candidate path is calculated, and the candidate path with the smallest comprehensive evaluation value is selected as the target path and the corresponding channel selection signal is generated. This makes the path selection based on the latest actual response state of each switching chip, avoiding the decrease in switching efficiency caused by the selection of high-delay switching chips.

[0015] Optionally, the method further includes: Based on the execution record of the switching operation, obtain the parameter configuration data and the corresponding switching result quality evaluation value for each switching operation. The parameter configuration data includes at least one of the following: the first maintenance period and / or the second maintenance period corresponding to each switch chip used during the execution of the switching operation, and the target path selected during the execution of the switching operation. Based on the parameter configuration data and corresponding handover result quality evaluation values ​​of multiple historical handover operations, the target parameter configuration data is determined through a preset parameter optimization algorithm. Based on the target parameter configuration data, update the first maintenance period and / or the second maintenance period used in subsequent handover operations, and / or update the path evaluation weights used when selecting the target path in subsequent handover operations.

[0016] By adopting the above technical solution, by accumulating the parameter configuration data and the quality evaluation value of each switch, the parameter optimization algorithm is used to find the parameter configuration combination that makes the quality evaluation value optimal from a large amount of historical data, and the maintenance period and path evaluation weights used in subsequent applications are updated accordingly, thus solving the problem that manual parameter tuning is difficult to cover the optimization space of multiple switches and multiple parameter combinations.

[0017] Optionally, the step of synchronously sending a turn-on signal to all the relevant switching chips includes: Obtain the latest historical actual response delay data for each of the relevant switching chips; Based on the maximum value of the latest historical actual response delay data of each of the relevant switch chips, the delay compensation value of each of the relevant switch chips is calculated respectively. Based on the delay compensation value of each related switch chip, the transmission time of the conduction signal of each related switch chip is determined, so that the transmission time of the conduction signal of each related switch chip is different and sorted according to the size of the delay compensation value. According to the determined turn-on signal transmission time of each of the relevant switch chips, a turn-on signal is sent to each of the relevant switch chips respectively, so that the actual turn-on time of each of the relevant switch chips is aligned.

[0018] By adopting the above technical solution, the latest response delay data of each relevant switch chip is obtained, and the delay compensation value of each chip is calculated based on the maximum value. Based on this, the transmission time of the conduction signal of each chip is determined in a differentiated manner, so that although each chip receives the conduction signal at different times, the actual conduction time is aligned after each response delay. This solves the problem that the actual conduction time is inconsistent after synchronous transmission of conduction signals due to individual differences of different switches.

[0019] Secondly, this application provides a radio frequency switch matrix control system, comprising: The target link acquisition module is used to acquire a set of target links, wherein the set of target links includes at least one target link for which a radio frequency signal transmission path needs to be established, and each target link includes an input port and an output port; The link conflict detection module is used to perform conflict detection on the target link set and determine whether there are any two target links that have the same input port or the same output port. The link conflict handling module is used to terminate the switching operation of all target links in the target link set and output fault information if a conflict exists. The target link switching module is used to perform a switching operation if there is no conflict. The switching operation includes: sending a global shutdown signal to all switch chips in the RF switch matrix; generating channel selection signals for each switch chip associated with the target link while maintaining the global shutdown signal; and after all channel selection signals for the switch chips associated with the target link are generated, synchronously sending a turn-on signal to all the associated switch chips to turn on all the target links at the same time, thereby completing the switching operation.

[0020] Thirdly, this application provides a radio frequency switch matrix control device, including a memory and a processor, wherein the memory stores a computer program that can be loaded by the processor and executed as described in any of the first aspects.

[0021] Fourthly, this application provides a computer-readable storage medium storing a computer program that can be loaded by a processor and executed as described in any of the first aspects.

[0022] In summary, this application includes at least one of the following beneficial technical effects: In this application, by detecting whether there are identical input ports or identical output ports in the target link set before switching, if there is a conflict, all switching is terminated and fault information is output, thus avoiding signal crosstalk and instrument damage; when there is no conflict, the three-step timing sequence of first globally shutting down, then generating channel selection signals, and finally synchronously turning on eliminates the problem of instantaneous multi-channel conduction and temporary illegal paths during the switching process.

[0023] Furthermore, after the switching is completed, the actual on / off status of the internal channel is verified by reading the status feedback signal of the switch chip. At the same time, the presence of radio frequency signals at both ends of the target link is detected to verify whether the actual signal transmission is completed. Only when both verifications pass is the switching considered normal. If either fails, it is handled in stages. This solves the problem of address latching errors caused by electromagnetic interference under open-loop control, which prevents the detection of abnormalities.

[0024] Furthermore, by limiting the global shutdown signal to a first duration before generating the channel selection signal, and the channel selection signal to a second duration before sending the turn-on signal, complete shutdown time and address stabilization time are provided for each switch chip, thus standardizing the timing parameters and making them compatible with different models of switch chips. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 This is a flowchart illustrating a radio frequency switch matrix control method disclosed in an embodiment of this application.

[0027] Figure 2 This application discloses a structural block diagram of an on / off radio frequency switch matrix control system.

[0028] Explanation of reference numerals in the attached diagram: 11. Target link acquisition module; 12. Link conflict detection module; 13. Link conflict handling module; 14. Target link switching module. Detailed Implementation

[0029] The following is in conjunction with the appendix Figure 1-2 This application will be described in further detail.

[0030] This application discloses a radio frequency (RF) switch matrix control method (hereinafter referred to as the control method). The execution entity of the control method is an RF switch matrix control system (hereinafter referred to as the control system), which includes an embedded MCU main control unit and an RF switch matrix. The embedded MCU main control unit is the core of the control system's computation and control, and it has built-in embedded software programs that execute the control method of this application. The RF switch matrix is ​​the execution component of the control system, composed of multiple cascaded switch chips (such as SP4T, SP6T), and is controlled by control signals issued by the embedded MCU main control unit to establish or disconnect the RF signal transmission path between each input port and each output port. The embedded MCU main control unit and the RF switch matrix are connected via signal lines. The embedded MCU main control unit outputs control levels to the enable pins and address pins of each switch chip in the RF switch matrix through its general-purpose input / output interface to drive each switch chip to perform channel turn-on or turn-off actions. The following will be described in conjunction with the appendix. Figure 1 This section provides a detailed explanation of the process by which the control system executes the control method.

[0031] S101, Obtain the target link set. The target link set contains at least one target link for which an RF signal transmission path needs to be established. Each target link includes an input port and an output port.

[0032] S102, perform conflict detection on the target link set to determine whether there are any two target links with the same input port or the same output port.

[0033] S103, if so, it indicates a conflict, and the switching operation of all target links in the target link set is terminated and fault information is output.

[0034] S104, if not, then perform a switching operation, which includes: sending a global shutdown signal to all switch chips in the RF switch matrix; during the period of maintaining the global shutdown signal, generating channel selection signals for each target link-related switch chip; after all target link-related switch chips have generated channel selection signals, synchronously sending a turn-on signal to all related switch chips to turn on all target links at the same time, thus completing the switching operation.

[0035] S105, after completing the switching operation, acquire the status feedback signals of each relevant switching chip. The status feedback signals are used to characterize the actual on / off state of each channel inside the switching chip; and detect whether there are radio frequency signals at the input and output ports of each target link. S106, determine whether the actual on / off state of each relevant switch chip is consistent with the conduction state corresponding to the channel selection signal based on the status feedback signal, and determine whether each target link is actually conducting based on the detection result of the radio frequency signal. S107, If both of the above judgment results are yes, then the switching is determined to be normal; S108. If any of the above judgment results are negative, a fault is considered to have occurred. The fault level is then determined based on the preset fault classification and handling strategy, and the corresponding handling operation is performed according to the fault level.

[0036] In S104, during the period of maintaining the global shutdown signal, the global shutdown signal is sent to all switch chips in the RF switch matrix, and then the step of generating the channel selection signal is executed after waiting for a preset first maintenance period; and after the channel selection signals of all target link-related switch chips are generated, the turn-on signal is sent to all related switch chips synchronously after waiting for a preset second maintenance period.

[0037] In implementation, the control system first needs to acquire the target link set. The control system establishes a communication connection with the host computer through a communication interface, which can be a USB interface or an Ethernet interface. This communication connection is used to receive the target link set sent by the host computer.

[0038] The host computer can be a personal computer (PC), industrial control computer, or touch screen terminal, or any device with a graphical interface and network communication capabilities. The host computer pre-stores a list of the corresponding numbers for each input and output port of the RF switch matrix. For example, the four input ports are numbered IN1, IN2, IN3, and IN4, and the 96 output ports are numbered OUT1, OUT2, ..., OUT96. On the host computer's interface, the test engineer selects an input port number and an output port number for each signal transmission path to be established, using drop-down menus or numerical input boxes. For example, when the test engineer needs to establish two signal transmission paths, they select input port IN1 and output port OUT3 for the first path and input port IN2 and output port OUT5 for the second path. The host computer then encapsulates these two paths into a target link set containing two target links. It should be noted that the host computer is only responsible for combining the selected input and output port numbers into the target link set and issuing it; the host computer does not perform pre-detection or interception of port conflicts between the target links in the target link set. The host computer encapsulates the target link set into data frames according to a preset communication protocol and sends them to the control system via a USB bus or Ethernet cable through the USB interface or RJ45 Ethernet interface on the control system. After receiving the data frame, the control system's communication interface parses the data frame according to the preset communication protocol, extracts the input port number and output port number of each target link, and stores them in the control system's memory for subsequent processing.

[0039] After acquiring the target link set, the control system performs conflict detection on the acquired target link set. The control system reads the target link set from the memory, extracts the input port number of each target link to form an input port number set, and extracts the output port number of each target link to form an output port number set.

[0040] The control system checks for duplicate input port numbers in the input port number set. If duplicate numbers are found, it indicates that two or more target links need to use the same input port. Similarly, the control system checks for duplicate output port numbers in the output port number set. If duplicate numbers are found, it indicates that two or more target links need to use the same output port. Both of these situations lead to port resource contention and signal crosstalk, and should be classified as conflicts.

[0041] Meanwhile, the control system's non-volatile memory (such as EEPROM or Flash) also stores a port occupancy status matrix of the current RF switch matrix. This matrix records the input and output ports occupied by each established and currently in use link. The control system compares the input and output port numbers of each target link in the target link set with the currently occupied ports recorded in the port occupancy status matrix. If an input port number or output port number of a target link is recorded as currently occupied, it indicates a port conflict between the target link and an existing link, and should be considered a conflict. This detection covers two dimensions: conflicts with currently occupied ports and conflicts between links within the target link set.

[0042] If any of the above-mentioned conflicts exist, the control system will terminate the switching operation of all target links in the target link set and will not execute any subsequent control actions involving hardware switching chips. Simultaneously, the control system generates fault information. In this embodiment, the fault information includes a conflict type identifier (such as "input port multiplexing conflict," "output port multiplexing conflict," or "conflict with currently occupied port"), the specific port number where the conflict occurred, and the number of the conflicting target link in the target link set. The control system sends this information to the host computer via a communication interface through a USB bus or Ethernet cable. Upon receiving the fault information, the host computer displays it on its interface to the test engineer, prompting the engineer to replan the target links.

[0043] If the collision detection result indicates no collision, meaning there are no identical input or output ports among the target links within the target link set, and none of the input and output ports specified for each target link are currently occupied as recorded by the port occupancy status matrix, the control system determines that the current target link set has passed the collision detection and then executes the subsequent switching operation. It should be noted that in this embodiment, the RF switch matrix adopts a non-blocking matrix architecture. The cascaded topology between its multi-level switch chips ensures that when the input ports and output ports of multiple target links are different, the channels traversed by these target links at each level of the switch chip will not share the same switch chip. In other words, the distinctness of the input port number and output port number implicitly guarantees that the physical paths between each target link are independent at each level of the switch chip. Therefore, after passing the above collision detection, all target links have the physical conditions for simultaneous conduction, and the control system can execute the synchronous conduction operation.

[0044] The switching operation includes the following steps: The first step is for the control system to send a global shutdown signal to all switch chips in the RF switch matrix. This global shutdown signal is sent simultaneously as a low-level signal to the enable pin (EN) of each switch chip in the RF switch matrix via the control system's I / O driver unit. The enable pin (EN) is a control input pin of the switch chip; when this pin receives a low-level signal, all channels inside the switch chip are forcibly shut down, and the connection between its common terminal and all output ports is severed. By simultaneously sending a low-level signal to all switch chips, the control system ensures that all switch chips in the RF switch matrix enter a global shutdown state at the same time, thereby ensuring that no switch chip is in a conducting state during subsequent address configuration.

[0045] After the control system sends a low-level signal to the enable pins of all switching chips, it does not immediately execute the subsequent channel selection signal generation operation. Instead, it waits for a preset first maintenance period before execution (i.e., the period of maintaining the global shutdown signal as described above). The first maintenance period is calculated as follows: During the initialization phase, the control system reads the pre-stored shutdown delay parameter TOFF_DEV and the MCU interface level falling edge setup time parameter TIO_FALL from the non-volatile memory. TOFF_DEV is the maximum value of the shutdown delay parameters among all switching chips used by the control system, obtained from the switch chip's datasheet, and is measured in microseconds. TIO_FALL is the falling edge setup time required for the MCU's general-purpose input / output interface to switch from a high output level to a low output level, obtained from the MCU's datasheet. The control system substitutes TOFF_DEV and TIO_FALL into the formula: T1 = TOFF_DEV + TIO_FALL, calculates the first maintenance period T1, and stores T1 in the control system's random access memory for subsequent switching operations. After the T1 period ends, the control system begins to generate and output the channel selection signal.

[0046] The generation and output of the channel selection signal specifically includes: the control system determines all the switching chips that the target link passes through and the channel number that needs to be turned on on each switching chip, based on the input port number and output port number of each target link and the cascaded topology of the RF switch matrix.

[0047] The RF switch matrix is ​​constructed by cascading multiple levels of switch chips. Taking a 4-input 96-output matrix built with 4 SP4T switch chips and 16 SP6T switch chips as an example: the input port number of each target link determines which SP4T switch chip is used in the first stage. For example, input port IN1 is connected to the common terminal of the first SP4T, input port IN2 is connected to the common terminal of the second SP4T, input port IN3 is connected to the common terminal of the third SP4T, and input port IN4 is connected to the common terminal of the fourth SP4T. The output port number of each target link determines which output channel of which SP6T switch chip is used in the second stage. For example, the 96 output ports are distributed across 16 SP6T switch chips, and each SP6T switch chip has 6 output channels, corresponding to 6 output port numbers.

[0048] The control system determines the target channel number corresponding to each stage of the target link on the switching chip by looking up a table, based on the mapping relationship between the input port number and the first-stage SP4T switching chip, the mapping relationship between the output port number and the second-stage SP6T switching chip and its channel, and the hardware connection relationship between the first-stage SP4T and the second-stage SP6T. Taking the target link IN1→OUT3 as an example, the control system first determines that it is connected to the common terminal of the first SP4T based on the input port number IN1, and determines that it is connected to a certain channel of a certain SP6T in the second stage based on the output port number OUT3. Then, based on the hardware connection relationship between the first SP4T and each SP6T in the second stage, it determines which output channel of the first SP4T is connected to the common terminal of the SP6T. Finally, the control system determines that all the switching chips and channels that need to be turned on for this target link are: channel X of the first SP4T and channel Y of a certain SP6T in the second stage.

[0049] Next, the control system generates the corresponding channel selection signal based on the target channel number of each relevant switch chip. Taking the SP4T or SP6T switch chip as an example, this type of switch chip has three address pins: D2, D1, and D0. Each address pin can receive a high level (logic 1) or a low level (logic 0). The combination of the levels of the three address pins forms a 3-bit binary code, which can represent 8 different states, corresponding to 8 output channels. Let the target channel number be Nch (channel numbers start from 1, i.e., Nch = 1, 2, ..., 8). Since the 3-bit binary numbers represented by the three address pins correspond to values ​​ranging from 0 to 7, to establish a one-to-one mapping between the channel number and the address level combination, the control system first calculates the value of Nch-1 (i.e., the value after subtracting 1 from the channel number), converts this value into a 3-bit binary number, and uses the highest bit as the output level of the D2 pin, the second highest bit as the output level of the D1 pin, and the lowest bit as the output level of the D0 pin. For example, when the target channel number Nch=3, Nch-1=2, and the 3-bit binary representation of 2 is 010. Therefore, D2=0, D1=1, and D0=0, meaning pin D2 outputs a low level, pin D1 outputs a high level, and pin D0 outputs a low level. Similarly, when the target channel number Nch=5, Nch-1=4, and the 3-bit binary representation of 4 is 100, then D2=1, D1=0, and D0=0, meaning pin D2 outputs a high level, pin D1 outputs a low level, and pin D0 outputs a low level.

[0050] The control system calculates the level values ​​of the three address pins of each relevant switch chip according to the above conversion formula, and outputs these level values ​​to the address pins of the corresponding switch chip through the IO drive unit, so that the channel indicated by the address pin of each switch chip matches the channel that the target link needs to be turned on on the switch chip.

[0051] The control system iterates through all target links, setting the corresponding level for the address pins of each relevant switch chip. After the channel selection signals of all target link-related switch chips are generated and output to the corresponding address pins, the control system does not immediately send a conduction signal to the switch chips. Instead, it waits for a preset second maintenance period before synchronously sending conduction signals to all relevant switch chips.

[0052] The second sustaining period is calculated as follows: During the initialization phase, the control system reads the pre-stored address setup and hold time parameter TSETUP and the MCU interface level rising edge setup time parameter TIO_RISE from the non-volatile memory. TSETUP is the maximum value of the address setup and hold time parameter among all the switching chips used by the control system; this parameter is obtained from the switch chip's datasheet and is in microseconds. TIO_RISE is the level rising edge setup time required for the general-purpose input / output interface of the MCU used by the control system to switch from a low output level to a high output level; this parameter is obtained from the MCU's datasheet. The control system substitutes TSETUP and TIO_RISE into the formula: T2 = TSETUP + TIO_RISE, to calculate the second sustaining period T2, and stores T2 in the control system's random access memory for subsequent switching operations. After the T2 period ends, the control system synchronously sends a high-level signal to the enable pin EN of all relevant switching chips through the IO drive unit; this high-level signal is the conduction signal. The "relevant switching chips" mentioned here refer to the set of all switching chips involved in all target links within the target link set. Synchronous transmission refers to the control system outputting a high-level signal to the enable pins of all these switching chips at the same time (e.g., within the same clock cycle). Since the channel selection signals on the address pins of all switching chips have stabilized for a specified duration (i.e., the second sustaining period) before the conduction signal is sent, when the enable pin EN receives a high-level signal, each switching chip can immediately connect its common terminal to the corresponding channel based on the stabilized level combination on its address pins, thus enabling all target links to physically conduct simultaneously. The switching operation is now complete.

[0053] After the switching operation is completed, the control system performs closed-loop verification. Closed-loop verification includes two levels of verification: the first level is the verification of the on / off status of the internal channels of the switching chip, and the second level is the verification of the actual transmission path of the radio frequency signal.

[0054] For the first level of verification: the control system reads the status feedback signal of each relevant switch chip through the IO drive unit. In this embodiment, the switch chip has an independent status feedback pin for each channel (i.e., the Indicator pin or Status pin known in the RF switch field). Taking an 8-channel switch chip as an example, it has 8 status feedback pins, corresponding to the on / off states of the 8 channels. The DC level output of each status feedback pin is used to characterize the actual on / off state of the corresponding channel: when a channel is in the on state, the status feedback pin corresponding to that channel outputs a high level (i.e., logic 1); when a channel is in the off state, the status feedback pin corresponding to that channel outputs a low level (i.e., logic 0). The control system reads the status feedback pin level corresponding to each channel of each relevant switch chip one by one through the IO drive unit, thus accurately knowing the actual on / off state of each channel of each relevant switch chip.

[0055] The control system compares the actual on / off state of each channel with the expected conduction state corresponding to the channel selection signal (i.e., the conduction state corresponding to the channel selection signal) one by one: if the channel selection signal of a certain switching chip indicates that it should conduct a certain channel, and the status feedback pin of the corresponding channel of the chip outputs a high level, it indicates that the switching result of the chip is correct; if the channel selection signal indicates that it should conduct a certain channel, and the status feedback pin of the corresponding channel outputs a low level, it indicates that the actual on / off state of the chip is inconsistent with the expected conduction state. The control system obtains the first-level verification result by comparing the expected conduction state and the actual on / off state of each channel of each related switching chip.

[0056] For the second level of verification: the control system uses radio frequency signal detection circuits set at each input port and each output port of the radio frequency switch matrix to detect whether there is a radio frequency signal at the input port and output port of each target link.

[0057] In this embodiment, the radio frequency (RF) signal detection circuit consists of a directional coupler and a detector diode. An RF signal detection circuit is installed on the signal transmission line of each input port and each output port. Taking the input port as an example: the directional coupler is installed on the signal transmission line of each input port of the RF switch matrix, with its coupling end connected to the input end of the detector diode, and the output end of the detector diode connected to the analog-to-digital converter (ADC) interface of the control system. The directional coupler couples a small portion of the RF signal energy from the signal transmission line of the input port of the RF switch matrix. This coupled signal is rectified by the detector diode and converted into a DC voltage signal. The amplitude of this DC voltage signal is positively correlated with the RF signal power on the signal transmission line of each input port of the RF switch matrix. The control system reads this DC voltage value through the ADC interface. When the value exceeds a preset voltage threshold, it determines that an RF signal exists at that port; when the value is lower than the preset voltage threshold, it determines that no RF signal exists at that input port.

[0058] The output port is also equipped with an RF signal detection circuit consisting of a directional coupler and a detector diode, with the same connection method and working principle as the input port. The control system performs the above detection on the input and output ports of each target link: if a DC voltage exceeding a preset voltage threshold is detected at the input port of a target link, and a DC voltage exceeding the preset voltage threshold is also detected at the output port of the same target link, then the target link is determined to be actually conducting; if no DC voltage exceeding the preset voltage threshold is detected at either the input or output port, then the target link is determined not to be actually conducting. The preset voltage threshold is pre-calculated based on the conduction voltage of the detector diode and the coupling coefficient of the directional coupler. For example, when a Schottky diode is used as the detector diode, its conduction voltage is approximately 0.2V to 0.3V, so the voltage threshold can be set to 0.15V.

[0059] Based on the verification results of the two levels mentioned above, the control system comprehensively judges whether the switching operation is successful. If the actual on / off state of each relevant switch chip in the first level of verification is consistent with the expected conduction state corresponding to the channel selection signal, and if a DC voltage exceeding the preset voltage threshold is detected at the input and output ports of each target link in the second level of verification, the control system determines that the switching operation is normal.

[0060] If either of the above two verification results is negative, the control system determines that a fault has occurred in this switching operation and, based on the pneumatically preset fault classification and handling strategy, classifies the fault level according to the specific manifestation of the fault and executes the corresponding handling operation. The fault classification and handling strategy includes three fault levels: first fault level, second fault level, and third fault level, arranged from low to high.

[0061] The first fault level corresponds to the situation where a non-target channel is abnormally connected, meaning that the status feedback signal in the first-level verification indicates that the switch chip channel corresponding to the non-target link is in a connected state, while this channel should be turned off. This fault is usually caused by the address latch of the switch chip being falsely triggered by electromagnetic interference, causing the channel that should be turned off to be incorrectly connected. The handling operations for the first fault level include: the control system automatically re-executes a complete switching operation (i.e., re-executes all steps described in S104: global shutdown signal transmission, first maintenance period waiting, channel selection signal generation and output, second maintenance period waiting, and synchronous transmission of the connection signal). If the verification results at both levels are positive after re-execution, the control system returns to normal and sends a confirmation message of successful switching to the host computer via the communication interface; if the first-level verification still indicates abnormal connection of the non-target channel after re-execution, the control system generates fault information containing the fault link identifier and a fault type description of "address latch error caused by electromagnetic interference," reports this fault information to the host computer via the communication interface, and maintains the current switch state unchanged.

[0062] The second fault level corresponds to a physical open circuit in the target link. This means that while the status feedback signal in the first-level verification indicates that the actual on / off state of the relevant switch chip matches the expected on / off state, no DC voltage exceeding a preset voltage threshold is detected at the input or output port of the target link in the second-level verification. This fault is typically caused by physical layer faults such as loose or broken RF cables outside the RF switch matrix or poor contact of RF connectors, rather than an abnormal state of the switch chip itself. The handling procedures for the second fault level include: the control system generating fault information containing a fault link identifier and a fault type description of "switch status normal but physical link not connected," and reporting this fault information to the host computer via the communication interface to prompt test engineers to check the corresponding physical connection; simultaneously, the RF switch matrix is ​​not locked, meaning it does not affect subsequent switching operations of other target links.

[0063] The third fault level corresponds to a situation where multiple channels are simultaneously abnormally conducting. This occurs when the status feedback signals of multiple switching chips or multiple channels simultaneously indicate conduction during the first-level verification, while the channel selection signal only indicates that some channels should be conducting. This fault is usually caused by an internal short circuit in the switching chip or damage to the address decoding logic, constituting a serious hardware failure. The handling procedures for the third fault level include: the control system immediately sends a low-level signal to the enable pin (EN) of all switching chips through the IO driver unit, turning off all channels of the entire RF switch matrix, effectively locking the RF switch matrix; simultaneously, it triggers a hardware alarm (e.g., illuminating a red alarm indicator and emitting a buzzer alarm sound through the control system's general-purpose output interface) and sends fault information containing a fault code to the host computer; the control system also writes the occurrence time, fault link identifier, and fault type description of this third fault level into the fault log area of ​​the control system's non-volatile memory for subsequent troubleshooting and analysis; thereafter, any subsequent switching operations are prohibited until a test engineer manually troubleshoots the fault and restarts the system.

[0064] After a successful handover operation and closed-loop verification, the control system updates the port occupancy status matrix stored in the non-volatile memory: marking the input and output port numbers of each target link successfully switched as "occupied". If a handover operation is performed again subsequently, the updated port occupancy status matrix will be used for conflict detection between the aforementioned currently occupied ports.

[0065] Optionally, after the switching operation is completed, the control method may also include the following steps: S201, obtain the actual response delay data of each relevant switch chip in this switching operation. The actual response delay data is the time length from sending the conduction signal to obtaining the status feedback signal and determining conduction. S202, Generate the response delay change trend of each relevant switch chip based on the historical actual response delay data of each relevant switch chip; S203, when the response delay change trend of any related switch chip meets the preset first adjustment condition, the first maintenance period of the corresponding switch chip is increased; S204, when the response delay change trend of any related switch chip meets the preset second adjustment condition, the second maintenance period of the corresponding switch chip is increased.

[0066] Accordingly, the step of "generating channel selection signals for the switching chips associated with each target link" in S104 specifically includes the following sub-steps: S1041, obtain the latest historical actual response delay data of each switch chip in each candidate path corresponding to each target link. The candidate path is a complete sequence of switch chips and channels at each level that need to be passed from the input port to the output port of the target link. Each candidate path corresponds to a delay set consisting of the response delay data of each level of switch chips on the path. S1042, Calculate the comprehensive evaluation value of the response delay for each candidate path based on the delay set corresponding to each candidate path; S1043, Select the target path from the candidate paths of each target link based on the comprehensive evaluation value of the response delay of each candidate path; S1044 generates channel selection signals for the switching chips associated with each target link according to the target path of each target link.

[0067] In implementation, after each switching operation and closed-loop verification (i.e., the verification process from S105 to S107 mentioned above), the control system will also use the data obtained in this verification phase to perform the following optimization steps. Specifically, when both levels of the closed-loop verification result are positive, the control system will record the actual response delay data of each relevant switching chip in this switching operation. This actual response delay data refers to the time elapsed from when the control system sends a high-level conduction signal to the enable pin EN of a certain switching chip through the IO drive unit, to when the corresponding status feedback pin of the switching chip outputs a high-level signal, confirming that the target channel of the switching chip has completed physical conduction. The control system measures this time length through its internal timer: the timer starts counting when the conduction signal is sent, and stops counting when the high-level signal of the status feedback pin is read. The count value of the timer is the actual response delay data of the switching chip in this switching operation. The control system classifies and stores the acquired actual response delay data in non-volatile memory according to the switch chip identifier and channel identifier, forming a historical actual response delay dataset for each channel of each switching chip.

[0068] Based on the historical actual response delay data of each channel of each switch chip stored above, the control system generates a corresponding response delay change trend for each switch chip. This response delay change trend refers to the control system reading the actual response delay data of a switch chip in the most recent N switching operations from non-volatile memory, and generating a sequence of the switch chip's response delay over time, with the execution time of the switching operations as the horizontal axis and the actual response delay data as the vertical axis. For example, the control system can record the response delay data of each switch chip in the most recent 100 switching operations; if the number of switching operations for a switch chip is less than 100, then all its historical data is recorded.

[0069] In this embodiment, the control system calculates the trend of response delay based on the sequence. Specifically, the control system uses the execution number of the switching operation as the independent variable (e.g., the 1st, 2nd, ..., Nth time) and the corresponding actual response delay data as the dependent variable. It then uses the least squares method to fit a linear regression line, the slope of which represents the trend of the switch chip's response delay. The calculation process is as follows: The control system first calculates the mean of the independent variable (execution number) and the dependent variable (actual response delay data). Then, it calculates the sum of the products of the deviations of each variable from its mean, divided by the sum of the squares of the deviations of the independent variables. The resulting quotient is the slope of the fitted line. When the slope is greater than zero, it indicates that the response delay of the switch chip increases over time, meaning the switch chip is gradually aging. When the slope is less than or equal to zero, it indicates that the response delay of the switch chip does not show an increasing trend, meaning the performance of the switch chip is relatively stable.

[0070] As the number of times a switching chip is used increases, its internal mechanical contacts or semiconductor switching structure gradually wears down and ages, resulting in a monotonically increasing actual response delay. The control system analyzes this trend to predict changes in the health status of the switching chips. Specifically, the control system compares the response delay trends of each switching chip with a preset first adjustment condition. The preset first adjustment condition refers to: the response delay trend of a certain switching chip satisfying a linear fitting slope exceeding a preset slope threshold, or the increase in the actual response delay data of the most recent M switching operations compared to the initial response delay data exceeding a preset percentage threshold. Specifically, the control system uses the typical response delay value of the switching chip model (i.e., the nominal factory response delay value in a brand-new state) recorded in the switching chip datasheet as 1% of the typical response delay value as the preset slope threshold for the switching chip, in microseconds per hundred switches. For example, if the typical response delay of a certain model of switching chip is 2.0 microseconds, then its preset slope threshold is 0.02 microseconds per hundred switches; when the slope calculated by the control system through linear fitting exceeds the preset slope threshold, the first adjustment condition is determined to be met. The value of M is determined based on the switching frequency in the actual application scenario. When the system performs a large number of switching operations per day (e.g., more than 1000 times per day), M can be 20; when the switching frequency is low (e.g., less than 100 times per day), M can be 10. The initial response delay data refers to the average of the actual response delay data in the first 10 switching operations of the switching chip during its initial use. The preset percentage threshold is set to 15% of the initial response delay data. The control system calculates the average of the actual response delay data of the most recent M switching operations, and calculates the percentage increase between this average and the initial response delay data. When this percentage increase exceeds 15%, the first adjustment condition is deemed met.

[0071] When the response delay change trend of any switching chip meets a preset first adjustment condition, the control system increases the first sustaining period corresponding to that switching chip. Specifically, the control system reads the currently stored first sustaining period value corresponding to that switching chip from the non-volatile memory, increments it by a preset step size (e.g., 0.1 microseconds), and rewrites the increased value back into the non-volatile memory for subsequent switching operations involving that switching chip. This preset step size is determined based on the typical response delay of the switching chip: the preset step size is equal to 10% of the typical response delay value of the switching chip, with a lower limit of 0.05 microseconds and an upper limit of 0.5 microseconds. For example, if the typical response delay of a switching chip is 2.0 microseconds, then the preset step size is 0.2 microseconds. The control system rewrites the increased value back into the non-volatile memory for subsequent switching operations involving that switching chip.

[0072] The control system also compares the response delay change trends of each switching chip with a preset second adjustment condition. The preset second adjustment condition refers to: the response delay change trend of a certain switching chip satisfying a linear fitting slope exceeding a preset slope threshold, or the increment of the actual response delay data of the most recent M switching operations compared to the initial response delay data exceeding a preset proportion threshold. The judgment logic of the second adjustment condition is the same as that of the first adjustment condition, but the physical objects it targets are different: the first adjustment condition targets the turn-off action delay of the switching chip (corresponding to the first maintenance period), while the second adjustment condition targets the address establishment delay of the switching chip (corresponding to the second maintenance period).

[0073] Since the turn-off delay and address setup delay of the same switching chip may vary with aging, the control system independently determines the two adjustment conditions and adjusts the two maintenance periods independently. Specifically, when the response delay change trend of a switching chip only meets the first adjustment condition, only the first maintenance period corresponding to that switching chip is increased by a first preset step value, without adjusting the second maintenance period; when the response delay change trend of a switching chip only meets the second adjustment condition, only the second maintenance period corresponding to that switching chip is increased by a second preset step value, without adjusting the first maintenance period; when both adjustment conditions are met simultaneously, the first maintenance period is increased by the first preset step value, and the second maintenance period is increased by the second preset step value respectively; when neither condition is met, the two maintenance periods remain unchanged. The first preset step value and the second preset step value can be the same or different, and both are preset fixed values, for example, both can be set to 0.1 microseconds, or determined independently based on the typical response delay of the switching chip (e.g., the first preset step value equals 10% of the typical turn-off delay, and the second preset step value equals 10% of the typical address setup delay).

[0074] Furthermore, when the control system executes the step of "generating channel selection signals for the switching chips associated with each target link" in S104, it will perform path optimization by combining the historical actual response delay data corresponding to the candidate paths of each target link. The premise of path optimization is that the control system first obtains the candidate path list for each target link in the target link set. A candidate path refers to the complete sequence of switching chips and channels at each level that need to be passed from the input port to the output port of a target link. As mentioned above, the RF switch matrix is ​​composed of multiple levels of cascaded switching chips. There may be multiple physical paths from the input port to the output port of a target link, that is, reaching the same output port through different combinations of intermediate switching chips. Taking a 4-input 96-output matrix as an example, a certain input port can be connected to the common terminal of a certain SP6T in the second level through a certain channel of a certain SP4T in the first level, and then connected to the target output port through a certain channel of that SP6T; the input port can also be connected to another SP6T in the second level through a different channel of another SP4T, and then connected to the same target output port. Each candidate path corresponds to a set of delay data composed of the response delay data of the switching chips at each level on that path.

[0075] First, for S1041, the control system reads the latest historical actual response delay data of each level of switching chip involved in each candidate path from the non-volatile memory, forming the delay set for each candidate path. It should be noted that the "latest historical actual response delay data" refers to the actual response delay data recorded in the most recent switching operation of each switching chip, rather than the historical average or historical maximum value, to ensure that the path selection is based on the latest actual state of each switching chip and reflects its latest aging status in real time.

[0076] Subsequently, for S1042, the control system calculates the comprehensive response delay evaluation value for each candidate path based on the delay set corresponding to each candidate path. Specifically, for each candidate path, the control system obtains the actual response delay data of each level of switching chips on that candidate path in the most recent switching operation and reads the path evaluation weights currently stored in the non-volatile memory. The path evaluation weights are a set of weight coefficients corresponding to the path length. For example, if a candidate path passes through three levels of switching chips, the path evaluation weights include three weight coefficients w1, w2, and w3, which correspond to the weight proportions of the response delays of the first, second, and third level switching chips in the weighted summation, respectively. The control system multiplies the actual response delay data of each level of switching chip by the corresponding weight coefficient and sums them to obtain the comprehensive response delay evaluation value of the candidate path, calculated as S = w1·t1 + w2·t2 + w3·t3. The smaller the comprehensive response delay evaluation value, the faster the overall response speed of each level of switching chips on the candidate path (after considering the different weights of each level), and the higher the switching reliability of the candidate path. The initial values ​​of each weight in the path evaluation weight W={w1, w2,……, wm} are preset by the test engineer during system initialization. For example, each weight is equal by default and satisfies w1+w2+……+wm=1.

[0077] Then, the control system filters out combinations that satisfy mutual exclusion constraints from all candidate path combinations for all target links. A mutual exclusion constraint means that, within the same set of target links, no two candidate paths corresponding to the same target link can share the same switching chip. When the control system detects that two sets of candidate paths contain the same switching chip, it marks the combination as invalid and excludes it from the set of options. This mutual exclusion constraint ensures that the physical paths of each target link remain independent at each level of the switching chip, thus providing the physical prerequisite for subsequent synchronous conduction operations.

[0078] Next, for S1043, the control system, among all combinations satisfying the mutual exclusion constraint, aims to minimize the weighted sum of the comprehensive evaluation values ​​of each target link, and jointly selects the target path from the candidate paths of each target link. That is, the control system does not independently select the optimal path for each link, but rather optimizes multiple links as a whole, ensuring that the overall path quality of all target links is optimal while guaranteeing that each link path does not share switching chips. Specifically, for each target link, the control system sorts all its corresponding candidate paths according to their comprehensive evaluation values ​​from smallest to largest, and selects the candidate path with the smallest comprehensive evaluation value as the target path for that target link. For example, if a target link has three candidate paths with comprehensive evaluation values ​​S1, S2, and S3, where S1 < S2 < S3, then the control system selects the candidate path with a comprehensive evaluation value of S1 as the target path for that target link.

[0079] For S1044, the control system generates channel selection signals for the switching chips associated with each target link based on the selected target path. Since the target path has determined the switching chips and their corresponding channel numbers from the input port to the output port, the control system generates corresponding address pin levels for each relevant switching chip on each target path according to the conversion relationship between the channel number and the address pin level (i.e., Nch-1 converted to a 3-bit binary number) and outputs them to the corresponding address pins through the IO drive unit.

[0080] Optionally, the control method may also include the following steps: S301, based on the execution record of the switching operation, obtain the parameter configuration data and the corresponding switching result quality evaluation value for each switching operation. The parameter configuration data includes at least one of the following: the first maintenance period and / or the second maintenance period corresponding to each switch chip used during the execution of the switching operation, and the target path selected during the execution of the switching operation. S302, Based on the parameter configuration data of multiple historical handover operations and the corresponding handover result quality evaluation values, the target parameter configuration data is determined through a preset parameter optimization algorithm; S303, based on the target parameter configuration data, update the first maintenance period and / or the second maintenance period used in subsequent handover operations, and / or update the path evaluation weight used when selecting the target path in subsequent handover operations.

[0081] In practice, during the execution of the aforementioned switching operation and closed-loop verification (i.e., S105 to S107), in addition to completing the verification and fault handling of this switching, the control system will also record various execution data of this switching as the data basis for subsequent parameter optimization.

[0082] The control system generates an execution record for each switching operation. This record contains parameter configuration data and the corresponding switching result quality evaluation value. The parameter configuration data includes the specific values ​​of the first and / or second sustain periods for each switching chip used in the current switching operation, as well as the target paths for each selected target link (i.e., the complete sequence of switching chips and channels involved in the selected target path). Before each switching operation, the control system reads the specific values ​​of the first and second sustain periods for each currently used switching chip from non-volatile memory, records the selected target path after path optimization, and writes this information as the parameter configuration data for that switching operation into the execution record.

[0083] The handover result quality evaluation value is a comprehensive indicator used to quantitatively assess the execution quality of a single handover operation. It differs from the aforementioned comprehensive evaluation value for response latency of candidate paths. The comprehensive evaluation value for response latency is an indicator used to predictively evaluate candidate paths based on historical response latency data of each switching chip before handover execution, guiding path selection for this handover. In contrast, the handover result quality evaluation value is an evaluation indicator obtained after the handover is completed, based on a comprehensive quantification of all execution data actually generated during the handover, characterizing the actual execution quality of this handover.

[0084] The control system obtains the parameter configuration data and corresponding switching result quality evaluation value for each switching operation based on the execution record of each switching operation. The specific method for determining the switching result quality evaluation value is as follows: the control system obtains four actual execution data items during the closed-loop verification phase (S105 to S107) of this switching operation, namely: actual response delay data of each relevant switching chip, feedback signal stability data, fault handling trigger data, and closed-loop verification pass data.

[0085] The actual response delay data is obtained as follows: The control system records the actual response delay value of each relevant switching chip during this switchover (i.e., the actual time from sending the conduction signal to the status feedback pin confirming conduction). The maximum or average value of the actual response delay values ​​of all relevant switching chips is taken as the actual response delay data D for this switchover. When the maximum value is taken, D is used to characterize the response speed of the slowest switching chip in this switchover; when the average value is taken, D is used to characterize the overall response level of each switching chip in this switchover. Whether to use the maximum value or the average value can be configured by the test engineer according to the application scenario during control system initialization.

[0086] The feedback signal stability data is obtained as follows: After the control system confirms the conduction of the status feedback pin, it continuously samples the level of the status feedback pin 10 times at a preset sampling frequency (e.g., once per microsecond). The standard deviation σ of these 10 sampled values ​​is calculated as the feedback signal stability data for this switch. The smaller σ is, the more stable the feedback signal and the more reliable the switch contact; the larger σ is, the more severe the feedback signal jitter, which may indicate poor contact or oxidation.

[0087] The fault handling trigger data is obtained as follows: the control system records whether the fault classification handling strategy in S108 was triggered during this switchover. If no fault handling is triggered during this switchover, the fault handling trigger data F=1; if the first fault level handling or the second fault level handling is triggered, then F=0. It should be noted that when the third fault level handling is triggered, this switchover is considered a serious failure and is no longer included in the calculation system of the switchover result quality evaluation value.

[0088] The closed-loop verification pass data is obtained as follows: the control system records whether the current switch has passed the closed-loop verification at both levels in S106. If both the first and second level verifications pass, the closed-loop verification pass data P=1; if either level verification fails, P=0.

[0089] The control system calculates the switching result quality evaluation value Q according to the following formula for the above four actual execution data: Q=100×(α×P+β×F×(1-D / D_ref)+γ×(1-σ / σ_ref)).

[0090] Wherein, D represents the actual response delay data, and D_ref is the preset response delay reference value (which is the typical response delay value recorded in the datasheet of the switch chip, for example, 2.0 microseconds); σ represents the feedback signal stability data, and σ_ref is the preset stability reference value (which is the upper limit of the standard deviation of the feedback signal level of the switch chip under factory testing conditions, for example, 0.05V); α, β, and γ are preset weighting coefficients, α+β+γ=1. P and F are both binary variables (taking values ​​of 0 or 1). When P=0, Q is directly 0, indicating that the switching failed; when P=1 and F=1, Q is determined by both the response delay and the feedback signal stability data, indicating that the switching was successful and no fault handling was triggered.

[0091] The default values ​​for the weighting coefficients α, β, and γ are α=0.4, β=0.3, and γ=0.3, respectively. These default values ​​are based on the fundamental principle that "passing the closed-loop verification is a prerequisite for successful handover," meaning that the data P that passes the closed-loop verification has the highest weight (40%). This is because if the verification fails, the handover itself fails, and other indicators (response latency, signal stability) become meaningless. When test engineers configure the system during initialization, they can adjust the default weighting coefficients according to the specific application scenario, but the sum of the adjusted weighting coefficients must equal 1. The adjustment methods for the three scenarios are as follows: When the primary goal of production line testing is changeover speed, i.e., to minimize changeover time while ensuring verification and avoiding fault handling, test engineers adjust the weighting coefficients to α=0.3, β=0.5, and γ=0.2, which means the weight of actual response latency is increased from 30% to 50%.

[0092] When the primary goal of production line testing is signal integrity, i.e., to ensure that the RF signal after switching is as stable as possible and the switch contacts are reliable, the test engineer adjusts the weighting coefficients to α=0.3, β=0.2, and γ=0.5, which means that the weight of feedback signal stability is increased from 30% to 50%.

[0093] When the primary goal of production line testing is to balance switch reliability and signal integrity, test engineers can keep the default weighting coefficients α=0.4, β=0.3, and γ=0.3 unchanged.

[0094] The specific values ​​for the weighting coefficient adjustments mentioned above are merely examples, not exhaustive. The control system stores the calculated switching result quality evaluation value Q (a quantitative score between 0 and 100) in association with the parameter configuration data for this switching in the execution record database of non-volatile memory, for subsequent parameter optimization.

[0095] Furthermore, the control system determines the target parameter configuration data based on the stored parameter configuration data of multiple historical handover operations and the corresponding handover result quality evaluation values ​​through a preset parameter optimization algorithm. The preset parameter optimization algorithm can employ a Bayesian optimization algorithm to find the parameter configuration combination that maximizes the handover result quality evaluation value. In this embodiment, the variables to be optimized include the first maintenance period T1_i and the second maintenance period T2_i corresponding to each switch chip, where i=1,2,……,n, n is the total number of switch chips in the RF switch matrix, and the path evaluation weight vector W={w_1,w_2,……,w_m}, where m is the maximum value of the sum of the number of switch chips at each level in the candidate path of the target link, and each path evaluation weight satisfies w_1+w_2+……+w_m=1 and each weight is greater than or equal to 0.

[0096] The values ​​of T1_i and T2_i range from [0.1 microseconds, 10 microseconds] to [0.1 microseconds, 10 microseconds], respectively. These ranges are determined based on the rated operating range specified in the switch chip datasheet: the lower limit of 0.1 microseconds represents the minimum turn-off delay and minimum address setup and hold time of the switch chip, while the upper limit of 10 microseconds represents the maximum turn-off delay and maximum address setup and hold time recommended in the switch chip datasheet. The path evaluation weight ranges from [0, 1] and satisfies the constraint that the sum of the weights must be 1.

[0097] The control system first generates an initial set of sampling points based on the aforementioned value range. Each sampling point represents a complete set of parameter configuration data, including the T1_i and T2_i values ​​corresponding to all switching chips, as well as the path evaluation weight vector W. For T1_i and T2_i, the control system uses the Latin hypercube sampling method to generate P sets of candidate values ​​within their respective value ranges, ensuring that each parameter is uniformly distributed across the entire value range to maximize the uniformity of the initial sampling points' coverage in the d-dimensional parameter space. For the path evaluation weight vector W, the control system uses a Dirichlet distribution for sampling. This distribution ensures that each component of the weight vector generated in each sampling is non-negative and sums to 1. The concentration parameter α of the Dirichlet distribution takes the value [1,1,……,1] (a total of m components), and the sampling results are uniformly distributed on the m-dimensional simplex. The number P of the initial sampling points is determined according to the dimension d of the variable to be optimized, specifically P = 10 × d. For example, when the RF switch matrix contains 20 switch chips, the variables to be optimized include 20 T1_i, 20 T2_i, and the weight values ​​in the path evaluation weight vector W, with a total dimension d=41. Therefore, the initial number of sampling points P=410. The control system applies each set of parameter configuration data to subsequent switching operations, recording the switching result quality evaluation value Q calculated after each switching operation, thus obtaining P sets of "parameter configuration-quality evaluation value" mapping data as the initial training sample set.

[0098] The control system, based on an initial training sample set, employs a Gaussian process as a surrogate model to construct a probabilistic mapping model from the parameter configuration space to the Q-value. The covariance function of the Gaussian process uses a Matrn kernel function, whose length scaling parameter is learned from the training samples using maximum likelihood estimation. Then, the control system uses expected improvement as the acquisition function to balance the exploration of the unknown parameter space with the utilization of known high-value regions. In each iteration, the control system determines the next set of candidate parameter configurations by maximizing the acquisition function. After applying this candidate parameter configuration to the actual switching operation and obtaining the corresponding Q-value, new data is added to the training sample set and the surrogate model is updated. This iterative process is repeated until the improvement in the Q-value after 20 consecutive iterations is less than 1% of the current maximum Q-value, at which point iteration stops. The optimal parameter configuration predicted by the surrogate model at the time of iteration termination is used as the target parameter configuration data.

[0099] The control system updates the parameter configuration for subsequent switching operations based on the target parameter configuration data determined by a preset parameter optimization algorithm. Specifically, the target parameter configuration data includes recommended values ​​for the first and / or second maintenance periods corresponding to each switching chip, as well as recommended path evaluation weights (i.e., the weight coefficients W={w1,w2,……,wm} used in calculating the comprehensive evaluation value of the candidate path response delay in S1042). The control system updates the first and / or second maintenance periods corresponding to each currently used switching chip stored in the non-volatile memory with the recommended values ​​in the aforementioned target parameter configuration data; simultaneously, it updates the currently used path evaluation weights W={w1,w2,……,wm} stored in the non-volatile memory with the recommended path evaluation weights in the aforementioned target parameter configuration data, for use in the subsequent calculation of the comprehensive evaluation value of the response delay in S1042. The updated first maintenance period, second maintenance period, and path evaluation weights then take effect, and the control system will automatically use the updated parameter values ​​when performing subsequent switching operations.

[0100] Optionally, the step of synchronously sending a turn-on signal to all the relevant switch chips in S104 includes the following steps: Obtain the latest historical actual response delay data for each relevant switching chip; Based on the maximum value of the latest historical actual response delay data of each relevant switch chip, the delay compensation value of each relevant switch chip is calculated respectively. Based on the delay compensation value of each relevant switch chip, the transmission time of the conduction signal of each relevant switch chip is determined, so that the transmission time of the conduction signal of each relevant switch chip is different and sorted according to the size of the delay compensation value. According to the determined turn-on signal transmission time of each relevant switch chip, a turn-on signal is sent to each relevant switch chip respectively, so that the actual turn-on time of each relevant switch chip is aligned.

[0101] In practice, when the control system executes "synchronously send conduction signals to all relevant switch chips" in S104, it can also use an asynchronous synchronization compensation mechanism to align the actual conduction times of each switch chip.

[0102] After each switching operation is completed (i.e., after the closed-loop verification is passed), the control system records and updates the latest historical actual response delay data of each relevant switching chip in the non-volatile memory. This actual response delay data refers to the time elapsed from when the control system sends a conduction signal to when the status feedback pin confirms that the switching chip has completed physical conduction. The measurement method is as follows: the control system starts an internal timer while sending the conduction signal, and stops timing when a high-level signal is read from the status feedback pin. The timer's count value is the actual response delay data of the switching chip in this switching operation. The latest historical actual response delay data of each switching chip, i.e., the actual response delay data recorded in the most recent switching operation, is stored in the non-volatile memory.

[0103] Before executing the synchronous transmission of the conduction signal step S104, the control system reads the latest historical actual response delay data of each relevant switch chip from the non-volatile memory and finds the maximum value t_max. Using this maximum value t_max as a reference, the control system calculates the delay compensation value for each relevant switch chip. The formula for calculating the delay compensation value is: for a switch chip k, if its actual response delay is t_k, then the delay compensation value Δ_k = t_max - t_k. When the actual response delay of a switch chip equals the maximum value, its delay compensation value is zero; when the actual response delay of a switch chip is less than the maximum value, its delay compensation value is positive, and the smaller the actual response delay, the larger the delay compensation value.

[0104] The control system determines the conduction signal transmission time of each relevant switching chip based on its delay compensation value. Specifically, the control system determines the conduction signal transmission time of each relevant switching chip based on the principle that the larger the delay compensation value, the earlier the conduction signal transmission time. That is, for the switching chip with the largest actual response delay (delay compensation value of zero), the control system sets the conduction signal transmission time to the reference time T0; for the switching chip with an actual response delay less than the maximum value, its conduction signal transmission time is T0-Δ_k, that is, the smaller the actual response delay of the switching chip, the earlier its conduction signal transmission time, so that after experiencing their respective response delays, the actual physical conduction time of each relevant switching chip is aligned with T0+t_max.

[0105] The control system sends high-level conduction signals to the enable pins of each relevant switch chip according to the determined conduction signal transmission times. The control system uses multiple independent timing channels of its internal timer to control the transmission time of the conduction signal for each relevant switch chip. Each independent timing channel of the timer can be independently set to its trigger time. When the trigger time is reached, the channel outputs a high-level signal to the enable pin of the corresponding switch chip, causing the switch chip to begin conducting. The control system configures the trigger time of each independent timing channel based on the calculated conduction signal transmission times (i.e., T0-Δ_k). When the timer channels trigger sequentially according to their configured times, the switch chip with the larger actual response delay receives the conduction signal first, followed by the switch chip with the smaller actual response delay. Each switch chip completes physical conduction after its respective response delay after receiving the conduction signal. The actual conduction times of all relevant switch chips are aligned with the reference time T0+t_max. Since the channel selection signals on the address pins of all switching chips have stabilized during the second maintenance period, each switching chip only needs its own response delay to complete physical conduction after receiving the conduction signal, and will not experience additional delay due to address instability.

[0106] This application also discloses a radio frequency switch matrix control system. (Refer to...) Figure 2 ,include: The target link acquisition module 11 is used to acquire a set of target links, wherein the set of target links includes at least one target link for which a radio frequency signal transmission path needs to be established, and each target link includes an input port and an output port; Link conflict detection module 12 is used to perform conflict detection on the target link set and determine whether there are any two target links with the same input port or the same output port. The link conflict handling module 13 is used to terminate the switching operation of all target links in the target link set and output fault information if a conflict exists. The target link switching module 14 is used to perform a switching operation if there is no conflict. The switching operation includes: sending a global shutdown signal to all switch chips in the radio frequency switch matrix; generating channel selection signals for each switch chip related to the target link while maintaining the global shutdown signal; and after all channel selection signals for the switch chips related to the target link are generated, synchronously sending a conduction signal to all the related switch chips to enable all the target links to conduct simultaneously, thereby completing the switching operation.

[0107] This application also discloses a radio frequency switch matrix control device, which includes a memory and a processor. The memory stores a computer program that can be loaded by the processor and executed as described above for the radio frequency switch matrix control method.

[0108] This application also discloses a computer-readable storage medium that stores a computer program that can be loaded by a processor and executed as described above for the radio frequency switch matrix control method. The computer-readable storage medium includes, for example, various media capable of storing program code, such as a USB flash drive, a portable hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0109] It should be noted that in this paper, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0110] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit the scope of protection of the application. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on these embodiments, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

Claims

1. A radio frequency switch matrix control method, characterized in that, include: Obtain a set of target links, which includes at least one target link for which a radio frequency signal transmission path needs to be established, and each target link includes an input port and an output port; Conflict detection is performed on the target link set to determine whether any two target links have the same input port or the same output port; If so, it indicates a conflict, and the switching operation of all target links in the target link set is terminated and fault information is output; If not, a switching operation is performed, which includes: sending a global shutdown signal to all switch chips in the RF switch matrix; generating channel selection signals for each switch chip associated with the target link while maintaining the global shutdown signal; and after all channel selection signals for the switch chips associated with the target link are generated, synchronously sending a conduction signal to all the associated switch chips to enable all the target links to conduct simultaneously, thus completing the switching operation.

2. The radio frequency switch matrix control method according to claim 1, characterized in that, After the switching operation is completed, the following is also included: After the switching operation is completed, the status feedback signal of each of the relevant switching chips is obtained. The status feedback signal is used to characterize the actual on / off state of each channel inside the switching chip. Also, the presence of radio frequency signals at the input and output ports of each target link is detected. Based on the status feedback signal, determine whether the actual on / off state of each of the related switch chips is consistent with the conduction state corresponding to the channel selection signal, and determine whether each of the target links is actually conducting based on the detection result of the radio frequency signal; If both of the above judgments are true, then the switching is considered normal; If any of the above judgments is negative, a fault is considered to have occurred, and the fault level is determined based on the preset fault classification and handling strategy, and the corresponding handling operation is performed according to the fault level.

3. The radio frequency switch matrix control method according to claim 2, characterized in that, The step of maintaining the global shutdown signal means that after sending the global shutdown signal to all switch chips in the radio frequency switch matrix, waiting for a preset first maintenance period before executing the step of generating channel selection signals for each switch chip related to the target link. Furthermore, after all the channel selection signals of the switch chips related to the target link are generated, the conduction signal is sent synchronously to all the related switch chips after waiting for a preset second maintenance period.

4. The radio frequency switch matrix control method according to claim 3, characterized in that, After the switching operation is completed, the following is also included: The actual response delay data of each of the relevant switching chips in this switching operation is obtained. The actual response delay data is the time length from sending the conduction signal to obtaining the status feedback signal and determining conduction. The response delay change trend of each of the relevant switching chips is generated based on the historical actual response delay data of each of the relevant switching chips; When the response delay change trend of any of the related switching chips meets the preset first adjustment condition, the first maintenance period of the corresponding switching chip is increased; When the response delay change trend of any of the related switching chips meets the preset second adjustment condition, the second maintenance period of the corresponding switching chip is increased.

5. The radio frequency switch matrix control method according to claim 3, characterized in that, The generation of channel selection signals for the switching chips associated with each of the target links includes: Obtain the latest historical actual response delay data of each switching chip in each candidate path corresponding to each target link. The candidate path is a complete sequence of switching chips and channels at each level that need to be passed from the input port to the output port of the target link. Each candidate path corresponds to a delay set consisting of the response delay data of each level of switching chips on the path. Based on the delay set corresponding to each candidate path, calculate the comprehensive evaluation value of the response delay for each candidate path. Based on the comprehensive evaluation value of the response delay of each candidate path, a target path is selected from the candidate paths of each target link; Based on the target path of each target link, channel selection signals for the switching chips associated with each target link are generated respectively.

6. The radio frequency switch matrix control method according to claim 5, characterized in that, The method further includes: Based on the execution record of the switching operation, obtain the parameter configuration data and the corresponding switching result quality evaluation value for each switching operation. The parameter configuration data includes at least one of the following: the first maintenance period and / or the second maintenance period corresponding to each switch chip used during the execution of the switching operation, and the target path selected during the execution of the switching operation. Based on the parameter configuration data and corresponding handover result quality evaluation values ​​of multiple historical handover operations, the target parameter configuration data is determined through a preset parameter optimization algorithm. Based on the target parameter configuration data, update the first maintenance period and / or the second maintenance period used in subsequent handover operations, and / or update the path evaluation weights used when selecting the target path in subsequent handover operations.

7. The radio frequency switch matrix control method according to claim 4, characterized in that, The step of synchronously sending a turn-on signal to all the relevant switching chips includes: Obtain the latest historical actual response delay data for each of the relevant switching chips; Based on the maximum value of the latest historical actual response delay data of each of the relevant switch chips, the delay compensation value of each of the relevant switch chips is calculated respectively. Based on the delay compensation value of each related switch chip, the transmission time of the conduction signal of each related switch chip is determined, so that the transmission time of the conduction signal of each related switch chip is different and sorted according to the size of the delay compensation value. According to the determined turn-on signal transmission time of each of the relevant switch chips, a turn-on signal is sent to each of the relevant switch chips respectively, so that the actual turn-on time of each of the relevant switch chips is aligned.

8. A radio frequency switch matrix control system, characterized in that, include: The target link acquisition module (11) is used to acquire a set of target links, wherein the set of target links includes at least one target link for which a radio frequency signal transmission path needs to be established, and each target link includes an input port and an output port; Link conflict detection module (12) is used to perform conflict detection on the target link set and determine whether there are any two target links with the same input port or the same output port; The link conflict handling module (13) is used to terminate the switching operation of all target links in the target link set and output fault information if a conflict exists. The target link switching module (14) is used to perform a switching operation if there is no conflict. The switching operation includes: sending a global shutdown signal to all switch chips in the radio frequency switch matrix; generating channel selection signals for each switch chip related to the target link while maintaining the global shutdown signal; and sending a turn-on signal to all the related switch chips synchronously after all the channel selection signals for the target links are generated, so that all the target links are turned on at the same time, thus completing the switching operation.

9. A radio frequency switch matrix control device, characterized in that, It includes a memory and a processor, wherein the memory stores a computer program that can be loaded by the processor and executed as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer program is stored that can be loaded by a processor and executed as described in any one of claims 1 to 7.

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