Method for reducing leakage current by controlling PMOS or NMOS tube voltage drop circuit

Abstract

The application discloses a method for reducing leakage current of a circuit module connected to a PMOS or NMOS transistor by controlling voltage drop of the PMOS or NMOS transistor, wherein the control voltage of a control signal of a gate of the PMOS transistor is higher than a source voltage of the PMOS transistor when the control signal is at a high level, or a substrate end voltage of the PMOS transistor is higher than the source voltage of the PMOS transistor, so as to reduce the leakage current of the circuit module connected to a drain of the PMOS transistor; or the control voltage of the control signal of the gate of the NMOS transistor is lower than a source voltage of the NMOS transistor when the control signal is at a low level, or a substrate end voltage of the NMOS transistor is lower than the source voltage of the NMOS transistor, so as to reduce the leakage current of the circuit module connected to a drain of the NMOS transistor.

Description

Technical Field

[0001] This invention relates to a method for reducing circuit turn-off leakage current by controlling the voltage of a PMOS or NMOS transistor. Background Technology

[0002] With advanced CMOS technology, the speed of digital circuits is significantly improved, but the leakage current during turn-off also increases accordingly. The magnitude of this leakage current is related to the threshold voltage Vth of the MOSFET and its dimensions W and L. A smaller threshold voltage Vth results in a larger leakage current; a smaller channel length L also results in a larger leakage current; and a larger channel width W also results in a larger leakage current. For large-scale digital circuits, to increase operating speed, MOSFETs with the smallest channel length L and the lowest threshold voltage Vth are typically used. This leads to a large leakage current during chip turn-off, especially in open-circuit (FF) processes and at high temperatures, potentially reaching tens of mA. In some low-power applications, such high standby power consumption may be unacceptable.

[0003] To address the issue of leakage current during shutdown, power gating technology has emerged. Traditional power gating solutions may employ... Figure 1 The methods for gated PMOS and NMOS transistors are shown.

[0004] like Figure 1 As shown in (a), when gating_pg=0, the PMOS transistor is turned on and the digital logic connected in series below works normally. When gating_pg=DVDD, the PMOS transistor is turned off and the digital logic connected in series below cannot work normally because the power supply DVDD is cut off.

[0005] like Figure 1 As shown in (b), when gating_ng=DVDD, the NMOS transistor is turned on and the series-connected digital logic works normally. When gating_pg=0, the NMOS transistor is turned off and the series-connected digital logic cannot work normally because the power supply ground line DGND is cut off.

[0006] The aforementioned gated power supply method can improve the turn-off leakage current under the TT process corner of the chip, but the leakage current is still unacceptable under the FF process corner and high temperature conditions. Therefore, there are also ways to further optimize the magnitude of the turn-off leakage current by increasing the channel length of the gated PMOS or NMOS transistors or using thick oxide transistors. However, considering that in order to prevent excessive loss of digital logic power supply voltage during normal chip operation, there are a large number of gated PMOS or NMOS transistors connected in parallel to reduce the on-resistance. In order to meet the voltage drop requirements, increasing the channel length L requires a proportional increase in the channel width of the MOS transistor, which may result in an unacceptable increase in the area of ​​the gated transistor. Summary of the Invention

[0007] To address the problems existing in the prior art, this invention proposes a method for reducing circuit turn-off leakage current by controlling the voltage of a PMOS or NMOS transistor. This method involves increasing the control voltage of the PMOS transistor's gate when it is high to be higher than the PMOS transistor's source voltage, or increasing the substrate voltage of the PMOS transistor to be higher than the PMOS transistor's source voltage, thereby reducing the turn-off leakage current of the circuit module connected to the drain of the PMOS transistor. Alternatively, this method involves decreasing the control voltage of the NMOS transistor's gate when it is low to be lower than the NMOS transistor's source voltage, or decreasing the substrate voltage of the NMOS transistor to be lower than the NMOS transistor's source voltage, thereby reducing the turn-off leakage current of the circuit module connected to the drain of the NMOS transistor.

[0008] In some embodiments, the circuit module includes digital or analog circuitry that generates leakage current exceeding the milliampere level when turned off.

[0009] In some embodiments, the source of the PMOS transistor is connected to a first power supply voltage (DVDD); the gate of the PMOS transistor is connected to a level shifting circuit; the first terminal of the voltage divider resistor is connected to a second power supply voltage (VDDIO), and the second terminal is grounded (DGND); the voltage divider output through a node of the voltage divider resistor (VDDIO_DIV) and the first power supply voltage (DVDD) are used as inputs to a comparator; the output of the comparator is used as a control signal (CMP_OUT) for a multiplexer; the inputs of the multiplexer include the voltage divider (VDDIO_DIV) and the first power supply voltage (DVDD); based on the control signal (CMP_OUT), the voltage divider (VDDIO_DIV) or the first power supply voltage (DVDD) is selected as the power supply voltage (VDD_SEL) of the level shifting circuit to reduce the turn-off leakage current of the circuit module connected to the drain of the PMOS transistor.

[0010] In some embodiments, the source of the PMOS transistor is connected to a first power supply voltage (DVDD); the gate of the PMOS transistor is connected to a level transfer circuit; the voltage output by the charge pump circuit is used as the power supply voltage (VDD_SEL) of the level transfer circuit and is greater than the first power supply voltage (DVDD) to reduce the turn-off leakage current of the circuit module connected to the drain of the PMOS transistor.

[0011] In some embodiments, the source of the PMOS transistor is connected to a first power supply voltage (DVDD); the gate of the PMOS transistor is connected to a level shifting circuit; the first terminal of the voltage divider resistor is connected to a third power supply voltage (AVDD), and the second terminal is grounded (DGND); the voltage divided by a node of the voltage divider resistor (AVDD_DIV) is used as the power supply voltage (VDD_SEL) of the level shifting circuit and is greater than the first power supply voltage (DVDD) to reduce the turn-off leakage current of the circuit module connected to the drain of the PMOS transistor. In some embodiments, the source of the PMOS transistor is connected to a first power supply voltage (DVDD); the gate of the PMOS transistor is connected to a control signal; the control voltage of the control signal when it is high is equal to the first power supply voltage (DVDD); the first terminal of the voltage divider resistor is connected to a third power supply voltage (VDDIO), and the second terminal is grounded (DGND); the voltage divider output through a node of the voltage divider resistor (VDDIO_DIV) and the first power supply voltage (DVDD) are used as inputs to a comparator; the output of the comparator is used as a control signal (CMP_OUT) for a multiplexer; the inputs of the multiplexer include the voltage divider (VDDIO_DIV) and the first power supply voltage (DVDD); based on the control signal (CMP_OUT), the voltage divider (VDDIO_DIV) or the first power supply voltage (DVDD) is selected to be connected to the substrate terminal to reduce the turn-off leakage current of the circuit module connected to the PMOS transistor.

[0012] In some embodiments, the source ground voltage (DGND) of the NMOS transistor; the gate of the NMOS transistor is connected to a level shifting circuit; the voltage output by the charge pump circuit is used as the ground voltage (VSS_SEL) of the level shifting circuit and is less than the ground voltage (DGND) to reduce the turn-off leakage current of the circuit module connected to the drain of the NMOS transistor.

[0013] In some embodiments, the source ground voltage (DGND) of the NMOS transistor; the gate of the NMOS transistor is connected to a control signal; the control voltage of the control signal at a low level is equal to the ground voltage (DGND); the voltage (VSSDD_SEL) output by the charge pump circuit is equal to or lower than the ground voltage (DGND) and connected to the substrate to reduce the turn-off leakage current of the circuit module connected to the NMOS transistor.

[0014] Compared with the prior art, the technical solution of the present invention improves the shutdown leakage current with only a small area and power consumption cost, ensuring a very low leakage current at all process corners and temperatures. Attached Figure Description

[0015] Figure 1 The diagram shows the circuit architecture of traditional gated power supply solutions that can use gated PMOS transistors and NMOS transistors.

[0016] Figure 2 This is a schematic diagram of a circuit architecture for reducing the turn-off leakage current of digital logic by selectively increasing the gate voltage of a gated PMOS transistor, according to an embodiment of the present invention.

[0017] Figure 3 For based on Figure 2 An exemplary timing diagram of the circuit architecture of the embodiment.

[0018] Figure 4 For based on Figure 2 Another exemplary timing diagram of the circuit architecture of the embodiment.

[0019] Figure 5 Another option in this embodiment of the invention is to increase the gate voltage of the gated PMOS transistor to reduce the turn-off leakage current of the digital logic.

[0020] Figure 6 Another option in this embodiment of the invention is to increase the gate voltage of the gated PMOS transistor to reduce the turn-off leakage current of the digital logic.

[0021] Figure 7 One embodiment of the present invention is to reduce the turn-off leakage current of digital logic by selectively increasing the substrate voltage of the gated PMOS transistor.

[0022] Figure 8 Another option in this embodiment of the invention is to increase the substrate voltage of the gated PMOS transistor to reduce the turn-off leakage current of the digital logic.

[0023] Figure 9 Another option in this embodiment of the invention is to increase the substrate voltage of the gated PMOS transistor to reduce the turn-off leakage current of the digital logic.

[0024] Figure 10 One embodiment of the present invention is to reduce the gate voltage of the gated NMOS transistor to reduce the turn-off leakage current of the digital logic.

[0025] Figure 11 For based on Figure 10 An exemplary timing diagram of the circuit architecture of the embodiment.

[0026] Figure 12 Another option in this embodiment of the invention is to reduce the substrate voltage of the gated NMOS transistor to reduce the turn-off leakage current of the digital logic. Detailed Implementation

[0027] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are merely some examples or embodiments of the present invention. For those skilled in the art, these drawings can be applied to other similar scenarios without creative effort. Unless obvious from the context or otherwise specified, the same reference numerals in the drawings represent the same structures or operations.

[0028] This invention proposes a method for reducing circuit turn-off leakage current by controlling the voltage of a PMOS or NMOS transistor. This is achieved by increasing the control voltage of the PMOS transistor's gate control signal when it is high above the PMOS transistor's source voltage, or by increasing the substrate voltage of the PMOS transistor when it is low above the PMOS transistor's source voltage, thereby reducing the turn-off leakage current of the circuit module connected to the drain of the PMOS transistor. Alternatively, this is achieved by decreasing the control voltage of the NMOS transistor's gate control signal when it is low below the NMOS transistor's source voltage, or by decreasing the substrate voltage of the NMOS transistor when it is low below the NMOS transistor's source voltage, thereby reducing the turn-off leakage current of the circuit module connected to the drain of the NMOS transistor. The circuit module includes digital or analog circuits that generate a leakage current exceeding milliamperes during turn-off.

[0029] The following diagram illustrates how to control the voltage of a PMOS or NMOS transistor to reduce the circuit's turn-off leakage current.

[0030] Figure 2 This invention provides a circuit architecture for reducing the turn-off leakage current of digital logic by selectively increasing the gate voltage of a gated PMOS transistor.

[0031] for Figure 2In the circuit structure shown, the source of the PMOS transistor is connected to the first power supply voltage (DVDD); the gate of the PMOS transistor is connected to the level transfer circuit.

[0032] The first terminal of the voltage divider resistor R is connected to the second power supply voltage (VDDIO), and the second terminal is grounded (DGND).

[0033] The voltage divided by a node of the voltage divider resistor R (VDDIO_DIV) and the first power supply voltage (DVDD) are used as inputs to the comparator.

[0034] The output (CMP_OUT) of the comparator (CMP) serves as the control signal (cmp_out) for the multiplexer.

[0035] The inputs of the multiplexer include a voltage divider (VDDIO_DIV) and a first supply voltage (DVDD). The voltage divider (VDDIO_DIV) or the first power supply voltage (DVDD) is selected as the power supply voltage (VDD_SEL) for the level shift circuit based on the control signal (CMP_OUT) to reduce the voltage drop of circuit modules connected to the drain of the PMOS transistor (such as...). Figure 2 The shutdown leakage current of the digital logic in the process.

[0036] Specifically, assuming DVDD uses a 1.1V voltage, VDDIO may be 1.8V or 1.2V depending on the usage requirements. This invention selects to divide the voltage across the voltage divider resistor R on VDDIO to generate a voltage VDDIO_DIV. The voltages of VDDIO and DVDD are compared, and based on the comparison result, DVDD or VDDIO is selected as the power supply voltage VDD_SEL for the level shift circuit. The input signal of the level shift circuit is gating_dg, and the output signal is gating_dg_bst, where the input signal range is 0~DVDD, and the output signal range is 0~VDD_SEL.

[0037] The signal rstn_dg is the global reset control signal for the input digital logic, and set_dg is the clamping control signal. In order to clamp the signal dg2ana sent to the analog circuit to a certain zero level when the digital logic is powered off by gate control, otherwise the uncertain voltage of the digital output may cause large leakage current when it is transmitted to the digital-analog interface, because there may be at least several hundred digital output signals here, and the leakage current may be very considerable. Here, when VDDIO is 1.8V, the voltage division result of the voltage divider resistor R, VDDIO_DIV, is 1.2V, and the result of cmp_out is 1, causing VDD_SEL to select VDDIO_DIV, with a voltage of 1.2V. The level shifting circuit thus increases the voltage range of the input signal from 0~DVDD to 0~1.2V. For a gated PMOS transistor, when the gate voltage is 1.2V and the source voltage is 1.1V, according to the exponential relationship between the subthreshold leakage current of the MOS transistor and Vsg-vth, a smaller Vsg voltage will significantly reduce the leakage current at turn-off (at this time, Vsg=-0.1V). When VDDIO is 1.2V, the voltage divider result VDDIO_DIV is 0.8V, and cmp_out is 0, causing VDD_SEL to select DVDD with a voltage of 1.1V. The output signal voltage range of the level shifter circuit remains 0~DVDD. For the gated PMOS transistor, both the gate and source voltages are 1.1V when turned off, so there is no improvement in leakage current. However, this application is mainly due to the variable voltage of VDDIO (1.8V and 1.2V compatible). 1.8V is the mainstream application, and some modules may use this voltage as the input of the LDO to generate a more stable output voltage to improve module performance. 1.2V is used as a test alternative or power-saving mode. If the solution of using VDDIO as 1.2V is determined in the future, VDDIO_DIV can also be directly connected to VDDIO through a metal connection to achieve the same effect of reducing leakage current when turning off digital logic as the above-mentioned VDDIO as 1.8V and then using resistor voltage divider.

[0038] In circuit design, the resistance value of the voltage divider resistor R can be increased as much as possible to reduce the current in the resistor-divider branch. The comparator current should also be optimized to save power consumption, since the comparator does not require high operating speed. Through circuit optimization, the power consumption of this invention's overall gated power control circuit can be reduced to around 1-2uA, thus saving the shutdown leakage current of the digital logic. In this way, the shutdown leakage current of the digital logic can be reduced by a factor of 10.

[0039] Figure 3The timing information for gating_dg, gating_dg_bst, set_dg, and rstn_dg is given when VDDIO is 1.8V.

[0040] When DVDD=1.1V, dvdd=1.1V, dvdd_bst=1.2V, and dgnd=0V in the diagram. The sequence can be generated by external hardware control signals through relevant logic.

[0041] Figure 2 In the process of transitioning from the hardware shutdown state to the power-on working state, the following sequence is followed to ensure that there is no abnormal leakage current at any moment during power-on: first, pull down gating_dg to stabilize the power supply, then release the clamp signal set_dg, and finally release the digital reset signal rstn_dg.

[0042] When switching from the working state to the power-off state, the reverse order is followed: first, pull rstn_dg low to reset the digital logic, then pull set_dg high to clamp the digital-to-analog interface signal, and finally remove the power supply to ensure that there is no abnormal leakage current at any moment during power-off.

[0043] Figure 4 The timing information for gating_dg, gating_dg_bst, set_dg, and rstn_dg when VDDIO = 1.2V is given.

[0044] and Figure 3 The difference is that the high level of gating_dg_bst is dvdd, which is 1.1V. As mentioned earlier, if the application specifies VDDIO as 1.2V, it can also be connected to VDDIO via a metal connection using VDDIO_DIV. In this case, the timing diagram will be the same as... Figure 3 Same.

[0045] Figure 5 Another option in this embodiment of the invention is to increase the gate voltage of the gated PMOS transistor to reduce the turn-off leakage current of the digital logic.

[0046] Specifically, the source of the PMOS transistor is connected to the first power supply voltage (DVDD); the gate of the PMOS transistor is connected to the level transfer circuit.

[0047] The first terminal of the voltage divider resistor is connected to the third power supply voltage (AVDD), and the second terminal is grounded (DGND). The voltage (AVDD_DIV) output from a certain node of the voltage divider resistor R is used as the power supply voltage (VDD_SEL) of the level shifting circuit and is greater than the first power supply voltage (DVDD) to reduce the voltage drop of circuit modules connected to the drain of the PMOS transistor (such as...). Figure 5The shutdown leakage current of the digital logic in the process.

[0048] For example, Figure 5 The third power supply voltage (AVDD) is directly divided to 1.2V using a resistor (AVDD is typically 2.8V), and then the divided voltage VDD_SEL is used as the power supply for the level shifting circuit. Subsequent logic implementation and... Figure 2 Similarly, the power supply voltage AVDD is fixed here. The resistance value of the voltage divider resistor R can be increased to reduce power consumption and control the power consumption of the entire circuit to less than 1~2uA. This is achieved by sacrificing 1~2uA of leakage current on AVDD in the off state in exchange for a significant reduction in the overall off leakage current of the digital logic.

[0049] Figure 6 Another option in this embodiment of the invention is to increase the gate voltage of the gated PMOS transistor to reduce the turn-off leakage current of the digital logic.

[0050] Specifically, the source of the PMOS transistor is connected to the first power supply voltage (DVDD); the gate of the PMOS transistor is connected to the level transfer circuit.

[0051] The voltage output by the charge pump circuit serves as the power supply voltage (VDD_SEL) for the level transfer circuit and is greater than the first power supply voltage (DVDD) to reduce the turn-off leakage current of the circuit module connected to the drain of the PMOS transistor. The specific structure of the charge pump can be any existing architecture, which will not be described in detail here.

[0052] For example, Figure 6 A charge pump circuit is used to boost the voltage to VDD_SEL of 1.2V. Subsequent logic implementation and... Figure 2 Similarly, the power consumption of the charge pump circuit can also be optimized to save on its own power consumption.

[0053] Figure 7 One embodiment of the present invention is to reduce the turn-off leakage current of digital logic by selectively increasing the substrate voltage of the gated PMOS transistor.

[0054] Specifically, the source of the PMOS transistor is connected to the first power supply voltage (DVDD).

[0055] The gate of the PMOS transistor is connected to the control signal; when the control signal is high, the control voltage is equal to the first power supply voltage (DVDD).

[0056] The first terminal of the voltage divider resistor R is connected to the third power supply voltage (VDDIO), and the second terminal is grounded (DGND).

[0057] The voltage divided by a node of the voltage divider resistor R (VDDIO_DIV) and the first power supply voltage (DVDD) are used as inputs to the comparator.

[0058] The comparator's output (CMP_OUT) serves as the control signal (CMP_OUT) for the multiplexer. The inputs of the multiplexer include a voltage divider (VDDIO_DIV) and a first supply voltage (DVDD).

[0059] The control signal (CMP_OUT) is used to select either the voltage divider (VDDIO_DIV) or the first power supply voltage (DVDD) to be connected to the substrate of the PMOS transistor, thereby reducing the load on circuit modules connected to the PMOS transistor (such as...). Figure 7 The shutdown leakage current of the digital logic in the process.

[0060] Figure 7 and Figure 2 The difference is that the selected voltage VDD_SEL is used to control the substrate of the gated PMOS transistor instead of the gate. This results in a larger threshold voltage Vth due to substrate modulation. According to the exponential relationship between the subthreshold leakage current of the MOS transistor and Vsg-Vth, a larger Vth will also help reduce the leakage current during turn-off. (The last part, "[removed here]", appears to be an error and is left untranslated.) Figure 2 The level shifting circuit in the circuit has a gate voltage range of 0 to DVDD for the gated PMOS transistor, and other circuits and Figure 2 Same, timing diagram and Figure 3 The difference is that there is no longer a gating_dg_bst signal.

[0061] Figure 8 Another option in this embodiment of the invention is to increase the substrate voltage of the gated PMOS transistor to reduce the turn-off leakage current of the digital logic.

[0062] The source of the PMOS transistor is connected to the first power supply voltage (DVDD).

[0063] The gate of the PMOS transistor is connected to the control signal (gating_dg); when the control signal is high, the control voltage is equal to the first power supply voltage (DVDD).

[0064] The first terminal of the voltage divider resistor R is connected to the third power supply voltage (AVDD), and the second terminal is grounded (DGND).

[0065] The voltage (AVDD_DIV) output from a certain node of the voltage divider resistor R, which is greater than the first power supply voltage (DVDD), is connected to the substrate to reduce the turn-off leakage current of the circuit module connected to the PMOS transistor.

[0066] Figure 9Another option in this embodiment of the invention is to increase the substrate voltage of the gated PMOS transistor to reduce the turn-off leakage current of the digital logic.

[0067] Specifically, the source of the PMOS transistor is connected to the first power supply voltage (DVDD).

[0068] The gate of the PMOS transistor is connected to the control signal gating_dg; when the control signal is high, the control voltage is equal to the first power supply voltage (DVDD).

[0069] The voltage (VDD_SEL) output by the charge pump circuit is greater than the first power supply voltage (DVDD) and is connected to the substrate of the PMOS transistor to reduce the turn-off leakage current of the circuit module connected to the PMOS transistor.

[0070] and Figure 6 The difference is that the VDD_SEL voltage here is used to control the substrate terminal of the gated PMOS transistor, not the gate terminal; the VDD_SEL voltage has been removed. Figure 6 The level shifting circuit in the circuit has a gate voltage range of 0 to DVDD for the gated PMOS transistor, and other circuits and Figure 6 Same, timing diagram and Figure 3 The difference is that there is no longer a gating_dg_bst signal.

[0071] Figure 10 This invention provides a method for reducing the turn-off leakage current of digital logic by controlling the gate voltage of an NMOS transistor.

[0072] Specifically, the source of the NMOS transistor is grounded (DGND); the gate of the PMOS transistor is connected to a level shifting circuit. One end of the level shifting circuit is connected to the input signal gating_dg.

[0073] The voltage (VSS_SEL) output by the charge pump circuit is used as the ground voltage (VSS_SEL) of the level transfer circuit and is less than the ground voltage (DGND) to reduce the turn-off leakage current of the circuit module connected to the drain of the NMOS transistor.

[0074] and Figure 6 The difference is here in such Figure 1 As shown, based on the pull-down NMOS transistor, a negative charge pump is used to reduce the minimum gate voltage of the NMOS transistor to below ground voltage, for example, -0.1V. Reducing the Vgs voltage of the NMOS transistor during turn-off can also achieve a similar effect to the turn-off leakage current of a PMOS transistor.

[0075] Generally, NMOS transistors have higher mobility than PMOS transistors, so using NMOS transistors may save area. The input signal of the level shift circuit here is `gating_dg`, with a voltage range from 0 to `dvdd` (1.1V), and the output signal is `gating_dg_down`, with a voltage range from -0.1V to `dvdd` (1.1V). The VSS_SEL voltage (-0.1V) output from the negative voltage charge pump is provided to the level shift circuit. The difference from the PMOS implementation is that the NOR gate before the `dig2ana` signal generation is replaced with a NAND gate. Because when the ground voltage of the digital logic is turned off by the gate, `digout` will be in an uncertain state. `set_dg` is used to control the NAND gate to clamp the output to 1, preventing leakage in subsequent circuits due to the uncertain output state.

[0076] Figure 11 Give Figure 10 The timing diagram implemented using an NMOS transistor shows that dgnd is 0V, dgnd_low is -0.1V, and... Figure 3 In contrast, the amplitude ranges of `gating_dg` and `set_dg` change in opposite directions. `gating_dg` shuts down the NMOS controller when low, `set_dg` clamps the output when low, and `rstn_dg` remains low to shut down the digital logic circuit. When transitioning from the hardware shutdown state to the power-on operating state, the sequence of first pulling `gating_dg` high for power stabilization, then releasing the clamping signal of `set_dg`, and finally releasing the digital reset signal `rstn_dg` ensures no abnormal leakage current at any moment during power-on. When switching from the operating state to the power-off state, the sequence is reversed: first pulling `rstn_dg` low to reset the digital signal, then pulling `set_dg` low to clamp the digital-to-analog interface signal, and finally removing the power supply to ensure no abnormal leakage current at any moment during power-off.

[0077] Figure 12 This invention provides a method for reducing the turn-off leakage current of digital logic by controlling the substrate voltage of an NMOS transistor.

[0078] Specifically, the source ground voltage (DGND) of the NMOS transistor.

[0079] The gate of the NMOS transistor is connected to the control signal (gating_dg); when the control signal is low, the control voltage is equal to the ground voltage (DGND).

[0080] By connecting the voltage (VSS_SEL) output by the charge pump circuit to the substrate of the NMOS transistor, which is lower than the ground voltage (DGND), the turn-off leakage current of the circuit module connected to the NMOS transistor is reduced.

[0081] By using a negative voltage output from the charge pump, such as -0.1V, to control the substrate of the NMOS transistor, the turn-off leakage current can be reduced by increasing the threshold voltage. Figure 10 Compared to eliminating the level shifting circuit, the gate voltage range of the gated NMOS is 0~DVDD, and other circuits and Figure 10 Same. Timing diagram and Figure 11 The difference is that there is no longer a gating_dg_down signal.

[0082] It should be noted that the specific voltage values ​​above are for illustrative purposes only. For example, the ground voltage (DGND) can be set to 0V, or it can be set to other values ​​depending on other application environments.

[0083] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the invention. Therefore, the embodiments should be considered exemplary and not restrictive in any way. Furthermore, it is clear that the word "comprising" does not exclude other elements and steps, and the word "a" does not exclude a plural. Multiple elements recited in the apparatus claims may also be implemented by a single element. The terms "first," "second," etc., are used to denote names and do not indicate any particular order.

Claims

1. A method for reducing circuit turn-off leakage current by controlling the voltage of a PMOS or NMOS transistor, characterized in that, By increasing the control voltage of the gate control signal of the PMOS transistor to a higher level than the source voltage of the PMOS transistor, or by increasing the substrate voltage of the PMOS transistor to a higher level than the source voltage of the PMOS transistor, the turn-off leakage current of the circuit module connected to the drain of the PMOS transistor is reduced. or By reducing the control voltage of the gate control signal of the NMOS transistor to a low level below the source voltage of the NMOS transistor, or by reducing the substrate voltage of the NMOS transistor to a lower level than the source voltage of the NMOS transistor, the turn-off leakage current of the circuit module connected to the drain of the NMOS transistor is reduced.

2. The method as described in claim 1, characterized in that, The circuit module includes digital or analog circuits that generate leakage current exceeding the milliampere level when turned off.

3. The method as described in claim 1, characterized in that, The source of the PMOS transistor is connected to the first power supply voltage (DVDD); the gate of the PMOS transistor is connected to a level shifting circuit. The first terminal of the voltage divider resistor is connected to the second power supply voltage (VDDIO), and the second terminal is grounded (DGND). The voltage divided by a node of the voltage divider resistor (VDDIO_DIV) and the first power supply voltage (DVDD) are used as inputs to the comparator. The output of the comparator serves as the control signal (CMP_OUT) for the multiplexer. The inputs of the multiplexer include the voltage divider (VDDIO_DIV) and the first power supply voltage (DVDD). Based on the control signal (CMP_OUT), the voltage divider (VDDIO_DIV) or the first power supply voltage (DVDD) is selected as the power supply voltage (VDD_SEL) of the level transfer circuit to reduce the turn-off leakage current of the circuit module connected to the drain of the PMOS transistor.

4. The method as described in claim 1, characterized in that, The source of the PMOS transistor is connected to the first power supply voltage (DVDD); the gate of the PMOS transistor is connected to a level shifting circuit. The voltage output by the charge pump circuit is used as the power supply voltage (VDD_SEL) of the level transfer circuit and is greater than the first power supply voltage (DVDD) to reduce the turn-off leakage current of the circuit module connected to the drain of the PMOS transistor.

5. The method as described in claim 1, characterized in that, The source of the PMOS transistor is connected to the first power supply voltage (DVDD); the gate of the PMOS transistor is connected to a level shifting circuit. The first terminal of the voltage divider resistor is connected to the third power supply voltage (AVDD), and the second terminal is grounded (DGND). The voltage (AVDD_DIV) output from a node of the voltage divider resistor is used as the power supply voltage (VDD_SEL) of the level transfer circuit and is greater than the first power supply voltage (DVDD) to reduce the turn-off leakage current of the circuit module connected to the drain of the PMOS transistor.

6. The method as described in claim 1, characterized in that, The source of the PMOS transistor is connected to the first power supply voltage (DVDD). The gate of the PMOS transistor is connected to a control signal; the control voltage of the control signal when it is high is equal to the first power supply voltage (DVDD). The first terminal of the voltage divider resistor is connected to the third power supply voltage (VDDIO), and the second terminal is grounded (DGND). The voltage divided by a node of the voltage divider resistor (VDDIO_DIV) and the first power supply voltage (DVDD) are used as inputs to the comparator. The output of the comparator serves as the control signal (CMP_OUT) for the multiplexer. The inputs of the multiplexer include the voltage divider (VDDIO_DIV) and the first power supply voltage (DVDD). Based on the control signal (CMP_OUT), the voltage divider (VDDIO_DIV) or the first power supply voltage (DVDD) is selected to be connected to the substrate to reduce the turn-off leakage current of the circuit module connected to the PMOS transistor.

7. The method as described in claim 1, characterized in that, The source of the PMOS transistor is connected to the first power supply voltage (DVDD). The gate of the PMOS transistor is connected to a control signal; the control voltage of the control signal when it is high is equal to the first power supply voltage (DVDD). The voltage (VDD_SEL) output by the charge pump circuit, which is greater than the first power supply voltage (DVDD), is connected to the substrate to reduce the turn-off leakage current of the circuit module connected to the PMOS transistor.

8. The method as described in claim 1, characterized in that, The source of the PMOS transistor is connected to the first power supply voltage (DVDD). The gate of the PMOS transistor is connected to a control signal; the control voltage of the control signal when it is high is equal to the first power supply voltage (DVDD). The first terminal of the voltage divider resistor is connected to the third power supply voltage (AVDD), and the second terminal is grounded (DGND). The voltage (AVDD_DIV) output from a node of the voltage divider resistor, which is greater than the first power supply voltage (DVDD), is connected to the substrate to reduce the turn-off leakage current of the circuit module connected to the PMOS transistor.

9. The method as described in claim 1, characterized in that, The source ground voltage (DGND) of the NMOS transistor; the gate level shift circuit of the NMOS transistor; The voltage output by the charge pump circuit is used as the ground voltage (VSS_SEL) of the level shift circuit and is less than the ground voltage (DGND) to reduce the turn-off leakage current of the circuit module connected to the drain of the NMOS transistor.

10. The method as described in claim 1, characterized in that, The source ground voltage (DGND) of the NMOS transistor. The gate of the NMOS transistor is connected to a control signal; the control voltage of the control signal when it is low is equal to the ground voltage (DGND). The voltage (VSS_SEL) output by the charge pump circuit is lower than the ground voltage (DGND) and is connected to the substrate to reduce the turn-off leakage current of the circuit module connected to the NMOS transistor.

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