An igbt desaturation short circuit protection system and method

Abstract

The application discloses an IGBT desaturation short-circuit protection system and method, which comprises a front limiting current module, a passive clamping branch is arranged in the front limiting current module, the passive clamping branch is connected between a first potential node, a second potential node on the emitter side of an IGBT and a gate of the IGBT, and is used for limiting the short-circuit current in advance when a short-circuit fault occurs; and a detection and shutdown module, the detection and shutdown module is internally provided with a detection loop, a transient suppression element, a fault recognition and shutdown component, a high-voltage isolation element, a resistance-capacitance element and a constant current source branch; the system realizes two-stage cooperative protection of "pre-limiting current + post-shutdown", breaks through the limitation that traditional DESAT protection can only be post-shutdown, and solves the problem that the short-circuit current has climbed to a peak value before detection is completed; the design that the transient suppression element is connected with a driving negative power supply solves the problem that a traditional one-way clamping cannot suppress high dv / dt negative overshoot, and prevents related functional devices from exceeding a safe working area.

Description

Technical Field

[0001] This invention relates to the field of IGBT drive protection circuit technology, and in particular to an IGBT desaturation short-circuit protection system. Background Technology

[0002] Insulated-gate bipolar transistors (IGBTs) are widely used in high-power applications such as frequency converters, new energy vehicles, rail transportation, and photovoltaic inverters. Under actual operating conditions, load short circuits, abnormal drive signals, or freewheeling circuit failures can all cause IGBT short-circuit faults. When a short circuit occurs, the IGBT current rises sharply to several times or even tens of times its rated current, and the collector-emitter voltage VCE subsequently rises to the bus voltage level. The short-circuit withstand time of an IGBT is typically only a short time... During this period, the protection circuit must complete fault detection and safely shut down the device; otherwise, the device will be damaged due to overheating.

[0003] The desaturation protection (DESAT) determines the IGBT's operating status by monitoring VCE: During normal conduction, VCE(sat) is typically below 4V. After short-circuit desaturation, VCE rises rapidly and exceeds the detection threshold, triggering fault protection. The detection circuit utilizes the high-voltage diode DH to capacitor the DESAT pin. Charging, when Voltage reaches comparator threshold When the comparator output flips, it triggers a soft shutdown sequence.

[0004] VCE overshoot during IGBT activation will generate high The high-voltage diode DH is coupled to the DESAT pin, causing interference to the detection circuit. The DESAT pin is typically clamped by a TVS diode (transient voltage suppressor diode) to prevent overvoltage damage to the subsequent comparator. In existing solutions, the TVS anode is grounded (GND), achieving only unidirectional (upper limit) clamping. Under certain conditions, rapid changes in VCE generate bidirectional overshoots (positive and negative) on the DESA pin. When the TVS anode is grounded, only the positive overshoot can be suppressed; the negative overshoot cannot be effectively suppressed, potentially causing the comparator input to exceed the safe operating area, leading to false triggering or even gate breakdown. Currently, there is a lack of a method to address this issue at high voltage levels. This paper proposes a technical solution for bidirectional clamping protection of Desat nodes under certain conditions. Existing Desat protection only triggers shutdown after a short circuit is detected, which is a "post-event shutdown" mechanism. After a short circuit occurs, before the protection circuit completes detection, the short-circuit current has already climbed to its peak value, typically reaching 8 to 12 times the rated current. During this stage, the device experiences extremely high transient power, causing thermal damage or module malfunction. Currently, there is a lack of a pre-current limiting method to actively reduce the peak short-circuit current before Desat protection activates. Summary of the Invention

[0005] In order to overcome the shortcomings of existing technologies, such as the lack of pre-current limiting methods and bidirectional clamping protection.

[0006] In a first aspect, the present invention provides an IGBT desaturation short-circuit protection system, comprising: The pre-current limiting module is configured with a passive clamping branch, which is connected between the first potential node and the second potential node on the emitter side of the IGBT and the gate of the IGBT, and is used to pre-limit the short-circuit current when a short-circuit fault occurs. The detection and shutdown module includes a built-in detection circuit, transient suppression element, fault identification and shutdown component, high-voltage isolation element, RC element, and constant current source branch. The detection circuit has a detection node, which is coupled to the transient suppression element, high-voltage isolation element, RC element, and constant current source branch. The fault identification and shutdown component is electrically coupled to the detection node to acquire the detection node signal and execute the IGBT shutdown action. The high-voltage isolation element is installed between the IGBT collector and the detection node. The RC element and constant current source branch are electrically connected to the detection node. The signal input terminal of the fault identification and shutdown component is connected to the detection node, and the transient suppression element is connected to both the drive negative power supply and the detection node.

[0007] Optionally, the RC element includes a charging resistor and a node capacitor, one end of the charging resistor is electrically connected to the detection node, and the other end of the charging resistor is electrically connected to the constant current source branch; one end of the node capacitor is electrically connected to the detection node.

[0008] Optionally, the constant current source branch is a built-in constant current source integrated into the IGBT driver chip, and the high-voltage isolation element is a high-voltage isolation diode with unidirectional conduction characteristics.

[0009] Optionally, the fault identification shutdown component has a built-in threshold generation circuit, which includes a bandgap reference voltage source, a unity-gain buffer circuit, and a calibrated common-source cascode current mirror. The output of the bandgap reference voltage source is connected to the input of the unity-gain buffer circuit, the output of the unity-gain buffer circuit is connected to the input of the calibrated common-source cascode current mirror, and the output of the calibrated common-source cascode current mirror constitutes the output of the threshold generation circuit and is connected to the first input terminal of the hysteresis comparator circuit.

[0010] Optionally, the fault identification and shutdown component incorporates a hysteresis comparator circuit, which includes a high-voltage differential pair, an asymmetric current mirror, and a voltage-to-current-to-voltage conversion structure. The two input terminals of the high-voltage differential pair respectively constitute the first and second input terminals of the hysteresis comparator circuit. The two output terminals of the high-voltage differential pair are connected to the two input branches of the asymmetric current mirror. The output terminal of the asymmetric current mirror is connected to the input terminal of the voltage-to-current-to-voltage conversion structure, and the output terminal of the voltage-to-current-to-voltage conversion structure constitutes the single-ended output terminal of the hysteresis comparator circuit.

[0011] Optionally, the hysteresis comparator circuit further includes a breakdown clamping structure, one end of which is electrically connected to the detection node.

[0012] Optionally, it further includes a gate voltage follower unit, which includes a first high-voltage field-effect transistor (MOSFET), a second high-voltage field-effect transistor (MOSFET), and a reset switch. The sources of the first and second MOSFETs are connected. The first MOSFET is connected between the IGBT gate and the internal follower node, and the second MOSFET is connected between the second access terminal of the fault identification shutdown component and the internal follower node. The reset switch is connected between the second access terminal of the fault identification shutdown component and the driver chip ground.

[0013] Optionally, the passive clamping branch includes an NPN transistor, a transient voltage suppressor (TVS) transistor, and a switching diode; the base of the NPN transistor is connected to a first potential node on the emitter side of the IGBT, the emitter of the NPN transistor is connected to a second potential node on the emitter side of the IGBT, the collector of the NPN transistor is connected to one end of the TVS transistor, and the other end of the TVS transistor is connected to the gate of the IGBT; the switching diode is connected in reverse parallel between the base and emitter of the NPN transistor.

[0014] Optionally, the fault identification shutdown component also integrates a shutdown execution circuit, wherein the threshold generation circuit, the hysteresis comparator circuit, and the shutdown execution circuit are electrically connected in sequence.

[0015] The beneficial effects of this invention are: This system achieves two-level coordinated protection of "pre-current limiting + post-shutdown", which breaks through the limitation of traditional DESAT protection that can only shut down after the fact and solves the problem that the short-circuit current has climbed to the peak value before the detection is completed; The design of the transient suppression element connected to the drive negative power supply solves the problem that traditional unidirectional clamping cannot suppress high dv / dt negative overshoot and prevents related functional devices from exceeding the safe operating area. Attached Figure Description

[0016] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0017] Figure 1 This is a schematic diagram of the overall architecture of the desaturation short-circuit protection system; Figure 2 These are schematic diagrams of the threshold generation circuit structure in some embodiments; Figure 3 These are schematic diagrams of hysteresis comparator circuit structures in some embodiments; Figure 4 These are schematic diagrams of gate voltage follower circuit structures in some embodiments; Figure 5 These are schematic diagrams of the TVS bidirectional clamping circuit for the DESAT pin in some embodiments; Figure 6 These are schematic diagrams of passive clamping branch current limiting circuits in some embodiments. Detailed Implementation

[0018] The following will clearly and completely describe the concept, specific structure, and technical effects of the present invention in conjunction with embodiments and accompanying drawings, so as to fully understand the purpose, features, and effects of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, not all of them. Other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are all within the scope of protection of the present invention. Furthermore, all connections / linkages involved in the patent do not simply refer to direct contact between components, but rather to the ability to form a better connection structure by adding or reducing connecting accessories according to specific implementation conditions. The various technical features in this invention can be combined interactively without contradicting each other.

[0019] This invention provides an IGBT desaturation short-circuit protection system. Figure 1 The overall architecture of the desaturation short-circuit protection system is demonstrated, including: The pre-current limiting module is configured with a passive clamping branch, which is connected between the first potential node and the second potential node on the emitter side of the IGBT and the gate of the IGBT, and is used to pre-limit the short-circuit current when a short-circuit fault occurs. The detection and shutdown module includes a built-in detection circuit, transient suppression element, fault identification and shutdown component, high-voltage isolation element, RC element, and constant current source branch. The detection circuit has a detection node, which is coupled to the transient suppression element, high-voltage isolation element, RC element, and constant current source branch. The fault identification and shutdown component is electrically coupled to the detection node to acquire the detection node signal and execute the IGBT shutdown action. The high-voltage isolation element is installed between the IGBT collector and the detection node. The RC element and constant current source branch are electrically connected to the detection node. The signal input terminal of the fault identification and shutdown component is connected to the detection node, and the transient suppression element is connected to the driving negative power supply.

[0020] Specifically, the pre-current limiting module operates through a passive clamping branch connected between the first and second potential nodes on the emitter side of the IGBT and the gate of the IGBT. When a short-circuit fault occurs in the IGBT, the potential difference generated by the short-circuit current flowing through the power circuit on the first and second potential nodes on the emitter side triggers the passive clamping branch to conduct, directly pulling down the gate-source voltage of the IGBT. This limits the rise of the short-circuit current in advance before the detection and turn-off module completes the fault detection. The detection and shutdown module is centered around the DESAT detection node: a high-voltage isolation element is installed between the IGBT collector and the detection node to isolate the high-voltage and low-voltage sides; the constant current source branch charges the detection node through RC components, the parameters of which determine the time constant of the detection circuit; the transient suppression element adopts the original core improvement scheme, connecting to the driver negative power supply instead of the traditional ground, utilizing its bidirectional conduction characteristics to simultaneously suppress the forward and reverse voltage overshoot of the detection node; the fault identification and shutdown component collects the voltage signal of the detection node in real time, and when the signal exceeds the preset desaturation threshold, it outputs a control signal to execute the IGBT soft shutdown action. All improvements in this system do not modify the internal circuitry of the IGBT driver chip, but are only implemented through external circuit optimization.

[0021] This system achieves two-level coordinated protection of "pre-current limiting + post-shutdown", breaking through the limitation of traditional DESAT protection that can only shut down after the fact, and solving the problem that the short-circuit current has climbed to the peak value before the detection is completed; the design of the transient suppression element connected to the drive negative power supply solves the problem that traditional unidirectional clamping cannot suppress high dv / dt negative overshoot, and prevents related functional devices from exceeding the safe operating area.

[0022] Furthermore, the constant current source branch is a built-in constant current source integrated within the IGBT driver chip. The high-voltage isolation element is a high-voltage diode DH with unidirectional conduction characteristics. The detection node is the DESAT pin. The anode of the high-voltage diode DH is connected to the collector C of the power device, and its cathode is connected to the DESAT pin, used to detect the desaturation state of the power device. The resistive-capacitive elements include a charging resistor and a node capacitor. One end of the charging resistor is electrically connected to the detection node, and the other end of the charging resistor is electrically connected to the constant current source branch. One end of the node capacitor is electrically connected to the detection node. That is, the DESAT pin is also connected to one end of the node capacitor Cb. The other end is grounded; charging resistor One end is connected to an internal constant current source The other end is connected to the DESAT pin, which is used to set the time constant of the DESAT detection circuit. The transient suppression element is the original TVS tube (SMAJ20CA) on the DESAT detection pin.

[0023] like Figure 5As shown, the anode connection of the original TVS diode on the DESAT detection pin is changed from GND to drive the negative power supply VEE, while the cathode of the TVS diode remains connected to the DESAT detection pin. This embodiment of the invention utilizes the bidirectional conduction characteristics of a bidirectional TVS diode to extend the clamping range of the DESAT pin from the upper limit of +20 V (TVS breakdown voltage) of the traditional grounding scheme to [-5.7 V, +15 V]. Under the high dv / dt conditions of the IGBT turn-on process, this scheme effectively suppresses the negative overshoot generated by rapid changes in VCE on the DESAT pin, preventing the comparator input from exceeding the safe operating area. Actual measurements show that this scheme can withstand dv / dt up to 46.8 V / ns, an improvement of more than 3 times, eliminating false triggering of the DESAT node caused by high-speed switching.

[0024] In some embodiments, the fault identification shutdown component has a built-in threshold generation circuit, which includes a bandgap reference voltage source, a unity-gain buffer circuit, and a calibrated common-source cascode current mirror. The output of the bandgap reference voltage source is connected to the input of the unity-gain buffer circuit, the output of the unity-gain buffer circuit is connected to the input of the calibrated common-source cascode current mirror, and the output of the calibrated common-source cascode current mirror constitutes the output of the threshold generation circuit and is connected to the first input of the hysteresis comparator circuit.

[0025] Specifically, the desaturation threshold generation circuit is used to generate a precise threshold voltage of 9V. The bandgap reference voltage source generates the bandgap reference voltage. Through the bandgap reference voltage High-precision current is generated through a unity-gain buffer circuit and a calibrated cascode current mirror. Multiplying the current by the calculated resistance value yields the precise threshold voltage. The threshold voltage is then output to the first input terminal of the hysteresis comparator circuit.

[0026] like Figure 2 As shown, the desaturation threshold generation circuit includes high-voltage PMOS transistors HMP1 and HMP2, low-voltage PMOS transistors MP1 and MP2, resistors R2, R3, R4, and R5, transient enhancement capacitors CTS1, CTS2, CTS3, and CTS4, and a bias voltage. .

[0027] The gate of high-voltage PMOS transistor HMP1 is connected to the bias voltage, its source is connected to the power supply VDD, and its drain is connected to the source of high-voltage PMOS transistor HMP2. The gate of high-voltage PMOS transistor HMP2 is connected to the internal current IBIAS, and its drain serves as the output terminal of the circuit, outputting the threshold voltage. .

[0028] The other end of resistor R2 is connected to one end of resistor R3, and it also serves as an internal node of the circuit, outputting a bias voltage. The other end of resistor R3 is grounded; the other end of resistor R4 is connected to one end of resistor R5; the other end of resistor R5 is grounded.

[0029] One end of transient enhancement capacitor CTS1 is connected to the gate of high-voltage PMOS transistor HMP1, and the other end is grounded; one end of transient enhancement capacitor CTS2 is connected to the gate of high-voltage PMOS transistor HMP2, and the other end is grounded; one end of transient enhancement capacitor CTS3 is connected to the connection node of resistors R2 and R3, and the other end is grounded; one end of transient enhancement capacitor CTS4 is connected to the connection node of resistors R4 and R5, and the other end is grounded.

[0030] Current The current flows into the gate of the high-voltage PMOS transistor HMP2, controlling its drain output voltage. Resistors R2 and R3 are connected in series and grounded, generating a bias voltage at their connection point. (Approximately 6V) provides bias for the subsequent comparator. Transient enhancement capacitors CTS1~CTS4 are used to reduce voltage and current jitter and improve the circuit's anti-interference capability.

[0031] In the circuit generating the "9V" threshold, resistors R2 and R3 use the same process angle as resistor R1 in the bandgap reference, thereby compensating for temperature drift and process angle deviations to form a current-mode reference voltage. Simulation results show that the generated... The voltage value process angle error is approximately 1.4~1.6%, and the worst temperature coefficient is... .

[0032] The formula for calculating the threshold voltage VDST,TH is:

[0033] In some embodiments, the fault identification and shutdown component incorporates a hysteresis comparator circuit, which includes a high-voltage differential pair, an asymmetric current mirror, and a voltage-to-current-to-voltage conversion structure. The two input terminals of the high-voltage differential pair respectively constitute the first and second input terminals of the hysteresis comparator circuit. The two output terminals of the high-voltage differential pair are connected to the two input branches of the asymmetric current mirror. The output terminal of the asymmetric current mirror is connected to the input terminal of the voltage-to-current-to-voltage conversion structure, and the output terminal of the voltage-to-current-to-voltage conversion structure constitutes the single-ended output terminal of the hysteresis comparator circuit.

[0034] Specifically, the high-voltage differential pair uses a high-voltage PMOS differential pair as the input stage, which can withstand the high common-mode input voltage of the detection node and convert the difference between the detection node voltage and the threshold voltage into a current signal; the asymmetric current mirror adopts an asymmetric cross-current mirror structure to achieve hysteresis function, so that the comparator has different forward and reverse flip thresholds to prevent output oscillation caused by voltage disturbances; the voltage-current-voltage conversion structure converts the differential current signal into a single-ended voltage signal and simultaneously achieves level shifting, converting the signal from the VDD-GND power rail to the VREG-GND power rail to match the input level requirements of the subsequent circuit.

[0035] In some embodiments, the hysteresis comparator circuit further includes a breakdown clamping structure, one end of which is electrically connected to a detection node.

[0036] Specifically, the breakdown-proof clamping structure is electrically connected to the detection node at one end and grounded at the other. When an abnormally high voltage occurs at the detection node, the high-voltage NMOS transistor in the clamping structure quickly turns on, limiting the voltage of the detection node to a safe range of approximately 2.2V. This prevents excessive voltage from being applied to the gate of the high-voltage PMOS input transistor in the subsequent fault identification and shutdown component, thus avoiding gate oxide breakdown. This structure utilizes the conduction characteristics of the MOS transistor to achieve voltage clamping, with a response speed reaching the nanosecond level.

[0037] like Figure 3 As shown, the hysteresis comparator circuit includes high-voltage PMOS transistors HMP1, HMP2, HMP3, HMP4, HMP5, HMP6, high-voltage NMOS transistors HMN1 and HMN2, low-voltage PMOS transistors MP1, MP2, MP3, MP4, MN1, MN2, MN3, MN4, MN5, MN6, MN7, and MN8.

[0038] The gate of the high-voltage PMOS transistor HMP1 is connected to the input voltage VIN+, its source is connected to the power supply VDD, and its drain is connected to the drain of the low-voltage NMOS transistor MN1 and the source of the high-voltage PMOS transistor HMP3; the gate of the high-voltage PMOS transistor HMP2 is connected to the input voltage VIN-, its source is connected to the power supply VDD, and its drain is connected to the drain of the low-voltage NMOS transistor MN2 and the source of the high-voltage PMOS transistor HMP4.

[0039] The gate of the high-voltage PMOS transistor HMP3 is connected to the bias voltage VBIAS, and its drain outputs the internal voltage VO-; the gate of the high-voltage PMOS transistor HMP4 is connected to the bias voltage VBIAS, and its drain outputs the internal voltage VO+. The sources of the high-voltage PMOS transistors HMP3 and HMP4 are connected to the drains of the low-voltage NMOS transistors MN1 and MN2, respectively.

[0040] The gate of high-voltage PMOS transistor HMP5 is connected to the gate of high-voltage PMOS transistor HMP2, its source is connected to the power supply VDD, and its drain is connected to the drain of high-voltage NMOS transistor HMN1; the gate of high-voltage PMOS transistor HMP6 is connected to the gate of high-voltage PMOS transistor HMP1, its source is connected to the power supply VDD, and its drain is connected to the drain of high-voltage NMOS transistor HMN2.

[0041] The gate of high-voltage NMOS transistor HMN1 is connected to the power supply VDD, and its source is grounded; the gate of high-voltage NMOS transistor HMN2 is connected to the power supply VDD, and its source is grounded. HMN1 and HMN2 form a breakdown protection structure, clamping VSEN to a safe range.

[0042] The gate of the low-voltage NMOS transistor MN1 is connected to the bias voltage, and its source is grounded; the gate of the low-voltage NMOS transistor MN2 is connected to the bias voltage, and its source is grounded.

[0043] The gate of low-voltage NMOS transistor MN3 is connected to the internal voltage VO+, and its drain is connected to the drain of low-voltage NMOS transistor MN5; the gate of low-voltage NMOS transistor MN4 is connected to the internal voltage VO+, and its drain is connected to the drain of low-voltage NMOS transistor MN6; the gate of low-voltage NMOS transistor MN5 is connected to the bias voltage, and its source is connected to the tail current IB; the gate of low-voltage NMOS transistor MN6 is connected to the bias voltage, and its source is connected to the tail current IB.

[0044] The gate of the low-voltage NMOS transistor MN7 is connected to the internal voltage VO-, and its drain is connected to the output terminal VOUT; the gate of the low-voltage NMOS transistor MN8 is connected to the bias voltage, its drain is connected to the tail current IB, and its source is grounded.

[0045] The gate of the low-voltage PMOS transistor MP1 is connected to the bias voltage, its source is connected to the power supply VREG, and its drain is connected to the source of the low-voltage NMOS transistor MN3; the gate of the low-voltage PMOS transistor MP2 is connected to the bias voltage, its source is connected to the power supply VREG, and its drain is connected to the source of the low-voltage NMOS transistor MN4.

[0046] The gate of the low-voltage PMOS transistor MP3 is connected to the gate of the low-voltage NMOS transistor MN3, its source is connected to the power supply VREG, and its drain is connected to the source of the low-voltage NMOS transistor MN7; the gate of the low-voltage PMOS transistor MP4 is connected to the gate of the low-voltage NMOS transistor MN4, its source is connected to the power supply VREG, and its drain is connected to the tail current IB.

[0047] When VSEN (Followed by VIN-) Less than V DST,TH When connected to VIN+, high-voltage PMOS transistor HMP1 is turned on, HMP2 is turned off, MN5 and MN6 are about to turn on, and the tail current IB flows entirely through HMP1 and MN5. VO+ outputs a high level, and V... OUT When the output is low, no fault occurs; when V SEN Greater than V DST,TH At this time, the high-voltage PMOS transistor HMP1 is cut off, HMP2 is turned on, and the tail current IB flows entirely through HMP2 and MN6, V O- Output high level, V OU When the output T is high, a desaturation fault occurs.

[0048] The circuit uses an asymmetric cross-current mirror to achieve hysteresis. The switching threshold satisfies the following formula: Positive threshold

[0049] Reverse threshold

[0050] Hysteresis window

[0051] The hysteresis comparator in this embodiment of the invention has the following characteristics: no hysteresis is set in the positive direction, and the flip occurs at VDST,TH; the reverse hysteresis window is about 0.2V to prevent oscillation caused by voltage disturbances.

[0052] Due to the reference potential The voltage is 9V, and the input uses a high-voltage PMOS pair. When the branch is fully turned on, the VO potential may exceed 5.5V (the breakdown voltage of the input transistor). Therefore, a bias VBIAS (approximately 6V) is added to limit VO to a safe range.

[0053] The output adopts a VIV structure to convert the dual-ended output to a single-ended output, while also realizing the level shifting function to convert the signal from the VDD-GND power rail to the VREG-GND power rail.

[0054] The breakdown protection structure consisting of HMN1 and HMN2 is used to protect the input tube: when VSEN rises, HMN2 conducts, turning on V... SEN Clamped to approximately 2.2V to prevent gate oxide breakdown of the high-voltage PMOS input transistor.

[0055] Simulation results show that the comparator's positive threshold 8.95V, reverse threshold The input voltage is 8.75V, the hysteresis window size is 0.2V, the input offset voltage is -100mV, the rising edge propagation delay is 10.5ns, and the falling edge propagation delay is 2.4ns.

[0056] In some embodiments, a gate voltage follower unit is further included, the gate voltage follower unit including a first high-voltage field-effect transistor, a second high-voltage field-effect transistor, and a reset switch transistor, the sources of the first high-voltage field-effect transistor and the second high-voltage field-effect transistor are connected; the first high-voltage field-effect transistor is connected between the IGBT gate and the internal follower node, the second high-voltage field-effect transistor is connected between the second access terminal of the fault identification shutdown component and the internal follower node; the reset switch transistor is connected between the second access terminal of the fault identification shutdown component and the driver chip ground.

[0057] Specifically, the first and second high-voltage MOSFETs are two high-voltage LDMOS transistors connected at their sources to form a source follower structure. The first high-voltage MOSFET is connected between the IGBT gate and the internal follower node, and the second high-voltage MOSFET is connected between the second access terminal of the fault identification and shutdown component and the internal follower node. The reset switch is a low-voltage NMOS transistor connected between the second access terminal of the fault identification and shutdown component and the driver chip ground. When the enable signal is valid, the two high-voltage LDMOS transistors are turned on, and the voltage of the internal follower node follows the change of the IGBT gate voltage, so that the voltage of the second access terminal of the fault identification and shutdown component is consistent with the IGBT gate voltage. When the IGBT gate voltage exceeds the overdrive voltage of the high-voltage LDMOS transistors, the MOSFETs enter the subthreshold region and gradually turn off, clamping the voltage of the second access terminal to a safe level of about 5V. When the cycle ends or a fault occurs, the reset switch is turned on, resetting the voltage of the second access terminal to 0V.

[0058] like Figure 4 The diagram shows the structure of a gate voltage follower circuit. It uses two high-voltage LDMOS transistors connected at their sources to achieve gate voltage following and clamping functions. The gate voltage follower circuit includes a high-voltage NMOS transistor MLD1 (first high-voltage field-effect transistor), a high-voltage NMOS transistor MLD2 (second high-voltage field-effect transistor), and a low-voltage NMOS transistor MPD1 (reset switch transistor).

[0059] The gate of the high-voltage NMOS transistor MLD1 is connected to the enable signal HON, its source is connected to the internal node VS, and its drain is connected to the power device gate GATE; the gate of the high-voltage NMOS transistor MLD2 is connected to the enable signal HON, its source is connected to the internal node VS, and its drain is connected to the input VFL of the comparator array.

[0060] The gate of the low-voltage NMOS transistor MPD1 is connected to the reset signal, its source is grounded, and its drain is connected to the input VFL of the comparator array.

[0061] As the HON signal goes high, GATE is pulled up, and the gate signals of MLD1 and MLD2 also go high. Initially, VGATE and VFL are both 0, and the source voltage VS of both transistors is also 0. At this time, MLD1 and MLD2 are both in the ON state. Since VFL is connected to the gate of the input transistor of the comparator array, almost no current flows through it. Therefore, although MLD1 and MLD2 are ON, they are both in the deep linear region, the VDS voltage drop is almost 0, VGATE≈VS≈VFL, and they remain in a following state.

[0062] This situation will continue until the VS voltage rises to the overdrive voltage VG,HON-VTH,MLD. After that, the two LDMOS will slowly enter the subthreshold region until they are completely turned off. Their VDS voltage will no longer follow, and VFL will be clamped near the gate voltage of the LDMOS. The high voltage of VGATE will be borne by the drain and source of the LDMOS.

[0063] In the logic circuit to which HON belongs, the power supply voltage is 5V. Therefore, when HON is high, the gate voltage of the two LDMOS is 5V, and VFL will eventually be clamped to about 5V.

[0064] The IV relationship within the subthreshold region is as follows:

[0065] Where ξ is the non-ideal factor and VT is the thermal voltage. From the IV relationship, it can be seen that there is no necessary correlation between the drain current ID and the drain-source voltage VDS in the subthreshold region. Therefore, even if ID=0, VDS cannot remain 0, and the tracking characteristic will deviate due to nonlinearity during this period. This segment needs to be avoided in design considerations.

[0066] Simulation results show that when VGATE is below 4V, VFL can follow VGATE changes well; however, above 4V, the nonlinear deviation becomes significant. As VGATE increases, VFL is eventually clamped at 5V, preventing breakdown of the input transistors of the subsequent comparator array. At the end of the cycle or when a desaturation fault occurs, MPD1 turns on, resetting VFL to 0V.

[0067] In some embodiments, the passive clamping branch includes an NPN transistor, a transient voltage suppressor (TVS) transistor, and a switching diode; the base of the NPN transistor is connected to a first potential node on the emitter side of the IGBT, the emitter of the NPN transistor is connected to a second potential node on the emitter side of the IGBT, the collector of the NPN transistor is connected to one end of the TVS transistor, and the other end of the TVS transistor is connected to the gate of the IGBT; the switching diode is connected in reverse parallel between the base and emitter of the NPN transistor.

[0068] Specifically, the base of the NPN transistor is connected to the first potential node (signal source SS) on the emitter side of the IGBT, and the emitter is connected to the second potential node (power source PS). The collector is connected to one end of the TVS diode; the other end of the TVS diode is connected to the gate of the IGBT. A switching diode is connected in reverse parallel between the base and emitter of the NPN transistor. When the IGBT is working normally, the potential difference between the signal source SS and the power source PS is very small, the base-emitter junction of the NPN transistor is not forward biased, and it is in the cutoff state, so the entire clamping branch is not working. When a short-circuit fault occurs, the short-circuit current flows through the power source PS, causing its potential to generate a forward voltage difference relative to the signal source SS. The base-emitter junction of the NPN transistor is forward biased and turns on. The collector current flows through the TVS diode, causing it to break down in reverse, pulling down the gate potential of the IGBT, reducing the gate-source voltage VGS, and bringing the IGBT into the linear region, thereby limiting the rise of the short-circuit current. Switching diodes are used to protect the base-emitter junction of an NPN transistor from reverse voltage breakdown.

[0069] like Figure 6 As shown, the base (B) of NPN transistor Q1 is connected to the signal source (SS), its emitter (E) is connected to the power source (PS), and its collector (C) is connected to the cathode of TVS transistor DTVS. The anode of TVS transistor DTVS is connected to the gate (G) of the power device, and its cathode is connected to the collector (C) of NPN transistor Q1. The anode of switching diode D1 is connected to the emitter (E) of NPN transistor Q1, and its cathode is connected to the base (B) of NPN transistor Q1 (connected in reverse parallel to the BE junction).

[0070] During normal conduction, the potential difference between the signal source SS and the power source PS of the power device is extremely small. The base-emitter junction of the NPN transistor Q1 is not forward biased, Q1 is cut off, and the entire clamping branch does not participate in the operation. When a short circuit occurs, the short-circuit current flows through the power source PS, causing its potential to generate a forward voltage difference relative to the signal source SS. The base-emitter junction of the NPN transistor Q1 becomes forward biased and conducts. After Q1 conducts, the collector current flows through the TVS diode DTVS, causing it to break down in reverse, pulling down the potential of the gate G of the power device. VGS decreases, the device enters the linear region, and the drain (collector) current is actively limited.

[0071] This process is completely passive, with a response speed in the nanosecond range. Together with the DESAT detection circuit, it forms a two-stage collaborative protection of "pre-current limiting + post-shutdown", which reduces peak current by 36% to 43% and short-circuit loss by 41% to 50%.

[0072] In some embodiments, the fault identification shutdown component also integrates a shutdown execution circuit, wherein the threshold generation circuit, the hysteresis comparator circuit, and the shutdown execution circuit are electrically connected in sequence.

[0073] The shutdown execution circuit is a five-segment adaptive soft shutdown circuit.

[0074] The threshold generation circuit, hysteresis comparator circuit, and turn-off execution circuit are electrically connected in sequence to form a complete fault identification and execution link. The threshold generation circuit outputs a stable 9V desaturation detection threshold voltage to the comparator circuit; the comparator circuit compares the voltage signal of the detection node with the threshold voltage, and outputs a high-level fault signal when the detected voltage exceeds the positive threshold of 8.95V; the turn-off execution circuit is the five-segment adaptive soft turn-off circuit proposed in the original paper. After receiving the fault signal, it gradually reduces the IGBT gate voltage according to the preset soft turn-off sequence to achieve safe turn-off of the IGBT and avoid damage to the IGBT caused by overvoltage during rapid turn-off.

[0075] This invention provides a method for protecting IGBTs from desaturation short circuits, comprising the following steps: When an IGBT experiences a short circuit fault, the passive clamping branch of the pre-current limiting module collects the potential difference between two different potential nodes on the emitter side of the IGBT and performs pre-limiting processing on the short circuit current. Based on the short-circuit current pre-limiting processing, the high-voltage isolation element of the detection and shutdown module collects the IGBT collector voltage signal and transmits it to the detection node. The constant current source branch and the resistor-capacitor element cooperate to electrically regulate the detection node. Specifically, the resistor-capacitor element is used to determine the time constant in the detection circuit, preset the time constant range, and configure the resistor-capacitor element parameters based on the time constant range. Based on the electrical regulation completed at the detection node, a transient suppression element connected between the detection node and the driving negative power supply performs bidirectional clamping processing on the positive and reverse abnormal voltages of the detection node; based on the bidirectional clamping and voltage regulation completed at the detection node, the fault identification and shutdown component collects the electrical signal of the detection node and performs IGBT shutdown operation according to the collected electrical signal.

[0076] Specifically, the first step involves the passive clamping branch of the pre-current limiting module acquiring the potential difference between two different potential nodes on the emitter side, triggering the branch to conduct, lowering the IGBT gate-source voltage, and pre-limiting the short-circuit current to suppress the current peak. The second step involves the high-voltage isolation element of the detection and turn-off module acquiring the IGBT collector voltage signal and transmitting it to the detection node. The constant current source branch, in conjunction with RC components, regulates the voltage change of the detection node through RC charging and discharging characteristics. Pre-set RC component parameters ensure that the time constant of the detection circuit simultaneously meets both blanking and protection constraints. The third step involves the transient suppression element connected between the detection node and the driving negative power supply, bidirectionally clamping the positive and reverse abnormal voltages appearing at the detection node to stabilize the detection node voltage. The fourth step involves the fault identification and turn-off component acquiring the stabilized electrical signal of the detection node. When the signal reaches the 9V fault judgment threshold, an IGBT soft turn-off operation is executed to complete the fault protection.

[0077] In the DESAT detection loop, the time constant Decided on Charging rate: The larger the size, the slower the charging speed; The smaller the size, the faster the charging. The DESAT detection circuit can be divided into two architectures: on-chip integrated and off-chip RC. In the on-chip integrated RC scheme, there is a large VCE overshoot voltage during the IGBT turn-on process. If the value is too small, the DESAT pin voltage will rise rapidly to the detection threshold due to overshoot, causing false triggering. Therefore... It must be large enough to provide blanking delay and prevent erroneous operation during activation. In off-chip RC solutions, If the value is too large, the DESAT pin voltage will rise slowly during a short circuit, prolonging the fault detection time. Given the limited short-circuit withstand time of the IGBT, the protection action margin will be insufficient. How can we design parameters to achieve this without adding extra components? Simultaneously satisfying both the lower bound of blanking and the upper bound of detection remains an unsolved problem.

[0078] Time constant of the DESAT detection loop It faces two conflicting constraints: the requirement for hidden content elimination. Sufficiently large to prevent VCE overshoot during IGBT turn-on from causing false triggering of the DESAT pin; protection constraints require... Small enough to withstand device short-circuit withstand time TSC (typically) Fault detection can be reliably completed within the specified timeframe. In existing solutions, The value of is usually a compromise between the two constraints, resulting in a longer detection time.

[0079] This method includes a constant current source branch and resistor-capacitor components working together to electrically regulate the detection node. Specifically, the resistor-capacitor components are used to determine the time constant in the detection circuit, a preset time constant range is defined, and the parameters of the resistor-capacitor components are configured based on the preset time constant range. Furthermore, the RC components include a charging resistor Rb and a node capacitor Cb. The values ​​of the charging resistor Rb and the node capacitor Cb are optimized collaboratively to improve the RC time constant. Simultaneously satisfying both hidden surface removal and protection constraints, the optimal parameters are selected between the two constraint boundaries, reducing fault detection time from that of traditional methods. shortened to Within this range, the risk of false activation is eliminated. The time constant τ = Rb × Cb must simultaneously satisfy the following two constraints: The blanking constraint requires τ to be sufficiently large to prevent VCE overshoot during IGBT turn-on from causing false triggering of the DESAT pin. The lower bound of blanking is:

[0080] Where: tf is the power device turn-on time; VCC is the power supply voltage; Vref is the comparator threshold voltage.

[0081] The protection constraint requires τ to be sufficiently small to reliably complete fault detection within the device's short-circuit withstand time (TSC) (typically 3–10 μs). The upper limit of the protection is:

[0082] Where: TSC is the short-circuit withstand time of the device; VD is the forward voltage drop of the high-voltage diode; VCE(sat) is the saturation voltage drop of the IGBT.

[0083] The formula for calculating the detection time is as follows:

[0084] The value ranges for each parameter are as follows: tf=100ns~500ns, VCC=15V~30V, Vref=4.8V~9V, TSC=3μs~10μs, VCE(sat)=1.5V~3.6V, VD=0.7V~1.5V, Rb=100kΩ, Cb=22pF, τ=2.2μs.

[0085] By selecting the optimal parameters between the two constraint boundaries, the fault detection time is reduced from that of traditional methods. shortened to Within this range, the risk of accidental activation is also eliminated.

[0086] The above is a detailed description of the preferred embodiments of the present invention. However, the present invention is not limited to the embodiments described. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of the present invention. All such equivalent modifications or substitutions are included within the scope defined by the claims of this application.

Claims

1. An IGBT desaturation short-circuit protection system, characterized in that, include: The pre-current limiting module is configured with a passive clamping branch, which is connected between the first potential node and the second potential node on the emitter side of the IGBT and the gate of the IGBT, and is used to pre-limit the short-circuit current when a short-circuit fault occurs. The detection and shutdown module includes a built-in detection circuit, transient suppression element, fault identification and shutdown component, high-voltage isolation element, RC element, and constant current source branch. The detection circuit has a detection node, which is coupled to the transient suppression element, high-voltage isolation element, RC element, and constant current source branch. The fault identification and shutdown component is electrically coupled to the detection node to collect the detection node signal and execute the IGBT shutdown action. The high-voltage isolation element is installed between the IGBT collector and the detection node, and the RC element and constant current source branch are electrically connected to the detection node. The signal input terminal of the fault identification and shutdown component is connected to the detection node, and the transient suppression element is connected to the driving negative power supply and the detection node respectively.

2. The IGBT desaturation short-circuit protection system according to claim 1, characterized in that, The RC element includes a charging resistor and a node capacitor. One end of the charging resistor is electrically connected to the detection node, and the other end of the charging resistor is electrically connected to the constant current source branch. One end of the node capacitor is electrically connected to the detection node.

3. The IGBT desaturation short-circuit protection system according to claim 1, characterized in that, The constant current source branch is a built-in constant current source integrated into the IGBT driver chip, and the high voltage isolation element is a high voltage isolation diode with unidirectional conduction characteristics.

4. The IGBT desaturation short-circuit protection system according to claim 1, characterized in that, The fault identification and shutdown component has a built-in threshold generation circuit, which includes a bandgap reference voltage source, a unity-gain buffer circuit, and a calibrated common-source cascode current mirror. The output of the bandgap reference voltage source is connected to the input of the unity-gain buffer circuit, the output of the unity-gain buffer circuit is connected to the input of the calibrated common-source cascode current mirror, and the output of the calibrated common-source cascode current mirror constitutes the output of the threshold generation circuit and is connected to the first input terminal of the hysteresis comparator circuit.

5. The IGBT desaturation short-circuit protection system according to claim 4, characterized in that, The fault identification and shutdown component incorporates a hysteresis comparator circuit, which includes a high-voltage differential pair, an asymmetric current mirror, and a voltage-to-current-to-voltage conversion structure. The two input terminals of the high-voltage differential pair respectively constitute the first and second input terminals of the hysteresis comparator circuit. The two output terminals of the high-voltage differential pair are connected to the two input branches of the asymmetric current mirror. The output terminal of the asymmetric current mirror is connected to the input terminal of the voltage-to-current-to-voltage conversion structure, and the output terminal of the voltage-to-current-to-voltage conversion structure constitutes the single-ended output terminal of the hysteresis comparator circuit.

6. The IGBT desaturation short-circuit protection system according to claim 5, characterized in that, The hysteresis comparator circuit also includes a breakdown clamping structure, one end of which is electrically connected to a detection node.

7. The IGBT desaturation short-circuit protection system according to claim 1, characterized in that, It also includes a gate voltage follower unit, which includes a first high-voltage field-effect transistor (MOSFET), a second high-voltage field-effect transistor (MOSFET), and a reset switch. The sources of the first and second MOSFETs are connected. The first MOSFET is connected between the IGBT gate and the internal follower node, and the second MOSFET is connected between the second access terminal of the fault identification shutdown component and the internal follower node. The reset switch is connected between the second access terminal of the fault identification shutdown component and the driver chip ground.

8. The IGBT desaturation short-circuit protection system according to claim 1, characterized in that, The passive clamping branch includes an NPN transistor, a transient voltage suppressor (TVS) transistor, and a switching diode. The base of the NPN transistor is connected to the first potential node on the emitter side of the IGBT, the emitter of the NPN transistor is connected to the second potential node on the emitter side of the IGBT, the collector of the NPN transistor is connected to one end of the TVS transistor, and the other end of the TVS transistor is connected to the gate of the IGBT. The switching diode is connected in reverse parallel between the base and emitter of the NPN transistor.

9. The IGBT desaturation short-circuit protection system according to claim 6, characterized in that, The fault identification shutdown component also integrates a shutdown execution circuit, wherein the threshold generation circuit, the hysteresis comparator circuit, and the shutdown execution circuit are electrically connected in sequence.

10. A method for protecting IGBTs from desaturation short circuits, characterized in that, Includes the following steps: When an IGBT experiences a short circuit fault, the passive clamping branch of the pre-current limiting module collects the potential difference between two different potential nodes on the emitter side of the IGBT and performs pre-limiting processing on the short circuit current. Based on the short-circuit current pre-limiting processing, the high-voltage isolation element of the detection and shutdown module collects the IGBT collector voltage signal and transmits it to the detection node. The constant current source branch and the resistor-capacitor element work together to electrically regulate the detection node. Specifically, the resistor-capacitor element is used to determine the time constant in the detection circuit, preset the time constant range, and configure the resistor-capacitor element parameters based on the preset time constant range. Based on the electrical regulation completed at the detection node, a transient suppression element connected between the detection node and the driving negative power supply performs bidirectional clamping processing on the positive and reverse abnormal voltages of the detection node. After the detection node completes bidirectional clamping and voltage regulation, the fault identification and shutdown component collects the electrical signal of the detection node and performs IGBT shutdown operation based on the collected electrical signal.

Images