An adjustable dead time control circuit for a dual channel driver

Abstract

This invention relates to the field of integrated circuit technology, specifically to an adjustable dead-time control circuit for a dual-channel driver, comprising: an input signal detection module and a dead-time adjustment module; the input signal detection module and the dead-time adjustment module are connected in series, and the output terminal of the dead-time adjustment module is connected to the input terminal of the dual-channel driver; the input signal detection module is used to perform step-down processing and logic operations on the first and second input signals respectively, and output an intermediate signal; the dead-time adjustment module is used to perform edge detection on the intermediate signal, obtain a dead-time control signal, and then superimpose the dead-time control signal and the intermediate signal to perform dead-time control, outputting a first output signal and a second output signal to the dual-channel driver, thus solving the problem that existing dead-time control for dual-channel drivers cannot output an effective dead time.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and more specifically to an adjustable dead-time control circuit for a dual-channel driver. Background Technology

[0002] In half-bridge or full-bridge drive circuit applications, in order to avoid the simultaneous conduction of high-side and low-side power transistors during switching, which would generate through current from the power supply to ground and cause device damage, a dead time must be inserted during the high-side and low-side switching to ensure that both are briefly turned off. However, if the dead time is set too small, there is still a risk of shoot-through, while if it is set too large, it will prolong the freewheeling time of the body diode of the power transistor, increase switching losses and reduce power conversion efficiency.

[0003] In existing technologies, dead time control often employs fixed modes or programmable adjustment schemes. For example, a fixed-width dead-time pulse can be generated by combining transmission gates and logic gates, or the dead time can be adjusted by controlling a programmable current source with an external voltage. Alternatively, an adjustable dead time can be achieved by changing the charging and discharging current of a capacitor using an external resistor. While these methods improve flexibility to some extent, they generally only focus on the generation and adjustment of dead time and fail to effectively accommodate the transmission delay or inherent dead-time characteristics that may exist in dual-channel input signals. That is, when the dual-ended input signals have mismatched transmission paths or already carry dead time, the dead-time control circuit still mechanically adds a preset dead interval, resulting in the dead time of the final output signal exceeding the actual requirements and causing unnecessary follow current loss. Summary of the Invention

[0004] To address the technical problem that existing dead-time control for dual-channel drivers cannot output an effective dead time, this application provides an adjustable dead-time control circuit for dual-channel drivers.

[0005] The adjustable dead-time control circuit for a dual-channel driver provided in this application adopts the following technical solution: An adjustable dead-time control circuit for a dual-channel driver includes an input signal detection module and a dead-time adjustment module. The input signal detection module is connected in series with the dead time adjustment module, and the output of the dead time adjustment module is connected to the input of the dual-channel driver. The input signal detection module is used to perform voltage reduction processing and logical operations on the first and second input signals respectively, and output an intermediate signal. The dead time adjustment module is used to perform edge detection on the incoming intermediate signal, obtain the dead time control signal, superimpose the dead time control signal and the intermediate signal to perform dead time control, and output the first output signal and the second output signal to the dual-channel driver.

[0006] Furthermore, the input signal detection module includes a first buck circuit, a second buck circuit, and a logic operation unit. The logic operation unit includes a first NOT gate, a second NOT gate, a first NAND gate, a second NAND gate, a third NAND gate, and a fourth NAND gate. The input terminal of the first step-down circuit is connected to the first input signal. The first output terminal of the first step-down circuit is connected to the first input terminal of the second NAND gate. The second output terminal of the first step-down circuit is connected to the input terminal of the first NOT gate. The output terminal of the first NOT gate is connected to the first input terminal of the first NAND gate. The output terminal of the first NAND gate is connected to the second input terminal of the second NAND gate. The input terminal of the second step-down circuit is connected to the second input signal, the output terminal of the second step-down circuit is connected to the input terminal of the second NOT gate, the output terminal of the second NOT gate is connected to the first input terminal of the third NAND gate, and the output terminal of the third NAND gate is connected to the second input terminal of the fourth NAND gate. The second input of the first NAND gate is connected to the connection line between the second and third NAND gates. The second input of the third NAND gate is connected to the connection line between the first step-down circuit and the first NAND gate. The first input of the fourth NAND gate is connected to the connection line between the first and third NAND gates.

[0007] Furthermore, the intermediate signal includes a first intermediate signal and a second intermediate signal, including: The first input signal is stepped down by the first step-down circuit to obtain a first in-phase signal that is in phase with the first input signal and a first in-phase signal that is out of phase with the first input signal. The second input signal is stepped down by the second step-down circuit to obtain a second in-phase signal that is in phase with the second input signal. The first in-phase signal, the second in-phase signal, and the first inverted signal are logically operated on by the logic operation unit to obtain the first intermediate signal and the second intermediate signal.

[0008] Furthermore, the dead time adjustment module includes a first reset-set trigger, a second reset-set trigger, a dead time control circuit, a first AND gate, and a second AND gate; The first input terminal of the first reset-set flip-flop is connected to the output terminal of the second NAND gate. The second input terminal of the first reset-set flip-flop is connected to the first pulse signal. The output terminal of the first reset-set flip-flop is connected to the first input terminal of the dead time control circuit. The second input terminal of the dead time control circuit and the first input terminal of the first AND gate are respectively connected to the output terminal of the second NAND gate. The second input terminal of the first AND gate is connected to the first output terminal of the dead time control circuit. The first input of the second reset-set flip-flop is connected to the output of the fourth NAND gate. The second input of the second reset-set flip-flop is connected to the second pulse signal. The output of the second reset-set flip-flop is connected to the third input of the dead time control circuit. The fourth input of the dead time control circuit and the first input of the second AND gate are respectively connected to the output of the fourth NAND gate. The second input of the second AND gate is connected to the second output of the dead time control circuit. The outputs of the first AND gate and the second AND gate are respectively connected to the inputs of the dual-channel driver.

[0009] Furthermore, the dead time control signal includes a first dead time control signal and a second dead time control signal, and the dead time control circuit includes a start-up unit, a first dead time control unit, and a second dead time control unit; The startup unit is connected to the first dead time control unit and the second dead time control unit respectively; A startup unit is used to provide startup voltage to the first dead-time control unit and the second dead-time control unit; The first dead time control unit is used to generate a first dead time control signal based on the first charging signal after generating a first charging signal based on the start-up voltage. The second dead time control unit is used to generate a second dead time control signal based on the second charging signal after generating a second charging signal based on the start-up voltage.

[0010] Furthermore, the startup unit includes a first P-type transistor, a first N-type transistor, and a first resistor; The gate of the first N-type transistor is connected to a control signal, the source of the first N-type transistor is connected to the drain of the first P-type transistor, the drain of the first N-type transistor is connected to one end of the first resistor, and the other end of the first resistor is connected to the dead time control terminal. An external resistor is connected to the connection line between the dead time control terminal and the first resistor.

[0011] Furthermore, the first dead time control unit includes a first delay comparison subunit and a first drive logic control subunit; The first delay comparator subunit includes a second P-type transistor, a second N-type transistor, a third N-type transistor, a fourth N-type transistor, a second resistor, a first capacitor, and a first comparator. The gate of the second P-type transistor is connected to the gate of the first P-type transistor, the drain of the second P-type transistor is connected to the drain of the second N-type transistor, the source of the second N-type transistor is connected to the source of the third N-type transistor, the gate of the third N-type transistor is connected to the connection line between the second P-type transistor and the second N-type transistor via the gate of the second N-type transistor, the drain of the third N-type transistor is connected to one end of the second resistor, the other end of the second resistor is connected to the drain of the fourth N-type transistor and one end of the first capacitor, the gate of the fourth N-type transistor is connected to the output terminal of the first reset-set flip-flop, the source of the fourth N-type transistor and the other end of the first capacitor are connected to the ground terminal, and the inverting input terminal of the first comparator is connected to the drain of the second P-type transistor. The first drive logic control subunit includes a third P-type transistor, a fourth P-type transistor, a fifth N-type transistor, a third NOT gate, a fourth NOT gate, and a fifth NOT gate. The gate of the third P-type transistor is connected to the output of the first comparator and the drain of the fourth P-type transistor, respectively. The drains of the third P-type transistor and the fifth N-type transistor are connected to the input of the third NOT gate. The gate of the fifth N-type transistor and the input of the fourth NOT gate are connected to the output of the first reset-set flip-flop. The output of the fourth NOT gate is connected to the gate of the fourth P-type transistor. The output of the third NOT gate is connected to the input of the fifth NOT gate. The output of the fifth NOT gate is connected to the second input of the first AND gate.

[0012] Furthermore, the second dead-time control unit includes a second delay comparison subunit and a second drive logic control subunit; The second delay comparator subunit includes a fifth P-type transistor, a sixth N-type transistor, a seventh N-type transistor, an eighth N-type transistor, a third resistor, a second capacitor, and a second comparator. The gate of the fifth P-type transistor is connected to the gate of the first P-type transistor. The drain of the fifth P-type transistor is connected to the drain of the sixth N-type transistor. The source of the sixth N-type transistor is connected to the source of the seventh N-type transistor. The gate of the seventh N-type transistor is connected to the connection line between the fifth P-type transistor and the sixth N-type transistor via the gate of the sixth N-type transistor. The drain of the seventh N-type transistor is connected to one end of the third resistor. The other end of the third resistor is connected to the drain of the eighth N-type transistor and one end of the second capacitor. The gate of the eighth N-type transistor is connected to the output terminal of the second reset-set flip-flop. The source of the eighth N-type transistor and the other end of the second capacitor are both connected to the ground terminal. The inverting input terminal of the second comparator is connected to the drain of the fifth P-type transistor. The second drive logic control subunit includes a sixth P-type transistor, a seventh P-type transistor, a ninth N-type transistor, a sixth NOT gate, a seventh NOT gate, and an eighth NOT gate. The gate of the sixth P-type transistor is connected to the output of the second comparator and the drain of the seventh P-type transistor, respectively. The drains of the sixth P-type transistor and the ninth N-type transistor are connected to the input of the sixth NOT gate. The gate of the ninth N-type transistor and the input of the seventh NOT gate are connected to the output of the second reset-set flip-flop. The output of the seventh NOT gate is connected to the gate of the seventh P-type transistor. The output of the sixth NOT gate is connected to the input of the eighth NOT gate. The output of the eighth NOT gate is connected to the second input of the second AND gate. Beneficial effects achieved: This application provides an adjustable dead-time control circuit for a dual-channel driver, including an input signal detection module and a dead-time adjustment module; the input signal detection module and the dead-time adjustment module are connected in series, and the output terminal of the dead-time adjustment module is connected to the input terminal of the dual-channel driver; the input signal detection module is used to perform step-down processing and logic operation on the first input signal and the second input signal respectively, and output an intermediate signal; the dead-time adjustment module is used to perform edge detection on the intermediate signal, obtain a dead-time control signal, and then superimpose the dead-time control signal and the intermediate signal to perform dead-time control, and output a first output signal and a second output signal to the dual-channel driver.

[0013] In this application, the first and second input signals are stepped down by the input signal detection module to adapt to wide voltage input and complete level conversion. Then, the phase relationship and inherent delay or dead time state of the two input signals are analyzed in real time through logic operations, and an intermediate signal representing the input characteristics is output. Subsequently, the dead time adjustment module performs edge detection on the intermediate signal to capture the signal transition edge, generates a dead time control signal corresponding to the set value, and performs logic operations on the dead time control signal and the intermediate signal in the superposition stage. Through an adaptive mechanism that takes the maximum value of the inherent delay of the input signal and the set dead time, the dead time is supplemented only when the interval of the input signal itself is insufficient, and redundant superposition is avoided when the input signal has a safe turn-off interval. Thus, while ensuring that the high-side and low-side power transistors do not shoot through, the problem of excessively long dead time caused by blindly superimposing dead time is effectively avoided, the freewheeling time of the power transistor body diode is significantly shortened, the switching loss is reduced and the driving efficiency is improved. Attached Figure Description

[0014] Figure 1 This is a schematic diagram of the adjustable dead-time control circuit for a dual-channel driver according to this application; Figure 2 This is an implementable circuit topology diagram for an adjustable dead-time control circuit used in a dual-channel driver according to this application; Figure 3 This is a schematic diagram of the dead time adjustment module in this application; Figure 4 This is a schematic diagram of the transistor structure with deep N-well isolation and body diode rectification and multiplexing functions in this application; Figure 5 The simulation waveform diagram is shown when there is no delay between two input signals and a 20kΩ resistor is connected to the dead time adjustment terminal. Figure 6 Simulation waveform diagram of two input signals with no delay and a large-value resistor of 220kΩ connected to the dead time adjustment terminal; Figure 7 The simulation waveform diagram is shown when the two input signals have no delay and the dead time adjustment terminal is shorted to the power supply. Figure 8 The simulation waveform is shown when a 20kΩ resistor is connected to the dead time adjustment terminal and there is a 50ns delay deviation between the two input signals. Figure 9 The simulation waveform is shown when a 20kΩ resistor is connected to the dead time adjustment terminal and there is a 500ns delay deviation between the two input signals. Explanation of icon numbers: 10. Input signal detection module; 20. Dead time adjustment module; VIA, first input signal; VIB, second input signal; VOA, first output signal; VOB, second output signal; VIA_Z, First in-phase signal; VIB_Z, Second in-phase signal; VIA_ZN, First inverted signal; NOT1, First NOT gate; NOT2, Second NOT gate; NAND1, First NAND gate; NAND2, Second NAND gate; NAND3, Third NAND gate; NAND4, Fourth NAND gate; RS1, First reset-set flip-flop; RS2, Second reset-set flip-flop; AND1, First AND gate; AND2, Second AND gate; VOA1, First intermediate signal; VOB1, Second intermediate signal; VMA, First pulse signal; VMB, Second pulse signal; VOA_DT, First dead-time control signal; VOB_DT, Second dead-time control signal; 201, Start-up unit; PM1, First P-type transistor; NM1, First N-type transistor; R1, First resistor; NVB, Control signal; VDD, Power supply voltage; DT, Dead time control terminal; 202, First dead-time control unit; 2021, First delay comparator subunit; PM2, Second P-type transistor; NM2, Second N-type transistor; NM3, Third N-type transistor; NM4, Fourth N-type transistor; C1, First capacitor; R2, Second resistor; COMP1, First comparator; 2022, First drive logic control subunit; PM3, Third P-type transistor; PM4, Fourth P-type transistor; NM5, Fifth N-type transistor; NOT3, Third NOT gate; NOT4, Fourth NOT gate; NOT5, Fifth NOT gate; PVB, Start-up voltage; VREF1, First reference voltage; 203. Second dead-time control unit; 2031. Second delay comparator subunit; PM5. Fifth P-type transistor; NM6. Sixth N-type transistor; NM7. Seventh N-type transistor; NM8. Eighth N-type transistor; C2. Second capacitor; R3. Third resistor; COMP2. Second comparator; 2032. Second drive logic control subunit; PM6. Sixth P-type transistor; PM7. Seventh P-type transistor; NM9. Ninth N-type transistor; NOT6. Sixth NOT gate; NOT7. Seventh NOT gate; NOT8. Eighth NOT gate; VREF2. Second reference voltage. Detailed Implementation

[0015] The following combination Figures 1 to 9 This application will be described in further detail. This application discloses an adjustable dead-time control circuit for a dual-channel driver.

[0016] Please refer to Figure 1 The adjustable dead time control circuit for a dual-channel driver proposed in this embodiment includes: an input signal detection module 10 and a dead time adjustment module 20; the input signal detection module 10 and the dead time adjustment module 20 are connected in series, and the output terminal of the dead time adjustment module 20 is connected to the input terminal of the dual-channel driver.

[0017] The input signal detection module 10 is used to perform step-down processing and logic operations on the first input signal VIA and the second input signal VIB respectively, and output an intermediate signal; the dead time adjustment module 20 is used to perform edge detection on the intermediate signal, obtain the dead time control signal, superimpose the dead time control signal and the intermediate signal to perform dead time control, and output the first output signal VOA and the second output signal VOB to the dual-channel driver.

[0018] In this embodiment, by setting up a series architecture for the input signal detection module 10 and the dead-time adjustment module 20, the problem of wide voltage range adaptation for dual-channel input signals is solved. Logical operations are used to identify the phase relationship between the first input signal VIA and the second input signal VIB, as well as their inherent delay or dead-time states, thus providing an intermediate signal for subsequent control. Based on this, the dead-time adjustment module 20 performs edge detection on the intermediate signal to obtain timing trigger points, thereby generating a flexibly configurable dead-time control signal. Through logical operations that superimpose this dead-time control signal with the intermediate signal, an adaptive dead-time adjustment function is achieved. This effectively solves the problem in the prior art where blindly superimposing a fixed dead-time due to the inability to identify the existing turn-off interval of the dual input signals leads to an excessively long final output dead-time and increased freewheeling losses in the power transistor diodes. This ensures that while preventing shoot-through of the upper and lower bridge arms, the optimal effective dead-time is always output, matching the input characteristics and set values, significantly improving drive efficiency. In one feasible implementation, refer to Figure 2 As shown, the input signal detection module 10 includes a first step-down circuit, a second step-down circuit, and a logic operation unit. The logic operation unit includes a first NOT gate (NOT1), a second NOT gate (NOT2), a first NAND gate (NAND1), a second NAND gate (NAND2), a third NAND gate (NAND3), and a fourth NAND gate (NAND4).

[0019] The first buck converter has a first input signal VIA connected to its input terminal. Its first output terminal is connected to the first input terminal of the second NAND gate NAND2. Its second output terminal is connected to the input terminal of the first NOT gate NOT1. The output terminal of the first NOT gate NOT1 is connected to the first input terminal of the first NAND gate NAND1. The output terminal of the first NAND gate NAND1 is connected to the second input terminal of the second NAND gate NAND2. The second buck converter has a second input signal VIB connected to its input terminal. Its output terminal is connected to the input terminal of the second NOT gate NOT2. The output of the second NOT gate NOT2 is connected to the first input of the third NAND gate NAND3, and the output of the third NAND gate NAND3 is connected to the second input of the fourth NAND gate NAND4. The second input of the first NAND gate NAND1 is connected to the connection line between the second NOT gate NOT2 and the third NAND gate NAND3, the second input of the third NAND gate NAND3 is connected to the connection line between the first buck circuit and the first NOT gate NOT1, and the first input of the fourth NAND gate NAND4 is connected to the connection line between the first NOT gate NOT1 and the third NAND gate NAND3.

[0020] It should be noted that the intermediate signals include a first intermediate signal VOA1 and a second intermediate signal VOB1, comprising: stepping down the first input signal VIA through a first step-down circuit to obtain a first in-phase signal VIA_Z that is in phase with the first input signal VIA and a first inverted signal VIA_ZN that is out of phase with the first input signal VIA; stepping down the second input signal VIB through a second step-down circuit to obtain a second in-phase signal VIB_Z that is in phase with the second input signal VIB; and performing logical operations on the first in-phase signal VIA_Z, the second in-phase signal VIB_Z, and the first inverted signal VIA_ZN through a logic operation unit to obtain the first intermediate signal VOA1 and the second intermediate signal VOB1.

[0021] The first buck circuit in the input signal detection module 10 receives the first input signal VIA. The first buck circuit integrates a differential level conversion architecture, which includes a pair of mirror-image driver transistors. When the high level of the first input signal VIA reaches the high voltage domain, one driver transistor conducts and outputs a high level after voltage division. This path is not logically inverted and directly outputs a first in-phase signal VIA_Z that is in phase with the first input signal VIA. The other driver transistor utilizes the complementary control characteristics of the first input signal VIA to internally invert the signal, directly outputting a first inverted signal VIA_ZN that is out of phase with the first input signal VIA. This first inverted signal VIA_ZN is not generated by the subsequent NOT gate but originates from the complementary output of the push-pull transistor structure within the buck circuit. Simultaneously, the second buck circuit receives the second input signal VIB, also performs buck processing to match the internal level standard, and outputs a second in-phase signal VIB_Z that is in phase with the second input signal VIB.

[0022] In the logic operation unit, the first in-phase signal VIA_Z is first input to the input of the first NOT gate NOT1, and after logic inversion, it is output to the first input of the first NAND gate NAND1. At the same time, the first in-phase signal VIA_Z is also directly connected to the second input of the third NAND gate NAND3 and the first input of the fourth NAND gate NAND4. The second in-phase signal VIB_Z is input to the input of the second NOT gate NOT2, and after logic inversion, one output is to the second input of the first NAND gate NAND1, and the other output is to the first input of the third NAND gate NAND3. At this time, the third NAND gate NAND3 outputs the processed signal value to the second input of the fourth NAND gate NAND4. The first inverted signal VIA_ZN is directly connected to the first input of the second NAND gate NAND2, and the second input of the second NAND gate NAND2 is connected to the node where the output of the first NAND gate NAND1 is located.

[0023] The above connections form a closed-loop cross-coupled logic network: the first NAND gate NAND1 performs a NAND operation on its first input (i.e., the inverted signal from the first in-phase signal VIA_Z) and its second input (i.e., the inverted signal from the second in-phase signal VIB_Z), and its output is fed back to the second input of the second NAND gate NAND2; the second NAND gate NAND2 performs a NAND operation on its first input (i.e., the first inverted signal VIA_ZN) and its second input (i.e., the output of the first NAND gate NAND1) to generate the second intermediate signal VOB1.

[0024] The third NAND gate NAND3 performs a NAND operation on its first input (i.e., the inverted signal of the second in-phase signal VIB_Z) and its second input (i.e., the first in-phase signal VIA_Z), and its output is connected to the second input of the fourth NAND gate NAND4; the fourth NAND gate NAND4 performs a NAND operation on its first input (i.e., the first in-phase signal VIA_Z) and its second input to generate the first intermediate signal VOA1.

[0025] Specifically, when the first input signal VIA and the second input signal VIB are in phase, the node potentials inside the logic network quickly reach a steady-state equilibrium, forcing the first intermediate signal VOA1 and the second intermediate signal VOB1 to lock at a constant low level. When the first input signal VIA and the second input signal VIB are out of phase, the cross-coupled path breaks the equilibrium, making the waveform of the second intermediate signal VOB1 consistent with the first input signal VIA, and the waveform of the first intermediate signal VOA1 consistent with the second input signal VIB. This completes the determination of the phase relationship between the dual-channel input signals. The circuit structure is simplified by utilizing the inherent complementary output characteristics of the buck circuit, and high robustness phase detection under wide voltage input conditions is achieved through the cross-coupled NAND gate network, providing an accurate logic reference for the subsequent adaptive adjustment of the dead time. Reference Figure 2As shown, the dead time adjustment module 20 includes a first reset-set trigger RS1, a second reset-set trigger RS2, a dead time control circuit, a first AND gate AND1, and a second AND gate AND2. The first input terminal of the first reset-set trigger RS1 is connected to the output terminal of the second AND gate AND2. The second input terminal of the first reset-set trigger RS1 is connected to a first pulse signal VMA. The output terminal of the first reset-set trigger RS1 is connected to the first input terminal of the dead time control circuit. The second input terminal of the first AND gate AND1 is connected to the first output terminal of the dead time control circuit. The first input terminal of the first AND gate AND1 is connected to the second AND gate AND2. The output of NAND gate NAND2 is connected; the first input of the second reset-set trigger RS2 is connected to the output of the fourth NAND gate NAND4, the second input of the second reset-set trigger RS2 is connected to the second pulse signal VMB, the output of the second reset-set trigger RS2 is connected to the second input of the dead time control circuit, the second input of the second AND gate AND2 is connected to the second output of the dead time control circuit, the first input of the second AND gate AND2 is connected to the output of the fourth NAND gate NAND4; the outputs of the first AND gate AND1 and the second AND gate AND2 are respectively connected to the inputs of the dual-channel driver.

[0026] according to Figure 2 As described in the structure and connection instructions above, the dead time adjustment module 20 performs timing processing based on the first intermediate signal VOA1 and the second intermediate signal VOB1 output by the input signal detection module 10. Specifically, the first input of the first reset-set trigger RS1 directly receives the second intermediate signal VOB1 from the second NAND gate NAND2, and its second input is connected to the first pulse signal VMA (typically a clock or synchronization signal) generated by the system. When the second intermediate signal VOB1 has a rising edge, the first reset-set trigger RS1 is set, and its output generates a high-level active edge detection pulse. This edge detection pulse is directly sent to the first input of the dead time control circuit as a trigger signal to start capacitor charging.

[0027] Meanwhile, the first input of the second reset-set flip-flop RS2 is connected to the first intermediate signal VOA1 of the fourth NAND gate NAND4, and its second input is connected to the second pulse signal VMB. When the first intermediate signal VOA1 has a falling edge, the second reset-set flip-flop RS2 is set and outputs another high-level active edge detection pulse to the second input of the dead time control circuit, thereby realizing independent capture of the transition edges of the two input signals.

[0028] Based on these two edge detection pulses, the dead-time control circuit generates an adjustable first dead-time control signal VOA_DT and a second dead-time control signal VOB_DT. Then, the first AND gate AND1 performs a logical AND operation on the second intermediate signal VOB1 and the second dead-time control signal VOB_DT output by the second NAND gate NAND2. Since the second dead-time control signal VOB_DT is a narrow pulse that is delayed to turn on after the falling edge of the first intermediate signal VOA1, the result of the operation makes the second output signal VOB finally output to the dual-channel driver have a delay interval determined by the width of the second dead-time control signal VOB_DT superimposed on the original falling edge of the second intermediate signal VOB1, thereby preventing the second output signal VOB from turning on prematurely.

[0029] Similarly, the second AND gate AND2 performs a logical AND operation on the first intermediate signal VOA1 output by the fourth NAND gate NAND4 and the first dead time control signal VOA_DT output by the dead time control circuit, so that the final output signal VOA is delayed after the falling edge of the first intermediate signal VOA1.

[0030] This mechanism, which uses a reset-set trigger to capture the transition edge of the intermediate signal to start and stop the delay, and uses logic superposition with the intermediate signal and dead time control signal of the gate, realizes a hardware logic-based, high-precision adaptive dead time insertion scheme. The interlocking principle it follows, which is "the first output signal VOA is delayed to start after the second output signal VOB falls, and the second output signal VOB is delayed to start after the first output signal VOA falls", can ensure that the high and low side drive signals will not overlap under any operating conditions, effectively eliminating the risk of bridge arm shoot-through.

[0031] Reference Figure 3 As shown, the dead time control signal includes a first dead time control signal VOA_DT and a second dead time control signal VOB_DT. The dead time control circuit includes a startup unit 201, a first dead time control unit 202, and a second dead time control unit 203. The startup unit 201 is connected to the first dead time control unit 202 and the second dead time control unit 203 respectively. The startup unit 201 is used to provide a startup voltage PVB to the first dead time control unit 202 and the second dead time control unit 203. The first dead time control unit 202 is used to generate a first charging signal based on the startup voltage PVB, and then generate the first dead time control signal VOA_DT based on the first charging signal. The second dead time control unit 203 is used to generate a second charging signal based on the startup voltage PVB, and then generate the second dead time control signal VOB_DT based on the second charging signal.

[0032] By introducing a startup unit 201 to uniformly provide the startup voltage PVB for the first dead-time control unit 202 and the second dead-time control unit 203, the aim is to ensure that the timing reference for the generation of the two dead-time control signals is consistent, avoiding signal deviations caused by power supply differences. Based on this, the first dead-time control unit 202 generates a first charging signal based on the startup voltage PVB, thus obtaining the first dead-time control signal VOA_DT; the second dead-time control unit 203 generates a second charging signal based on the startup voltage PVB, thus obtaining the second dead-time control signal VOB_DT. This combined structure enables independent generation and precise control of the two dead-time control signals, effectively solving the signal crosstalk and timing mismatch problems caused by traditional single-path control or shared charging paths, preventing bridge arm shoot-through during power switching, thereby reducing switching losses and electromagnetic interference, improving the stability and reliability of system operation, and ultimately achieving efficient and safe operation of the power conversion circuit. Specifically, refer to Figure 4 As shown, the startup unit 201 includes a first P-type transistor PM1, a first N-type transistor NM1, and a first resistor R1; the gate of the first N-type transistor NM1 is connected to the control signal NVB, the source of the first N-type transistor NM1 is connected to the drain of the first P-type transistor PM1, the drain of the first N-type transistor NM1 is connected to one end of the first resistor R1, and the other end of the first resistor R1 is connected to the dead time control terminal DT; an external resistor is connected to the connection line between the dead time control terminal DT and the first resistor R1.

[0033] When the control signal NVB is applied to the gate of the first N-type transistor NM1, the first N-type transistor NM1 turns on when its gate-source voltage is greater than the threshold voltage. At this time, the drain of the first P-type transistor PM1 is connected to the source of the first N-type transistor NM1. The first P-type transistor PM1 can withstand high voltage due to its wide voltage range characteristics. Its source is connected to the power supply voltage VDD, and its gate voltage is controlled by the conduction state of the first N-type transistor NM1. After the first N-type transistor NM1 turns on, the current flows out from its drain and through the first resistor R1 to the dead time control terminal DT. The dead time control terminal DT and the externally connected resistor form a current path. The first resistor R1 and the external resistor are connected in series to divide the voltage, so that the start-up voltage PVB at the dead time control terminal DT can be established. The magnitude of the start-up voltage PVB is determined by the power supply voltage VDD, the resistance value of the first resistor R1, the resistance value of the external resistor, and the conduction characteristics of the first P-type transistor PM1 and the first N-type transistor NM1. When the resistance value of the external resistor changes, the series voltage division ratio changes accordingly, thereby adjusting the value of the starting voltage PVB. This starting voltage PVB serves as the power supply reference for the first dead time control unit 202 and the second dead time control unit 203, ensuring that the two dead time control units operate under the same voltage reference, thus achieving the effect of linearly adjusting the dead time according to the resistance value of the external resistor.

[0034] The formula for the starting voltage PVB is as follows: ; in, This refers to the resistance value of the externally connected resistor (usually corresponding to the external drive resistor or setting resistor of the chip). This represents the electron mobility of the gate oxide layer, a physical parameter in semiconductor manufacturing processes. The capacitance per unit area of ​​the gate oxide layer is also a process parameter; The aspect ratio of the first P-type transistor in the circuit is a geometric parameter that determines the transistor's driving capability. The reference voltage corresponds to the bias voltage of the control signal NVB; This is the threshold voltage of the first N-type transistor NM1, that is, the critical voltage required for the first N-type transistor NM1 to start conducting; This is the threshold voltage of the first P-type transistor. According to this formula, the larger the external resistor value, the higher the startup voltage PVB, resulting in a smaller capacitor charging current, i.e., a faster charging speed. Size: ; And the capacitor charging speed meets the following requirements: ; in, The magnitude of the current flowing through the transistor; This represents the overall effective gate-source voltage, which is the potential difference that drives the transistor into saturation conduction. This refers to the required time, i.e., the time required to complete the charging and discharging process; The equivalent capacitance value refers to the driven load capacitance or node parasitic capacitance. The voltage corresponding to the voltage difference or the amount of charge that needs to be accumulated across the capacitor.

[0035] In addition, in practical applications, the connection line between the dead time control terminal DT and the first resistor R1 can be connected to other external devices or external power supplies besides an external resistor. When the dead time control terminal DT is connected to an external power supply, the voltage at the PVB terminal will be raised to approximately equal to the power supply voltage VDD. At this time, the first P-type transistor PM1 is in the off state, and the first capacitor has no charging current, so no dead time control signal is generated. At this time, there is no dead time between the two output signals.

[0036] The first dead time control unit 202 includes a first delay comparison subunit 2021 and a first drive logic control subunit 2022.

[0037] The first delay comparison subunit 2021 includes a second P-type transistor PM2, a second N-type transistor NM2, a third N-type transistor NM3, a fourth N-type transistor NM4, a second resistor R2, a first capacitor C1, and a first comparator COMP1. The gate of the second P-type transistor PM2 is connected to the gate of the first P-type transistor PM1. The drain of the second P-type transistor PM2 is connected to the drain of the second N-type transistor NM2. The source of the second N-type transistor NM2 is connected to the source of the third N-type transistor NM3. The gate of the third N-type transistor NM3 is connected to the connection line between the second P-type transistor PM2 and the second N-type transistor NM2 via the gate of the second N-type transistor NM2. The drain of the third N-type transistor NM3 is connected to one end of the second resistor R2. The other end of the second resistor R2 is connected to the drain of the fourth N-type transistor NM4 and one end of the first capacitor C1. The gate of the fourth N-type transistor NM4 is connected to the output terminal of the first reset-set trigger RS1. The source of the fourth N-type transistor NM4 and the first capacitor C1 are connected to the first capacitor C1. The other end of C1 is connected to the ground terminal. The inverting input of the first comparator COMP1 is connected to the drain of the second P-type transistor PM2. The first drive logic control subunit 2022 includes a third P-type transistor PM3, a fourth P-type transistor PM4, a fifth N-type transistor NM5, a third NOT gate NOT3, a fourth NOT gate NOT4, and a fifth NOT gate NOT5. The gate of the third P-type transistor PM3 is connected to the output of the first comparator COMP1 and the drain of the fourth P-type transistor PM4. The drains of the third P-type transistor PM3 and the fifth N-type transistor NM5 are connected to the input of the third NOT gate NOT3. The gate of the fifth N-type transistor NM5 and the input of the fourth NOT gate NOT4 are connected to the output of the first reset-set flip-flop RS1. The output of the fourth NOT gate NOT4 is connected to the gate of the fourth P-type transistor PM4. The output of the third NOT gate NOT3 is connected to the input of the fifth NOT gate NOT5. The output of the fifth NOT gate NOT5 is connected to the second input of the first AND gate AND1.

[0038] according to Figure 4It can be seen that the first dead-time control unit 202 operates based on the edge detection pulse output by the first reset-set trigger RS1. When the first reset-set trigger RS1 outputs a high-level pulse, this high-level pulse is directly connected to the gate of the fourth N-type transistor NM4 to turn it on, and is also connected to the gate of the fifth N-type transistor NM5 to synchronously control the drive logic. At the same time, the conduction of the fourth N-type transistor NM4 pulls the first capacitor C1 low, ending the discharge state of the previous cycle, and the mirror current source structure composed of the second P-type transistor PM2, the second N-type transistor NM2, and the third N-type transistor NM3 begins to operate. In this circuit, the gate of the second P-type transistor PM2 is interconnected with the gate of the first P-type transistor PM1 to ensure consistent bias voltage. The second P-type transistor PM2 injects a constant charging current into the second resistor R2 and the first capacitor C1 through a current mirror formed by the second N-type transistor NM2 and the third N-type transistor NM3. Due to the current limiting effect of the second resistor R2, the charging current mainly charges the first capacitor C1 linearly, and the voltage across the first capacitor C1 rises slowly. This voltage is fed back to the inverting input of the first comparator COMP1 in real time and continuously compared with the first reference voltage VREF1 connected to the non-inverting input.

[0039] Once the voltage across the first capacitor C1 rises above the first reference voltage VREF1, the output state of the first comparator COMP1 flips from high to low. Because the output of the first comparator COMP1 is simultaneously connected to the gate of the third P-type transistor PM3 and the drain of the fourth P-type transistor PM4, when the first comparator COMP1 outputs a low level, the third P-type transistor PM3 is turned on, while the fourth P-type transistor PM4 is turned off. Simultaneously, the fourth NOT gate NOT4 inverts the low level of the first comparator COMP1 and outputs a high level to the gate of the fourth P-type transistor PM4 to maintain its off state. The fifth N-type transistor NM5 is turned on because its gate is connected to the high level of the first reset-set trigger RS1. This causes the high level output of the third P-type transistor PM3 to be shaped by the third NOT gate NOT3 and then inverted by the fifth NOT gate NOT5 to output a low-level pulse, which generates the first dead time control signal VOA_DT. The first dead time control signal VOA_DT is finally input to the second input terminal of the first AND gate AND1 and performs a logical AND operation with the first intermediate signal VOA1, thereby inserting a dead interval determined by the charging time of the first capacitor C1 after the falling edge of the first intermediate signal VOA1.

[0040] The circuit described above precisely controls the charging rate through a current mirror, uses the first comparator COMP1 to make voltage threshold decisions, and ensures a steep edge of the output first dead time control signal VOA_DT through the shaping of two stages of NOT gates. This converts the edge signal triggered by digital logic into a high-precision, linearly adjustable analog delay pulse, providing stable and reliable dead time control for the dual-channel driver and effectively avoiding the shoot-through risk of the power transistor.

[0041] The second dead time control unit 203 includes a second delay comparison subunit 2031 and a second drive logic control subunit 2032.

[0042] The second delay comparator subunit 2031 includes a fifth P-type transistor PM5, a sixth N-type transistor NM6, a seventh N-type transistor NM7, an eighth N-type transistor NM8, a third resistor R3, a second capacitor C2, and a second comparator COMP2. The gate of the fifth P-type transistor PM5 is connected to the gate of the first P-type transistor PM1. The drain of the fifth P-type transistor PM5 is connected to the drain of the sixth N-type transistor NM6. The source of the sixth N-type transistor NM6 is connected to the source of the seventh N-type transistor NM7. The gate of the seventh N-type transistor NM7 is connected to the connection line between the fifth P-type transistor PM5 and the sixth N-type transistor NM6 via the gate of the sixth N-type transistor NM6. The drain of the seventh N-type transistor NM7 is connected to one end of the third resistor R3. The other end of the third resistor R3 is connected to the drain of the eighth N-type transistor NM8 and one end of the second capacitor C2. The gate of the eighth N-type transistor NM8 is connected to the output terminal of the second reset-set flip-flop RS2. The source of the eighth N-type transistor NM8 and the second capacitor C2 are connected to the second capacitor C2. The other end of C2 is connected to the ground terminal. The inverting input of the second comparator COMP2 is connected to the drain of the fifth P-type transistor PM5. The second drive logic control subunit 2032 includes a sixth P-type transistor PM6, a seventh P-type transistor PM7, a ninth N-type transistor NM9, a sixth NOT gate NOT6, a seventh NOT gate NOT7, and an eighth NOT gate NOT8. The gate of the sixth P-type transistor PM6 is connected to the output of the second comparator COMP2 and the drain of the seventh P-type transistor PM7. The drains of the sixth P-type transistor PM6 and the ninth N-type transistor NM9 are connected to the input of the sixth NOT gate NOT6. The gate of the ninth N-type transistor NM9 and the input of the seventh NOT gate NOT7 are connected to the output of the second reset-set flip-flop RS2. The output of the seventh NOT gate NOT7 is connected to the gate of the seventh P-type transistor PM7. The output of the sixth NOT gate NOT6 is connected to the input of the eighth NOT gate NOT8. The output of the eighth NOT gate NOT8 is connected to the second input of the second AND gate AND2.

[0043] according to Figure 4It can be seen that the second dead-time control unit 203, as a mirror structure completely symmetrical to the first dead-time control unit 202, specifically responds to the edge detection pulse output by the second reset-set trigger RS2 to generate another dead-time control timing. When the second reset-set trigger RS2 outputs a high-level pulse, this high-level pulse is directly connected to the gate of the eighth N-type transistor NM8 to turn it on, and also connected to the gate of the ninth N-type transistor NM9 to synchronously control the subsequent drive logic; the conduction of the eighth N-type transistor NM8 pulls the second capacitor C2 low to achieve reset, while the mirror structure composed of the fifth P-type transistor PM5, the sixth N-type transistor NM6, and the seventh N-type transistor NM7... As the current source begins to operate, the gate of the fifth P-type transistor PM5 is interconnected with the gate of the first P-type transistor PM1 to ensure bias consistency. The fifth P-type transistor PM5 injects a constant charging current into the third resistor R3 and the second capacitor C2 through a current mirror formed by the sixth N-type transistor NM6 and the seventh N-type transistor NM7. The voltage across the second capacitor C2 rises linearly during the charging process. This voltage is fed back to the inverting input of the second comparator COMP2 in real time and continuously compared with the second reference voltage VREF2 connected to the non-inverting input. When the voltage of the second capacitor C2 exceeds the second reference voltage VREF2, the output state of the second comparator COMP2 changes from high to low. This switching signal... The signal is then input to the second drive logic control subunit 2032, simultaneously acting on the gate of the sixth P-type transistor PM6 and the drain of the seventh P-type transistor PM7. This causes the sixth P-type transistor PM6 to conduct while the seventh P-type transistor PM7 is turned off. The seventh NOT gate inverts the low level of the second comparator COMP2 and outputs a high level to the gate of the seventh P-type transistor PM7 to maintain its off state. Meanwhile, the ninth N-type transistor NM9 is turned on because its gate is connected to the high level of the second reset-set flip-flop RS2. This causes the high level output from the sixth P-type transistor PM6 to be shaped by the sixth NOT gate, and then inverted by the eighth NOT gate, outputting a low-level pulse, thus generating the second dead zone. The timing control signal VOB_DT, the second dead-time control signal VOB_DT, is ultimately input to the second input terminal of the second AND gate AND2. It performs a logical AND operation with the second intermediate signal VOB1, thereby inserting a dead interval determined by the charging time of the second capacitor C2 after the falling edge of the second intermediate signal VOB1. Together with the first dead-time control unit 202, it constructs a completely symmetrical dual-channel dead-time control architecture, which can implement precise dead-time insertion of the first output signal VOA independently of the second output signal VOB. This ensures that the switching timing of the high and low side power transistors in the dual-channel driver does not interfere with each other, further enhancing the system's anti-shoot-through capability and reliability under complex operating conditions.

[0044] In addition, according to Figures 5 to 9 The implementation effects of this embodiment will be further explained.

[0045] Figure 5 The actual operating timing and output characteristics of the dead-time adjustment module 20 are demonstrated under the conditions that the first input signal VIA and the second input signal VIB have no delay and a 20kΩ resistor is connected externally to the dead-time adjustment terminal. From Figure 5 The first two rows of waveforms in the upper middle section show that the first input signal VIA experiences a rising edge transition at approximately 46.0 μs, and the second input signal VIB also experiences a falling edge transition at the same time. According to... Figure 5 As shown in the lower center of the output waveform, the first output signal VOA and the second output signal VOB exhibit a typical dead-time insertion effect: after the input transition edge at 46.0μs, neither output signal responds immediately, but rather undergoes a significant delay before the state transitions. The figure clearly indicates this delay width as 200ns via a vertical double-headed arrow, directly reflecting the dead-time constant set by the charging / discharging network composed of an external 20kΩ resistor and internal capacitors. Furthermore, the waveform shows that during the stable phase when the input signal is at a high or low level, both output signals maintain a stable level without glitches or unnecessary oscillations, indicating that the circuit has good noise suppression capabilities and stable level holding characteristics. In summary, this figure clearly demonstrates that the dead-time control circuit can precisely control the width of the dead time by adjusting the external resistor value, successfully inserting a 200ns safety interval between the two output signals. This effectively avoids the risk of shoot-through short circuits in the upper and lower bridge arms of the power converter, ensuring the safe and stable operation of the system.

[0046] Figure 6 This demonstrates the dynamic response and output characteristics when a large-value resistor of 220kΩ is connected to the dead-time adjustment terminal, under the condition that the first input signal VIA and the second input signal VIB maintain a no-delay and in an inverted logic relationship. According to... Figure 6 As can be seen from the first two sets of waveforms, the first input signal VIA and the second input signal VIB undergo synchronous transition at approximately 51.0 μs. As the external resistance of the dead time adjustment terminal increases from 20 kΩ to 220 kΩ, the charging and discharging time delay constant increases significantly, resulting in a substantial extension of the dead time. Figure 6 The double-headed arrow clearly indicates that this delay width has been extended to 2μs. Specifically, after the input transition edge at 51.0μs, both the first output signal VOA and the second output signal VOB experience a long wait period of 2μs before their states change. This extended delay means that the upper and lower bridge arm power transistors have a longer safe isolation time before switching their conduction states, perfectly demonstrating the adaptive capability of this dead-time adjustment circuit to linearly control the dead-time width using a single external resistor.

[0047] Figure 7This demonstrates the extreme operating characteristics when the dead-time adjustment terminal is shorted to the power supply, under the condition that the two input signals have no delay and are in an inverted logic relationship. From Figure 7 The first two rows of waveforms in the upper middle section show that the first input signal VIA and the second output signal VOB undergo synchronous transitions at approximately 51.0 μs. According to... Figure 7 As can be seen from the output waveform in the lower middle section, when the dead time adjustment terminal is shorted to the power supply, the constant current source in the delay comparison subunit of the dead time control circuit stops working or is in a saturated state, causing the capacitor to no longer charge linearly or to charge for an extremely short time, thus making the dead time approach zero. Specifically, the timing is as follows: after the input transition edge of 51.0 μs, the first output signal VOA and the second output signal VOB almost simultaneously flip, and the output waveform closely follows the input signal transition with almost no noticeable delay interval. This elimination of dead time means that there is almost no safety isolation time when the upper and lower bridge arm power transistors switch their conduction states, demonstrating the extreme response characteristics of this dead time adjustment circuit under extreme conditions.

[0048] Figure 8 The output characteristics were demonstrated under test conditions with an external 20kΩ resistor connected to the dead time adjustment terminal and a 50ns delay deviation between the two input signals. According to... Figure 8 As can be seen from the first two rows of waveforms in the upper middle section, the first input signal VIA and the second output maintain an inverse logic relationship in the initial stage (before about 41.0μs), but a significant phase difference appears in the subsequent transitions; Figure 8 The diagram clearly indicates, via bidirectional arrows, that the falling edge of the first input signal VIA lags behind the second input signal VIB by 50ns. Despite this 50ns delay mismatch, the first output signal VOA and the second output signal VOB still exhibit strong anti-interference capabilities and stable timing control characteristics after adjustment by the dead-time control unit. Specifically, after the initial 41.0μs transition edge, both output signals undergo a 200ns delay as indicated in the diagram before their states flip; and during the subsequent 46.0μs period, the waveform delay characteristics of the output signals remain strictly maintained at 200ns. This indicates that because the 20kΩ resistor connected to the dead-time adjustment terminal sets a significant and fixed dead time (200ns), this fixed dead-time window is much larger than the small delay fluctuation of the input signal itself (50ns). Therefore, the two output waveforms are not affected by the input delay mismatch and still exhibit symmetrical and stable square wave outputs.

[0049] Figure 9This demonstrates the output characteristics under test conditions with an external 20kΩ resistor connected to the dead-time adjustment terminal and a 500ns delay deviation between the two input signals. As shown in the first two rows of waveforms at the top of the figure, the first input signal VIA and the second input signal VIB exhibit significant asymmetry across the entire time axis. The figure clearly indicates, through bidirectional arrows, a significant 500ns delay mismatch between the rising and falling edges of both input signals. Figure 9 As shown in the two waveforms at the bottom center, the first output signal VOA and the second output signal VOB, after being adjusted by the dead-time control unit, still exhibit strong anti-interference capabilities and stable timing control characteristics. Specifically, the timing is as follows: in the initial period of 40.0μs to 45.0μs, the first input signal VIA changes before the second input signal VIB, but the two output signals only change state after a 500ns delay as indicated in the figure; in the subsequent 46.0μs period, although the delay relationship of the input signals reverses, the delay characteristic of the output waveform remains strictly maintained at 500ns. This indicates that because the 20kΩ resistor connected to the dead-time adjustment terminal sets a significant and fixed dead time (500ns), this fixed dead-time window matches numerically with the externally introduced input delay mismatch (500ns), thus causing the output waveform to exhibit a following characteristic that changes synchronously with the input delay. The above are all preferred embodiments of this application, and are not intended to limit the scope of protection of this application. Therefore, all equivalent changes made in accordance with the structure, shape and principle of this application should be covered within the scope of protection of this application.

Claims

1. An adjustable dead-time control circuit for a dual-channel driver, characterized in that, Includes an input signal detection module and a dead time adjustment module; The input signal detection module is connected in series with the dead time adjustment module, and the output terminal of the dead time adjustment module is connected to the input terminal of the dual-channel driver. The input signal detection module is used to perform voltage reduction processing and logical operations on the first and second input signals respectively, and output an intermediate signal. The dead time adjustment module is used to perform edge detection on the incoming intermediate signal, obtain a dead time control signal, superimpose the dead time control signal and the intermediate signal to perform dead time control, and output a first output signal and a second output signal to the dual-channel driver.

2. The adjustable dead-time control circuit for a dual-channel driver according to claim 1, characterized in that, The input signal detection module includes a first step-down circuit, a second step-down circuit, and a logic operation unit. The logic operation unit includes a first NOT gate, a second NOT gate, a first NAND gate, a second NAND gate, a third NAND gate, and a fourth NAND gate. The input terminal of the first step-down circuit is connected to the first input signal. The first output terminal of the first step-down circuit is connected to the first input terminal of the second NAND gate. The second output terminal of the first step-down circuit is connected to the input terminal of the first NOT gate. The output terminal of the first NOT gate is connected to the first input terminal of the first NAND gate. The output terminal of the first NAND gate is connected to the second input terminal of the second NAND gate. The input terminal of the second step-down circuit is connected to the second input signal, the output terminal of the second step-down circuit is connected to the input terminal of the second NOT gate, the output terminal of the second NOT gate is connected to the first input terminal of the third NAND gate, and the output terminal of the third NAND gate is connected to the second input terminal of the fourth NAND gate. The second input terminal of the first NAND gate is connected to the connection line between the second NOT gate and the third NAND gate, the second input terminal of the third NAND gate is connected to the connection line between the first step-down circuit and the first NOT gate, and the first input terminal of the fourth NAND gate is connected to the connection line between the first NOT gate and the third NAND gate.

3. The adjustable dead-time control circuit for a dual-channel driver according to claim 2, characterized in that, The intermediate signal includes a first intermediate signal and a second intermediate signal, including: The first input signal is stepped down by the first step-down circuit to obtain a first in-phase signal that is in phase with the first input signal and a first in-phase signal that is out of phase with the first input signal; and the second input signal is stepped down by the second step-down circuit to obtain a second in-phase signal that is in phase with the second input signal. The first in-phase signal, the second in-phase signal, and the first inverted signal are logically operated on by the logic operation unit to obtain the first intermediate signal and the second intermediate signal.

4. The adjustable dead-time control circuit for a dual-channel driver according to claim 3, characterized in that, The dead time adjustment module includes a first reset-set trigger, a second reset-set trigger, a dead time control circuit, a first AND gate, and a second AND gate; The first input terminal of the first reset-set trigger is connected to the output terminal of the second NAND gate, the second input terminal of the first reset-set trigger is connected to the first pulse signal, the output terminal of the first reset-set trigger is connected to the first input terminal of the dead time control circuit, the second input terminal of the dead time control circuit and the first input terminal of the first AND gate are respectively connected to the output terminal of the second NAND gate, and the second input terminal of the first AND gate is connected to the first output terminal of the dead time control circuit. The first input terminal of the second reset-set trigger is connected to the output terminal of the fourth NAND gate, the second input terminal of the second reset-set trigger is connected to the second pulse signal, the output terminal of the second reset-set trigger is connected to the third input terminal of the dead time control circuit, the fourth input terminal of the dead time control circuit and the first input terminal of the second AND gate are respectively connected to the output terminal of the fourth NAND gate, and the second input terminal of the second AND gate is connected to the second output terminal of the dead time control circuit. The outputs of the first AND gate and the second AND gate are respectively connected to the input of the dual-channel driver.

5. The adjustable dead-time control circuit for a dual-channel driver according to claim 4, characterized in that, The dead time control signal includes a first dead time control signal and a second dead time control signal, and the dead time control circuit includes a start unit, a first dead time control unit and a second dead time control unit; The startup unit is connected to the first dead time control unit and the second dead time control unit, respectively; The startup unit is used to provide startup voltage to the first dead time control unit and the second dead time control unit; The first dead time control unit is used to generate a first charging signal based on the first charging signal after generating a first charging signal based on the start-up voltage; The second dead time control unit is used to generate a second dead time control signal based on the second charging signal after generating a second charging signal based on the start-up voltage.

6. The adjustable dead-time control circuit for a dual-channel driver according to claim 5, characterized in that, The startup unit includes a first P-type transistor, a first N-type transistor, and a first resistor; The gate of the first N-type transistor is connected to a control signal, the source of the first N-type transistor is connected to the drain of the first P-type transistor, the drain of the first N-type transistor is connected to one end of the first resistor, and the other end of the first resistor is connected to the dead time control terminal. An external resistor is connected to the connection line between the dead time control terminal and the first resistor.

7. The adjustable dead-time control circuit for a dual-channel driver according to claim 6, characterized in that, The first dead-time control unit includes a first delay comparison subunit and a first drive logic control subunit; The first delay comparison subunit includes a second P-type transistor, a second N-type transistor, a third N-type transistor, a fourth N-type transistor, a second resistor, a first capacitor, and a first comparator. The gate of the second P-type transistor is connected to the gate of the first P-type transistor, the drain of the second P-type transistor is connected to the drain of the second N-type transistor, the source of the second N-type transistor is connected to the source of the third N-type transistor, the gate of the third N-type transistor is connected to the connection line between the second P-type transistor and the second N-type transistor via the gate of the second N-type transistor, the drain of the third N-type transistor is connected to one end of the second resistor, the other end of the second resistor is connected to the drain of the fourth N-type transistor and one end of the first capacitor, the gate of the fourth N-type transistor is connected to the output terminal of the first reset-set flip-flop, the source of the fourth N-type transistor and the other end of the first capacitor are connected to the ground terminal, and the inverting input terminal of the first comparator is connected to the drain of the second P-type transistor. The first drive logic control subunit includes a third P-type transistor, a fourth P-type transistor, a fifth N-type transistor, a third NOT gate, a fourth NOT gate, and a fifth NOT gate. The gate of the third P-type transistor is connected to the output terminal of the first comparator and the drain of the fourth P-type transistor, respectively. The drains of the third P-type transistor and the fifth N-type transistor are connected to the input terminal of the third NOT gate. The gate of the fifth N-type transistor and the input terminal of the fourth NOT gate are connected to the output terminal of the first reset-set flip-flop. The output terminal of the fourth NOT gate is connected to the gate of the fourth P-type transistor. The output terminal of the third NOT gate is connected to the input terminal of the fifth NOT gate. The output terminal of the fifth NOT gate is connected to the second input terminal of the first AND gate.

8. The adjustable dead-time control circuit for a dual-channel driver according to claim 7, characterized in that, The second dead-time control unit includes a second delay comparison subunit and a second drive logic control subunit; The second delay comparator subunit includes a fifth P-type transistor, a sixth N-type transistor, a seventh N-type transistor, an eighth N-type transistor, a third resistor, a second capacitor, and a second comparator. The gate of the fifth P-type transistor is connected to the gate of the first P-type transistor. The drain of the fifth P-type transistor is connected to the drain of the sixth N-type transistor. The source of the sixth N-type transistor is connected to the source of the seventh N-type transistor. The gate of the seventh N-type transistor is connected to the connection line between the fifth P-type transistor and the sixth N-type transistor via the gate of the sixth N-type transistor. The drain of the seventh N-type transistor is connected to one end of the third resistor. The other end of the third resistor is connected to the drain of the eighth N-type transistor and one end of the second capacitor. The gate of the eighth N-type transistor is connected to the output terminal of the second reset-set flip-flop. The source of the eighth N-type transistor and the other end of the second capacitor are both connected to the ground terminal. The inverting input terminal of the second comparator is connected to the drain of the fifth P-type transistor. The second drive logic control subunit includes a sixth P-type transistor, a seventh P-type transistor, a ninth N-type transistor, a sixth NOT gate, a seventh NOT gate, and an eighth NOT gate. The gate of the sixth P-type transistor is connected to the output terminal of the second comparator and the drain of the seventh P-type transistor, respectively. The drains of the sixth P-type transistor and the ninth N-type transistor are connected to the input terminal of the sixth NOT gate. The gate of the ninth N-type transistor and the input terminal of the seventh NOT gate are connected to the output terminal of the second reset-set flip-flop. The output terminal of the seventh NOT gate is connected to the gate of the seventh P-type transistor. The output terminal of the sixth NOT gate is connected to the input terminal of the eighth NOT gate. The output terminal of the eighth NOT gate is connected to the second input terminal of the second AND gate.

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