Driving circuit of tuning element selection switch, power supply chip and wireless charging device

Abstract

The application provides a driving circuit of a tuning element selection switch, a power supply chip and a wireless charging device. The driving circuit of the tuning element selection switch comprises a level conversion unit configured to convert an input control signal to a floating voltage domain that changes with a power stage switch node potential; and a driving unit comprising a first driving path configured to control a potential rise of a control end of a selection switch and a second driving path configured to control a potential fall of the control end of the selection switch, wherein the first driving path and the second driving path each comprise an independent driving transistor; and wherein the driving circuit is configured to keep the first driving path and the second driving path in an off state in a default state. The driving circuit of the tuning element selection switch can realize stable driving of the selection switch in the floating voltage domain, keep the default off state in the absence of input or in an abnormal state, avoid the risk of mis-conduction and straight-through, and improve system safety and reliability.

Description

Technical Field

[0001] This application belongs to the field of wireless charging technology, specifically relating to a driving circuit for a tuning element selection switch, a power chip, and a wireless charging device. Background Technology

[0002] In the field of wireless charging, in applications where an H-bridge drives an LC load, the switching of the tuning capacitor is typically achieved using an N-type transistor switch. For example... Figure 1 As shown, when the selection switch is closed, capacitor C_1 is not connected to the LC resonant cavity, and the resonant cavity capacitance constant is C_0; when the selection switch is on, capacitor C_1 is connected to the LC resonant cavity, and the resonant cavity capacitance constant increases to C_0 + C_1. Thus, the resonant frequency is adjusted by controlling the on and off states of capacitor C_1. However, this circuit cannot switch in real time while the H-bridge is operating; the resonant capacitor must be selected before the H-bridge is turned on when it is not operating. Furthermore, the overlapping on and off states of the driver stage power transistors cause efficiency degradation and even the risk of burnout. Moreover, the existing architecture is inconvenient for initial and default state settings and is not user-friendly for chip pin withstand voltage testing.

[0003] It should be noted that the above statements are only used to provide background information related to this application and do not necessarily constitute prior art. Summary of the Invention

[0004] This application proposes a driving circuit, power chip, and wireless charging device for a tuner element selection switch, which can achieve stable driving of the tuner element selection switch in a floating voltage domain.

[0005] The first aspect of this application provides a driving circuit for a tuning element selection switch, comprising: The level conversion unit is used to convert the input control signal to a floating voltage domain that varies with the potential of the power stage switching node; The driving unit includes a first driving path for controlling the rise of the control terminal potential of the selection switch and a second driving path for controlling the fall of the control terminal potential, wherein the first driving path and the second driving path each include an independent driving transistor. The driving circuit is configured to keep both the first driving path and the second driving path off by default.

[0006] In some alternative embodiments, the level shifting unit includes a cross-coupling unit, an input unit, and a default state setting resistor.

[0007] In some optional embodiments, the cross-coupling unit includes a first pull-up transistor, a second pull-up transistor, a first pull-down transistor, and a second pull-down transistor; the control terminals of the first pull-up transistor and the second pull-up transistor are respectively connected to the corresponding nodes of the other to form a cross-coupling structure.

[0008] In some alternative embodiments, the input unit includes at least two input transistors for coupling input signals to two nodes of the cross-coupled unit.

[0009] In some optional embodiments, the default state setting resistor includes a resistive device for setting the default pull-up and pull-down voltages.

[0010] In some optional embodiments, the level conversion unit further includes a level shift output unit for controlling the output potential of the cross-coupled unit, wherein the level shift output unit is configured to set the default output state of the level conversion unit to a high level or a low level.

[0011] In some alternative embodiments, the level shift output unit includes an input shaping circuit, which includes an inverter.

[0012] In some optional embodiments, a drive control unit is also included, which is configured to enable mutually exclusive conduction of the first drive path and the second drive path.

[0013] In some optional embodiments, the drive control unit includes an interlock control circuit, which includes cross-coupled logic gates, each logic gate having two outputs connected to the input of the other.

[0014] In some alternative embodiments, the floating voltage domain is formed between the H-bridge switching node and the bootstrap power supply node; the tuning element is a capacitor and / or an inductor.

[0015] An embodiment of the second aspect of this application provides a power management chip that integrates a drive circuit for the tuning element selection switch described in the first aspect.

[0016] An embodiment of the third aspect of this application provides an electronic device including the power management chip described in the second aspect.

[0017] The technical solutions provided in this application embodiment have at least the following technical effects or advantages: The driving circuit for the tuning element selection switch provided in this application uses a level conversion unit to map the control signal to a reference frame that varies with the SW node, thus stabilizing the gate-source voltage. The first and second driving paths are responsible for the gate charging and discharging of the selection switch, respectively. A default double-off condition ensures that neither path provides effective driving current, causing the gate-source voltage of the selection switch to approach 0, keeping the selection switch off and thus providing fail-safe characteristics. In this way, stable driving of the selection switch can be achieved in the floating voltage domain, and the default off condition is maintained even in the absence of input or abnormal states, avoiding the risks of false turn-on and shoot-through, and improving system safety and reliability. Attached Figure Description

[0018] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the scope of this application. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings: Figure 1 A schematic diagram of the framework structure of a conventional tuning element selection switch drive circuit is shown. Figure 2 A schematic diagram of the frame structure of the driving circuit for a tuning element selection switch provided in an embodiment of this application is shown. Figure 3 This illustration shows a schematic diagram of the specific structure of a level conversion unit provided in an embodiment of this application in the default 0 state; Figure 4 This paper shows a schematic diagram of the specific structure of a level conversion unit provided in an embodiment of the present application in the default 1 state; Figure 5 A schematic diagram showing the simulation results of the driving circuit provided in the embodiment of this application is shown; Figure 6 A schematic diagram of the application structure of the driving circuit for the tuning element selection switch provided in another embodiment of this application is shown. Detailed Implementation

[0019] Exemplary embodiments of this application will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of this application are shown in the drawings, it should be understood that this application may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of this application and to fully convey the scope of this application to those skilled in the art.

[0020] It should be noted that, unless otherwise stated, the technical or scientific terms used in this application shall have the ordinary meaning as understood by one of ordinary skill in the art to which this application pertains.

[0021] In related technologies, the basic selection switch driver circuit has the following technical problems: it cannot switch in real time when the H-bridge is working; the resonant capacitor can only be selected before the H-bridge is turned on when the H-bridge is not working. The overlapping of the power transistors' on / off states in the driver stage causes efficiency degradation and even the risk of burnout. The existing architecture is inconvenient for setting initial and default states and is not user-friendly for chip pin withstand voltage testing. The inability to switch in real time when the H-bridge is working is mainly due to the limitation of the level shifter, requiring a level shifter that can switch continuously and has good common-mode immunity. The overlapping of the power transistors' on / off states in the driver stage is caused by the lack of non-overlapping control for the pull-up and pull-down transistors. The inconvenience of setting initial and default states in the existing architecture is due to the lack of separate paths in the driver stage, making it impossible to simultaneously default to the off state for both the pull-up P-transistor and the pull-down N-transistor.

[0022] To address the aforementioned problems, embodiments of this application provide a driving circuit for a tuning element selection switch, such as... Figure 2 As shown, the driving circuit of the tuning element selection switch includes: a level conversion unit for converting the input control signal to a floating voltage domain that varies with the potential of the power stage switching node; a driving unit including a first driving path for controlling the rise of the control terminal potential of the selection switch and a second driving path for controlling the fall of the control terminal potential, wherein the first driving path and the second driving path each include an independent driving transistor; wherein the driving circuit is configured to keep both the first driving path and the second driving path in a turned-off state by default to facilitate the withstand voltage test of the driving pin.

[0023] The tuning element can be a tuning capacitor, i.e., a capacitor in an LC oscillator circuit; or it can be a tuning inductor, i.e., an inductor in an LC oscillator circuit. The selection switch is used to select the tuning element, such as... Figure 1 and Figure 2 The switching MOSFET Q is used in this embodiment. The level conversion unit can be any level conversion device capable of performing the above-mentioned level conversion function; its specific structure is not specifically limited in this embodiment.

[0024] In this embodiment, the level shifting unit maps the control signal to a reference frame that varies with the SW (switch) node, making the gate-source voltage relatively stable. The first and second drive paths are responsible for the gate charging and discharging of the selector switch, respectively. The default double shutdown ensures that neither path provides effective drive current, causing the gate-source voltage of the selector switch to tend to 0, keeping the selector switch off. This provides fail-safe characteristics and facilitates withstand voltage testing of the drive pin. Thus, stable driving of the selector switch can be achieved in the floating voltage domain, maintaining default shutdown in the absence of input or abnormal conditions, avoiding the risks of false turn-on and shoot-through, and improving system safety and reliability.

[0025] Specifically, this embodiment can achieve at least the following technical effects: (1) Implement a safe default state to improve system reliability This embodiment sets both the first and second drive paths to a default off state, so that the control terminal of the selector switch remains off when there is no input signal or an abnormal state, avoiding false turn-on caused by the drive node being floating or falsely triggered, thereby improving system safety. It is especially suitable for pin withstand voltage testing and power-on transient processes.

[0026] (2) Eliminate the risk of overlapping conduction of driving forces This embodiment divides the drive path into independent pull-up and pull-down paths and combines them with subsequent control to avoid the shoot-through current problem caused by the simultaneous conduction of the pull-up and pull-down paths, thereby reducing power consumption and preventing device damage.

[0027] (3) Improve driving stability under floating voltage domain This embodiment uses a level conversion unit to convert the input signal to a floating voltage domain that varies with the power stage nodes, ensuring that the drive signal is always based on a local reference potential, thereby guaranteeing the effectiveness and stability of the drive signal during the switching process of the power circuit.

[0028] (4) Supports stable switching during the resonant parameter adjustment process Based on the above structure, the drive circuit can reliably control the selection switch during the operation of the power circuit, so that the tuning element can be stably connected or disconnected, thereby realizing the adjustment of the resonance parameters.

[0029] The technical effects of this invention are achieved based on the following physical and circuit principles: (1) Circuit mechanism of default double turn-off state In the driving circuit, the first driving path (pull-up path) and the second driving path (pull-down path) control the rise and fall of the potential at the control terminal of the selector switch, respectively.

[0030] When both are in the off state: the pull-up path does not provide charging current; the pull-down path does not provide discharging current. At this time, the potential of the selector switch control terminal is maintained in the preset safe range (usually the off range), so that the gate-source voltage Vgs≈0, and therefore the selector switch remains off. That is, as long as there is no effective driving source in the default state, the system naturally has the "fail-safe" characteristic.

[0031] (2) Mechanism of independent drive path to avoid straight-through If both the pull-up and pull-down paths are conducting simultaneously, the following current path will be formed: power supply voltage VDD → pull-up transistor → pull-down transistor → GND. This path is a typical "shoot-through" current.

[0032] This invention structurally separates the two paths and prevents them from conducting simultaneously, ensuring that the current path is not valid at any given time. This reduces power consumption, avoids localized overheating, and improves device reliability. (3) The necessity of floating voltage domain drive In an H-bridge or half-bridge architecture, the switching node potential (SW) changes rapidly between high and low levels as the power devices switch: the reference to ground is no longer fixed, and dv / dt is large. If the drive signal is still based on a fixed ground reference, this will result in: Vgs = Vg In Vs, Vs changes rapidly, causing the driver to fail.

[0033] This invention uses a level conversion unit to make the drive signal reference the same floating node, thereby ensuring the stability of the gate-source voltage Vgs and making the selection switch controllable.

[0034] (4) Circuit basis of resonance regulation When a switch-controlled tuning element (capacitor or inductor) is connected to the resonant network, its resonant frequency satisfies: Therefore: increasing the capacitor C will decrease the frequency f; increasing the inductor L will also decrease the frequency.

[0035] This invention achieves reliable switching of the tuning element by stably driving the selection switch, thereby realizing dynamic adjustment of the resonance parameters.

[0036] In some alternative embodiments, such as Figure 3 and Figure 4 As shown, Figure 3 The diagram shows the specific structure of the level conversion unit in the default 0 state. Figure 4 The diagram illustrates the specific structure of the level shifting unit in its default 1 state. The level shifting unit includes a cross-coupling unit, an input unit, and a default state setting resistor. The input unit provides the circuit's trigger condition, the cross-coupling unit provides bistable state holding, and the default state setting resistor provides operating current and disturbance rejection capability. These three components work together to form a stable level shifting and state holding mechanism. Thus, the hierarchical structure of the cross-coupling unit, input unit, and default state setting resistor improves stability and controllability in high dv / dt environments.

[0037] In some alternative embodiments, such as Figure 3 and Figure 4 As shown, the cross-coupling unit includes a first pull-up transistor M1, a second pull-up transistor M2, a first pull-down transistor M3, and a second pull-down transistor M4; the control terminals of the first pull-up transistor M1 and the second pull-up transistor M2, as well as the control terminals of the first pull-down transistor M3 and the second pull-down transistor M4, are respectively connected to the corresponding nodes of the other to form a cross-coupling control structure.

[0038] In this embodiment, the two pairs of transistors are cross-connected to form a positive feedback loop. Based on this positive feedback loop, any node potential change is amplified by feedback, enabling the system to quickly converge to one of the two stable states (high / low), improving noise immunity, forming a strong anti-interference bistable output, and suppressing false flips caused by common-mode disturbances.

[0039] In some alternative embodiments, the input unit includes at least two input transistors for converting the input signal to two nodes of the cross-coupled unit.

[0040] In this embodiment, the input transistor converts the control signal to the latch node, breaks the original balance through instantaneous current, triggers cross-coupled positive feedback, and completes the state flip, which can effectively trigger the latch node, ensuring reliable flipping and controllable speed.

[0041] Specifically, such as Figure 3 and Figure 4 As shown, the input unit can include four input transistors, namely M5, M6, M7, and M8, and an input inverter. M6 and M8 are high-voltage input transistors; when turned on, they pull down the corresponding cross-coupled nodes; when turned off, they do not pull down the corresponding cross-coupled nodes. M5 and M7 are high-voltage clamping transistors, used to protect the low-voltage transistors in the cross-coupled unit. The working principle is to pull down the input nodes of the cross-coupled pair (i.e., the two nodes in the cross-coupled pair where the resistors are pulled up and down by default), pulling down one while leaving the other unpulled. This locks the state where one side is 0 and the other is 1, and then transmits the result to the subsequent circuitry.

[0042] In some alternative embodiments, the default state setting resistor includes a resistive device for setting the default pull-up and pull-down voltages.

[0043] like Figure 3 and Figure 4 As shown, the default state setting resistor can include resistors acting at the two pairs of transistor connections of the cross-coupled unit, and a resistor acting at the output terminal, i.e. Figure 3 and Figure 4 The structure represented by the black solid square in the figure can be a resistive load or a circuit composed of a resistive load. This embodiment does not specifically limit the specific structure of the resistor set in the default state.

[0044] In some optional embodiments, the level conversion unit further includes a level shift output unit for controlling the output voltage of the cross-coupled unit. The level shift output unit is configured to set the default output state of the level conversion unit to a high level or a low level. This level shift output unit can control the controllable initial state of the level conversion unit's output, facilitating system power-on and testing.

[0045] In some optional embodiments, the level-shift output unit includes an input shaping circuit for level shaping, logic latching, and output driving. This input shaping circuit may include an inverter or a logic circuit including NOT gates and / or NAND gates. This embodiment does not specifically limit the structure of the input shaping circuit, as long as it can achieve the control functions of the level-shift output unit described above.

[0046] In this embodiment, the inverter can quickly pull the intermediate voltage to logic high / low, shorten the transition time, reduce the probability of glitches being amplified by subsequent stages, eliminate the analog transition region, increase the steepness of the signal edge, and reduce false triggering.

[0047] Specifically, such as Figure 3 and Figure 4 As shown, the level-shift output unit may further include cross-feedback logic circuitry and output buffer stage logic circuitry. The cross-feedback logic circuitry includes multiple inverters and two cross-feedback logic gates, which can form SR latching and bistable logic control. The output buffer stage logic circuitry may include two inverters connected in series to provide sufficient drive capability.

[0048] In some alternative embodiments, the drive circuit further includes a drive control unit configured to enable mutually exclusive conduction of the first drive path and the second drive path.

[0049] In this embodiment, the "level conversion" and "drive control" are separated to avoid malfunctions caused by direct drive. Independent control is introduced at the drive level to improve system stability and safety.

[0050] In some alternative embodiments, such as Figure 2 As shown, the drive control unit includes an interlock control circuit, which includes cross-coupled logic gate circuits. The logic gate circuits include two logic gates, and the outputs of the two logic gate circuits are respectively connected to the inputs of the other.

[0051] In this embodiment, the interlocking logic uses state constraints to make the two control signals logically mutually exclusive, eliminating the condition for simultaneous conduction at the source. This prevents the upper and lower drive paths from conducting simultaneously and avoids shoot-through current. Furthermore, the two logic gates are cross-connected to form a structure similar to an SR latch, so that the conduction of one side automatically inhibits the conduction of the other side, achieving a stable interlocking relationship and avoiding race conditions.

[0052] Specifically, the logic gate circuits with cross-coupling connections mentioned above may include NOT gates, AND gates, NOR gates, and buffers, etc. This embodiment does not specifically limit their specific structure, as long as they can implement the above interlocking control logic.

[0053] In addition, the drive control unit may also include a signal shaping circuit, which includes an inverter. Multi-stage inverters or buffer amplifiers can provide drive capability, ensuring the output signal has sufficient drive current and clear logic boundaries, thereby further improving drive signal quality and enhancing anti-interference capabilities.

[0054] Furthermore, the drive circuit may also include a default state setting resistor to provide a default state voltage to the gate of the transistors (P-type, N-type, and selection switch Q), such as... Figure 2 As shown in the solid black square.

[0055] In some alternative embodiments, the floating voltage domain is formed between the H-bridge switching node and the bootstrap power supply node. The tuning element can be a capacitor and / or an inductor; that is, the drive circuit can also be applied to, for example... Figure 6 The inductor selection architecture shown.

[0056] In this embodiment, the floating voltage domain (SW-BST, where SW is the switching node and BST is the bootstrap node, providing the floating gate drive voltage) provides a high-side drive reference, enabling the drive circuit to operate stably in the resonant system. Frequency adjustment is achieved by controlling the connection / disconnection of the tuning element, which is applicable to H-bridges and resonant systems, thus expanding the application range.

[0057] In some specific embodiments, such as Figure 2 - Figure 5 As shown, the driving circuit consists of two parts: two level shifters and an interlocked drive chain. The level shifters employ the following... Figure 3 and Figure 4 The structure shown has two level shifters with high-side outputs of high and low initial states (and default states), corresponding to the initial state (and default state) of the driver stage. Both P-channel and N-channel transistors are turned off to facilitate pin withstand voltage testing. The low-to-high cross-coupling structure provides excellent common-mode immunity in applications where speed is not critical, allowing for easy switching of the capacitor selection switch during H-bridge operation.

[0058] Interlocked drive chains are drive units, such as Figure 2As shown, the drive chain controls the P-channel and N-channel transistors separately, using an interlock structure to achieve non-overlapping processing. Simultaneously, the separately controlled drive chain allows for initial and default state settings where both P-channel and N-channel transistors are simultaneously off, facilitating pin withstand voltage testing. The selector switch Q is an external MOSFET, and Q's gate corresponds to the output pin of this drive circuit. When performing withstand voltage testing on this pin, an external voltage can be pumped from this pin, requiring both the pull-up P-channel and pull-down N-channel transistors to be turned off. This architecture perfectly meets this withstand voltage testing requirement; the pull-up P-channel and pull-down N-channel transistors are turned off by default due to resistors, and the default state of the preceding level shifter also corresponds to the off state of the P-channel and N-channel transistors, eliminating the risk of logic misinterpretation.

[0059] The simulation results of the circuit operation are as follows: Figure 5 As shown, where Vgs is the gate-source voltage of the selection switch Q, as... Figure 5 The thinner red line (the first line from top to bottom) indicates this; Vds is the source-drain voltage, as shown below. Figure 5 The yellow line in the middle (the second line from the top) indicates this; RX_VOUT is the output voltage of the wireless charging receiver, as shown below. Figure 5 The thicker red line (the third line from the top) indicates this; COIL is the intermediate node of the LC load, as shown below. Figure 5 The darker blue line (fourth line from the top) indicates this; D represents the drain voltage of the selector switch Q, as shown below. Figure 5 The lighter blue line (the fifth line from the top) indicates this. When Vgs is 0V, the selector switch Q is off, and Vds experiences the resonant high voltage from the H-bridge switch. At this time, the LC intrinsic frequency is close to the switching frequency, resulting in a higher output power from the wireless charger, a higher RX_VOUT output, and a larger COIL resonant amplitude. The drain voltage of the selector switch Q shows a negative voltage initially after Q is turned off, as the body diode of the selector switch Q conducts to charge capacitor C_1. When Vgs is 4.5V, the selector switch Q is on, and Vds immediately drops. At this time, the LC intrinsic frequency is far from the switching frequency, resulting in a lower output power from the wireless charger, a lower RX_VOUT output, and a smaller COIL resonant amplitude. Figure 5 As can be seen, in this embodiment, the selected switch Q exhibits excellent performance in terms of hot switching, output convergence, and output power regulation in wireless charging applications.

[0060] In addition, this driving circuit can also be used in the driving circuit of the tuning inductor switching switch in wireless charging applications, that is, the driving circuit of the H-bridge driving the LC load and the tuning inductor switching transistor. For example Figure 6As shown, the same driving architecture can be used on the inductor side to switch the tuning inductor. When the switch is closed, the tuning inductance is L_0, and when the switch is open, the tuning inductance is L_0+L_1.

[0061] Based on the same concept as the driving circuit of the tuning element selection switch described above, this embodiment also provides a power management chip, on which the driving circuit of the tuning element selection switch described above is integrated.

[0062] The power management chip provided in this embodiment is based on the same concept as the driving circuit of the above-mentioned tuning element selection switch. Therefore, it can at least achieve the beneficial effects that the driving circuit of the above-mentioned tuning element selection switch can achieve. Furthermore, any implementation of the driving circuit of the above-mentioned tuning element selection switch can be applied to the chip provided in this embodiment, and will not be described in detail here.

[0063] Based on the same concept as the driving circuit of the tuning element selection switch described above, this embodiment also provides an electronic device including the power management chip described above.

[0064] The electronic device chip provided in this embodiment is based on the same concept as the driving circuit of the above-mentioned tuning element selection switch. Therefore, it can at least achieve the beneficial effects that the driving circuit of the above-mentioned tuning element selection switch can achieve. Furthermore, any implementation of the driving circuit of the above-mentioned tuning element selection switch can be applied to the chip provided in this embodiment, and will not be described in detail here.

[0065] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and not to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application, and they should all be covered within the scope of the claims and specification of this application. In particular, as long as there is no structural conflict, the various technical features mentioned in the embodiments can be combined in any way. This application is not limited to the specific embodiments disclosed herein, but includes all technical solutions falling within the scope of the claims.

Claims

1. A driving circuit for a tuning element selection switch, characterized in that, include: The level conversion unit is used to convert the input control signal to a floating voltage domain that varies with the potential of the power stage switching node; The driving unit includes a first driving path for controlling the rise of the control terminal potential of the selection switch and a second driving path for controlling the fall of the control terminal potential, wherein the first driving path and the second driving path each include an independent driving transistor. The driving circuit is configured to keep both the first driving path and the second driving path off by default.

2. The driving circuit for the tuning element selection switch as described in claim 1, characterized in that, The level conversion unit includes a cross-coupling unit, an input unit, and a default state setting resistor.

3. The driving circuit for the tuning element selection switch as described in claim 2, characterized in that, The cross-coupling unit includes a first pull-up transistor, a second pull-up transistor, a first pull-down transistor, and a second pull-down transistor; the control terminals of the first pull-up transistor and the second pull-up transistor are respectively connected to the corresponding nodes of the other to form a cross-coupling structure.

4. The driving circuit for the tuning element selection switch as described in claim 2, characterized in that, The input unit includes at least two input transistors for coupling input signals to two nodes of the cross-coupled unit.

5. The driving circuit for the tuning element selection switch as described in claim 2, characterized in that, The default state setting resistor includes a resistor device used to set the default pull-up and pull-down voltages.

6. The driving circuit for the tuning element selection switch as described in claim 2, characterized in that, The level conversion unit further includes a level shift output unit for controlling the output potential of the cross-coupling unit. The level shift output unit is configured to set the default output state of the level conversion unit to a high level or a low level.

7. The driving circuit for the tuning element selection switch as described in claim 6, characterized in that, The level shift output unit includes an input shaping circuit, which includes an inverter.

8. The driving circuit for the tuning element selection switch as described in claim 1, characterized in that, It also includes a drive control unit configured to enable mutually exclusive conduction of the first drive path and the second drive path.

9. The driving circuit for the tuning element selection switch as described in claim 1 or 8, characterized in that, The drive control unit includes an interlock control circuit, which includes cross-coupled logic gate circuits. Each logic gate circuit has two logic gates, and the outputs of the two logic gate circuits are respectively connected to the input of the other.

10. The driving circuit for the tuning element selection switch as described in claim 1, characterized in that, The floating voltage domain is formed between the H-bridge switching node and the bootstrap power supply node; the tuning element is a capacitor and / or an inductor.

11. A power management chip, characterized in that, It integrates a drive circuit for the tuning element selection switch as described in any one of claims 1-10.

12. An electronic device, characterized in that, Includes the power management chip as described in claim 11.

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