A level shifting circuit

Abstract

The application belongs to the technical field of electronic circuits and provides a level conversion circuit.The level conversion circuit comprises a switching module, a first current mirror module, a second current mirror module and a logic module; the first end of the switching module is connected with the first end of the first current mirror module, the second end of the switching module is connected with the first end of the second current mirror module, the first end of the logic module is connected with the second end of the first current mirror module, the second end of the logic module is connected with the second end of the second current mirror module, the third end of the logic module is connected with the third end of the second current mirror module, the fourth end of the logic module is connected with the third end of the first current mirror module, and the control end of the switching module is used for receiving an input signal of a first power supply domain.The level conversion circuit provided by the application effectively reduces the parasitic capacitance at the key nodes, thereby improving the conversion speed; meanwhile, the driving capability of the key signals is improved, and it is ensured that the key nodes will not be misinverted due to disturbance.

Description

Technical Field

[0001] This application belongs to the field of electronic circuit technology, and in particular relates to a level conversion circuit. Background Technology

[0002] In switching power supply chips, there are typically multiple voltage domains, and many signals need to be converted between different voltage domains. The function of a level conversion circuit is to convert signals between different voltage domains. However, existing solutions suffer from slow conversion speeds and false switching errors. Summary of the Invention

[0003] This application provides a level conversion circuit that can solve the problems of slow conversion speed and accidental flipping in existing solutions.

[0004] In a first aspect, embodiments of this application provide a level conversion circuit, including a switch module, a first current mirror module, a second current mirror module, and a logic module; a first terminal of the switch module is connected to a first terminal of the first current mirror module, a second terminal of the switch module is connected to a first terminal of the second current mirror module, a first terminal of the logic module is connected to a second terminal of the first current mirror module, a second terminal of the logic module is connected to a second terminal of the second current mirror module, a third terminal of the logic module is connected to a third terminal of the second current mirror module, and a fourth terminal of the logic module is connected to a third terminal of the first current mirror module; the control terminal of the switch module is used to receive an input signal from a first power domain. When the input signal becomes high, the switching module outputs a first signal to the first current mirror module to activate it, and outputs a second signal to the logic module. The logic module then uses the second signal to change its output signal and its inverted output signal to the first voltage of the second power domain and the second voltage of the second power domain, respectively. The first current mirror module uses the inverted output signal to stabilize the second signal. When the input signal becomes low, the switching module outputs a third signal to the second current mirror module to activate it, and outputs a fourth signal to the logic module. The logic module uses the fourth signal to change its output signal and its inverted output signal to the second voltage of the second power domain and the first voltage of the second power domain, respectively. The second current mirror module uses the fourth output signal to stabilize the fourth signal.

[0005] In one possible implementation of the first aspect, the switching module includes a first transistor, a second transistor, a first pulse generator, a second pulse generator, a first resistor, and a second resistor; the input terminals of the first pulse generator and the second pulse generator are respectively used to receive input signals; the power supply terminals of the first pulse generator and the second pulse generator respectively receive a first power supply voltage; the output terminal of the first pulse generator is connected to the gate of the first transistor; the drain of the first transistor is connected to the first end of the first resistor; the second end of the first resistor is connected to the first end of the second current mirror module; the output terminal of the second pulse generator is connected to the gate of the second transistor; the drain of the second transistor is connected to the first end of the second resistor; the second end of the second resistor is connected to the first end of the first current mirror module; the ground terminal of the first pulse generator, the source of the first transistor, the source of the second transistor, and the ground terminal of the second pulse generator are respectively connected to the first power supply ground.

[0006] In one possible implementation of the first aspect, the first current mirror module includes a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor; the gate of the fifth transistor is connected to the gate of the sixth transistor, the drain of the sixth transistor, the gate of the fourth transistor, and a first terminal of the switching module; the sources of the fifth transistor, the sixth transistor, and the third transistor receive a first voltage from a second power supply domain; the gate of the third transistor is connected to a fourth terminal of the logic module; the drain of the third transistor is connected to the source of the fourth transistor; and the drain of the fourth transistor is connected to the drain of the fifth transistor and a first terminal of the logic module.

[0007] In one possible implementation of the first aspect, the second current mirror module includes a seventh transistor, an eighth transistor, a ninth transistor, and a tenth transistor; the gate of the ninth transistor is connected to the gate of the seventh transistor, the gate of the eighth transistor, the drain of the eighth transistor, and the second terminal of the switching module, respectively; the source of the eighth transistor, the source of the seventh transistor, and the source of the tenth transistor receive a first voltage of the second power supply domain, respectively; the gate of the tenth transistor is connected to the third terminal of the logic module; the drain of the tenth transistor is connected to the source of the ninth transistor; and the drain of the ninth transistor is connected to the drain of the seventh transistor and the second terminal of the logic module, respectively.

[0008] In one possible implementation of the first aspect, the logic module includes a first inverter, a second inverter, a third inverter, a fourth inverter, a first NAND gate, and an eleventh transistor; the input terminal of the first inverter serves as the first terminal of the logic module, and is connected to the output terminal of the second inverter, the first input terminal of the first NAND gate, and the second terminal of the first current mirror module, respectively; the output terminal of the first inverter serves as the second terminal of the logic module, and is connected to the input terminal of the second inverter, the input terminal of the third inverter, and the second terminal of the second current mirror module, respectively; the output terminal of the third inverter serves as the third terminal of the logic module, and is connected to the drain of the eleventh transistor, the input terminal of the fourth inverter, the second input terminal of the first NAND gate, and the third terminal of the second current mirror module, respectively; the output terminal of the first NAND gate is connected to the gate of the eleventh transistor; the source of the eleventh transistor receives a first voltage of a second power supply domain; the output terminal of the fourth inverter serves as the fourth terminal of the logic module, and is connected to the third terminal of the first current mirror module; the ground terminals of the first inverter and the third inverter respectively receive a second voltage of the second power supply domain.

[0009] Secondly, embodiments of this application provide a level conversion circuit, including a switch module, a first current mirror module, a second current mirror module, and a logic module; a first terminal of the switch module is connected to a first terminal of the first current mirror module, a second terminal of the switch module is connected to a first terminal of the second current mirror module, a first terminal of the logic module is connected to a second terminal of the second current mirror module, a second terminal of the logic module is connected to a second terminal of the first current mirror module, a third terminal of the logic module is connected to a third terminal of the first current mirror module, and a fourth terminal of the logic module is connected to a third terminal of the second current mirror module; the control terminal of the switch module is used to receive an input signal from a first power domain. When the input signal becomes high, the switching module outputs a fifth signal to the first current mirror module to activate it, and outputs a sixth signal to the logic module. The logic module then uses the sixth signal to change its output signal and its inverted output signal to the first voltage and the second voltage of the third power domain, respectively. The first current mirror module uses the output signal to keep the sixth signal stable. When the input signal becomes low, the switching module outputs a seventh signal to the second current mirror module to activate it, and outputs an eighth signal to the logic module. The logic module uses the eighth signal to change its output signal and its inverted output signal to the second voltage and the first voltage of the third power domain, respectively. The second current mirror module uses the inverted output signal to keep the eighth signal stable.

[0010] In one possible implementation of the second aspect, the switching module includes a twelfth transistor, a thirteenth transistor, a third pulse generator, a fourth pulse generator, a third resistor, and a fourth resistor; the input terminals of the third pulse generator and the fourth pulse generator are respectively used to receive input signals; the power supply terminals of the third pulse generator, the fourth pulse generator, the source of the twelfth transistor, and the source of the thirteenth transistor respectively receive a power supply voltage from a first power domain; the ground terminals of the third pulse generator and the fourth pulse generator are respectively connected to the ground of the first power domain; the output terminal of the third pulse generator is connected to the gate of the twelfth transistor; the output terminal of the fourth pulse generator is connected to the gate of the thirteenth transistor; the drain of the twelfth transistor is connected to the first terminal of the third resistor; the second terminal of the third resistor is connected to the first terminal of the second current mirror module; the drain of the thirteenth transistor is connected to the first terminal of the fourth resistor; and the second terminal of the fourth resistor is connected to the first terminal of the first current mirror module.

[0011] In one possible implementation of the second aspect, the first current mirror module includes a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, and a seventeenth transistor; the gate of the fourteenth transistor is connected to the drain of the fourteenth transistor, the gate of the fifteenth transistor, the gate of the sixteenth transistor, and a first terminal of the switching module, respectively; the sources of the fourteenth transistor, the fifteenth transistor, and the seventeenth transistor receive a second voltage from a third power supply domain, respectively; the source of the sixteenth transistor is connected to the drain of the seventeenth transistor; the gate of the seventeenth transistor is connected to a third terminal of the logic module; and the drain of the sixteenth transistor is connected to the drain of the fifteenth transistor and a second terminal of the logic module, respectively.

[0012] In one possible implementation of the second aspect, the second current mirror module includes an eighteenth transistor, a nineteenth transistor, a twentieth transistor, and a twenty-first transistor; the gate of the eighteenth transistor is connected to the drain of the eighteenth transistor, the gate of the nineteenth transistor, the gate of the twentyth transistor, and the second terminal of the switching module, respectively; the sources of the eighteenth transistor, the nineteenth transistor, and the twenty-first transistor receive a second voltage from a third power supply domain, respectively; the source of the twentyth transistor is connected to the drain of the twenty-first transistor; the gate of the twenty-first transistor is connected to the fourth terminal of the logic module; and the drain of the nineteenth transistor is connected to the drain of the twentyth transistor and the first terminal of the logic module, respectively.

[0013] In one possible implementation of the second aspect, the logic module includes a fifth inverter, a sixth inverter, a seventh inverter, an eighth inverter, a second NAND gate, and a twenty-second transistor; the input terminal of the sixth inverter serves as the first terminal of the logic module, connected to the output terminal of the fifth inverter, the first input terminal of the second NAND gate, and the second terminal of the second current mirror module; the output terminal of the sixth inverter serves as the second terminal of the logic module, connected to the input terminals of the seventh inverter, the fifth inverter, and the first current mirror module; the output terminal of the seventh inverter serves as the third terminal of the logic module, connected to the input terminal of the eighth inverter, the second input terminal of the second NAND gate, the drain of the twenty-second transistor, and the third terminal of the first current mirror module; the gate of the twenty-second transistor is connected to the output terminal of the second NAND gate; the source of the twenty-second transistor receives a first voltage from a third power supply domain; the output terminal of the eighth inverter serves as the fourth terminal of the logic module, connected to the third terminal of the second current mirror module; and the ground terminals of the sixth and seventh inverters respectively receive a second voltage from the third power supply domain.

[0014] Thirdly, embodiments of this application provide a power supply chip, including the level conversion circuit described in any one of the first aspects or the level conversion circuit described in any one of the second aspects.

[0015] Fourthly, embodiments of this application provide an electronic device including the power chip described in the third aspect.

[0016] The beneficial effects of the embodiments in this application compared with the prior art are: This application provides a level conversion circuit, including a switch module, a first current mirror module, a second current mirror module, and a logic module. A first terminal of the switch module is connected to a first terminal of the first current mirror module, a second terminal of the switch module is connected to a first terminal of the second current mirror module, a first terminal of the logic module is connected to a second terminal of the first current mirror module, a second terminal of the logic module is connected to a second terminal of the second current mirror module, a third terminal of the logic module is connected to a third terminal of the second current mirror module, and a fourth terminal of the logic module is connected to a third terminal of the first current mirror module. The control terminal of the switch module is used to receive an input signal from a first power domain.

[0017] When the input signal becomes high, the switching module outputs a first signal to the first current mirror module to start it up, and outputs a second signal to the logic module. The logic module then uses the second signal to convert its output signal and its inverted output signal to the first voltage of the second power domain and the second voltage of the second power domain, respectively. The first current mirror module uses the inverted output signal to keep the second signal stable. When the input signal becomes low, the switching module outputs a third signal to the second current mirror module to start it up, and outputs a fourth signal to the logic module. The logic module uses the fourth signal to convert its output signal and its inverted output signal to the second voltage of the second power domain and the first voltage of the second power domain, respectively. The second current mirror module uses the output signal to keep the fourth signal stable. This completes the conversion from the input signal of the first power domain to the output signal of the second power domain.

[0018] Compared to the slow switching speed of existing solutions using high-voltage and low-voltage transistors as current comparison structures, this application improves the switching speed by setting up a first current mirror module and a second current mirror module composed of low-voltage transistors to compare currents with low-voltage transistors in the logic module (i.e., all devices involved in the current comparison are low-voltage transistors). This effectively reduces the parasitic capacitance at critical nodes (i.e., the common terminal of the first terminal of the switching module and the first terminal of the first current mirror module, and the common terminal of the second terminal of the switching module and the first terminal of the second current mirror module). Simultaneously, under different output states, the signals output from the logic module control the first and second current mirror modules respectively, thereby increasing the pull-up capability of the second and fourth signals and ensuring that critical nodes do not erroneously flip due to disturbances. Therefore, the level conversion circuit provided in this application solves the problems of slow switching speed and erroneous flipping in existing solutions.

[0019] It is understood that the beneficial effects of the second to fourth aspects mentioned above can be found in the relevant descriptions in the first aspect mentioned above, and will not be repeated here. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a circuit connection diagram of an existing level conversion circuit; Figure 2 This is a schematic diagram of a level conversion circuit provided in an embodiment of this application; Figure 3This is a circuit connection diagram of a level conversion circuit provided in an embodiment of this application; Figure 4 This is a schematic diagram of a level conversion circuit provided in another embodiment of this application; Figure 5 This is a circuit connection diagram of a level conversion circuit provided in another embodiment of this application.

[0022] In the diagram: 10, Level conversion circuit; 101, Switch module; 102, First current mirror module; 103, Second current mirror module; 104, Logic module. Detailed Implementation

[0023] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0024] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.

[0025] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0026] As used in this application specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if [the described condition or event] is detected" may be interpreted, depending on the context, as "once determined," "in response to determination," "once [the described condition or event] is detected," or "in response to detection of [the described condition or event]."

[0027] Furthermore, in the description of this application and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0028] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0029] The structure of existing level conversion circuits is as follows: Figure 1 As shown, its working principle is as follows: the input signal Data_in serves as the gate signal for the high-voltage transistors ML1 and ML2 in the low-voltage domain, controlling their on / off states. This, in turn, controls the on / off states of the low-voltage transistors ML5 and ML6 in the high-voltage domain. The high-voltage transistors ML3 and ML4 are used to clamp nodes A and B. The on / off states of the low-voltage transistors ML5 and ML6 in the high-voltage domain control whether node A is in VGH or VGH_SUB5, thus determining whether the output signal Data_out is in VGH or VGH_SUB5. This completes the conversion from the input signal Data_in (VDD to DGND low-voltage domain) to the output signal Data_out (VGH to VGH_SUB5 high-voltage domain), where VGH_SUB5 = VGH - 5V.

[0030] When the input signal Data_in is high (i.e., Data_in = VDD), ML1 is turned on and ML2 is turned off. Node C is pulled to DGND by ML1. Node C pulls node B to VGH_SUB5 + Vth3 (i.e., the turn-on threshold voltage of ML3), thereby turning on ML6. The turn-on of ML6 pulls node A high to VGH. Then, after passing through two stages of inverters, the output signal Data_out is pulled high to VGH, thus completing the conversion from VDD in the low voltage domain to VGH in the high voltage domain. At the same time, node A pulls node D high to VGH_SUB5 + Vth4 (i.e., the turn-on threshold voltage of ML4).

[0031] When the input signal Data_in is low (i.e., Data_in=DGND), the same principle pulls the output signal Data_out low to VGH_SUB5, thus completing the conversion from DGND in the low-voltage domain to VGH_SUB5 in the high-voltage domain.

[0032] However, existing technologies have the following problems in practice: First, when the input signal Data_in is high, node C is pulled low, which in turn pulls node B low. However, ML5 is actually conducting, pulling node B up. This requires ML1 to have a stronger pull-down capability than ML5, thus requiring ML1 to have a larger area. Since ML1 and ML3 are both high-voltage transistors, the parasitic capacitance at node C is very large, resulting in a slow switching speed at node C. Similarly, the parasitic capacitance at node D is also very large, and its switching speed is also very slow. Second, there is a large parasitic capacitance between the SUB (Substrate) and DRAIN (Drain) of the high-voltage transistor. When SUB jitters, this jitter is transmitted to the drains of ML1 and ML2, i.e., nodes C and D. If the disturbances at nodes C and D are asymmetrical, it may cause node A to flip incorrectly, thus causing the output signal Data_out to flip incorrectly.

[0033] To address the aforementioned issues, this application provides a level conversion circuit. Compared to the slow conversion speed of existing solutions using high-voltage and low-voltage transistors as current comparison structures, this application effectively reduces parasitic capacitance at critical nodes (i.e., the common terminal of the first terminal of the switching module and the first terminal of the first current mirror module, and the common terminal of the second terminal of the switching module and the first terminal of the second current mirror module) by setting a first current mirror module composed of low-voltage transistors and comparing it with the low-voltage transistors in the logic module (i.e., all devices involved in the current comparison are low-voltage transistors). This improves the conversion speed. Simultaneously, under different output states, the signals output by the logic module control the first and second current mirror modules respectively, thereby increasing the pull-up capability of the second and fourth signals and ensuring that critical nodes do not erroneously flip due to disturbances.

[0034] To illustrate the technical solution described in this application, specific embodiments are provided below.

[0035] Figure 2 A schematic diagram of a level conversion circuit according to an embodiment of this application is shown. Figure 2As shown, the level conversion circuit 10 includes a switch module 101, a first current mirror module 102, a second current mirror module 103, and a logic module 104. The first terminal of the switch module 101 is connected to the first terminal of the first current mirror module 102, the second terminal of the switch module 101 is connected to the first terminal of the second current mirror module 103, the first terminal P1 of the logic module 104 is connected to the second terminal of the first current mirror module 102, the second terminal P2 of the logic module 104 is connected to the second terminal of the second current mirror module 103, the third terminal P3 of the logic module 104 is connected to the third terminal of the second current mirror module 103, and the fourth terminal P4 of the logic module 104 is connected to the third terminal of the first current mirror module 102. The control terminal of the switch module 101 is used to receive the first power domain input signal Data_in, wherein the first power domain is a low-voltage domain.

[0036] Specifically, when the input signal Data_in goes high, the switch module 101 outputs a first signal to the first current mirror module 102 to start the first current mirror module 102, and outputs a second signal LatchA1 to the logic module 104. In this embodiment, the first signal is a pull-down signal, and the second signal LatchA1 is the first voltage VGH of the second power domain. At this time, the second current mirror module 103 is not started. The logic module 104 is used to change its output signal Data_out and its inverted output signal Data_out_n to the first voltage VGH and the second voltage VGH_SUB5 of the second power domain, respectively, according to the second signal LatchA1, where the second power domain is a high-voltage domain. The first current mirror module 102 is used to keep the second signal LatchA1 stable according to the inverted output signal Data_out_n. In this embodiment, the first current mirror module 102 increases the pull-up capability of the second signal LatchA1 according to the inverted output signal Data_out_n, thereby keeping the second signal LatchA1 stable.

[0037] When the input signal Data_in goes low, the switch module 101 outputs a third signal to the second current mirror module 103 to start the second current mirror module 103, and outputs a fourth signal LatchB1 to the logic module 104. In this embodiment, the third signal is a pull-down signal, and the fourth signal LatchB1 is the first voltage VGH of the second power domain. At this time, the first current mirror module 102 is not started. The logic module 104 is used to change its output signal Data_out and its inverted output signal Data_out_n to the second voltage VGH_SUB5 of the second power domain and the first voltage VGH of the second power domain, respectively, according to the fourth signal LatchB1. The second current mirror module 103 is used to keep the fourth signal LatchB1 stable according to the output signal Data_out. In this embodiment, the second current mirror module 103 increases the pull-up capability of the fourth signal LatchB1 according to the output signal Data_out, thereby keeping the fourth signal LatchB1 stable. This completes the conversion from the input signal Data_in in the low-voltage domain to the output signal Data_out in the high-voltage domain.

[0038] Compared to the slow switching speed of existing solutions using high-voltage and low-voltage transistors as current comparison structures, this application improves the switching speed by setting a first current mirror module 102 and a second current mirror module 103 composed of low-voltage transistors to compare currents with the low-voltage transistors in the logic module 104 (i.e., all devices involved in the current comparison are low-voltage transistors). This effectively reduces the parasitic capacitance at critical nodes (i.e., the common terminal of the first terminal of the first end of the switching module 101 and the first end of the first current mirror module 102, and the common terminal of the second end of the switching module 101 and the first end of the second current mirror module 103). Simultaneously, under different output states, the signals output by the logic module 104 control the first current mirror module 102 and the second current mirror module 103 respectively, thereby increasing the pull-up capability of the second signal LatchA1 and the fourth signal LatchB1, ensuring that critical nodes do not erroneously flip due to disturbances. Therefore, the level conversion circuit 10 provided by this application solves the problems of slow switching speed and erroneous flipping in existing solutions.

[0039] In one embodiment of this application, such as Figure 3As shown, the switching module 101 includes a first transistor M1, a second transistor M2, a first pulse generator PG1, a second pulse generator PG2, a first resistor R1, and a second resistor R2. The input terminals of the first pulse generator PG1 and the second pulse generator PG2 are used to receive the input signal Data_in, respectively. The power supply terminals of the first pulse generator PG1 and the second pulse generator PG2 receive the first power domain voltage VDD, respectively. The output terminal of the first pulse generator PG1 is connected to the gate of the first transistor M1. The drain of the first transistor M1 is connected to the first end of the first resistor R1. The second end of the first resistor R1 is connected to the first end of the second current mirror module 103. The output terminal of the second pulse generator PG2 is connected to the gate of the second transistor M2. The drain of the second transistor M2 is connected to the first end of the second resistor R2. The second end of the second resistor R2 is connected to the first end of the first current mirror module 102. The ground terminal of the first pulse generator PG1, the source of the first transistor M1, the source of the second transistor M2, and the ground terminal of the second pulse generator PG2 are connected to the first power domain ground DGND, respectively.

[0040] Specifically, the first pulse generator PG1 is used to generate a positive pulse on the falling edge of the input signal Data_in. The second pulse generator PG2 is used to generate a positive pulse on the rising edge of the input signal Data_in.

[0041] When the input signal Data_in goes high, the second transistor M2 turns on according to the pulse output by the second pulse generator PG2 and pulls node E low through the second resistor R2, that is, outputs the first signal to the first current mirror module 102.

[0042] When the input signal Data_in goes low, the first transistor M1 turns on according to the pulse output by the first pulse generator PG1 and pulls node F low through the first resistor R1, that is, outputs the third signal to the second current mirror module 103.

[0043] In one embodiment of this application, such as Figure 3 As shown, the first current mirror module 102 includes a third transistor M3, a fourth transistor M4, a fifth transistor M5, and a sixth transistor M6. The gate of the fifth transistor M5 is connected to the gate of the sixth transistor M6, the drain of the sixth transistor M6, the gate of the fourth transistor M4, and the first terminal of the switching module 101. The sources of the fifth transistor M5, the sixth transistor M6, and the third transistor M3 receive the first voltage VGH of the second power supply domain. The gate of the third transistor M3 is connected to the fourth terminal P4 of the logic module 104. The drain of the third transistor M3 is connected to the source of the fourth transistor M4. The drain of the fourth transistor M4 is connected to the drain of the fifth transistor M5 and the first terminal P1 of the logic module 104.

[0044] Specifically, when the input signal Data_in goes high, the second transistor M2 turns on according to the pulse output by the second pulse generator PG2, and pulls node E low through the second resistor R2, causing the sixth transistor M6 to turn on. The sixth transistor M6 operates in the saturation region, which means the first current mirror module 102 starts up. The fifth transistor M5 mirrors the current of the sixth transistor M6, and the fifth transistor M5 pulls the second signal LatchA1 high to the first voltage VGH of the second power supply domain.

[0045] When the input signal Data_in goes low, the first current mirror module 102 does not start.

[0046] In one embodiment of this application, such as Figure 3 As shown, the second current mirror module 103 includes a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, and a tenth transistor M10. The gate of the ninth transistor M9 is connected to the gate of the seventh transistor M7, the gate of the eighth transistor M8, the drain of the eighth transistor M8, and the second terminal of the switching module 101. The sources of the eighth transistor M8, the seventh transistor M7, and the tenth transistor M10 receive the first voltage VGH of the second power supply domain. The gate of the tenth transistor M10 is connected to the third terminal P3 of the logic module 104. The drain of the tenth transistor M10 is connected to the source of the ninth transistor M9. The drain of the ninth transistor M9 is connected to the drain of the seventh transistor M7 and the second terminal P2 of the logic module 104.

[0047] Specifically, the second current mirror module 103 does not start when the input signal Data_in goes high.

[0048] When the input signal Data_in goes low, the first transistor M1 turns on according to the pulse output by the first pulse generator PG1, and pulls node F low through the first resistor R1, causing the eighth transistor M8 to turn on. The eighth transistor M8 operates in the saturation region, which means the second current mirror module 103 starts. The seventh transistor M7 mirrors the current of the eighth transistor M8, and the seventh transistor M7 pulls the fourth signal LatchB1 high to the first voltage VGH of the second power domain.

[0049] In one embodiment of this application, such as Figure 3As shown, logic module 104 includes a first inverter inv1, a second inverter inv2, a third inverter inv3, a fourth inverter inv4, a first NAND gate nand1, and an eleventh transistor M11. The input terminal of the first inverter inv1 serves as the first terminal P1 of logic module 104, and is connected to the output terminal of the second inverter inv2, the first input terminal of the first NAND gate nand1, and the second terminal of the first current mirror module 102. The output terminal of the first inverter inv1 serves as the second terminal P2 of logic module 104, and is connected to the input terminal of the second inverter inv2, the input terminal of the third inverter inv3, and the second terminal of the second current mirror module 103. The third inverter inv3... The output terminal P3 of the logic module 104 is connected to the drain of the eleventh transistor M11, the input of the fourth inverter inv4, the second input of the first NAND gate nand1, and the third terminal of the second current mirror module 103. The output terminal of the first NAND gate nand1 is connected to the gate of the eleventh transistor M11. The source of the eleventh transistor M11 receives the first voltage VGH of the second power domain. The output terminal of the fourth inverter inv4 is connected to the third terminal of the first current mirror module 102 as the fourth terminal P4 of the logic module 104. The ground terminals of the first inverter inv1 and the third inverter inv3 receive the second voltage VGH_SUB5 of the second power domain.

[0050] Specifically, when the input signal Data_in goes high, the second current mirror module 103 is not activated. The second transistor M2 is activated by the pulse output from the second pulse generator PG2, and pulls node E low through the second resistor R2, causing the sixth transistor M6 to activate. The sixth transistor M6 operates in the saturation region, which means the first current mirror module 102 is activated. The fifth transistor M5 mirrors the current of the sixth transistor M6. The fifth transistor M5 pulls the second signal LatchA1 high to the first voltage VGH of the second power domain. After passing through the first inverter inv1 and the third inverter inv3, the second signal LatchA1 pulls the output signal Data_out high to the first voltage VGH of the second power domain. After passing through the fourth inverter inv4, the output inverted signal Data_out_n is pulled low to the second voltage VGH_SUB5 of the second power domain. At this time, the third transistor M3 is turned on according to the output inverted signal Data_out_n, thereby improving the pull-up capability of the second signal LatchA1 and preventing erroneous switching caused by the SUB disturbance being transmitted to node E through the conduction of the second transistor M2. Since only the second transistor M2 is a high-voltage transistor, the sixth transistor M6 only acts as a current mirror, not as a pull-up for current comparison. The actual pull-up and pull-down for comparison are the fifth transistor M5 and the NMOS transistor in the first inverter inv1, both of which are low-voltage MOS transistors. Therefore, the parasitic capacitance at node E is reduced, improving the switching speed.

[0051] When the input signal Data_in goes low, the first current mirror module 102 is not activated. The first transistor M1 is turned on according to the pulse output by the first pulse generator PG1, and pulls node F low through the first resistor R1, turning on the eighth transistor M8. The eighth transistor M8 operates in the saturation region, which means the second current mirror module 103 is activated. The seventh transistor M7 mirrors the current of the eighth transistor M8. The seventh transistor M7 pulls the fourth signal LatchB1 high to the first voltage VGH of the second power domain. After passing through the third inverter inv3, the fourth signal LatchB1 pulls the output signal Data_out low to the second voltage VGH_SUB5 of the second power domain. After passing through the fourth inverter inv4, the output inverted signal Data_out_n is pulled high to the first voltage VGH of the second power domain. At this time, the tenth transistor M10 is turned on according to the output signal Data_out, thereby improving the pull-up capability of the fourth signal LatchB1 and preventing erroneous flipping caused by the SUB disturbance being transmitted to node F through the conduction of the first transistor M1. Because only the first transistor M1 is a high-voltage transistor, and the eighth transistor M8 only acts as a current mirror, not as a pull-up for current comparison, the actual pull-up and pull-up are the seventh transistor M7 and the NMOS transistor in the third inverter inv3, both of which are low-voltage MOS transistors. Therefore, reducing the parasitic capacitance at node F improves the conversion speed. The eleventh transistor M11 serves as a debouncing transistor. Nodes E and F are critical nodes, and the second signal LatchA1 and the fourth signal LatchB1 are critical signals. This completes the conversion from the low-voltage domain input signal Data_in to the high-voltage domain output signal Data_out.

[0052] Figure 4 A schematic diagram of a level conversion circuit according to another embodiment of this application is shown. Figure 4 As shown, the level conversion circuit 10 includes a switch module 101, a first current mirror module 102, a second current mirror module 103, and a logic module 104. The first terminal of the switch module 101 is connected to the first terminal of the first current mirror module 102, the second terminal of the switch module 101 is connected to the first terminal of the second current mirror module 103, the first terminal P1 of the logic module 104 is connected to the second terminal of the second current mirror module 103, the second terminal P2 of the logic module 104 is connected to the second terminal of the first current mirror module 102, the third terminal P3 of the logic module 104 is connected to the third terminal of the first current mirror module 102, and the fourth terminal P4 of the logic module 104 is connected to the third terminal of the second current mirror module 103. The control terminal of the switch module 101 is used to receive the input signal Data_in from the first power domain.

[0053] Specifically, when the input signal Data_in goes high, the switch module 101 outputs a fifth signal to the first current mirror module 102 to start the first current mirror module 102, and outputs a sixth signal LatchB2 to the logic module 104. In this embodiment, the fifth signal is a pull-up signal, and the sixth signal LatchB2 is the second voltage VGL of the third power domain. At this time, the second current mirror module 103 is not started. The logic module 104 is used to change its output signal Data_out and its inverted output signal Data_out_n to the first voltage VGL_PLUS5 and the second voltage VGL of the third power domain, respectively, according to the sixth signal LatchB2. The third power domain is a negative voltage domain, and VGL_PLUS5 = VGL + 5. The first current mirror module 102 is used to keep the sixth signal LatchB2 stable according to the output signal Data_out. In this embodiment, the first current mirror module 102 is used to increase the pull-down capability of the sixth signal LatchB2 according to the output signal Data_out, thereby keeping the sixth signal LatchB2 stable.

[0054] When the input signal Data_in goes low, the switch module 101 outputs a seventh signal to the second current mirror module 103, enabling the second current mirror module 103 to start, and outputs an eighth signal LatchA2 to the logic module 104. In this embodiment, the seventh signal is a pull-up signal, and the eighth signal LatchA2 is the second voltage VGL of the third power domain. At this time, the first current mirror module 102 is not started. The logic module 104 is configured to change its output signal Data_out and its inverted output signal Data_out_n to the second voltage VGL and the first voltage VGL_PLUS5 of the third power domain, respectively, based on the eighth signal LatchA2. The second current mirror module 103 is configured to keep the eighth signal LatchA2 stable based on the inverted output signal Data_out_n. In this embodiment, the second current mirror module 103 is configured to increase the pull-down capability of the eighth signal LatchA2 based on the inverted output signal Data_out_n, thereby keeping the eighth signal LatchA2 stable. This completes the conversion from the input signal Data_in in the low-voltage domain to the output signal Data_out in the negative-voltage domain.

[0055] Compared to the slow switching speed of existing solutions using high-voltage and low-voltage transistors as current comparison structures, this application improves the switching speed by setting a first current mirror module 102 and a second current mirror module 103 composed of low-voltage transistors to compare currents with the low-voltage transistors in the logic module 104 (i.e., all devices involved in the current comparison are low-voltage transistors). This effectively reduces the parasitic capacitance at critical nodes (i.e., the common terminal of the first terminal of the first end of the switching module 101 and the first end of the first current mirror module 102, and the common terminal of the second end of the switching module 101 and the first end of the second current mirror module 103). Simultaneously, under different output states, the signals output by the logic module 104 control the first current mirror module 102 and the second current mirror module 103 to correspondingly increase the pull-down capability of the sixth signal LatchB2 and the eighth signal LatchA2, ensuring that critical nodes do not erroneously flip due to disturbances. Therefore, the level conversion circuit 10 provided by this application solves the problems of slow switching speed and erroneous flipping in existing solutions.

[0056] In one embodiment of this application, such as Figure 5 As shown, the switching module 101 includes a twelfth transistor M12, a thirteenth transistor M13, a third pulse generator PG3, a fourth pulse generator PG4, a third resistor R3, and a fourth resistor R4. The input terminals of the third pulse generator PG3 and the fourth pulse generator PG4 are used to receive the input signal Data_in, respectively. The power supply terminals of the third pulse generator PG3 and the fourth pulse generator PG4, the source of the twelfth transistor M12, and the source of the thirteenth transistor M13 respectively receive the power supply voltage VDD of the first power domain. The ground terminal and the ground terminal of the fourth pulse generator PG4 are respectively connected to the ground DGND of the first power domain. The output terminal of the third pulse generator PG3 is connected to the gate of the twelfth transistor M12. The output terminal of the fourth pulse generator PG4 is connected to the gate of the thirteenth transistor M13. The drain of the twelfth transistor M12 is connected to the first end of the third resistor R3. The second end of the third resistor R3 is connected to the first end of the second current mirror module 103. The drain of the thirteenth transistor M13 is connected to the first end of the fourth resistor R4. The second end of the fourth resistor R4 is connected to the first end of the first current mirror module 102.

[0057] Specifically, the third pulse generator PG3 is used to generate a negative pulse on the falling edge of the input signal Data_in. The fourth pulse generator PG4 is used to generate a negative pulse on the rising edge of the input signal Data_in.

[0058] When the input signal Data_in goes high, the thirteenth transistor M13 turns on according to the pulse output by the fourth pulse generator PG4, and pulls node E high through the fourth resistor R4, that is, outputs the fifth signal to the first current mirror module 102.

[0059] When the input signal Data_in goes low, the twelfth transistor M12 turns on according to the pulse output by the third pulse generator PG3, and pulls node F high through the third resistor R3, that is, outputs the seventh signal to the second current mirror module 103.

[0060] In one embodiment of this application, such as Figure 5 As shown, the first current mirror module 102 includes a fourteenth transistor M14, a fifteenth transistor M15, a sixteenth transistor M16, and a seventeenth transistor M17. The gate of the fourteenth transistor M14 is connected to the drain of the fourteenth transistor M14, the gate of the fifteenth transistor M15, the gate of the sixteenth transistor M16, and the first terminal of the switching module 101. The sources of the fourteenth transistor M14, the fifteenth transistor M15, and the seventeenth transistor M17 receive the second voltage VGL of the third power supply domain. The source of the sixteenth transistor M16 is connected to the drain of the seventeenth transistor M17. The gate of the seventeenth transistor M17 is connected to the third terminal P3 of the logic module 104. The drain of the sixteenth transistor M16 is connected to the drain of the fifteenth transistor M15 and the second terminal P2 of the logic module 104.

[0061] Specifically, when the input signal Data_in goes high, the thirteenth transistor M13 turns on according to the pulse output by the fourth pulse generator PG4, and pulls node E high through the fourth resistor R4. The fourteenth transistor M14 turns on and operates in the saturation region, that is, the first current mirror module 102 starts. The fifteenth transistor M15 mirrors the current of the fourteenth transistor M14. The fifteenth transistor M15 pulls down the sixth signal LatchB2 to the second voltage VGL of the third power domain.

[0062] When the input signal Data_in goes low, the first current mirror module 102 does not start.

[0063] In one embodiment of this application, such as Figure 5As shown, the second current mirror module 103 includes an eighteenth transistor M18, a nineteenth transistor M19, a twentieth transistor M20, and a twenty-first transistor M21. The gate of the eighteenth transistor M18 is connected to the drain of the eighteenth transistor M18, the gate of the nineteenth transistor M19, the gate of the twentieth transistor M20, and the second terminal of the switching module 101. The sources of the eighteenth transistor M18, the nineteenth transistor M19, and the twenty-first transistor M21 receive the second voltage VGL of the third power supply domain. The source of the twentieth transistor M20 is connected to the drain of the twenty-first transistor M21. The gate of the twenty-first transistor M21 is connected to the fourth terminal P4 of the logic module 104. The drain of the nineteenth transistor M19 is connected to the drain of the twentieth transistor M20 and the first terminal P1 of the logic module 104.

[0064] Specifically, the second current mirror module 103 does not start when the input signal Data_in goes high.

[0065] When the input signal Data_in goes low, the twelfth transistor M12 turns on according to the pulse output by the third pulse generator PG3, and pulls node F high through the third resistor R3. The eighteenth transistor M18 turns on and operates in the saturation region, which means the second current mirror module 103 starts. The nineteenth transistor M19 mirrors the current of the eighteenth transistor M18, pulling the eighth signal LatchA2 low to the second voltage VGL of the third power domain.

[0066] In one embodiment of this application, such as Figure 5As shown, logic module 104 includes a fifth inverter inv5, a sixth inverter inv6, a seventh inverter inv7, an eighth inverter inv8, a second NAND gate nand2, and a twenty-second transistor M22. The input terminal of the sixth inverter inv6 serves as the first terminal P1 of logic module 104, connected to the output terminal of the fifth inverter inv5, the first input terminal of the second NAND gate nand2, and the second terminal of the second current mirror module 103. The output terminal of the sixth inverter inv6 serves as the second terminal P2 of logic module 104, connected to the input terminal of the seventh inverter inv7, the input terminal of the fifth inverter inv5, and the second terminal of the first current mirror module 102. The seventh inverter inv7... The output terminal P3, which serves as the third terminal of logic module 104, is connected to the input terminal of the eighth inverter inv8, the second input terminal of the second NAND gate nand2, the drain of the twenty-second transistor M22, and the third terminal of the first current mirror module 102. The gate of the twenty-second transistor M22 is connected to the output terminal of the second NAND gate nand2. The source of the twenty-second transistor M22 receives the first voltage VGL_PLUS5 of the third power supply domain. The output terminal P4, which serves as the fourth terminal of logic module 104, is connected to the third terminal of the second current mirror module 103. The ground terminals of the sixth inverter inv6 and the seventh inverter inv7 receive the second voltage VGL of the third power supply domain, respectively.

[0067] Specifically, when the input signal Data_in goes high, the second current mirror module 103 is not activated. The thirteenth transistor M13 is activated by the pulse output from the fourth pulse generator PG4, and pulls node E high through the fourth resistor R4. The fourteenth transistor M14 is activated and operates in the saturation region, meaning the first current mirror module 102 is activated. The fifteenth transistor M15 mirrors the current of the fourteenth transistor M14, and pulls the sixth signal LatchB2 down to the second voltage VGL of the third power domain. The sixth signal LatchB2, after passing through the seventh inverter inv7, pulls the output signal Data_out high to the first voltage VGL_PLUS5 of the third power domain, and then, after passing through the eighth inverter inv8, pulls the inverted output signal Data_out_n low to the second voltage VGL of the third power domain. At this time, the seventeenth transistor M17 is turned on according to the output signal Data_out to improve the pull-down capability of the sixth signal LatchB2 and prevent false flipping caused by SUB disturbances being transmitted to node E through the conduction of the thirteenth transistor M13. Since only the thirteenth transistor M13 is a high-voltage transistor, the fourteenth transistor M14 only acts as a current mirror, not as a pull-up / pull-down for current comparison. The actual pull-up / pull-down for comparison is the fifteenth transistor M15 and the NMOS transistor in the seventh inverter inv7, both of which are low-voltage MOS transistors. Therefore, the parasitic capacitance at node E is reduced, improving the switching speed.

[0068] When the input signal Data_in goes low, the first current mirror module 102 is not activated. The twelfth transistor M12 is activated by the pulse output from the third pulse generator PG3, and pulls node F high through the third resistor R3. The eighteenth transistor M18 is activated and operates in the saturation region, which means the second current mirror module 103 is activated. The nineteenth transistor M19 mirrors the current of the eighteenth transistor M18, pulling the eighth signal LatchA2 low to the second voltage VGL of the third power domain. After passing through the sixth inverter inv6 and the seventh inverter inv7, it pulls the output signal Data_out low to the second voltage VGL of the third power domain. After passing through the eighth inverter inv8, it pulls the output inverted signal Data_out_n high to the first voltage VGL_PLUS5 of the third power domain. At this time, the twenty-first transistor M21 is activated by the output inverted signal Data_out_n to improve the pull-down capability of the eighth signal LatchA2 and prevent erroneous flipping caused by SUB disturbances being transmitted to node F through the activation of the twelfth transistor M12. Because only the twelfth transistor M12 is a high-voltage transistor, and the eighteenth transistor M18 only acts as a current mirror, not as a pull-up / pull-down for current comparison, the actual pull-up / pull-down for comparison is the nineteenth transistor M19 and the NMOS transistor in the sixth inverter inv6, both of which are low-voltage MOS transistors. Therefore, reducing the parasitic capacitance at node F improves the conversion speed. The twenty-second transistor M22 serves as a debouncing mechanism. Nodes E and F are critical nodes, and the sixth signal LatchB2 and the eighth signal LatchA2 are critical signals. This completes the conversion from the low-voltage domain input signal Data_in to the negative-voltage domain output signal Data_out.

[0069] In summary, this application changes the circuit structure in the existing scheme that uses high-voltage and low-voltage transistors as current comparisons to a circuit structure that uses low-voltage transistors as current comparisons, thereby improving the conversion speed; at the same time, it achieves anti-interference by further enhancing the driving capability of key signals under different output states.

[0070] This application can improve the switching speed and anti-interference capability of the level conversion circuit 10, thereby improving its reliability. The circuit can be directly integrated into the power chip, thereby reducing the number of external components, simplifying the peripheral design, and reducing production costs.

[0071] This application also provides a power supply chip, including the level conversion circuit described above. Since the power supply chip provided in this application adopts all the technical solutions of all the above embodiments, it possesses at least all the beneficial effects brought about by the technical solutions of the above embodiments, and will not be elaborated further here.

[0072] This application also provides an electronic device including the power chip described above. Since the electronic device provided in this application adopts all the technical solutions of all the above embodiments, it possesses at least all the beneficial effects brought about by the technical solutions of the above embodiments, which will not be elaborated upon here.

[0073] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0074] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A level conversion circuit, characterized in that, It includes a switch module, a first current mirror module, a second current mirror module, and a logic module; the first terminal of the switch module is connected to the first terminal of the first current mirror module, the second terminal of the switch module is connected to the first terminal of the second current mirror module, the first terminal of the logic module is connected to the second terminal of the first current mirror module, the second terminal of the logic module is connected to the second terminal of the second current mirror module, the third terminal of the logic module is connected to the third terminal of the second current mirror module, and the fourth terminal of the logic module is connected to the third terminal of the first current mirror module; the control terminal of the switch module is used to receive input signals from a first power domain. When the input signal becomes high, the switching module outputs a first signal to the first current mirror module to activate it, and outputs a second signal to the logic module. The logic module then uses the second signal to change its output signal and its inverted output signal to the first voltage of the second power domain and the second voltage of the second power domain, respectively. The first current mirror module uses the inverted output signal to stabilize the second signal. When the input signal becomes low, the switching module outputs a third signal to the second current mirror module to activate it, and outputs a fourth signal to the logic module. The logic module uses the fourth signal to change its output signal and its inverted output signal to the second voltage of the second power domain and the first voltage of the second power domain, respectively. The second current mirror module uses the fourth output signal to stabilize the fourth signal.

2. The level conversion circuit according to claim 1, characterized in that, The switching module includes a first transistor, a second transistor, a first pulse generator, a second pulse generator, a first resistor, and a second resistor. The input terminals of the first pulse generator and the second pulse generator are respectively used to receive input signals. The power supply terminals of the first pulse generator and the second pulse generator respectively receive the power supply voltage of a first power domain. The output terminal of the first pulse generator is connected to the gate of the first transistor. The drain of the first transistor is connected to the first end of the first resistor. The second end of the first resistor is connected to the first end of the second current mirror module. The output terminal of the second pulse generator is connected to the gate of the second transistor. The drain of the second transistor is connected to the first end of the second resistor. The second end of the second resistor is connected to the first end of the first current mirror module. The ground terminal of the first pulse generator, the source of the first transistor, the source of the second transistor, and the ground terminal of the second pulse generator are respectively connected to the first power domain ground.

3. The level conversion circuit according to claim 1 or 2, characterized in that, The first current mirror module includes a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor; the gate of the fifth transistor is connected to the gate of the sixth transistor, the drain of the sixth transistor, the gate of the fourth transistor, and the first terminal of the switching module, respectively; the source of the fifth transistor, the source of the sixth transistor, and the source of the third transistor receive a first voltage from the second power supply domain, respectively; the gate of the third transistor is connected to the fourth terminal of the logic module; the drain of the third transistor is connected to the source of the fourth transistor; and the drain of the fourth transistor is connected to the drain of the fifth transistor and the first terminal of the logic module, respectively.

4. The level conversion circuit according to claim 1 or 2, characterized in that, The second current mirror module includes a seventh transistor, an eighth transistor, a ninth transistor, and a tenth transistor; the gate of the ninth transistor is connected to the gate of the seventh transistor, the gate of the eighth transistor, the drain of the eighth transistor, and the second terminal of the switching module, respectively; the source of the eighth transistor, the source of the seventh transistor, and the source of the tenth transistor receive a first voltage from the second power supply domain, respectively; the gate of the tenth transistor is connected to the third terminal of the logic module; the drain of the tenth transistor is connected to the source of the ninth transistor; and the drain of the ninth transistor is connected to the drain of the seventh transistor and the second terminal of the logic module, respectively.

5. The level conversion circuit according to claim 1 or 2, characterized in that, The logic module includes a first inverter, a second inverter, a third inverter, a fourth inverter, a first NAND gate, and an eleventh transistor. The input terminal of the first inverter serves as the first terminal of the logic module, and is connected to the output terminal of the second inverter, the first input terminal of the first NAND gate, and the second terminal of the first current mirror module. The output terminal of the first inverter serves as the second terminal of the logic module, and is connected to the input terminals of the second inverter, the third inverter, and the second terminal of the second current mirror module. The output terminal of the third inverter serves as the third terminal of the logic module, and is connected to the drain of the eleventh transistor, the input terminal of the fourth inverter, the second input terminal of the first NAND gate, and the third terminal of the second current mirror module. The output terminal of the first NAND gate is connected to the gate of the eleventh transistor. The source of the eleventh transistor receives a first voltage from a second power supply domain. The output terminal of the fourth inverter serves as the fourth terminal of the logic module and is connected to the third terminal of the first current mirror module. The ground terminals of the first inverter and the third inverter receive a second voltage from the second power supply domain.

6. A level conversion circuit, characterized in that, It includes a switch module, a first current mirror module, a second current mirror module, and a logic module; the first terminal of the switch module is connected to the first terminal of the first current mirror module, the second terminal of the switch module is connected to the first terminal of the second current mirror module, the first terminal of the logic module is connected to the second terminal of the second current mirror module, the second terminal of the logic module is connected to the second terminal of the first current mirror module, the third terminal of the logic module is connected to the third terminal of the first current mirror module, and the fourth terminal of the logic module is connected to the third terminal of the second current mirror module; the control terminal of the switch module is used to receive input signals from a first power domain. When the input signal becomes high, the switching module outputs a fifth signal to the first current mirror module to activate it, and outputs a sixth signal to the logic module. The logic module then uses the sixth signal to change its output signal and its inverted output signal to the first voltage and the second voltage of the third power domain, respectively. The first current mirror module uses the output signal to keep the sixth signal stable. When the input signal becomes low, the switching module outputs a seventh signal to the second current mirror module to activate it, and outputs an eighth signal to the logic module. The logic module uses the eighth signal to change its output signal and its inverted output signal to the second voltage and the first voltage of the third power domain, respectively. The second current mirror module uses the inverted output signal to keep the eighth signal stable.

7. The level conversion circuit according to claim 6, characterized in that, The switching module includes a twelfth transistor, a thirteenth transistor, a third pulse generator, a fourth pulse generator, a third resistor, and a fourth resistor. The input terminals of the third pulse generator and the fourth pulse generator are used to receive input signals. The power supply terminals of the third pulse generator, the fourth pulse generator, the source of the twelfth transistor, and the source of the thirteenth transistor receive the power supply voltage of a first power domain. The ground terminals of the third pulse generator and the fourth pulse generator are connected to the ground of the first power domain. The output terminal of the third pulse generator is connected to the gate of the twelfth transistor, and the output terminal of the fourth pulse generator is connected to the gate of the thirteenth transistor. The drain of the twelfth transistor is connected to the first terminal of the third resistor, the second terminal of the third resistor is connected to the first terminal of the second current mirror module, the drain of the thirteenth transistor is connected to the first terminal of the fourth resistor, and the second terminal of the fourth resistor is connected to the first terminal of the first current mirror module.

8. The level conversion circuit according to claim 6 or 7, characterized in that, The first current mirror module includes a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, and a seventeenth transistor; the gate of the fourteenth transistor is connected to the drain of the fourteenth transistor, the gate of the fifteenth transistor, the gate of the sixteenth transistor, and the first terminal of the switching module, respectively; the sources of the fourteenth transistor, the fifteenth transistor, and the seventeenth transistor receive a second voltage from a third power supply domain, respectively; the source of the sixteenth transistor is connected to the drain of the seventeenth transistor; the gate of the seventeenth transistor is connected to the third terminal of the logic module; and the drain of the sixteenth transistor is connected to the drain of the fifteenth transistor and the second terminal of the logic module, respectively.

9. The level conversion circuit according to claim 6 or 7, characterized in that, The second current mirror module includes an eighteenth transistor, a nineteenth transistor, a twentieth transistor, and a twenty-first transistor; the gate of the eighteenth transistor is connected to the drain of the eighteenth transistor, the gate of the nineteenth transistor, the gate of the twentieth transistor, and the second terminal of the switching module, respectively; the sources of the eighteenth transistor, the nineteenth transistor, and the twenty-first transistor receive the second voltage of the third power domain, respectively; the source of the twentyth transistor is connected to the drain of the twenty-first transistor; the gate of the twenty-first transistor is connected to the fourth terminal of the logic module; and the drain of the nineteenth transistor is connected to the drain of the twentyth transistor and the first terminal of the logic module, respectively.

10. The level conversion circuit according to claim 6 or 7, characterized in that, The logic module includes a fifth inverter, a sixth inverter, a seventh inverter, an eighth inverter, a second NAND gate, and a twenty-second transistor. The input terminal of the sixth inverter serves as the first terminal of the logic module, connected to the output terminal of the fifth inverter, the first input terminal of the second NAND gate, and the second terminal of the second current mirror module. The output terminal of the sixth inverter serves as the second terminal of the logic module, connected to the input terminals of the seventh inverter, the fifth inverter, and the first current mirror module. The output terminal of the seventh inverter serves as the third terminal of the logic module, connected to the input terminal of the eighth inverter, the second input terminal of the second NAND gate, the drain of the twenty-second transistor, and the third terminal of the first current mirror module. The gate of the twenty-second transistor is connected to the output terminal of the second NAND gate. The source of the twenty-second transistor receives a first voltage from a third power supply domain. The output terminal of the eighth inverter serves as the fourth terminal of the logic module, connected to the third terminal of the second current mirror module. The ground terminals of the sixth and seventh inverters respectively receive a second voltage from the third power supply domain.

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