A high-speed cml latch structure

Abstract

The application relates to a high-speed CML latch structure, belonging to the technical field of semiconductors and communications, and the structure comprises: a sensing branch used for sensing an input signal and outputting a sensing signal in a sensing mode; a latch branch used for latching the input signal and outputting a latched signal in a latching mode; a tail current source used for providing an accurate reference current source for a basic current mirror; the basic current mirror is used for providing a fixed first tail current source and a controlled second tail current source for the sensing branch, and providing a fixed first tail current source and a controlled third tail current source for the latch branch; and a dynamic load used for reducing circuit impedance in the sensing mode and increasing circuit impedance in the latching mode, and providing a dynamic load impedance for the circuit. The application effectively controls power consumption while realizing high-speed performance, and can improve the working speed and performance of the circuit without significantly increasing the power consumption.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor and communication technology, and specifically relates to a high-speed CML latch structure. Background Technology

[0002] With the development of semiconductor and communication technologies, there is an increasing demand for higher operating frequencies of integrated circuits, especially radio frequency integrated circuits. Current-mode logic (CML) circuits are high-speed digital logic circuits that use current instead of voltage as the carrier of logic states. Due to their high-speed performance and low latency, CML circuits are widely used in many high-speed circuits, such as frequency dividers, clock recovery circuits, RF front-end modules, mixers, and frequency synthesizers.

[0003] However, since traditional CML circuits rely on current as the logic carrier for operation, the circuit has a constant tail current, resulting in high static power consumption. Furthermore, since the gain of the circuit decreases at high frequencies, a larger current is required to ensure that the subsequent circuits can be driven normally. Therefore, the operating frequency and power consumption of CML circuits are positively correlated, which limits their application in high-speed and low-power scenarios. Summary of the Invention

[0004] Based on the above analysis, the present invention aims to disclose a high-speed CML latch structure that effectively controls power consumption while achieving high-speed performance, making it suitable for high-speed, low-power scenarios.

[0005] This invention discloses a high-speed CML latch structure, comprising: a dynamic load, a sensing branch, a latching branch, a basic current mirror, and a tail current source;

[0006] The sensing branch is used to sense the input signal and output the sensing signal in sensing mode;

[0007] The latch branch is used to latch the input signal and output a latched signal in latch mode.

[0008] Tail current source, used to provide a precise reference current source for the basic current mirror;

[0009] A basic current mirror is used to provide a fixed first tail current source and a controlled second tail current source for the sensing branch, and a fixed first tail current source and a controlled third tail current source for the latching branch.

[0010] In the sensing mode, the second tail current source is turned on and the third tail current source is turned off; in the latching mode, the third tail current source is turned on and the second tail current source is turned off, providing dynamic current bias for the circuit.

[0011] Dynamic load is used to reduce circuit impedance in sensing mode and increase circuit impedance in latching mode, providing dynamic load impedance for the circuit.

[0012] This invention can achieve one of the following beneficial effects:

[0013] Compared with traditional latches, the high-speed CML latch structure disclosed in this invention effectively controls power consumption while achieving high-speed performance through dynamic bias and load control, reasonable configuration of tail current source, and optimization of current source switching control signal. It can improve the operating speed and performance of the circuit without significantly increasing power consumption. Attached Figure Description

[0014] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0015] Figure 1 A block diagram of a high-speed CML latch structure provided for an example of the present invention;

[0016] Figure 2 A schematic diagram of a high-speed CML latch structure circuit provided for an example of the present invention;

[0017] Figure 3 A schematic diagram of a level detection circuit provided for an example of the present invention;

[0018] Figure 4 The output waveform diagram of the CML circuit at the same operating frequency is provided for the example of the present invention;

[0019] Figure 5 The waveform of the highest operating frequency of the improved CML circuit at the same power consumption is provided as an example of the present invention.

[0020] Figure 6 The waveform diagram of the highest operating frequency of a conventional CML circuit at the same power consumption is provided as an example of the present invention. Detailed Implementation

[0021] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0022] First, let's explain the relevant technical terms mentioned in the embodiments:

[0023] Current-mode logic (CML)

[0024] MOS (Metal-Oxide-Semiconductor)

[0025] NMOS (N-channel metal-oxide-semiconductor)

[0026] PMOS (P-channel metal-oxide-semiconductor)

[0027] SVT (Standard Threshold Voltage)

[0028] UMC (United Microelectronics Corporation)

[0029] One embodiment of the present invention discloses a high-speed CML latch structure, such as Figure 1 As shown, it includes: dynamic load, sensing branch, latching branch, basic current mirror and tail current source;

[0030] The sensing branch is used to sense the input signal and output the sensing signal in sensing mode;

[0031] The latch branch is used to latch the input signal and output a latched signal in latch mode.

[0032] Tail current source, used to provide a precise reference current source for the basic current mirror;

[0033] A basic current mirror is used to provide a fixed first tail current source I for the sensing branch. DC and a controlled second tail current source I A This provides a fixed first tail current source and a controlled third tail current source I for the latching branch. B ;

[0034] In the sensing mode, the second tail current source I is connected. A Turn off the third tail current source I B In latching mode, the third tail current source I is connected. B Turn off the second tail current source I A This provides dynamic current bias for the circuit;

[0035] Dynamic load is used to reduce circuit impedance in sensing mode and increase circuit impedance in latching mode, providing dynamic load impedance for the circuit.

[0036] In sensing mode, the first tail current source I DC Second tail current source I A The superposition, combined with the low impedance of the dynamic load, meets the requirements of high-frequency operation, low current, and low impedance in this mode; and by shutting down the third tail current source I... B This reduces the loss of the latch branch;

[0037] In latching mode, the first tail current source I DC and the third tail current source I B The superposition, combined with the high impedance of the dynamic load, meets the requirements of high-frequency operation, high current, and high impedance in this mode; and by shutting down the second tail current source I... A This reduces the loss of the sensing branch.

[0038] like Figure 2 As shown, in a specific circuit structure of this embodiment, the sensing branch includes differential NMOS transistors Mn3 and Mn4, and an NMOS switch Mn1; wherein,

[0039] The sources of the differential NMOS pair transistors Mn3 and Mn4 are connected to the positive terminal of the power supply through a dynamic load, and their drains are connected to the source of the NMOS switch transistor Mn1. Their gates are connected to the input signals Vin+ and Vin-, respectively.

[0040] The drain of the NMOS switch Mn1 is connected to the basic current mirror, and the gate is connected to the control signal.

[0041] In sensing mode, under the control of the gate access control signal of NMOS switch Mn1, NMOS switch Mn1 is turned on, and the current source provided by the basic current mirror is connected to the differential NMOS pair Mn3 and Mn4. This enables the input voltage signal to be received through the gate of differential NMOS pair Mn3 and Mn4, and converted into a current signal through the transconductance of the transistor for output, thereby realizing the sensing of the input signal.

[0042] The latching branch includes differential NMOS transistors Mn5 and Mn6, and an NMOS switch Mn2. The sources of differential NMOS transistors Mn5 and Mn6 are connected to the positive terminal of the power supply through a dynamic load, and their drains are connected to the source of the NMOS switch Mn2. The gates of differential NMOS transistors Mn5 and Mn6 are connected to the sources of Mn6 and Mn5, respectively, and are also connected to the sources of differential NMOS transistors Mn3 and Mn4 at the output of the sensing branch.

[0043] The drain of the NMOS switch Mn2 is connected to the basic current mirror, and the gate is connected to the control signal.

[0044] In latching mode, under the control of the gate access control signal of NMOS switch Mn2, NMOS switch Mn2 is turned on, and the current source provided by the basic current mirror is connected to the differential NMOS pair Mn5 and Mn6. This enables the sensing signal of the sensing branch to be received through the gate of the differential NMOS pair Mn5 and Mn6, and converted into a current signal through the transconductance of the transistor for output, thereby achieving latching of the sensing signal.

[0045] The tail current source is a constant DC current source, providing a precise reference current I for the basic current mirror. DC ;

[0046] The basic current mirror includes: NMOS transistors Mn7, Mn8, Mn9, and Mn 10 ;in,

[0047] NMOS transistor Mn 10 The source of the tail current source I is connected to the source. DC The gate and source are shorted, and the drain is grounded;

[0048] The gate of NMOS transistor Mn7 and Mn 10 The gates of the transistors are connected together, the drain is grounded, and the source is connected to the drain of the switching transistors Mn1 and Mn2 in the sensing branch and latching branch, respectively.

[0049] The source of the NMOS transistor Mn8 is connected to the drain of the switching transistor in the sensing branch, the source is grounded, and the gate is controlled.

[0050] The source of NMOS transistor Mn9 is connected to the drain of the switching transistor in the latch branch, the source is grounded, and the gate is controlled.

[0051] In the basic current mirror, a fixed first tail current source I is provided for the sensing branch and the latching branch respectively through the NMOS transistor Mn7. DC ;

[0052] By using the gate-controlled NMOS transistor Mn8 as the sensing branch, a controlled second tail current source I is added during signal sensing. A ;

[0053] By using a gate-controlled NMOS transistor Mn9 as the latching branch, a controlled third tail current source I is added during signal latching. B .

[0054] The dynamic load includes: PMOS transistors Mp1 and Mp2;

[0055] The PMOS transistors Mp1 and Mp2 are respectively connected between the differential pair transistors of the sensing branch and the latching branch and the power supply, so that the power supply supplies power to each differential pair transistor of the sensing branch and the latching branch through the source and drain of the PMOS transistors Mp1 and Mp2, and the gates of the PMOS transistors Mp1 and Mp2 are controlled.

[0056] The PMOS transistors Mp1 and Mp2 dynamically change their loads according to different control signals.

[0057] In sensing mode, PMOS transistors Mp1 and Mp2 are controlled and operate in the linear region, providing low-impedance loads for the two differential branches of the sensing branch; and the second current source I... A Under the combined effect, the load impedance is reduced while satisfying the sensing current.

[0058] In latching mode, PMOS transistors Mp1 and Mp2 are controlled and operate in the cutoff region, providing a high-impedance load for the two differential branches of the latching branch; and the third current source I... B Under the combined effect, the load impedance is increased while satisfying the latching current.

[0059] Specifically, the switching between sensing mode and latching mode is jointly controlled by two control clocks, CLK+ and CLK-, which are complementary in phase and have a duty cycle of 50%.

[0060] Among them, the first control clock CLK+ is connected to the gate of the switching transistor Mn1 and the basic current mirror NMOS transistor Mn8 of the sensing branch respectively.

[0061] The second control clock CLK is connected to the gates of the latch branch switching transistor Mn2 and the basic current mirror NMOS transistor Mn9, as well as the gates of the dynamic load PMOS transistors Mp1 and Mp2.

[0062] In sensing mode, the clock CLK+ is high and CLK- is low. The high level of the clock CLK+ is output to the gates of the switching transistor Mn1 and the basic current mirror NMOS transistor Mn8, turning on the switching transistor Mn1 and the NMOS transistor Mn8. The low level of the clock CLK- is output to the gates of the switching transistor Mn2 and the basic current mirror NMOS transistor Mn9, as well as the gates of the dynamic load PMOS transistors Mp1 and Mp2, turning off the switching transistor Mn2 and the NMOS transistor Mn9, while making the PMOS transistors Mp1 and Mp2 operate in the linear region.

[0063] The conducting switching transistors Mn1 and Mn8 provide the first tail current source I for the sensing branch. DC Second tail current source I AFurthermore, the PMOS transistors Mp1 and Mp2, which operate in the linear region, provide a lower load impedance for the sensing branch. This reduces the load impedance and improves the sensing sensitivity while still providing the sensing current. At the same time, the tail current source of the latching branch is cut off by the cut-off switching transistors Mn2 and Mn9, reducing energy loss.

[0064] Reducing the load impedance can decrease the time constant of the circuit output node. A smaller time constant can follow changes in the input signal more quickly, thereby improving the sensitivity of the sensing mode.

[0065] In latching mode, the clock CLK+ is low and CLK- is high. The low level of the clock CLK+ is output to the gates of the switching transistor Mn1 and the basic current mirror NMOS transistor Mn8, turning off the switching transistor Mn1 and the NMOS transistor Mn8. The high level of the clock CLK- is output to the gates of the switching transistor Mn2 and the basic current mirror NMOS transistor Mn9, as well as the gates of the dynamic load PMOS transistors Mp1 and Mp2, turning on the switching transistors Mn2 and the NMOS transistor Mn9 while keeping the PMOS transistors Mp1 and Mp2 in the cutoff region.

[0066] The conducting switching transistors Mn2 and Mn9 provide the first tail current source I for the latch branch. DC and the third tail current source I B Furthermore, the PMOS transistors Mp1 and Mp2, operating in the cutoff region, provide a higher load impedance for the cutoff branch. This increases the load impedance while ensuring sufficient latching current, thus guaranteeing a high enough gain to drive the subsequent latch to switch quickly at high speeds. At the same time, the tail current source of the sensing branch is cut off by the cutoff switching transistors Mn1 and Mn8, reducing energy loss.

[0067] Specifically, traditional CML latch circuits use resistive loads. The parasitic capacitance of the resistive load forms an RC low-pass filter with the resistor. When the operating frequency of the circuit increases, the impedance of the resistor decreases, causing the output signal to be attenuated and resulting in a decrease in gain. However, by using a dynamic load, its impedance can be controlled by designing the size of the transistor, and the impedance of the transistor at the operating frequency can be clearly determined through simulation, effectively alleviating the problem of gain reduction at high frequencies.

[0068] Specifically, determine the first tail current source I in the basic current mirror. DC Second tail current source I A and the third tail current source I B The process of sizing includes:

[0069] 1) By means of circuit simulation, the minimum tail current values ​​I1 and I2 required in sensing mode and latching mode are determined respectively;

[0070] When simulating the tail current of the sensing mode, fix the tail current of the latching mode and ensure that the tail current of the latching mode is large enough to ensure that the latching mode can work properly. Gradually increase the tail current of the sensing mode until the entire latch can work properly (can output the latched waveform normally), and the corresponding minimum current can be found.

[0071] When it is necessary to find the tail current of the latching mode, fix the tail current of the sensing mode and make it large enough, and gradually increase the tail current of the latching mode until the minimum current corresponding to when the circuit can output the latched waveform normally is reached.

[0072] 2) Determine the first tail current source I based on the selected tail current source. DC Second tail current source I A and the third tail current source I B ;

[0073] In this embodiment, the tail current source is selected by comprehensively considering factors including power consumption, operating frequency, transistor area, and phase noise; wherein,

[0074] The larger the tail current, the higher the power consumption of the circuit;

[0075] The larger the tail current, the higher the operating frequency of the circuit.

[0076] The larger the tail current, the larger the transistor size in the circuit;

[0077] The larger the tail current, the smaller the output phase noise of the circuit and the higher the quality of the output signal. Among them, phase noise is a key indicator for measuring the short-term stability of the signal frequency. It is used to describe the random fluctuation of the signal phase over time and represents the noise energy distribution of the signal around the ideal frequency.

[0078] A suitable tail current source was determined by comprehensively considering power consumption, operating frequency, transistor area, and phase noise.

[0079] After identifying the tail current source in the circuit, the first tail current source I is obtained. DC Then, the second tail current source I is calculated. A =I1-I DC Third tail current source I B =I2-I DC ;

[0080] 3) By setting the width-to-length ratio of tail current transistors Mn8 and Mn9, the magnitude of their drain current can be determined;

[0081] The formula for the current in the transistor saturation region is:

[0082]

[0083] Where μ n Carrier mobility; Cox gate oxide capacitance per unit area; This represents the aspect ratio of the transistor.

[0084] The magnitude of the drain current can be determined by setting the width-to-length ratio of the tail current transistor.

[0085] 4) Set the tail current transistors Mn8 and Mn9 to have the same length L, and the width ratio to be equal to that of the second tail current source I. A and the third tail current source I B The current ratio.

[0086] In one specific embodiment

[0087] Based on factors such as application scenarios, total system power consumption allocation, and operating frequency, the following typical reference values ​​can be obtained for UMC28nm: Low-power clock divider circuit, total tail current of 0.2mA to 0.5mA, applicable frequency of 5GHz and below; High-speed SerDes interface circuit, total tail current of 1 to 2mA, applicable frequency of 10 to 20GHz; High-precision PLL, total tail current of 0.5 to 1mA, applicable frequency of 5 to 10GHz;

[0088] To comprehensively measure the relationship between tail current magnitude and circuit power consumption and phase noise performance, the FoM value (figure of merit: a comprehensive evaluation index of power consumption and phase noise) is introduced as an indicator to evaluate the quality of the circuit. Its formula is shown below, where σ... t RMS jitter, P is DC power consumption.

[0089]

[0090] The relationship between circuit jitter and phase noise can be obtained using the following formula:

[0091]

[0092] Where PN is the phase noise of the circuit, which can be obtained through simulation; f1 and f2 are the integration bandwidths, usually chosen from 10KHz to 30MHz; and f0 is the center frequency.

[0093] Through simulation and calculation of different current distribution methods, it can be concluded that the FoM value of the circuit is optimal when the fixed current is around 150μA and the adjustable tail current is around 46μA and 139μA.

[0094] Therefore, in a specific embodiment, a variable tail current source I is selected. A and I B The sizes are approximately 50 μA and 150 μA.

[0095] To allow the transistors to be stacked together on the layout, their lengths L must be the same. Therefore, the width ratio W of the tail current transistors Mn8 and Mn9 for the two variable current sources must be determined. A :W B =1:3.

[0096] Specifically, simulation methods for determining the optimal FoM value include:

[0097] When it is necessary to determine the optimal FoM value of the sensing mode, the current of the latching mode is fixed and large enough, the magnitudes of the fixed tail current and the adjustable tail current are changed, the phase noise of the circuit is simulated, and the FoM value of the circuit is calculated according to the formula to find the current magnitude that makes the FoM value optimal.

[0098] When it is necessary to determine the optimal FoM value of the latching mode, fix the current of the sensing mode and make it large enough, change the magnitude of the fixed tail current and the adjustable tail current, simulate the phase noise of the circuit, calculate the FoM value of the circuit according to the formula, and find the current magnitude that makes the FoM value optimal.

[0099] In latch circuits, the input clock signal is often not an ideal 50% duty cycle square wave. The CML signal can be incorrectly inverted due to this non-ideal clock signal, causing the output signal duty cycle to deviate from 50%. This is something that needs to be avoided in clock circuits, as an incorrect duty cycle can lead to race conditions and timing errors in subsequent circuits.

[0100] To prevent the above problems, in this embodiment, a level detection circuit is used to shape the input clock signal and output two control clocks CLK+ and CLK- with complementary phases and a duty cycle of 50%.

[0101] Specifically, such as Figure 3 As shown, the level detection circuit includes a first self-biased inverter and a second self-biased inverter; wherein,

[0102] The DC operating point of the first self-biased inverter is the midpoint of the power supply voltage, VDD / 2; it is used to invert and shape the input clock signal and output a second control clock, CLK-, with a duty cycle of 50%.

[0103] The DC operating point of the second self-biased inverter is the midpoint of the power supply voltage, VDD / 2; it is used to invert the input second control clock CLK- and output a first control clock CLK+ with a 50% duty cycle that is phase-complementary to the second control clock CLK-.

[0104] More specifically, the level detection circuit includes: a PMOS transistor Mp 11 Mp 21, NMOS transistor Mn 12 Mn 22 Resistors R1 and R2; among which,

[0105] PMOS transistor Mp 11 NMOS transistor Mn 12 Together with resistor R1, they form a second self-biased inverter;

[0106] PMOS transistor Mp 21 NMOS transistor Mn 22 Together with resistor R2, they form the first self-biased inverter;

[0107] In the first self-biased inverter, the positive power supply VDD passes through the PMOS transistor Mp. 21 The source and drain of the NMOS transistor Mn 22 The source and drain of the PMOS transistor are connected to ground; 21 and NMOS transistor Mn 22 The gates of the two transistors are connected together to form the input of the inverter, and the PMOS transistor Mp... 21 The drain and NMOS transistor Mn 22 The sources of the inverter are connected together to form the output of the inverter, and resistor R2 is connected between the input and output of the inverter.

[0108] In the second self-biased inverter, the positive power supply VDD passes through the PMOS transistor Mp. 11 The source and drain of the NMOS transistor Mn 12 The source and drain of the PMOS transistor are connected to ground; 11 and NMOS transistor Mn 12 The gates of the two transistors are connected together to form the input of the inverter, and the PMOS transistor Mp... 11 The drain and NMOS transistor Mn 12 The sources of the inverter are connected together to form the output of the inverter, and resistor R1 is connected between the input and output of the inverter.

[0109] In this embodiment, the self-biased inverter establishes negative feedback by introducing a feedback resistor, thereby stabilizing the static operating point.

[0110] Specifically, the static operating point can be determined using the following formula:

[0111]

[0112] V bias For the voltage of the quiescent operating point that needs to be set, VDD / 2 is selected as the quiescent operating point in this embodiment. R F For feedback resistor; P eq This represents the on-resistance of a PMOS or NMOS transistor; the formulas for the on-resistance of PMOS and NMOS transistors are as follows:

[0113]

[0114] Among them, R eqp R eqn μ represents the on-resistance of the PMOS and NMOS. p μ n C represents the carrier mobility of PMOS and NMOS. ox V is the capacitance per unit area of ​​the gate oxide layer. gsp V gsn V represents the gate-source voltage of the PMOS and NMOS. thn V thp This refers to the turn-on voltage of NMOS and PMOS. The aspect ratios of NMOS and PMOS are given.

[0115] Based on the on-resistance formulas for PMOS and NMOS, the on-resistance is adjusted by changing the width-to-length ratio of the NMOS and PMOS transistors in the self-biased inverter. This eliminates the difference in on-resistance caused by the different carrier mobilities, allowing the quiescent operating point voltage to reach VDD / 2.

[0116] Preferably, by changing the size of the PMOS while keeping the channel length constant, the channel width is increased, so that the on-resistance of the PMOS and NMOS in the self-biased inverter is matched, and the voltage at the static operating point reaches VDD / 2.

[0117] By properly setting the static operating point of the self-biased inverter, ensuring the symmetry of the output signal between high and low levels and between the rise and fall times, the self-biased inverter will improve the duty cycle performance of the input clock signal, adjusting the duty cycle of the input clock signal to close to 50%, and ensuring the normal timing of the latch.

[0118] In summary, compared with traditional latches, the high-speed CML latch structure disclosed in this embodiment effectively controls power consumption while achieving high-speed performance through dynamic bias and load control, reasonable configuration of tail current source, and optimization of current source switching control signal. It can improve the circuit's operating speed and performance without significantly increasing power consumption.

[0119] As semiconductor manufacturing processes advance, the maximum operating voltage supported by transistors also decreases. For example, in a 28nm process, the supply voltage of an SVT transistor (Standard Threshold Voltage Transistor, Standard Vth) is only about 900mV. If a traditional current-mode logic (CML) circuit topology is still used at this time, the maximum operating frequency and output voltage swing of the circuit will be significantly affected due to the limitations of static load resistance and static DC current.

[0120] Because integrated circuits have inherent manufacturing errors, it is extremely difficult to precisely manufacture resistors with the designed values. This leads to significant errors in traditional current-mode logic (CML) circuits under advanced manufacturing processes. These errors are unrelated to the circuit design and are introduced during manufacturing. Therefore, traditional current-mode logic (CML) circuits can significantly impact the overall clock quality in circuits with high requirements for phase noise and spurious emissions, such as clock circuits.

[0121] In this embodiment, using transistors as dynamic loads can first alleviate the problem of resistance value errors caused during integrated circuit manufacturing. While it is difficult to precisely manufacture circuit devices with exact values ​​(e.g., manufacturing a calculated load resistor), certain ratios in the manufactured circuit are very precise. The resistance of a transistor in the linear region is a function of its transconductance gm, which in turn is a function of its width-to-length ratio. Therefore, the desired transistor transconductance can be fabricated relatively accurately through layout design.

[0122] Dynamic loads can adaptively adjust their impedance according to the circuit's operating mode, achieving low impedance in sensing mode to maintain a stable circuit time constant, and high impedance in latching mode to ensure sufficient gain to drive subsequent circuits.

[0123] In this embodiment, the output of the self-biased inverter is chosen as the switching signal for the circuit tail current instead of directly using the clock signal to control the circuit state because the input clock signal is often not an ideal square wave signal with a 50% duty cycle. The CML signal will invert incorrectly due to the non-ideal clock signal, causing the output signal duty cycle to deviate from 50%. This should be avoided as much as possible in clock circuits, as an incorrect duty cycle can lead to race conditions and timing errors in subsequent circuits.

[0124] To increase the operating frequency of the circuit while reducing its power consumption, this embodiment employs a dynamic current bias circuit. By dividing the tail current of the circuit into three parts, the required current of the circuit is dynamically adjusted according to the circuit's operating mode. This significantly increases the operating frequency of the circuit without increasing transistor resources and with the overall power consumption of the circuit being similar to that of traditional current-mode logic (CML) circuits.

[0125] A comparison was made between the traditional current-mode logic (CML) circuit and the improved circuit using the UMC 28nm process. When both circuits operated at 26.4GHz, the total power consumption of the traditional current-mode logic circuit was 1.14mW, while the improved current-mode logic circuit only required 725uW.

[0126] When all circuits operate at around 520uW, the highest operating frequency of the traditional current-mode logic circuit is 19.2GHz; the highest operating frequency of the improved CML circuit is 22.4GHz.

[0127] like Figure 4 The figure shows the output waveform of the CML circuit at the same operating frequency;

[0128] like Figure 5 The figure shown is the waveform of the highest operating frequency of the improved CML circuit at the same power consumption.

[0129] like Figure 6 The figure shown is the waveform of the highest operating frequency of a traditional CML circuit at the same power consumption.

[0130] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention.

Claims

1. A high-speed CML latch structure, characterized in that, include: Dynamic load, sensing branch, latching branch, basic current mirror and tail current source; The sensing branch is used to sense the input signal and output the sensing signal in sensing mode; The latch branch is used to latch the input signal and output a latched signal in latch mode. Tail current source, used to provide a precise reference current source for the basic current mirror; A basic current mirror is used to provide a fixed first tail current source and a controlled second tail current source for the sensing branch, and a fixed first tail current source and a controlled third tail current source for the latching branch. In the sensing mode, the second tail current source is turned on and the third tail current source is turned off; in the latching mode, the third tail current source is turned on and the second tail current source is turned off, providing dynamic current bias for the circuit. Dynamic load is used to reduce circuit impedance in sensing mode and increase circuit impedance in latching mode, providing dynamic load impedance for the circuit.

2. The high-speed CML latch structure according to claim 1, characterized in that, The basic current mirror includes: NMOS transistors Mn7, Mn8, Mn9, and Mn 10 ;in, NMOS transistor Mn 10 The source of the tail current source I is connected to the source. DC The gate and source are shorted, and the drain is grounded; The gate of NMOS transistor Mn7 and Mn 10 The gates of the transistors are connected together, the drain is grounded, and the source is connected to the drain of the switching transistors Mn1 and Mn2 in the sensing branch and latching branch, respectively. The source of the NMOS transistor Mn8 is connected to the drain of the switching transistor in the sensing branch, the source is grounded, and the gate is controlled. The source of NMOS transistor Mn9 is connected to the drain of the switching transistor in the latch branch, the source is grounded, and the gate is controlled. In the basic current mirror, a fixed first tail current source I is provided for the sensing branch and the latching branch respectively through the NMOS transistor Mn7. DC ; By using the gate-controlled NMOS transistor Mn8 as the sensing branch, a controlled second tail current source I is added during signal sensing. A ; By using a gate-controlled NMOS transistor Mn9 as the latching branch, a controlled third tail current source I is added during signal latching. B .

3. The high-speed CML latch structure according to claim 2, characterized in that, Determine the first tail current source I in the basic current mirror DC Second tail current source I A and the third tail current source I B The process of sizing includes: 1) By means of circuit simulation, the minimum tail current values ​​I1 and I2 required in sensing mode and latching mode are determined respectively; 2) Determine the first tail current source I based on the selected tail current source. DC Second tail current source I A and the third tail current source; Among them, the tail current source is selected by comprehensively considering factors including power consumption, operating frequency, transistor area and phase noise. After identifying the tail current source in the circuit, the first tail current source I is obtained. DC Then, the second tail current source I is calculated. A =I1-I DC Third tail current source I B =I2-I DC ; 3) By setting the width-to-length ratio of tail current transistors Mn8 and Mn9, the magnitude of their drain current can be determined; 4) Set the tail current transistors Mn8 and Mn9 to have the same length L, and the width ratio to be equal to that of the second tail current source I. A and the third tail current source I B The current ratio.

4. The high-speed CML latch structure according to claim 2, characterized in that, The dynamic load includes: PMOS transistors Mp1 and Mp2; The PMOS transistors Mp1 and Mp2 are respectively connected between the differential pair transistors of the sensing branch and the latching branch and the power supply, so that the power supply supplies power to each differential pair transistor of the sensing branch and the latching branch through the source and drain of the PMOS transistors Mp1 and Mp2, and the gates of the PMOS transistors Mp1 and Mp2 are controlled. The PMOS transistors Mp1 and Mp2 dynamically change their loads according to different control signals. In sensing mode, PMOS transistors Mp1 and Mp2 are controlled and operate in the linear region, providing low impedance loads for the two differential branches of the sensing branch. In latching mode, PMOS transistors Mp1 and Mp2 are controlled and operate in the cutoff region, providing high impedance loads for the two differential branches of the latching branch.

5. The high-speed CML latch structure according to claim 4, characterized in that, The switching between sensing mode and latching mode is jointly controlled by two control clocks, CLK+ and CLK-, which are complementary in phase and have a duty cycle of 50%. Among them, the first control clock CLK+ is connected to the gate of the switching transistor Mn1 and the basic current mirror NMOS transistor Mn8 of the sensing branch respectively. The second control clock CLK is connected to the gates of the latch branch switching transistor Mn2 and the basic current mirror NMOS transistor Mn9, as well as the gates of the dynamic load PMOS transistors Mp1 and Mp2. In sensing mode, the clock CLK+ is high and CLK- is low; in latching mode, the clock CLK+ is low and CLK- is high.

6. The high-speed CML latch structure according to claim 5, characterized in that, The sensing branch includes differential NMOS transistors Mn3 and Mn4, and an NMOS switch Mn1; among them, The sources of the differential NMOS pair transistors Mn3 and Mn4 are connected to the positive terminal of the power supply through a dynamic load, and their drains are connected to the source of the NMOS switch transistor Mn1. Their gates are connected to the input signals Vin+ and Vin-, respectively. The drain of the NMOS switch Mn1 is connected to a basic current mirror, and the gate is connected to a control signal.

7. The high-speed CML latch structure according to claim 5, characterized in that, The latching branch includes differential NMOS transistors Mn5 and Mn6, and an NMOS switch Mn2; among which, The sources of differential NMOS transistors Mn5 and Mn6 are connected to the positive terminal of the power supply through a dynamic load, and their drains are connected to the source of NMOS switching transistor Mn2. The gates of differential NMOS transistors Mn5 and Mn6 are connected to the sources of Mn6 and Mn5, respectively, and are also connected to the sources of differential NMOS transistors Mn3 and Mn4 at the output of the sensing branch. The drain of the NMOS switch Mn2 is connected to a basic current mirror, and the gate is connected to a control signal.

8. The high-speed CML latch structure according to claim 5, characterized in that, A level detection circuit is used to shape the input clock signal and output two control clocks, CLK+ and CLK-, with complementary phases and a duty cycle of 50%.

9. The high-speed CML latch structure according to claim 8, characterized in that, The level detection circuit includes: PMOS transistor Mp 11 Mp 21 , NMOS transistor Mn 12 Mn 22 Resistors R1 and R2; among which, PMOS transistor Mp 11 NMOS transistor Mn 12 Together with resistor R1, they form a second self-biased inverter; PMOS transistor Mp 21 NMOS transistor Mn 22 Together with resistor R2, they form the first self-biased inverter; In the first self-biased inverter, the positive power supply VDD passes through the PMOS transistor Mp. 21 The source and drain of the NMOS transistor Mn 22 The source and drain of the PMOS transistor are connected to ground; 21 and NMOS transistor Mn 22 The gates of the two transistors are connected together to form the input of the inverter, and the PMOS transistor Mp... 21 The drain and NMOS transistor Mn 22 The sources of the inverter are connected together to form the output of the inverter, and resistor R2 is connected between the input and output of the inverter. In the second self-biased inverter, the positive power supply VDD passes through the PMOS transistor Mp. 11 The source and drain of the NMOS transistor Mn 12 The source and drain of the PMOS transistor are connected to ground; 11 and NMOS transistor Mn 12 The gates of the two transistors are connected together to form the input of the inverter, and the PMOS transistor Mp... 11 The drain and NMOS transistor Mn 12 The sources of the inverter are connected together to form the output of the inverter, and resistor R1 is connected between the input and output of the inverter.

10. The high-speed CML latch structure according to claim 8, characterized in that, The quiescent operating point voltage of each self-biased inverter is VDD / 2. In each self-biased inverter, while keeping the channel length of the PMOS transistor constant, the channel width is increased to match the on-resistance of the PMOS transistor and the NMOS transistor in the self-biased inverter, so that the quiescent operating point voltage reaches VDD / 2.

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