A frequency locked loop circuit

Abstract

The application discloses a frequency-locked loop circuit and relates to the technical field of electronic circuits.The circuit comprises an error amplifier, a voltage-controlled oscillator, a filter capacitor, a frequency divider and a switched capacitor module.The error amplifier is used for generating a frequency control voltage according to a first voltage received by its non-inverting input terminal and a second voltage received by its inverting input terminal;the voltage-controlled oscillator is used for generating a first clock signal and a second clock signal according to the frequency control voltage;the filter capacitor is used for filtering the frequency control voltage;the frequency divider is used for generating a third clock signal according to the first clock signal and a fourth clock signal according to the second clock signal;and the switched capacitor module is used for acquiring the first clock signal, the second clock signal, the third clock signal and the fourth clock signal and generating the second voltage.In the case that the frequency of the clock signal output by the voltage-controlled oscillator is constant, the second capacitor and the third capacitor can be relatively small, the function of the frequency-locked loop circuit can be realized, and the circuit area is reduced.

Description

Technical Field

[0001] This application relates to the field of electronic circuit technology, and in particular to a frequency-locked loop circuit. Background Technology

[0002] In such Figure 1 In the conventional frequency-locked loop circuit shown, after the signal frequency is locked, capacitor C 00 Under the influence of clock signals CLKA and CLKB, the amplifier undergoes repeated charging and discharging (CLKA and CLKB are clock signals of the same frequency but opposite phase), resulting in significant ripple at the output voltage of amplifier EA. This causes large instantaneous frequency jumps in the output signal of the voltage-controlled oscillator (VCO) modulated by the output voltage of the error amplifier. Typically, increasing the capacitor C simultaneously... 00 and capacitor C 01 This problem can be overcome, but it will result in a larger area overhead for passive components, creating a trade-off between frequency accuracy and circuit area. Summary of the Invention

[0003] To resolve the trade-off between frequency accuracy and circuit area in frequency-locked loop circuits, this application provides the following technical solution: A frequency-locked loop circuit is provided, comprising: An error amplifier is used to generate a frequency control voltage based on a first voltage received at its non-inverting input and a second voltage received at its inverting input. A voltage-controlled oscillator is used to generate a first clock signal and a second clock signal according to a frequency-controlled voltage, wherein the first clock signal and the second clock signal are opposite clock signals with the same frequency. Filter capacitors are used to filter the frequency control voltage. A frequency divider is used to generate a third clock signal based on a first clock signal and a fourth clock signal based on a second clock signal, wherein the frequency of the third clock signal is half the frequency of the first clock signal and the frequency of the fourth clock signal is half the frequency of the second clock signal. The switched capacitor module is used to acquire the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal to generate the second voltage.

[0004] Furthermore, the switched capacitor module includes: a first switched capacitor unit, a second switched capacitor unit, and a third switched capacitor unit; The first terminal of the first switched capacitor unit, the first terminal of the second switched capacitor unit, and the first terminal of the third switched capacitor unit are connected to the first node. The second terminal of the second switched capacitor unit and the second terminal of the third switched capacitor unit are connected to the non-inverting input terminal of the error amplifier. The first switched capacitor unit, the second switched capacitor unit, and the third switched capacitor unit share a common ground.

[0005] Furthermore, the first switched capacitor unit includes: a first capacitor, a first switch, and a second switch; One end of the first switch is connected to one end of the first capacitor and one end of the second switch. The other end of the first switch serves as the first end of the first switch-capacitor unit. The other end of the first capacitor is connected to the other end of the second switch and used for grounding. The on or off state of the first switch is controlled by the first clock signal, and the on or off state of the second switch is controlled by the second clock signal.

[0006] Furthermore, the second switched capacitor unit includes: a second capacitor, a third switch, and a fourth switch; One end of the third switch is connected to one end of the second capacitor and one end of the fourth switch. The other end of the third switch serves as the second end of the second switched capacitor unit, and the other end of the fourth switch serves as the first end of the second switched capacitor unit. The other end of the second capacitor is used for grounding. The on or off state of the third switch is controlled by the fourth clock signal, and the on or off state of the fourth switch is controlled by the third clock signal.

[0007] Furthermore, the third switched capacitor unit includes: a third capacitor, a fifth switch, and a sixth switch; One end of the fifth switch is connected to one end of the third capacitor and one end of the sixth switch. The other end of the fifth switch serves as the first end of the third switching capacitor unit, and the other end of the sixth switch serves as the second end of the third switching capacitor unit. The other end of the third capacitor is used for grounding. The on or off state of the fifth switch is controlled by the fourth clock signal, and the on or off state of the sixth switch is controlled by the third clock signal.

[0008] Furthermore, the frequency-locked loop circuit also includes: a first current source, a second current source, and a resistor; After one end of the first current source is connected to one end of the second current source, it is used to connect the working voltage. The other end of the first current source is connected to one end of the resistor and the inverting input of the error amplifier to provide the first voltage; The other end of the resistor is used for grounding; The other end of the second current source is connected to the first node.

[0009] Furthermore, when the first switch is turned on under the action of the first clock signal, the second switch is turned off under the action of the second clock signal, the third and fifth switches are turned on under the action of the fourth clock signal, and the fourth and sixth switches are turned off under the action of the third clock signal, the second current source charges the first capacitor and the third capacitor through the first node, and the second capacitor discharges to the non-inverting input terminal of the error amplifier.

[0010] Furthermore, when the first switch is turned on under the action of the first clock signal, the second switch is turned off under the action of the second clock signal, the third and fifth switches are turned off under the action of the fourth clock signal, and the fourth and sixth switches are turned on under the action of the third clock signal, the second current source charges the first capacitor and the second capacitor through the first node, and the third capacitor discharges to the non-inverting input terminal of the error amplifier.

[0011] Furthermore, when the first switch is turned off under the action of the first clock signal, the second switch is turned on under the action of the second clock signal, the third and fifth switches are turned on under the action of the fourth clock signal, and the fourth and sixth switches are turned off under the action of the third clock signal, the second current source charges the third capacitor through the first node, the first capacitor discharges to ground, and the second capacitor discharges to the non-inverting input terminal of the error amplifier.

[0012] Furthermore, when the first switch is turned on under the action of the first clock signal, the second switch is turned off under the action of the second clock signal, the third and fifth switches are turned on under the action of the fourth clock signal, and the fourth and sixth switches are turned off under the action of the third clock signal, the second current source charges the second capacitor through the first node, the first capacitor discharges to ground, and the third capacitor discharges to the non-inverting input terminal of the error amplifier.

[0013] By implementing the frequency-locked loop circuit described in the embodiments of this application, the function of the frequency-locked loop circuit can be realized by using a smaller second capacitor and a smaller third capacitor, thus reducing the circuit area, when the frequency of the clock signal output by the voltage-controlled oscillator is constant. Attached Figure Description

[0014] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0015] Figure 1 This is a schematic diagram of a conventional frequency-locked loop circuit; Figure 2 This is a schematic diagram of a frequency-locked loop circuit provided in an embodiment of this application; Figure 3This is a schematic diagram of a frequency-locked loop circuit under timing control provided in an embodiment of this application; Figure 4 This is a schematic diagram of another frequency-locked loop circuit under timing control provided in an embodiment of this application; Figure 5 This is a schematic diagram of another frequency-locked loop circuit under timing control provided in the embodiments of this application; Figure 6 This is a schematic diagram of another frequency-locked loop circuit under timing control provided in the embodiments of this application; Figure 7 This is a schematic diagram of the voltage waveform provided in the embodiment of this application. Detailed Implementation

[0016] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0017] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The numbers in the accompanying drawings are only used to distinguish individual functional parts or modules and do not indicate logical relationships between parts or modules. The terms “comprising,” “including,” or “including,” and similar terms mean that the element or object preceding the term encompasses the element or object listed following the term and its equivalents, without excluding other elements or objects. The terms “connected,” “linked,” and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. “Above,” “below,” “left,” “right,” etc., are used only to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0018] The various embodiments according to this disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that in the drawings, the same reference numerals are assigned to components having substantially the same or similar structure and function, and repeated descriptions of them will be omitted.

[0019] To address the conflict between frequency accuracy and circuit area in frequency-locked loop circuits, this application provides the following implementation method.

[0020] like Figure 2 As shown, a frequency-locked loop circuit includes: Error amplifier 100 is used to generate a frequency control voltage based on a first voltage received at its non-inverting input and a second voltage received at its inverting input. The voltage-controlled oscillator 200 is used to generate a first clock signal CLK1 and a second clock signal CLK2 according to the frequency control voltage, wherein the first clock signal CLK1 and the second clock signal CLK2 are opposite clock signals with the same frequency. Filter capacitor C F It is used to filter the frequency control voltage; Frequency divider 300 is used to generate a third clock signal DCLK1 based on the first clock signal CLK1, and to generate a fourth clock signal DCLK2 based on the second clock signal CLK2, wherein the frequency of the third clock signal DCLK1 is half the frequency of the first clock signal CLK1, and the frequency of the fourth clock signal DCLK2 is half the frequency of the second clock signal CLK2. The switched capacitor module 400 is used to acquire the first clock signal CLK1, the second clock signal CLK2, the third clock signal DCLK1, and the fourth clock signal DCLK2 to generate the second voltage.

[0021] The output of error amplifier 100 is connected to the input of voltage-controlled oscillator 200. The output of error amplifier 100 transmits the frequency control voltage to the input of voltage-controlled oscillator 200.

[0022] Specifically, the switched capacitor module 400 includes: a first switched capacitor unit 410, a second switched capacitor unit 420, and a third switched capacitor unit 430. The first terminal of the first switched capacitor unit 410, the first terminal of the second switched capacitor unit 420, and the first terminal of the third switched capacitor unit 430 are connected to the first node N. A The second terminal of the second switched capacitor unit 420 and the second terminal of the third switched capacitor unit 430 are connected to the non-inverting input terminal of the error amplifier 100. The first switched capacitor unit 410, the second switched capacitor unit 420 and the third switched capacitor unit 430 share a common ground.

[0023] Specifically, the first switched capacitor unit 410 includes: a first capacitor C1, a first switch S1, and a second switch S2; One end of the first switch S1 is connected to one end of the first capacitor C1 and one end of the second switch S2. The other end of the first switch S1 serves as the first end of the first switched capacitor unit 410 and is connected to the first node N.A The other end of the first capacitor C1 is connected to the other end of the second switch S2 and then used to ground GND. The on or off state of the first switch S1 is controlled by the first clock signal CLK1, and the on or off state of the second switch S2 is controlled by the second clock signal CLK2.

[0024] Specifically, the second switched capacitor unit 420 includes: a second capacitor C2, a third switch S3, and a fourth switch S4; One end of the third switch S3 is connected to one end of the second capacitor C2 and one end of the fourth switch S4. The other end of the third switch S3 serves as the second end of the second switched capacitor unit 420 and is connected to the first node N. A The other end of the fourth switch S4 is used as the first end of the second switching capacitor unit 420, and the other end of the second capacitor C2 is used to ground GND. The on or off state of the third switch S3 is controlled by the fourth clock signal DCLK2, and the on or off state of the fourth switch S4 is controlled by the third clock signal DCLK1.

[0025] Specifically, the third switched capacitor unit 430 includes: a third capacitor C3, a fifth switch S5, and a sixth switch S6; One end of the fifth switch S5 is connected to one end of the third capacitor C3 and one end of the sixth switch S6. The other end of the fifth switch S5 serves as the first end of the third switched capacitor unit 430 and is connected to the first node N. A The other end of the sixth switch S6 is used as the second end of the third switch capacitor unit 430, and the other end of the third capacitor C3 is used for grounding GND. The on or off state of the fifth switch S5 is controlled by the fourth clock signal DCLK2, and the on or off state of the sixth switch S6 is controlled by the third clock signal DCLK1.

[0026] The frequency-locked loop circuit also includes: a first current source I REF1 Second current source I REF2 And the resistance R; First current source I REF1 One end is connected to the second current source I REF2 One end is connected and used to connect the working voltage V. DD ; First current source I REF1 The other end is connected to one end of resistor R and the inverting input of error amplifier 100 to provide the first voltage; The other end of resistor R is used for grounding GND; Second current source I REF2 The other end is connected to the first node NA .

[0027] like Figure 3 As shown, when the first switch S1 is turned on under the action of the first clock signal CLK1, the second switch S2 is turned off under the action of the second clock signal CLK2, the third switch S3 and the fifth switch S5 are turned on under the action of the fourth clock signal DCLK2, and the fourth switch S4 and the sixth switch S6 are turned off under the action of the third clock signal DCLK1, the second current source I... REF2 via the first node N A The first capacitor C1 and the third capacitor C3 are charged, while the second capacitor C2 discharges to the non-inverting input terminal of the error amplifier 100.

[0028] like Figure 4 As shown, when the first switch S1 is turned on under the action of the first clock signal CLK1, the second switch S2 is turned off under the action of the second clock signal CLK2, the third switch S3 and the fifth switch S5 are turned off under the action of the fourth clock signal DCLK2, and the fourth switch S4 and the sixth switch S6 are turned on under the action of the third clock signal DCLK1, the second current source I... REF2 via the first node N A The first capacitor C1 and the second capacitor C2 are charged, and the third capacitor C3 is discharged to the non-inverting input terminal of the error amplifier 100.

[0029] like Figure 5 As shown, when the first switch S1 is turned off under the action of the first clock signal CLK1, the second switch S2 is turned on under the action of the second clock signal CLK2, the third switch S3 and the fifth switch S5 are turned on under the action of the fourth clock signal DCLK2, and the fourth switch S4 and the sixth switch S6 are turned off under the action of the third clock signal DCLK1, the second current source I... REF2 via the first node N A The third capacitor C3 is charged, the first capacitor C1 is discharged to ground, and the second capacitor C2 is discharged to the non-inverting input terminal of the error amplifier 100.

[0030] like Figure 6 As shown, when the first switch S1 is turned on under the action of the first clock signal CLK1, the second switch S2 is turned off under the action of the second clock signal CLK2, the third switch S3 and the fifth switch S5 are turned on under the action of the fourth clock signal DCLK2, and the fourth switch S4 and the sixth switch S6 are turned off under the action of the third clock signal DCLK1, the second current source I... REF2 via the first node N A The second capacitor C2 is charged, the first capacitor C1 is discharged to ground, and the third capacitor C3 is discharged to the non-inverting input terminal of the error amplifier 100.

[0031] The first switch S1, the second switch S2, the third switch S3, the fourth switch S4, the fifth switch S5, and the sixth switch S6 are all controlled switches. They are turned on when a high-level signal is received and turned off when a low-level signal is received.

[0032] Optionally, the first switch S1, the second switch S2, the third switch S3, the fourth switch S4, the fifth switch S5, and the sixth switch S6 are N-channel MOSFETs.

[0033] The working principle of the frequency-locked loop circuit described in the embodiments of this application will be explained below.

[0034] Voltage amplitude at the inverting input of error amplifier 100 V REF Represented as: V REF = I REF1 · R .

[0035] The first clock signal CLK1 and the second clock signal CLK2 output by the voltage-controlled oscillator 200 are fed back to the first switched capacitor unit 410. The resistance value of the equivalent resistor of the first switched capacitor unit 410... R eq for: R eq = 1 / f VCO · C 1.

[0036] in, f VCO This indicates the frequency of either the first clock signal CLK1 or the second clock signal CLK2. C 1 represents the capacitance value of the first capacitor C1. The voltage amplitude at the inverting input of error amplifier 100 when the system is locked. V REF Voltage amplitude at the non-inverting input of error amplifier 100 V CAP Equal, that is: V REF = V CAP .

[0037] The voltage amplitude at the non-inverting input of error amplifier 100 V CAP It can also be expressed as: V CAP = I REF2 / f VCO · C 1.

[0038] In circuit design, the first current source I REF1 current value I REF10 With the second current source I REF2 current value I REF2 Since they are set to be equal, therefore: I REF2 = I REF1 = V REF / R .

[0039] Then the frequencies of the first clock signal CLK1 and the second clock signal CLK2 are determined. f VCO for: f VCO = 1 / RC 1.

[0040] The entire system constitutes negative feedback. If the frequencies of the first clock signal CLK1 and the second clock signal CLK2... f VCO The voltage amplitude at the non-inverting input of the error amplifier 100 is too large. V CAP If they are equal, the value will be too small, the output voltage of the error amplifier 100 will decrease, and the frequency of the first clock signal CLK1 and the second clock signal CLK2 of the voltage-controlled oscillator 200 will decrease. f vco.

[0041] To save circuit area, a second capacitor C2 and a third capacitor C3 with small capacitance values ​​(typically in the picofarad range) are used. Meanwhile, the non-inverting input of the error amplifier 100 is connected to the first node N via a second switched capacitor unit 420 or a third switched capacitor unit 430. A The third clock signal DCLK1 controls the third switch S3 and the fifth switch S5, and the fourth clock signal DCLK2 controls the fourth switch S4 and the sixth switch S6. This ensures that the voltage at the non-inverting input of the error amplifier 100 is equal to the voltage at the first node N. A The average voltage amplitude is used to avoid large fluctuations in the voltage at the non-inverting input of error amplifier 100. For example... Figure 7As shown, when the falling edge of the first clock signal CLK1 arrives, the third clock signal DCLK1 and the fourth clock signal DCLK2 toggle. Whenever the fourth switch S4 is turned off, the voltage across the second capacitor C2 is exactly equal to the voltage across the first node N. A The average voltage; correspondingly, whenever the fifth switch S5 is turned off, the voltage across the third capacitor C3 is exactly equal to the voltage across the first node N. A The average voltage. Furthermore, whenever the fourth switch S4 is turned off, the third switch S3 is turned on; whenever the fifth switch S5 is turned off, the sixth switch S6 is turned on, thus turning the first node N... A The average voltage is transmitted to the non-inverting input of error amplifier 100. Therefore, the voltage amplitude at the non-inverting input of error amplifier 100 is always related to the voltage at the first node N. A The average voltage values ​​are constant, avoiding large fluctuations. For ease of waveform visualization, Figure 7 When comparing waveforms, different colors are used to represent the corresponding waveforms. V NA Indicates the first node N A voltage amplitude, V C2 This indicates the voltage amplitude across the second capacitor C2. V C3 This indicates the voltage amplitude across the third capacitor C3.

[0042] By implementing the frequency-locked loop circuit described in the embodiments of this application, under the condition that the frequency of the clock signal output by the voltage-controlled oscillator is constant, the function of the frequency-locked loop circuit can be realized by using a smaller second capacitor and a smaller third capacitor, thereby reducing the circuit area; at the same time, the capacitance value of the filter capacitor only needs to meet the circuit stability requirements, simplifying the circuit design.

[0043] All of the above-mentioned optional technical solutions can be combined in any way to form the optional embodiments of this application, and will not be described in detail here.

[0044] Note that the above description is merely a preferred embodiment and the technical principles employed in this application. Those skilled in the art will understand that this application is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application. Therefore, although this application has been described in detail through the above embodiments, this application is not limited to the above embodiments. Many other equivalent embodiments may be included without departing from the concept of this application, and the scope of this application is determined by the scope of the appended claims.

Claims

1. A frequency-locked loop circuit, characterized in that, include: An error amplifier (100) is used to generate a frequency control voltage based on a first voltage received at its non-inverting input and a second voltage received at its inverting input. A voltage-controlled oscillator (200) is used to generate a first clock signal (CLK1) and a second clock signal (CLK2) according to the frequency control voltage, wherein the first clock signal (CLK1) and the second clock signal (CLK2) are inverse clock signals with the same frequency; Filter capacitor (C) F ), used to filter the frequency control voltage; A frequency divider (300) is used to generate a third clock signal (DCLK1) based on the first clock signal (CLK1) and a fourth clock signal (DCLK2) based on the second clock signal (CLK2), wherein the frequency of the third clock signal (DCLK1) is half the frequency of the first clock signal (CLK1) and the frequency of the fourth clock signal (DCLK2) is half the frequency of the second clock signal (CLK2). The switched capacitor module (400) is used to acquire the first clock signal (CLK1), the second clock signal (CLK2), the third clock signal (DCLK1), and the fourth clock signal (DCLK2) to generate the second voltage.

2. The frequency-locked loop circuit according to claim 1, characterized in that, The switched capacitor module (400) includes: a first switched capacitor unit (410), a second switched capacitor unit (420), and a third switched capacitor unit (430). The first terminal of the first switched capacitor unit (410), the first terminal of the second switched capacitor unit (420), and the first terminal of the third switched capacitor unit (430) are connected to the first node (N). A The second terminal of the second switched capacitor unit (420) and the second terminal of the third switched capacitor unit (430) are connected to the non-inverting input terminal of the error amplifier (100), and the first switched capacitor unit (410), the second switched capacitor unit (420) and the third switched capacitor unit (430) are grounded together.

3. The frequency-locked loop circuit according to claim 2, characterized in that, The first switched capacitor unit (410) includes: a first capacitor (C1), a first switch (S1), and a second switch (S2); One end of the first switch (S1) is connected to one end of the first capacitor (C1) and one end of the second switch (S2). The other end of the first switch (S1) serves as the first end of the first switch-capacitor unit (410). The other end of the first capacitor (C1) is connected to the other end of the second switch (S2) and then used for grounding. The on or off state of the first switch (S1) is controlled by the first clock signal (CLK1), and the on or off state of the second switch (S2) is controlled by the second clock signal (CLK2).

4. The frequency-locked loop circuit according to claim 3, characterized in that, The second switched capacitor unit (420) in the switched capacitor module (400) includes: a second capacitor (C2), a third switch (S3), and a fourth switch (S4); One end of the third switch (S3) is connected to one end of the second capacitor (C2) and one end of the fourth switch (S4). The other end of the third switch (S3) serves as the second end of the second switched capacitor unit (420), and the other end of the fourth switch (S4) serves as the first end of the second switched capacitor unit (420). The other end of the second capacitor (C2) is used for grounding. The on or off state of the third switch (S3) is controlled by the fourth clock signal (DCLK2), and the on or off state of the fourth switch (S4) is controlled by the third clock signal (DCLK1).

5. The frequency-locked loop circuit according to claim 4, characterized in that, The third switched capacitor unit (430) in the switched capacitor module (400) includes: a third capacitor (C3), a fifth switch (S5), and a sixth switch (S6); One end of the fifth switch (S5) is connected to one end of the third capacitor (C3) and one end of the sixth switch (S6). The other end of the fifth switch (S5) serves as the first end of the third switching capacitor unit (430), and the other end of the sixth switch (S6) serves as the second end of the third switching capacitor unit (430). The other end of the third capacitor (C3) is used for grounding. The on or off state of the fifth switch (S5) is controlled by the fourth clock signal (DCLK2), and the on or off state of the sixth switch (S6) is controlled by the third clock signal (DCLK1).

6. The frequency-locked loop circuit according to claim 5, characterized in that, The frequency-locked loop circuit further includes: a first current source (I REF1 ), second current source (I) REF2 ) and resistance (R); The first current source (I) REF1 One end of ) is connected to the second current source (I) REF2 After connecting one end, it is used to connect the working voltage (V). DD ); The first current source (I) REF1 The other end of the resistor (R) is connected to one end of the resistor (R) and the inverting input of the error amplifier (100) to provide the first voltage; The other end of the resistor (R) is used for grounding; The second current source (I) REF2 The other end is connected to the first node (N) A ).

7. The frequency-locked loop circuit according to claim 6, characterized in that, When the first switch (S1) is turned on under the action of the first clock signal (CLK1), the second switch (S2) is turned off under the action of the second clock signal (CLK2), the third switch (S3) and the fifth switch (S5) are turned on under the action of the fourth clock signal (DCLK2), and the fourth switch (S4) and the sixth switch (S6) are turned off under the action of the third clock signal (DCLK1), the second current source (I REF2 ) via the first node (N) A The first capacitor (C1) and the third capacitor (C3) are charged, and the second capacitor (C2) is discharged to the non-inverting input terminal of the error amplifier (100).

8. The frequency-locked loop circuit according to claim 6, characterized in that, When the first switch (S1) in the switched capacitor module (400) is turned on under the action of the first clock signal (CLK1), the second switch (S2) in the switched capacitor module (400) is turned off under the action of the second clock signal (CLK2), the third switch (S3) and the fifth switch (S5) in the switched capacitor module (400) are turned off under the action of the fourth clock signal (DCLK2), and the fourth switch (S4) and the sixth switch (S6) in the switched capacitor module (400) are turned on under the action of the third clock signal (DCLK1), the second current source (I REF2 ) via the first node (N) A The first capacitor (C1) and the second capacitor (C2) in the switched capacitor module (400) are charged, and the third capacitor (C3) in the switched capacitor module (400) is discharged to the non-inverting input terminal of the error amplifier (100).

9. The frequency-locked loop circuit according to claim 6, characterized in that, When the first switch (S1) in the switched capacitor module (400) is turned off under the action of the first clock signal (CLK1), the second switch (S2) in the switched capacitor module (400) is turned on under the action of the second clock signal (CLK2), the third switch (S3) and the fifth switch (S5) in the switched capacitor module (400) are turned on under the action of the fourth clock signal (DCLK2), and the fourth switch (S4) and the sixth switch (S6) in the switched capacitor module (400) are turned off under the action of the third clock signal (DCLK1), the second current source (I REF2 ) via the first node (N) A The third capacitor (C3) in the switched capacitor module (400) is charged, the first capacitor (C1) in the switched capacitor module (400) is discharged to ground, and the second capacitor (C2) in the switched capacitor module (400) is discharged to the non-inverting input terminal of the error amplifier (100).

10. The frequency-locked loop circuit according to claim 6, characterized in that, When the first switch (S1) in the switched capacitor module (400) is turned on under the action of the first clock signal (CLK1), the second switch (S2) in the switched capacitor module (400) is turned off under the action of the second clock signal (CLK2), the third switch (S3) and the fifth switch (S5) in the switched capacitor module (400) are turned on under the action of the fourth clock signal (DCLK2), and the fourth switch (S4) and the sixth switch (S6) in the switched capacitor module (400) are turned off under the action of the third clock signal (DCLK1), the second current source (I REF2 ) via the first node (N) A The first capacitor (C1) is charged to the second capacitor (C2) in the switched capacitor module (400), the first capacitor (C1) is discharged to ground, and the third capacitor (C3) is discharged to the non-inverting input terminal of the error amplifier (100).

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