Delay-locked loop circuit and semiconductor device

Abstract

The disclosure provides a delay-locked loop circuit and a semiconductor device, and relates to the technical field of semiconductors. The delay-locked loop circuit comprises a DCC CLK module, a DCC CMD module and a delay-locked loop DLL controller. The DLL controller generates a DCC control code based on a duty cycle detection result of a target clock signal. The DCC CLK module adjusts the clock duty cycle of an original clock signal to a target duty cycle based on the DCC control code, and obtains a clock correction signal. A first adjusting module adjusts the timing deviation of the clock correction signal. The DCC CMD module adjusts an in-chip command signal based on the DCC control code, and obtains a command correction signal. A second adjusting module adjusts the time delay of the command signal path relative to the clock signal path. Through the technical scheme of the disclosure, the timing deviation generated by the DCC module is compensated for, so that the timing synchronization accuracy of the clock and the command signal in a high-speed scene is improved.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a time-delay phase-locked loop circuit and a semiconductor device. Background Technology

[0002] With the development of integrated circuits, various computing chips have increasingly higher requirements for data transmission speed. At high speeds, the data sampling window is extremely small. For DRAM (Dynamic Random Access Memory), data reading and writing must be precisely synchronized and controlled by the clock signal CLK (Clock) and the command signal CMD (Command). Any slight delay, jitter, or timing deviation may lead to data sampling errors or even system crashes. Therefore, the timing matching of the CLK signal and the CMD signal has become the main bottleneck restricting the high-frequency performance of DRAM.

[0003] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0004] The purpose of this disclosure is to provide a time-delay phase-locked loop circuit and a semiconductor device that at least to some extent overcomes the problem of insufficient timing matching between the CLK signal and the CMD signal in related technologies.

[0005] Other features and advantages of this disclosure will become apparent from the following detailed description, or may be learned in part from practice of this disclosure.

[0006] According to one aspect of this disclosure, a delay-locked loop (PLL) circuit is provided, comprising: a clock signal path including a clock duty cycle correction (DCC) CLK module and a first adjustment module connected in series, configured to receive an original clock signal and output a corresponding output signal; a command signal path including a command duty cycle correction (DCC) CMD module and a second adjustment module connected in series, configured to receive an on-chip command signal and output a synchronization command signal; a delay-locked loop (DLL) controller configured to receive a duty cycle detection result for the corresponding output signal and generate a DCC control code based on the detection result; the DCC CLK module adjusting the clock duty cycle of the original clock signal to a target duty cycle based on the DCC control code to obtain a corresponding clock correction signal; the first adjustment module being configured to adjust the timing deviation of the clock correction signal to adjust the corresponding output signal to the target clock signal; the DCC CMD module performing a DCC control on the on-chip command signal based on the DCC control code. The CLK module matching adjustment process obtains a command correction signal. The second adjustment module is configured to adjust the command correction signal to adjust the delay of the command signal path relative to the clock signal path, so that the command signal path outputs the synchronization command signal. The relative delay between the synchronization command signal and the target clock signal is consistent with the relative delay between the original clock signal and the on-chip command signal.

[0007] In one embodiment of this disclosure, the first adjustment module is connected to the DLL controller to receive a first adjustment signal from the DLL controller. The first adjustment module configures the drive parameters or capacitive load of its own path based on the first adjustment signal to adjust the timing deviation of the clock correction signal and outputs a clock adjustment signal. The second adjustment module is connected to the DLL controller to receive a second adjustment signal from the DLL controller. The second adjustment module configures the drive parameters or capacitive load of its own path based on the second adjustment signal to adjust the delay of the command signal path relative to the clock signal path and outputs a command adjustment signal.

[0008] In one embodiment of this disclosure, the DCC CLK module and the DCC CMD module are respectively connected to the DLL controller to access the DCC control code. The DCC CLK module is configured to reduce the toggle rate of the rising or falling edge of the original clock signal based on the DCC control code to adjust the duty cycle and output the clock correction signal. The DCC CMD module is configured to, when the duty cycle detection result is greater than the target duty cycle, reduce the toggle rate of the rising and falling edges of the on-chip command signal based on the DCC control code, or not adjust the rising and falling edges of the on-chip command signal, and output the command correction signal, so that the relative delay between the clock correction signal and the command correction signal is consistent with the relative delay between the original clock signal and the on-chip command signal.

[0009] In one embodiment of this disclosure, the DLL controller is further configured to: detect the relationship between the DCC control code and the compensation reference code value; if the DCC control code is greater than the compensation reference code value, generate a first compensation control signal for unilateral compensation of the clock correction signal, as the first adjustment signal; the first adjustment module includes: a CLK delay compensation module, which is connected to the DCC CLK module and the DLL controller respectively, and is configured to access the first compensation control signal and the clock correction signal, and configure the capacitive load of its own path based on the first compensation control signal to perform delay compensation on the rising edge or falling edge of the clock correction signal that reduces the flip rate, thereby obtaining a clock adjustment signal.

[0010] In one embodiment of this disclosure, the CLK delay compensation module includes: a plurality of first MOS capacitor unit branches arranged in parallel, each first MOS capacitor unit branch including a first PMOS capacitor, a first control switch, a second control switch and a first NMOS capacitor connected in series, wherein the first compensation control signal is used to close the first control switch or the second control switch in the corresponding branch, so that the first PMOS capacitor or the first NMOS capacitor is individually connected to the clock signal path to configure the capacitive load for single-sided delay compensation.

[0011] In one embodiment of this disclosure, the DLL controller is further configured to: query the one-sided timing offset amplitude of the clock correction signal using the DCC control code as an index; determine the number of the first MOS capacitor cell branches to be turned on and the type of control switch to be closed based on the one-sided timing offset amplitude; and generate a level command to turn on the first control switch or the second control switch based on the number of the first MOS capacitor cell branches and the type of control switch to be closed, as the first compensation control signal.

[0012] In one embodiment of this disclosure, the DLL controller is further configured to: generate a second compensation control signal for bilateral compensation of the command correction signal, as the first adjustment signal; the second adjustment module includes: a CMD delay compensation module, which is connected to the DCC CMD module and the DLL controller respectively, and is configured to access the second compensation control signal and the command correction signal, and configure the capacitive load of its own path based on the second compensation control signal to perform delay compensation on the rising edge and the falling edge of the command correction signal adjusted by the synchronization edge, so as to obtain the command adjustment signal.

[0013] In one embodiment of this disclosure, the CMD delay compensation module includes: a plurality of second MOS capacitor unit branches arranged in parallel, each second MOS capacitor unit branch including a second PMOS capacitor, a third control switch, a fourth control switch, and a second NMOS capacitor connected in series, wherein the second compensation control signal is used to close the third control switch and the fourth control switch in the corresponding branch, so that the second PMOS capacitor and the second NMOS capacitor are connected to the command signal path to configure the capacitive load for bilateral delay compensation.

[0014] In one embodiment of this disclosure, the DLL controller is further configured to: query the total timing offset amplitude corresponding to the bilateral edges of the command correction signal using the DCC control code as an index; determine the number of the second MOS capacitor cell branches that need to be turned on based on the total timing offset amplitude; and generate a combined level command for synchronously turning on the third control switch and the fourth control switch based on the number of the second MOS capacitor cell branches, as the second compensation control signal.

[0015] In one embodiment of this disclosure, the DCC control code is divided into multiple numerical ranges, and different numerical ranges correspond to the number of first MOS capacitor cell branches or second MOS capacitor cell branches that are turned on. The higher the code value of the DCC control code, the more first MOS capacitor cell branches or second MOS capacitor cell branches that are turned on are corresponding to.

[0016] In one embodiment of this disclosure, the first adjustment module includes: a DCC CLK mirror module, which is connected to the DCC CLK module and the DLL controller respectively, forms a mirror topology with the DCC CLK module for path load matching, is configured to receive the clock correction signal and the DCC control code as the first adjustment signal, configure the drive parameters of its own path based on the DCC control code, and output a clock adjustment signal to reduce the native static timing offset of the DCC CLK module.

[0017] In one embodiment of this disclosure, the second adjustment module includes: a DCC CMD mirror module, connected to both the DCC CMD module and the DLL controller, forming a mirror topology with the DCC CMD module for path load matching to reduce the native static timing offset of the DCC CMD module, configured to access the DCC control code and the command correction signal as the second adjustment signal, configure the drive parameters of its own path based on the DCC control code, and output a command adjustment signal to reduce the native static timing offset of the DCC CMD module, wherein, when the detection result is greater than the target duty cycle, the DCC CMD mirror module is further configured to reduce the toggling rate of the falling edge of the command correction signal based on the DCC control code.

[0018] In one embodiment of this disclosure, a first delay processing component is further included. The first delay processing component includes a first delay line and a clock tree connected in series. The first delay line is connected to a clock adjustment signal output from the first adjustment module, and the clock adjustment signal is processed to adjust the transmission delay, and a clock delay processing signal is output. The clock tree is used to perform fan-out buffering on the clock delay processing signal and output the target clock signal.

[0019] In one embodiment of this disclosure, it further includes: a phase detector configured to receive the original clock signal and the clock delay processing signal, and to perform a phase comparison between the original clock signal and the clock delay processing signal to obtain a phase comparison result; the DLL controller receives the phase comparison result and outputs the delay level of the transmission delay adjustment processing to the first delay line according to the phase comparison result.

[0020] In one embodiment of this disclosure, a second delay processing component is further included. The second delay processing component includes a second delay line and a signal line connected in series. The second delay line is connected to a command adjustment signal output by the second adjustment module to perform transmission delay adjustment processing on the command adjustment signal and output a command delay processing signal. The signal line is used to perform long-line buffering processing on the command delay processing signal and output the synchronization command signal.

[0021] In one embodiment of this disclosure, it further includes: a duty cycle detection module, configured to access the corresponding output signal and output the duty cycle detection result of the target clock signal.

[0022] According to another aspect of this disclosure, a semiconductor device is provided, comprising: a logic controller configured to receive an original clock signal, an original command signal, and an address signal, and to sample and decode the original command signal and the address signal based on the original clock signal to obtain an on-chip command signal; a time-locked loop circuit provided in the above embodiments configured to receive the original clock signal and the on-chip command signal, and to output a target clock signal and a synchronization command signal; a first I / O drive buffer configured to receive the target clock signal, and to drive and amplify the target clock signal before outputting it from a clock signal output terminal; and a second I / O drive buffer configured to receive the synchronization command signal, and to drive and amplify the synchronization command signal before outputting it from a data signal output terminal.

[0023] The time-delay phase-locked loop circuit and semiconductor device provided in the embodiments of this disclosure generate DCC control codes based on the clock duty cycle deviation fed back by the duty cycle detection module through the DLL controller. This enables the DCC CLK module and the DCC CMD module to complete the 50% standard duty cycle correction of the clock and the synchronization edge matching of the command signal based on the same DCC control code. Furthermore, a first adjustment module is configured to adjust the DCC based on the DCC control code. The offset generated by the slow edge of the CLK module is compensated with reverse delay. The second adjustment module determines the offset amplitude of the CMD signal path after amplification based on the same DCC control code and applies an appropriate reverse compensation delay. The two adjustment modules work together to reduce the inherent timing deviation of the DCC module and suppress the offset amplification phenomenon of fast edges in the CMD signal path. Through the differentiated delay compensation of the first and second adjustment modules, the first delay processing component outputs the target clock signal and the second delay processing component outputs the synchronization command signal. The relative delay between the synchronization command signal and the target clock signal can be kept consistent with the original input signal. While realizing duty cycle adjustment and timing matching through the DCC module, the defect of timing offset introduced by the DCC module is made up, which is conducive to improving the timing synchronization accuracy of the clock and command signals in high-speed scenarios.

[0024] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0025] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0026] Figure 1This diagram illustrates a comparison between an ideal waveform and the actual waveform of a CMD signal after processing by the DCC CMD module. Figure 2 This diagram illustrates a comparison between an ideal waveform and the actual waveform of the CMD signal after processing by the DCC CMD module. Figure 3 A schematic block diagram of a delay phase-locked loop circuit according to an embodiment of the present disclosure is shown; Figure 4 This diagram shows a comparison between the waveform of the original signal and the waveform of the corrected signal after correction by the DCC module in an embodiment of this disclosure. Figure 5 Show the generation Figure 4 A schematic diagram of the DCC CLK module for the CLK_DCC signal; Figure 6 This shows the CLK signal passing through Figure 5 A schematic diagram of the ideal waveform processed by the DCC CLK module in the diagram; Figure 7 Show the generation Figure 4 A schematic diagram of the DCC CMD module for the DCC_CMD signal in the middle; Figure 8 The CMD signal is shown passing through Figure 7 A schematic diagram of the ideal waveform processed by the DCC CMD module in the diagram; Figure 9 A comparison diagram is shown between the waveform of another original signal in an embodiment of this disclosure and the waveform of the corrected signal after correction by the DCC module. Figure 10 Show the generation Figure 9 A schematic diagram of the DCC CLK module for the CLK_DCC signal; Figure 11 This shows the CLK signal passing through Figure 10 A schematic diagram of the ideal waveform processed by the DCC CLK module in the diagram; Figure 12 Show the generation Figure 9 A schematic diagram of the DCC CMD module for the DCC_CMD signal in the middle; Figure 13 The CMD signal is shown passing through Figure 12 A schematic diagram of the ideal waveform processed by the DCC CMD module in the diagram; Figure 14 A circuit diagram of a CLK delay compensation module according to an embodiment of the present disclosure is shown; Figure 15 A circuit diagram of a CMD delay compensation module according to an embodiment of the present disclosure is shown; Figure 16The diagram illustrates a cascaded circuit of a DCC CLK module and a DCC CLK mirror module according to an embodiment of this disclosure, as well as the waveforms generated by the step-by-step processing. Figure 17 The diagram illustrates a cascaded circuit of another DCC CLK module and a DCC CLK mirror module in an embodiment of this disclosure, along with the waveforms generated by the step-by-step processing. Figure 18 The diagram illustrates a cascaded circuit of a DCC CMD module and a DCC CMD mirror module according to an embodiment of this disclosure, as well as the waveforms generated by the step-by-step processing. Figure 19 This illustration shows another cascaded circuit of a DCC CMD module and a DCC CMD mirror module in an embodiment of this disclosure, as well as the waveforms generated by the step-by-step processing. Figure 20 A schematic diagram of the structure of a semiconductor device according to an embodiment of the present disclosure is shown; Figure 21 A schematic diagram of the structure of another semiconductor device according to an embodiment of this disclosure is shown. Detailed Implementation

[0027] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that this disclosure will be more comprehensive and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0028] Furthermore, the accompanying drawings are merely illustrative of this disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0029] As computing demands for data rates increase, DRAM operating frequencies are constantly rising, and data sampling windows are becoming increasingly narrow. Timing matching between the clock CLK signal and the command CMD signal has become crucial for high-frequency performance.

[0030] In mass-produced DRAM, an EFUSE (electronic fuse) module can be integrated inside the chip. By programming fixed compensation parameters, the static timing offset compensation between the clock signal path and the command signal path is locked, correcting the inter-chip timing differences caused by the wafer process. Although this module can improve the yield, it requires additional testing and adjustment of the chip during the testing process, which leads to an increase in testing time and cost.

[0031] To save testing time and costs, DCC (Duty Cycle Corrector) circuits are set on both the clock signal path and the command signal path to achieve duty cycle correction and phase synchronization, thereby reducing the overhead of EFUSE resources. Although setting up DCC CLK and DCC CMD modules can improve the timing synchronization between CMD and CLK signals, in practical applications, on the one hand, due to the existence of voltage intermediate states in the DCC circuit, the current sources of the upper and lower branches may be turned on simultaneously at times. The difference in the strength of the upper and lower current sources will introduce timing offsets in the CMD and CLK signals. On the other hand, because the parasitic capacitance of the output nodes of the clock signal path and the command signal path is inconsistent, the capacitance difference will further aggravate the timing offset.

[0032] In addition, since the DCC CLK module corrects for slow edges that participate in duty cycle adjustment, while the DCC CMD module only generates timing offset for fast edges that are not subject to duty cycle adjustment, when the same degree of current mismatch and capacitance mismatch is applied to the fast edges of the command signal path, the effect of timing offset will be amplified, resulting in a further increase in the timing offset amplitude of the output signal of the command signal path.

[0033] like Figure 1 As shown, in the CMD DCC module operating with a clock duty cycle of less than 50%, the rising and falling edges of the command signal are not adjusted. That is, the rising and falling edges of the signal are fast edges without duty cycle adjustment. Waveforms 1, 2, and 3 correspond to the waveforms of the input original CMD signal, the signal output from the intermediate node of the first-stage inverter, and the output CMD_DCC signal, respectively. The transition range of the fast edge level switching is narrow. The solid line a is the ideal waveform without offset, while the dashed line b is the actual waveform with timing offset caused by current mismatch and / or capacitor mismatch.

[0034] like Figure 2As shown, in the CMD DCC module operating with a clock duty cycle greater than 50%, both the rising and falling edges of the command signal are adjusted. That is, by adjusting the width-to-length ratio of the internal driving MOS transistor in the module, the switching rate of both the rising and falling edges of the signal is slowed down. In other words, the rising and falling edges of the CMD signal are both fast edges, which is changed to the rising and falling edges of the CMD_DCC signal being both slow edges. Waveforms 1, 2, and 3 correspond to the waveforms of the original input CMD signal, the signal output from the intermediate node of the first-stage inverter, and the output CMD_DCC signal, respectively. The level transition window is greatly widened. The dashed line a is the ideal waveform, and the dashed line b is the actual waveform with timing offset.

[0035] To simultaneously address the inherent timing skew of the DCC module and the amplification of fast-edge timing skew in the command signal path, this disclosure proposes a time-delay phase-locked loop (TLL) circuit. The DLL controller generates DCC control codes based on the clock duty cycle deviation fed back by the duty cycle detection module. This enables the DCC CLK and DCC CMD modules to perform 50% standard duty cycle correction and command signal synchronization edge matching based on the same DCC control code. Furthermore, a first adjustment module is configured to adjust the DCC based on the DCC control code. The offset generated by the slow edge of the CLK module is compensated with reverse delay. The second adjustment module determines the offset amplitude of the CMD signal path after amplification based on the same DCC control code and applies an appropriate reverse compensation delay. The two adjustment modules work together to reduce the inherent timing deviation of the DCC module and suppress the offset amplification phenomenon of fast edges in the CMD signal path. Through the differentiated delay compensation of the first and second adjustment modules, the first delay processing component outputs the target clock signal and the second delay processing component outputs the synchronization command signal. The relative delay between the synchronization command signal and the target clock signal can be kept consistent with the original input signal. While realizing duty cycle adjustment and timing matching through the DCC module, the defect of timing offset introduced by the DCC module is made up, which is conducive to improving the timing synchronization accuracy of the clock and command signals in high-speed scenarios.

[0036] As will be understood by those skilled in the art, in the scheme disclosed herein, access and input represent the same operation, and access and output represent the same operation, and can be used interchangeably.

[0037] like Figure 3 As shown, a time-delay phase-locked loop circuit according to an embodiment of the present disclosure includes: The clock signal path 10 includes a series-connected clock duty cycle correction DCC CLK module and a first adjustment module. The DCCCLK module is configured to receive the original clock signal. The goal of the clock signal path 10 is to output the target clock signal. It is understood by those skilled in the art that, in this disclosure, before the clock signal path 10 is able to output the target clock signal, the output signal is referred to as the output signal corresponding to the clock signal path.

[0038] In some embodiments, the clock signal path 10 may further include a first delay processing component for outputting a target clock signal.

[0039] Command signal path 20 includes a series-connected command duty cycle correction DCC CMD module and a second adjustment module. The DCCCMD module is configured to receive on-chip command signals, and command signal path 20 is configured to output synchronous command signals.

[0040] In some embodiments, the command signal path 20 may further include a second delay processing component for outputting a synchronization command signal.

[0041] The signal output from the first adjustment module is called the clock adjustment signal, and the signal output from the second adjustment module is called the command adjustment signal, to distinguish them from the clock correction signal output by the DCC CLK module and the command correction signal output by the DCC CMD module.

[0042] The duty cycle detection module DCD is configured to receive the corresponding output signal and output the duty cycle detection result of the target clock signal. It is understood by those skilled in the art that when the duty cycle detection result of the duty cycle detection module DCD is the target duty cycle, i.e., 50%, the corresponding output signal output by the clock signal path 10 after processing by the DCC CLK module and the first adjustment module is called the target clock signal.

[0043] The Delay Locked Loop (DLL) controller is configured to receive the duty cycle detection result for the corresponding output signal and generate DCC control code based on the detection result. The DCC CLK module adjusts the clock duty cycle of the original clock signal to the target duty cycle based on the DCC control code and obtains the corresponding clock correction signal. The first adjustment module is configured to adjust the timing deviation of the clock correction signal to adjust the corresponding output signal to the target clock signal.

[0044] The DLL controller is connected to the DCC CLK module and the first adjustment module, respectively.

[0045] In one embodiment of this disclosure, the first adjustment module is connected to the DLL controller to receive a first adjustment signal from the DLL controller. The first adjustment module configures the drive parameters or capacitive load of its own path based on the first adjustment signal to adjust the timing deviation of the clock correction signal and outputs a clock adjustment signal.

[0046] In some embodiments, configuring the driving parameters of its own path can be configured by configuring the width-to-length ratio of the driving MOS transistor inside the first adjustment module, and configuring the capacitive load of its own path can be configured by connecting an appropriate number of capacitive devices to the clock signal path and introducing a controllable delay by changing the equivalent capacitance value of the path.

[0047] The target clock signal is output by the first delay processing component.

[0048] In some embodiments, the DCC control code is generated by the DLL controller based on the clock duty cycle deviation output by the duty cycle detection module. The control code simultaneously carries the MOS width-to-length ratio adjustment range required to correct the original clock to 50% duty cycle, as well as the inherent edge offset of the DCC CLK module and DCC CMD module under this range due to current mismatch, parasitic capacitance, etc.

[0049] In some embodiments, the first adjustment signal received by the first adjustment module may be a DCC control code directly issued by the DLL controller, or a dedicated compensation control signal for the clock signal path 10 generated by the DLL controller based on the DCC control code, in order to compensate for the timing offset of the CLK signal generated by the DCC CLK module.

[0050] The DCC CMD module performs adjustment processing on the on-chip command signal based on the DCC control code to match the DCC CLK module and obtains the command correction signal. The second adjustment module is used to adjust the command correction signal to adjust the time delay of the command signal path relative to the clock signal path, so that the command signal path outputs a synchronous command signal.

[0051] The DLL controller is connected to the DCC CMD module and the second adjustment module, respectively.

[0052] In one embodiment of this disclosure, the second adjustment module is connected to the DLL controller to receive a second adjustment signal from the DLL controller. The second adjustment module configures the drive parameters or capacitive load of its own path based on the second adjustment signal to adjust the time delay of the command signal path relative to the clock signal path and outputs a command adjustment signal.

[0053] In some embodiments, configuring the driving parameters of its own path can be configured by configuring the width-to-length ratio of the driving MOS transistor inside the second adjustment module, and configuring the capacitive load of its own path can be configured by connecting an appropriate number of capacitive devices to the command signal path to adjust the overall transmission delay of the command signal path relative to the clock signal path.

[0054] The synchronization command signal is received by the second delay processing component.

[0055] In some embodiments, the second adjustment signal received by the second adjustment module may be a DCC control code directly issued by the DLL controller, or a dedicated compensation control signal for the command signal path 20 generated by the DLL controller based on the DCC control code, in order to compensate for the timing offset of the CMD signal generated by the CMD module.

[0056] The relative delay between the synchronization command signal and the target clock signal is consistent with the relative delay between the original clock signal and the on-chip command signal.

[0057] In this embodiment, the delay-locked loop (PLL) circuit uses a DLL controller to generate DCC control codes based on the clock duty cycle deviation fed back by the duty cycle detection module. This enables the DCC CLK module and the DCC CMD module to complete 50% standard duty cycle correction of the clock and synchronization edge matching of the command signal based on the same DCC control code. Furthermore, the first adjustment module adjusts the DCC based on the DCC control code. The offset generated by the slow edge of the CLK module is compensated with reverse delay. The second adjustment module determines the offset amplitude of the CMD signal path after amplification based on the same DCC control code and applies an appropriate reverse compensation delay. The two adjustment modules work together to reduce the inherent timing deviation of the DCC module and suppress the offset amplification phenomenon of fast edges in the CMD signal path. Through the differentiated delay compensation of the first and second adjustment modules, the first delay processing component outputs the target clock signal and the second delay processing component outputs the synchronization command signal. The relative delay between the synchronization command signal and the target clock signal can be kept consistent with the original input signal. While realizing duty cycle adjustment and timing matching through the DCC module, the defect of timing offset introduced by the DCC module is made up, which is conducive to improving the timing synchronization accuracy of the clock and command signals in high-speed scenarios.

[0058] In one embodiment of this disclosure, the DCC CLK module and the DCC CMD module are respectively connected to the DLL controller to access DCC control codes. The DCC CLK module is configured to reduce the toggle rate of the rising or falling edge of the original clock signal based on the DCC control code to adjust the duty cycle and output a clock correction signal. If the duty cycle detection result is greater than the target duty cycle (typically set to 50%), the DCC CMD module is configured to reduce the toggle rate of the rising and falling edges of the on-chip command signal based on the DCC control code. If the duty cycle detection result is less than the target duty cycle, no toggle rate adjustment is made for the rising and falling edges of the on-chip command signal to maintain the aspect ratio of the MOS transistor and finally output a command correction signal so that the clock correction signal and the command correction signal maintain their original relative delay.

[0059] The CLK_DCC module receives the DCC control code from the DLL controller, adjusts the driving capability of the internal MOS transistor based on the control code, reduces the toggle rate of the rising or falling edge of the original clock signal, adjusts the duty cycle by changing the duration of the high and low levels, and outputs a clock correction signal.

[0060] Reference Figure 4 and Figure 5 When the duty cycle detection result is that the clock duty cycle is greater than 50%, the DCC control code configures the DCCLK module to reduce the signal falling edge switching rate, lengthen the low level duration, and compress the high level duration, thereby reducing the clock duty cycle to 50%.

[0061] like Figure 4 As shown, since the duty cycle of the original clock CLK signal is greater than 50%, the rising and falling edges of the original CMD signal are aligned with the rising edge of the original CLK signal. After correction by the CLK DCC module of the clock signal path, the CLK_DCC signal is output, and the high-level duration is compressed to a standard duty cycle close to 50%. The corresponding command signal path is corrected by the CMD DCC module and outputs the CMD_DCC signal, so that the CMD_DCC signal maintains the rising edge timing matching relationship between the CMD signal and the CLK signal relative to the CLK signal, thereby realizing clock duty cycle correction while preserving the original timing offset characteristics of the CLK signal and CMD.

[0062] like Figure 5As shown, the DCC CLK module is a two-stage cascaded CMOS inverter topology. Each stage of the CMOS inverter consists of a stacked PMOS transistor and a pull-down NMOS transistor. The source of the PMOS transistor is connected to the power supply, and the source of the NMOS transistor is grounded. The two stages of inverters are connected in series to form a signal transmission path. Both the PMOS and NMOS transistors support independent adjustment of their width-to-length ratio (W / L). By reducing the width-to-length ratio (W / L) of the pull-down NMOS in the first stage and the width-to-length ratio (W / L) of the pull-up PMOS in the second stage, the switching rate of the corresponding transistors is reduced.

[0063] like Figure 6 As shown, waveform 1 is the original clock signal; waveform 2 is the waveform of waveform 1 after the W / L ratio of the pull-down transistor in the first-stage CMOS inverter is reduced, resulting in a slower falling edge and a longer low-level duration; waveform 3 is the waveform of waveform 3 after the W / L ratio of the pull-up transistor in the second-stage CMOS inverter is reduced, resulting in a slower rising edge and a shorter high-level duration. By synchronously stretching the low-level range and compressing the high-level range, the waveform is adjusted and corrected to the target duty cycle, which deviates from the original clock by 50%. Figure 1 The CLK_DCC signal in the system.

[0064] Reference Figure 4 and Figure 7 When the duty cycle detection result is that the clock duty cycle is greater than 50%, the toggle rate of the corresponding edge of the on-chip command signal is reduced based on the same DCC control code. Specifically, two-stage series inverters are set in the command signal path. According to the DCC control code, the W / L ratio of the PMOS and NMOS transistors in the two-stage inverters is reduced synchronously, and the rising and falling edges of the command signal are slowed down synchronously, so as to obtain a command correction signal with smooth edges and a duty cycle matching clock correction signal.

[0065] like Figure 8 As shown, waveform 1 is the waveform of the original input CMD signal, waveform 2 is the waveform of the intermediate node signal output by the first stage inverter, and waveform 3 is the waveform of the corrected CMD_DCC signal output by the second stage. By reducing the rising and falling edge toggling rates of the clock correction signal relative to the on-chip command signal, the clock correction signal and the command correction signal maintain their original relative time delay.

[0066] The DCC_CMD module is used to perform matching adjustments following the clock signal path, ensuring that the output command correction signal and the clock correction signal maintain their original relative time delay.

[0067] Reference Figure 9 and Figure 10 When the duty cycle detection result is that the clock duty cycle is less than 50%, the DCC control code configures the DCCLK module to reduce the signal rising edge toggling rate, lengthen the high level duration, and compress the low level duration, thereby increasing the clock duty cycle to 50%.

[0068] Reference Figure 9 and Figure 12 When the duty cycle detection result is that the clock duty cycle is less than 50%, the DCC CMD module does not adjust the rising and falling edge toggling rates of the on-chip command signal based on the DCC control code, and directly outputs the command correction signal.

[0069] like Figure 9 As shown, the duty cycle of the original clock CLK signal is less than 50%. The rising and falling edges of the original CMD signal are aligned with the rising edge of the original CLK signal. After DCC correction, the CLK signal is converted into the CLK_DCC signal. The high-level range is stretched to close to the standard 50% duty cycle. After corresponding DCC correction, the CMD signal is output as the CMD_DCC signal. The edge offset of the synchronous matching clock signal path is used to preserve the original inherent relative delay relationship between CLK and CMD. This ensures that the CMD_DCC signal maintains the rising edge timing matching relationship between the CMD signal and the CLK signal relative to the CLK_DCC signal.

[0070] like Figure 10 As shown, under the condition of duty cycle less than 50%, CLK_DCC includes a two-stage inverter circuit structure. By reducing the width-to-length ratio W / L of the first-stage pull-up PMOS and the second-stage pull-down NMOS, the signal switching rate of the corresponding transistor is reduced.

[0071] like Figure 11 As shown, waveform 1 is the waveform of the original input CLK signal, waveform 2 is the waveform of the intermediate node signal output by the first stage inverter, and waveform 3 is the waveform of the second stage output correction clock CLK_DCC signal, which corrects the original clock signal with a duty cycle of less than 50% to a duty cycle of 50%.

[0072] like Figure 12 As shown, under the condition that the duty cycle is less than 50%, the two-stage inverter circuit structure of the DCC CMD module for duty cycle correction of the command signal path does not require adjustment of the transistor width-to-length ratio W / L, and both stages of inverters maintain symmetrical standard driving capability.

[0073] like Figure 13As shown, waveforms 1, 2, and 3 correspond to the input waveform, intermediate node waveform, and output waveform of the CMD signal, respectively. This circuit does not change the self-edge flip rate of the CMD signal; it only serves as a synchronization matching path, replicating the overall timing offset introduced by the clock DCC. This ensures that the relative delay between the corrected CMD_DCC signal and the CLK_DCC signal is consistent with the original signal, without adding any additional timing deviation. In one embodiment of this disclosure, the DLL controller is further configured to: detect the relationship between the DCC control code and the compensation reference code value; if the DCC control code is greater than the compensation reference code value, generate a first compensation control signal for unilateral compensation of the clock correction signal and a second compensation signal for bilateral compensation of the command correction signal.

[0074] In some embodiments, the DLL controller compares the DCC control code with a preset compensation reference code. When the DCC control code is greater than the compensation reference code, it performs encoding conversion based on the one-sided timing offset of the slow edge of the signal output by the DCC CLK module corresponding to the DCC control code to generate the first compensation control signal.

[0075] In some embodiments, the DLL controller synchronously indexes the total timing offset amplitude after the fast edge amplification of the CMD signal path based on the same DCC control code that is greater than the compensation reference code, and encodes it to generate a second compensation control signal.

[0076] In this embodiment, the two compensation control signals are distinguished by comparing the values ​​of the DCC control code and the compensation reference code. The two signals are matched to the differentiated compensation requirements of the clock signal path single-sided offset and the command signal path double-sided amplification offset, respectively. This enables automatic switching between the two compensation modes, accurately matches the timing distortion characteristics of the two paths, distinguishes between single-sided and double-sided compensation logic from the control source, and provides matching switching control instructions for the subsequent delay compensation module.

[0077] In one embodiment of this disclosure, the DLL controller is further configured to: detect the relationship between the DCC control code and the compensation reference code value; if the DCC control code is greater than the compensation reference code value, generate a first compensation control signal for unilateral compensation of the clock correction signal.

[0078] The first adjustment module includes a CLK delay compensation module, which is connected to the DCC CLK module and the DLL controller respectively. It is configured to receive a first compensation control signal and a clock correction signal, and to configure the capacitive load of its own path based on the first compensation control signal to perform delay compensation on the rising or falling edge of the clock correction signal that reduces the toggle rate, so as to obtain a clock adjustment signal.

[0079] The CLK delay compensation module is used to adjust the delay of the clock correction signal.

[0080] In some embodiments, the CLK delay compensation module receives the clock correction signal output by the DCC CLK module and the first compensation control signal issued by the DLL controller. The CLK delay compensation module may include multiple capacitive devices. The specific number of capacitive devices is determined based on the first compensation control signal so as to connect an appropriate number of capacitive devices in the clock signal path to complete the capacitive load configuration. Additional capacitive load is introduced only for the single-sided slow edge in the clock correction signal whose switching rate is reduced by the DCC CLK module. The connected capacitive devices generate a reverse delay to offset the timing offset inherent in the single edge.

[0081] In this embodiment, the CLK delay compensation module only performs targeted delay compensation on a single slow edge with timing offset, without introducing unnecessary load delay on the other edge without distortion. This ensures that the overall waveform symmetry of the clock correction signal is not destroyed by the compensation operation, which helps to reduce the unilateral timing deviation caused by the DCC CLK module adjusting the duty cycle.

[0082] In one embodiment of this disclosure, the CLK delay compensation module includes: a plurality of first MOS capacitor unit branches arranged in parallel, each first MOS capacitor unit branch including a first PMOS capacitor, a first control switch, a second control switch and a first NMOS capacitor connected in series, wherein a first compensation control signal is used to close the first control switch or the second control switch in the corresponding branch, so that the first PMOS capacitor or the first NMOS capacitor is individually connected to the clock signal path to configure a capacitive load for unilateral delay compensation.

[0083] like Figure 14 As shown, the CLK delay compensation module consists of 8 parallel branches of identical first MOS capacitor units, numbered 0 to 7. For any branch of the first MOS capacitor unit, the internal series components are arranged in the following order: first PMOS capacitor, first control switch, second control switch, and first NMOS capacitor. The first PMOS capacitors corresponding to branches 0 to 7 are MP0, MP1 to MP7, respectively, and the first NMOS capacitors corresponding to branches 0 to 7 are MN0, MN1 to MN7, respectively. The first control switches and second control switches corresponding to branches 0 to 7 are K0, K1 to K15, respectively. An intermediate node is led out between the first and second control switches of each branch, such as the node between K0 and K1. All intermediate nodes of the 8 branches can be electrically connected to form a common trace and connect to the external clock correction signal.

[0084] In one embodiment of this disclosure, the DLL controller is further configured to: query the one-sided timing offset amplitude of the clock correction signal using the DCC control code as an index; determine the number of first MOS capacitor cell branches to be turned on and the type of control switch to be closed based on the one-sided timing offset amplitude; and generate a level command to turn on the first control switch or the second control switch based on the number of first MOS capacitor cell branches and the type of control switch to be closed, as a first compensation control signal.

[0085] In some embodiments, the CLK delay compensation module consists of multiple parallel first MOS capacitor unit branches. Each branch includes a first PMOS capacitor, a first control switch, a second control switch, and a first NMOS capacitor connected in series. After the DLL controller obtains the single-sided timing offset amplitude through the DCC control code index, it determines the number of branches and switch types to be turned on and outputs a first compensation control signal. This signal selects only one switch in the closed branch. If the first control switch is closed, only the first PMOS capacitor is connected to the clock signal path. If the second control switch is closed, only the first NMOS capacitor is connected to the clock signal path. Single-sided delay compensation for only a single edge is achieved based on the single-sided capacitor load.

[0086] In this embodiment, by adopting a multi-branch parallel segmented capacitor load architecture, compensation capacitors of corresponding capacity can be dynamically connected based on the offset size corresponding to the DCC control code. The compensation delay is adaptively adjusted with the offset amplitude, which can ensure the accuracy of reducing the unilateral timing offset of the clock correction signal output by the DCC CLK module.

[0087] In one embodiment of this disclosure, the DLL controller is further configured to: generate a second compensation control signal for bilateral compensation of the command correction signal; the second adjustment module includes: a CMD delay compensation module, which is connected to the DCC CMD module and the DLL controller respectively, and is configured to access the second compensation control signal and the command correction signal, and configure the capacitive load of its own path based on the second compensation control signal to perform delay compensation on the rising edge and the falling edge of the command correction signal adjusted by the synchronization edge, so as to obtain the command adjustment signal.

[0088] The CMD delay compensation module is used to adjust the delay of the command correction signal.

[0089] In some embodiments, the CMD delay compensation module receives the command correction signal output by the DCC CMD module and the second compensation control signal issued by the DLL controller. The CMD delay compensation module may include multiple capacitive devices. The specific number of capacitive devices is determined based on the second compensation control signal so as to connect an appropriate number of capacitive devices in the command signal path to complete the capacitive load configuration. An equivalent capacitive load delay is synchronously introduced on both the rising and falling edges of the command correction signal. A synchronous reverse delay is generated by the connected capacitive devices to uniformly offset the timing offset difference formed by the synchronous amplification of both edges.

[0090] In this embodiment, the CMD delay compensation module applies equal delay compensation to the rising and falling edges of the command signal simultaneously, which can solve the problem of offset amplification caused by the fast edge of the DCC CMD module output signal being sensitive to device mismatch and parasitic parameters, and ensure that the original relative delay of the command correction signal and the clock correction signal remains unchanged.

[0091] In one embodiment of this disclosure, the CMD delay compensation module includes: a plurality of second MOS capacitor unit branches arranged in parallel, each second MOS capacitor unit branch including a second PMOS capacitor, a third control switch, a fourth control switch and a second NMOS capacitor connected in series, wherein a second compensation control signal is used to close the third control switch and the fourth control switch in the corresponding branch, so that the second PMOS capacitor and the second NMOS capacitor are connected to the command signal path to configure a capacitive load for bilateral delay compensation.

[0092] like Figure 15As shown, the CMD delay compensation module consists of 8 parallel branches of identical second MOS capacitor units, numbered 8 to 15. For any branch of the second MOS capacitor unit, the vertical series arrangement of the components is as follows: second PMOS capacitor, third control switch, fourth control switch, and second NMOS capacitor. The second PMOS capacitors corresponding to branches 8 to 15 are MP8, MP9 to MP15, and the second NMOS capacitors corresponding to branches 8 to 15 are MN8, MN9 to MN15. In each branch, the third control switch corresponds to the reference numerals K16, K18...K30, and the fourth control switch corresponds to the reference numerals K17, K19...K31. An intermediate common node is led out between the third and fourth control switches of each branch. All intermediate common nodes of the 8 branches are electrically connected to each other, forming a common trace and connecting to the externally input command correction signal. When the circuit is working, the second compensation control signal can output synchronous conduction commands to the third and fourth control switches in a single branch. When the two sets of control switches in the same branch are closed at the same time, the second PMOS capacitor and the second NMOS capacitor of the branch will be connected to the command signal path at the same time, and the rising and falling edges of the command correction signal will be applied simultaneously to achieve bilateral time delay compensation and offset the total timing offset caused by the bilateral edges of the command correction signal.

[0093] In one embodiment of this disclosure, the DLL controller is further configured to: query the total timing offset amplitude corresponding to the bilateral edges of the command correction signal using the DCC control code as an index; determine the number of second MOS capacitor cell branches that need to be turned on based on the total timing offset amplitude; and generate a combined level command for synchronously turning on the third control switch and the fourth control switch based on the number of second MOS capacitor cell branches, as a second compensation control signal.

[0094] In some embodiments, the CMD delay compensation module is configured with multiple parallel second MOS capacitor unit branches. Each branch is connected in series with a second PMOS capacitor, a third control switch, a fourth control switch, and a second NMOS capacitor. The DLL controller retrieves the total offset amplitude corresponding to the bilateral edges of the command correction signal output by the DCC CMD module based on the same DCC control code, determines the number of conducting branches, and generates a second compensation control signal. This signal will synchronously close the third and fourth control switches of each selected branch, so that the PMOS capacitors and NMOS capacitors in the branch are connected in series and connected to the command signal transmission link as a whole. The capacitors on both sides jointly provide load delay and synchronously perform bilateral delay compensation for the rising and falling edges of the signal.

[0095] In this embodiment, a dual-sided compensation mode with simultaneous connection of capacitors on both sides is achieved by synchronously conducting dual switches. This mode can match the circuit characteristics of synchronous amplification of fast edge offset on both sides of the DCC CMD module output signal. Combined with the multi-branch parallel structure, the total compensation capacitor capacity is dynamically adjusted to adaptively reduce the overall timing offset generated by the DCC CMD module under different DCC adjustment levels.

[0096] In one embodiment of this disclosure, the DCC control code is divided into multiple numerical ranges, with different numerical ranges corresponding to the number of MOS capacitor cell branches that are turned on. Furthermore, the higher the code value of the DCC control code, the more first or second MOS capacitor cell branches are turned on.

[0097] In some embodiments, the compensation level is determined during the design phase because the magnitude of the DCC control code (DCC code) value is positively correlated with the magnitude of the timing offset. The compensation level is divided into multiple segments in the circuit according to the magnitude of the DCC code. Assuming the DCC code is 0~127, no offset compensation is performed in the range of 0~63, offset compensation is performed in the range of 64~96, for example, by connecting half of the compensation capacitor, and offset compensation is performed in the range of 97~127 by connecting all the compensation capacitors.

[0098] In addition, the magnitude of the offset in the circuit can be determined through simulation. That is, the correspondence between the offset and the DC code can be confirmed through simulation, thereby determining the compensation level and the number of conducting branches of the corresponding compensation capacitor and the size of the compensation delay.

[0099] In this embodiment, multiple numerical intervals are divided based on the DCC control code. The higher the code value, the more MOS capacitor unit branches are simultaneously turned on and a larger equivalent compensation capacitor is connected. The compensation delay increases stepwise as the DCC control code increases. It can adaptively match the corresponding amplitude of the reverse compensation amount according to the DCC real-time duty cycle adjustment level, so as to reduce the inherent timing offset generated by the DCC CLK module and DCC CMD module under different adjustment levels, prevent the problem of insufficient or excessive compensation, and ensure the matching accuracy of single-sided and double-sided delay.

[0100] In one embodiment of this disclosure, the first adjustment module includes: a DCC CLK mirror module, which is connected to the DCC CLK module and the DLL controller respectively, forms a mirror topology with the DCC CLK module for path load matching, is configured to access clock correction signals and DCC control codes, configure the driving parameters of its own path based on the DCC control codes, and output a clock adjustment signal to reduce the native static timing offset of the DCCCLK module.

[0101] Among them, the DCC CLK mirror module is used to adjust the electrical performance of the clock correction signal. The native static timing offset is a fixed timing deviation caused by process mismatch between the PMOS and NMOS of the inverter inside the DCC CLK module or DCC CMD module.

[0102] In some embodiments, the DCC CLK mirror module adjusts the width-to-length ratio parameter of the internal driving transistor based on the DCC control code to complete its own path driving parameter configuration, so as to match the conduction driving strength of the MOS transistor inside the DCC CLK module, and form a balanced path load based on the mirror topology, which helps to offset the unilateral static timing offset caused by the circuit asymmetry of the DCC CLK module.

[0103] In some embodiments, Figure 16 The diagram illustrates the cascaded structure of the DCC CLK module and its mirror module (i.e., the DCC CLK M module) under the condition that the duty cycle of the original clock signal is greater than 50%. The clock signal paths are cascaded sequentially, and both are two-stage CMOS inverter series structures. The arrows in the diagram represent the corresponding MOS transistors having their width-to-length ratio (W / L) reduced and their driving capability decreased, thereby slowing down the switching rate of the corresponding signal edge. The DCC CLK module internally pulls down the NMOS transistors to reduce W / L, slowing down the falling edge of the original clock, resulting in waveform 2. The subsequent DCC CLK mirror module adopts a symmetrical load topology that matches the DCC CLK, and only superimposes a synchronous load offset on this slow falling edge, corresponding to waveform 4. Finally, it outputs a clock correction signal with a controllable timing offset on a single edge, i.e., waveform 5. The dashed part in the waveform is the part that is adjusted.

[0104] In some embodiments, such as Figure 17 As shown, for the operating condition where the duty cycle of the original clock signal is less than 50%, the clock signal path includes a DCC CLK module and a DCC CLK mirror module cascaded in sequence. Both modules adopt a two-stage CMOS inverter cascaded structure. The arrows in the figure indicate that the width-to-length ratio (W / L) of the corresponding MOS transistor is reduced, thereby slowing down the corresponding signal edge switching rate by reducing the driving capability. Waveform 1 corresponds to the original clock signal and is input to the first-stage inverter of the DCC CLK module. The MOSFET on one side of this inverter has its W / L ratio reduced, slowing down a single edge (i.e., the dashed edge), resulting in waveform 2. Waveform 2 is input to the second-stage inverter of the DCC CLK module. This inverter reduces the W / L ratio of the MOSFET on the other side, further adjusting the single-edge switching speed, resulting in waveform 3. Waveform 3 is input to the first-stage inverter of the DCC CLK mirror module, resulting in waveform 4. Waveform 4 is input to the second-stage inverter of the DCC CLK mirror module, resulting in waveform 5, which is the clock adjustment signal. The mirror module uses a symmetrical load topology that matches the previous stage, superimposing a synchronous load offset on the slow edge on one side, further lengthening the edge transition time.

[0105] In this embodiment, the DCC CLK mirror module and the preceding DCC CLK module adopt the same path topology. The two are connected in series to form a symmetrical matching link. The mirror module replicates the MOS drive loss, device and trace parasitics of the original module. The static timing offsets generated by the two can offset each other, which helps to reduce the original static offset caused by the DCC CLK module adjusting the MOS width-to-length ratio on one side. It balances the transmission delay difference of the signal rising or falling edge at the electrical level, suppresses signal jitter and edge distortion caused by unilateral load imbalance, and improves signal integrity and timing margin without destroying the calibrated 50% target duty cycle.

[0106] In one embodiment of this disclosure, the second adjustment module includes: a DCC CMD mirror module, which is connected to both the DCC CMD module and the DLL controller, forming a mirror topology with the DCC CMD module for path load matching to reduce the native static timing offset of the DCC CMD module. It is configured to access DCC control codes and command correction signals, configure its own path drive parameters based on the DCC control codes, and output a command adjustment signal to reduce the native static timing offset of the DCC CMD module. Furthermore, when the duty cycle detection result is greater than 50%, the DCC CMD mirror module is also configured to reduce the toggle rate of the falling edge of the command correction signal based on the DCC control codes.

[0107] The DCC CMD mirror module is used to adjust the electrical performance of the command correction signal.

[0108] In some embodiments, the DCC CMD mirror module adjusts the width-to-length ratio of its internal driving MOS transistors according to the DCC control code to complete its own path drive parameter configuration, so that the drive conduction strength of the mirror module matches the internal driving devices of the DCC CMD module. Based on the mirror topology of the two, the path load is balanced, which helps to offset the static timing offset caused by the asymmetry of the DCC CMD module's native circuit.

[0109] In some embodiments, Figure 18The diagram illustrates a cascaded structure of a DCC CMD module and its mirror module (i.e., a DCC CMD M module) operating with a duty cycle greater than 50% for the original clock signal. The command signal path is connected in series along the signal flow direction, with the DCC CMD module and its mirror module connected sequentially. Both modules internally employ the same topology of two-stage CMOS inverters connected in series. The arrows in the diagram indicate a reduction in the width-to-length ratio (W / L) of the corresponding MOSFET. By reducing the MOSFET's drive capability, the transition time of the corresponding signal edge is lengthened. Waveform 1 is the original on-chip command signal input to the DCC CMD module. Waveform 2 is the signal waveform after processing by the first-stage inverter in the DCC CMD module, where the transition rate of the dashed edge is slowed down. Waveform 3 is the signal waveform after processing by the second-stage inverter in the DCC CMD module, where the transition rate of the dashed edge is further slowed down. Waveform 3 is input to the first-stage inverter of the DCC CMD M module, resulting in waveform 4, which includes dashed lines a and b representing the same edge as the dashed lines in waveform 3. Waveform 4 is then input to the DCC CMD module. The second-stage inverter of the M module produces waveform 5, which is the command adjustment signal. Line a is the waveform without the DCC CMD M module, and line b is the waveform processed by the DCC CMD M module. Combining lines a and b, we can see that the timing offset that was originally generated on the first edge is transferred to the second edge. Taking waveform 4 as an example, without the mirror module, the effective edge is a, and the timing offset is superimposed on a. After the DCC CMD M module is connected, the timing offset is transferred to the fast edge c, and edge a is corrected to edge b.

[0110] In some embodiments, such as Figure 19 As shown, corresponding to the operating condition where the original clock duty cycle is less than or equal to 50%, the command signal path includes a cascaded DCC CMD module and a DCC CMD mirror module. The DCC CMD module and its mirror module do not reduce the width-to-length ratio of the MOS transistors, i.e., they do not adjust the device drive capability; timing offset compensation is only achieved through the mirror topology. Waveform 1 is the original on-chip command signal input to the DCC CMD module. After passing through the first-stage CMOS inverter inside the DCC CMD module, waveform 2 is obtained. After passing through the second-stage CMOS inverter inside the DCC CMD module, waveform 3 is obtained. After passing through the first-stage CMOS inverter inside the DCC CMD M module, waveform 4 is obtained. Solid line a represents the ideal waveform, and dashed line b represents the actual waveform. After passing through the second-stage CMOS inverter inside the DCC CMD M module, waveform 5 is obtained. Figure 17 As can be seen from the CLK link, Figure 17The CLK path adjusts the edge slope by reducing the W / L ratio of the MOS transistor, which introduces timing offset due to process mismatch. The edge distortion modes of each waveform in the CMD link match those of the CLK link. During output, the phase and duty cycle deviations between the two are suppressed, and the timing correspondence between CLK and CMD is stably maintained.

[0111] In this embodiment, the original static timing offset of the command signal path is reduced by the mirror topology of the DCC CMD mirror module and the DCC CMD module. At the same time, the timing offset introduced by the duty cycle matching adjustment is limited to the fast edge, which helps to reduce the offset. The adjustment unit that physically distinguishes the rising edge and the falling edge can prevent the defect of synchronous amplification of timing offset by both edges, stabilize the original relative delay between the clock correction signal and the command correction signal, and thus improve the timing synchronization accuracy in high-speed transmission scenarios.

[0112] In one embodiment of this disclosure, the first delay processing component includes a first delay line and a clock tree connected in series. The first delay line is connected to a clock adjustment signal output from the first adjustment module, and the clock adjustment signal is processed to adjust the transmission delay, and a clock delay processing signal is output. The clock tree is used to perform fan-out buffering on the clock delay processing signal and output a target clock signal.

[0113] In one embodiment of this disclosure, it further includes: a phase detector configured to receive the original clock signal and the clock delay processing signal, and to perform a phase comparison between the original clock signal and the clock delay processing signal to obtain a phase comparison result; the DLL controller receives the phase comparison result and outputs the delay level of the transmission delay adjustment processing to the first delay line according to the phase comparison result.

[0114] In one embodiment of this disclosure, the second delay processing component includes a second delay line and a signal line connected in series. The second delay line is connected to a command adjustment signal output by the second adjustment module, performs transmission delay adjustment processing on the command adjustment signal, and outputs a command delay processing signal. The signal line is used to perform long-line buffering processing on the command delay processing signal and outputs a synchronization command signal.

[0115] A semiconductor device according to an embodiment of the present disclosure includes: a logic controller configured to receive an original clock signal, an original command signal, and an address signal, and to sample and decode the original command signal and the address signal based on the original clock signal to obtain an on-chip command signal; a time-locked loop circuit provided in the above embodiment configured to receive the original clock signal and the on-chip command signal, and to output a target clock signal and a synchronization command signal; a first I / O drive buffer configured to receive the target clock signal, and to drive and amplify the target clock signal before outputting it from a clock signal output terminal; and a second I / O drive buffer configured to receive the synchronization command signal, and to drive and amplify the synchronization command signal before outputting it from a data signal output terminal.

[0116] In some embodiments, the semiconductor device may be a DRAM memory, GDDR video memory, SRAM, parallel Flash, FPGA, AI-accelerated SoC, or high-speed PHY transceiver chip.

[0117] like Figure 20 As shown, in a semiconductor device according to an embodiment of the present disclosure, the external input is divided into two raw signals: one is a raw clock signal, and the other is a raw command signal and a raw address signal. The raw command signal and the address signal are first sent to the logic controller for preprocessing, and the output on-chip clock signal is then sent to the delay phase-locked loop. The raw clock signal is directly input to the delay phase-locked loop as a circuit timing reference.

[0118] The delay phase-locked loop (PLL) has a DLL controller. The phase detector acquires the phase difference between the input raw clock and the feedback clock. The DCD detects the clock duty cycle in real time. The two detection results are sent to the DLL controller. The DLL controller generates DCC control codes based on the duty cycle deviation and phase deviation. The DCC control codes are synchronously sent to the DCC CLK module and the DCC CMD module to control the two modules to synchronously adjust the signal edge rate, complete the 50% duty cycle calibration of the clock, and match the command edge with the clock edge.

[0119] In the clock signal path, the DLL controller generates a first compensation control signal based on the offset parameter corresponding to the DCC control code and sends it to the CLK delay compensation module. The CLK delay compensation module connects a single-sided compensation capacitor according to the first compensation control signal to apply a reverse delay, which reduces the single-sided timing offset generated by the DCC CLK module to a certain extent and makes up for the timing difference caused by the hardware topology difference of the clock and command signal paths.

[0120] The compensated clock signal is sent to the first delay line, which receives an independent phase adjustment signal for coarse global clock phase alignment. After passing through the first delay line and clock tree equalization fan-out, the signal generates the target clock signal, which is then output as a differential data gating clock signal through the first IO drive buffer.

[0121] In the command signal path, the DLL controller, in conjunction with the command signal path offset parameter corresponding to the DCC control code, generates a second compensation control signal and sends it to the CMD delay compensation module. The CMD delay compensation module simultaneously turns on two sets of compensation capacitors according to the second compensation control signal, and applies reverse compensation delay synchronously to the rising and falling edges to reduce the timing offset after the command signal path is amplified.

[0122] The compensated command signal is sent to the second delay line. The second delay line receives a phase adjustment signal that is different from that of the first delay line, thus completing the overall phase alignment of the command signal path. After the signal passes through the second delay line and the signal line in sequence, a synchronous command signal is generated, and the data signal is output through the second IO drive buffer.

[0123] In this embodiment, the DCC control code uniformly controls the DCC CLK module and the DCC CMD module to achieve synchronous adjustment of the duty cycle of the two channels. In view of the differences in the topology and offset characteristics of the two paths, the DLL controller generates a first compensation control signal and a second compensation control signal according to the DCC control code, respectively, and applies differentiated reverse delays to the two delay compensation modules to reduce the differential timing offset caused by DCC adjustment. The first delay line and the second delay line are indispensable phase adjustment components of the DLL. The delay introduced by the two is only used for global phase locking and is unrelated to the inherent offset of DCC. It does not interfere with the compensation effect. Finally, the relative delay of the output synchronization command signal and the target clock signal is consistent with the initial relative delay of the original input clock and command address signal, which is beneficial to improving the timing synchronization accuracy of the clock and command under high-speed DRAM.

[0124] like Figure 21 As shown, in another embodiment of the semiconductor device according to this disclosure, the external input is divided into two raw signals: one is a raw clock signal, and the other is a raw command signal and a raw address signal. The raw command signal and the address signal are first sent to the logic controller for preprocessing, and the output on-chip clock signal is then sent to the delay phase-locked loop. The raw clock signal is directly input to the delay phase-locked loop as the timing reference for the entire circuit.

[0125] The delay phase-locked loop has a DLL controller. The phase detector collects the phase difference between the input original clock and the feedback clock. The DCD detects the clock duty cycle in real time. The two detection results are sent to the DLL controller. The DLL controller generates DCC control codes based on the duty cycle deviation and phase deviation. The DCC control codes are synchronously sent to the DCC CLK module, DCC CLK mirror module, DCC CMD module and DCCCMD mirror module. The two signal paths share the same set of control parameters.

[0126] In the clock signal path, the original clock signal is input to the DCC CLK module. The DCC CLK module adjusts the width-to-length ratio of the MOS transistor according to the DCC control code, reduces the driving capability of the MOS on one side, slows down the corresponding edge switching rate, calibrates the original clock to 50% standard duty cycle, and outputs a clock correction signal.

[0127] The clock correction signal is sent to the DCC CLK mirror module. The DCC CLK mirror module and the DCC CLK module adopt a completely symmetrical two-stage inverter topology, replicating all device dimensions, trace parasitics and drive attenuation characteristics of the DCC CLK module. The two form a load-matched mirror path. The original static timing offset caused by the unilateral adjustment of the MOS in the DCC CLK module is offset by the equal reverse offset generated by the mirror module, reducing the unilateral timing offset in terms of circuit electrical aspects, and retaining only the calibrated 50% duty cycle waveform.

[0128] After electrical equalization by the mirror module, the clock signal is sent to the first delay line for overall phase coarse adjustment, and then fan-out equalization is performed by the clock tree to generate the target clock signal. The target clock signal is input to the first IO drive buffer and finally outputs the differential data gating clock signal.

[0129] In the command signal path, the on-chip clock signal output by the logic controller is sent to the DCC CMD module. The DCC CMD module reuses the DCC control code, which is from the same source as the clock signal path, and synchronously matches the edge adjustment logic of the DCC CLK module to complete the synchronous edge processing of the command signal.

[0130] The command correction signal is sent to the DCC CMD mirror module. The DCC CMD mirror module and the DCC CMD module build a symmetrical mirror topology, physically separating the rising edge and falling edge adjustment units. The timing offset generated by the duty cycle adjustment is constrained to the fast edge of the command signal, reducing the overall amplitude of the timing offset. At the same time, based on symmetrical load matching, the DCC CMD module's own native static timing offset is reduced, improving the signal edge drive balance and weakening the defect of fast edge offset amplification.

[0131] The command signal, after electrical optimization by the mirror module, is sent to the second delay line to complete phase alignment, and then transmitted through the signal line to generate a synchronous command signal. The synchronous command signal is sent to the second IO drive buffer, and finally outputs the data signal to the outside.

[0132] In this embodiment, the clock signal path is based on the DCC CLK mirror module, and the command signal path is based on the DCC CMD mirror module. By matching the mirror topology load, the static timing offset introduced by the DCC module adjustment is reduced from the underlying electrical characteristics. No additional capacitor delay compensation branch is required. The two paths share the same DCC control code to achieve duty cycle calibration and edge synchronization. The differentiated mirror structure is adapted to the offset characteristics of the single-sided slow edge of the clock and the double-sided fast edge of the command. Finally, the relative delay of the output synchronization command signal and the target clock signal is consistent with the initial relative delay of the input original clock and original command address signals. While completing the duty cycle matching, the timing offset amplification problem is suppressed, the signal integrity is optimized, and the timing synchronization accuracy of the clock and command signals in high-speed DRAM transmission scenarios is improved.

[0133] In this disclosure, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance; the term "multiple" refers to two or more unless otherwise expressly defined. The terms "install," "connect," "link," and "fix" should be interpreted broadly. For example, "connect" can be a fixed connection, a detachable connection, or an integral connection; "link" can be a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances.

[0134] In the description of this disclosure, it should be understood that the terms "upper," "lower," "left," "right," "front," "rear," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this disclosure and simplifying the description, and do not indicate or imply that the device or unit referred to must have a specific orientation or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this disclosure.

[0135] In the description of this specification, the terms "one embodiment," "some embodiments," "specific embodiment," etc., refer to a specific feature, structure, material, or characteristic described in connection with that embodiment or example, which is included in at least one embodiment or example of this disclosure. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0136] The above description is merely a preferred embodiment of this disclosure and is not intended to limit the scope of this disclosure. Various modifications and variations can be made to this disclosure by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure. Other embodiments of this disclosure will be readily apparent to those skilled in the art upon consideration of the specification and practice of the embodiments disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and embodiments are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. A time-delay phase-locked loop circuit, characterized in that, include: The clock signal path, including a series-connected clock duty cycle correction DCC CLK module and a first adjustment module, is configured to receive the original clock signal and output the corresponding output signal. The command signal path, including the series-connected command duty cycle correction DCC CMD module and the second adjustment module, is configured to receive the on-chip command signal and output the synchronization command signal. A delay-locked loop (DLL) controller is configured to receive the duty cycle detection result of the corresponding output signal and generate a DCC control code based on the detection result. The DCC CLK module adjusts the clock duty cycle of the original clock signal to the target duty cycle based on the DCC control code and obtains a corresponding clock correction signal. The first adjustment module is configured to adjust the timing deviation of the clock correction signal to adjust the corresponding output signal to the target clock signal. The DCC CMD module performs adjustment processing on the on-chip command signal based on the DCC control code to match the DCC CLK module to obtain a command correction signal. The second adjustment module is configured to adjust the command correction signal to adjust the time delay of the command signal path relative to the clock signal path, so that the command signal path outputs the synchronization command signal.

2. The time-delay phase-locked loop circuit according to claim 1, characterized in that, The first adjustment module is connected to the DLL controller to receive the first adjustment signal output by the DLL controller. The first adjustment module configures the drive parameters or capacitive load of its own path based on the first adjustment signal to adjust the timing deviation of the clock correction signal and outputs a clock adjustment signal. The second adjustment module is connected to the DLL controller to receive the second adjustment signal output by the DLL controller. The second adjustment module configures the drive parameters or capacitive load of its own path based on the second adjustment signal to adjust the time delay of the command signal path relative to the clock signal path and outputs the command adjustment signal.

3. The time-delay phase-locked loop circuit according to claim 1, characterized in that, The DCC CLK module and the DCCCMD module are respectively connected to the DLL controller to receive the DCC control code. The DCC CLK module is configured to reduce the toggle rate of the rising or falling edge of the original clock signal based on the DCC control code to adjust the duty cycle and output the clock correction signal. The DCC CMD module is configured to reduce the toggle rate of the rising and falling edges of the on-chip command signal based on the DCC control code when the detection result is greater than the target duty cycle, or not adjust the rising and falling edges of the on-chip command signal and output the command correction signal, so that the relative delay between the clock correction signal and the command correction signal is consistent with the relative delay between the original clock signal and the on-chip command signal.

4. The time-delay phase-locked loop circuit according to claim 1, characterized in that, The DLL controller is further configured to: detect the relationship between the DCC control code and the compensation reference code value; if the DCC control code is greater than the compensation reference code value, generate a first compensation control signal for unilateral compensation of the clock correction signal, as a first adjustment signal; The first adjustment module includes: The CLK delay compensation module is connected to the DCC CLK module and the DLL controller respectively. It is configured to receive the first compensation control signal and the clock correction signal, and configure the capacitive load of its own path based on the first compensation control signal to perform delay compensation on the rising or falling edge of the clock correction signal that reduces the toggle rate, so as to obtain the clock adjustment signal.

5. The time-delay phase-locked loop circuit according to claim 4, characterized in that, The CLK delay compensation module includes: Multiple first MOS capacitor unit branches are arranged in parallel. Each first MOS capacitor unit branch includes a first PMOS capacitor, a first control switch, a second control switch, and a first NMOS capacitor connected in series. The first compensation control signal is used to close the first control switch or the second control switch in the corresponding branch, so that the first PMOS capacitor or the first NMOS capacitor is connected to the clock signal path to configure the capacitive load for single-sided delay compensation.

6. The time-delay phase-locked loop circuit according to claim 5, characterized in that, The DLL controller is also used for: Using the DCC control code as an index, query the one-sided timing offset amplitude of the clock correction signal; The number of first MOS capacitor cell branches that need to be turned on and the type of control switch that needs to be closed are determined based on the single-sided timing offset amplitude. Based on the number of branches of the first MOS capacitor unit and the type of control switch to be closed, a level command is generated to turn on the first control switch or the second control switch, which serves as the first compensation control signal.

7. The time-delay phase-locked loop circuit according to claim 5, characterized in that, The DLL controller is further configured to: generate a second compensation control signal for bilateral compensation of the command correction signal, as a second adjustment signal; The second adjustment module includes: The CMD delay compensation module is connected to the DCC CMD module and the DLL controller respectively. It is configured to access the second compensation control signal and the command correction signal, and to configure the capacitive load of its own path based on the second compensation control signal to perform delay compensation on the rising edge and the falling edge of the command correction signal adjusted by the synchronization edge, so as to obtain the command adjustment signal.

8. The time-delay phase-locked loop circuit according to claim 7, characterized in that, The CMD delay compensation module includes: Multiple second MOS capacitor unit branches are arranged in parallel. Each second MOS capacitor unit branch includes a second PMOS capacitor, a third control switch, a fourth control switch, and a second NMOS capacitor connected in series. The second compensation control signal is used to close the third and fourth control switches in the corresponding branch, so that the second PMOS capacitor and the second NMOS capacitor are connected to the command signal path to configure the capacitive load for bilateral time delay compensation.

9. The time-delay phase-locked loop circuit according to claim 8, characterized in that, The DLL controller is also used for: Using the DCC control code as an index, query the total timing offset amplitude corresponding to the two-sided edges of the command correction signal; The number of second MOS capacitor cell branches that need to be turned on is determined based on the total timing offset amplitude; Based on the number of branches of the second MOS capacitor unit, a combined level command is generated to synchronously turn on the third control switch and the fourth control switch, which serves as the second compensation control signal.

10. The time-delay phase-locked loop circuit according to claim 9, characterized in that, The DCC control code is divided into multiple numerical ranges. Different numerical ranges correspond to the number of first MOS capacitor cell branches or second MOS capacitor cell branches that are turned on. The higher the code value of the DCC control code, the more first MOS capacitor cell branches or second MOS capacitor cell branches that are turned on.

11. The time-delay phase-locked loop circuit according to claim 1, characterized in that, The first adjustment module includes: The DCC CLK mirror module is connected to both the DCC CLK module and the DLL controller. It forms a mirror topology with the DCC CLK module for path load matching. It is configured to receive the clock correction signal and the DCC control code as the first adjustment signal. Based on the DCC control code, it configures the drive parameters of its own path and outputs a clock adjustment signal to reduce the native static timing offset of the DCCCLK module.

12. The time-delay phase-locked loop circuit according to claim 1, characterized in that, The second adjustment module includes: The DCC CMD mirror module is connected to both the DCC CMD module and the DLL controller, forming a mirror topology with the DCC CMD module for path load matching. It is configured to receive the DCC control code as a second adjustment signal and the command correction signal, configure its own path drive parameters based on the DCC control code, and output a command adjustment signal to reduce the native static timing offset of the DCC CMD module. Wherein, when the detection result is greater than the target duty cycle, the DCC CMD mirroring module is further configured to reduce the toggle rate of the falling edge of the command correction signal based on the DCC control code.

13. The time-delay phase-locked loop circuit according to claim 1, characterized in that, It also includes a first delay processing component, which comprises a first delay line and a clock tree connected in series. The first delay line is connected to the clock adjustment signal output from the first adjustment module, and the clock adjustment signal is processed to adjust the transmission delay, resulting in a clock delay processing signal. The clock tree is used to fan out and buffer the clock delay processing signal to output the target clock signal.

14. The time-delay phase-locked loop circuit according to claim 13, characterized in that, Also includes: A phase detector is configured to receive the original clock signal and the clock delay processing signal, and to perform a phase comparison between the original clock signal and the clock delay processing signal to obtain a phase comparison result; The DLL controller receives the phase comparison result and outputs the delay level of the transmission delay adjustment process to the first delay line according to the phase comparison result.

15. The time-delay phase-locked loop circuit according to claim 1, characterized in that, It also includes a second delay processing component, which comprises a second delay line and a signal line connected in series. The second delay line is connected to the command adjustment signal output by the second adjustment module, and the transmission delay of the command adjustment signal is adjusted to output a command delay processing signal. The signal line is used to perform long-line buffering of the command delay processing signal and output the synchronization command signal.

16. The time-delay phase-locked loop circuit according to claim 1, characterized in that, Also includes: The duty cycle detection module is configured to receive the corresponding output signal and output the duty cycle detection result of the target clock signal.

17. A semiconductor device, characterized in that, include: The logic controller is configured to receive a raw clock signal, a raw command signal, and an address signal, and to sample and decode the raw command signal and the address signal based on the raw clock signal to obtain an on-chip command signal; The delay phase-locked loop circuit as described in any one of claims 1 to 16 is configured to receive the original clock signal and the on-chip command signal, and output the target clock signal and the synchronization command signal; The first IO drive buffer is configured to receive the target clock signal, and after driving and amplifying the target clock signal, it is output from the clock signal output terminal. The second IO drive buffer is configured to receive the synchronization command signal, and after driving and amplifying the synchronization command signal, it is output from the data signal output terminal.

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