Synchronization circuitry and communication interface circuitry

Abstract

The system includes a synchronization circuit and a communication interface circuit. The synchronization circuit comprises a comparator circuit, a first charge pump circuit, a loop filter, a voltage-controlled oscillator, and a current generation circuit. The comparator circuit compares the phase of the input signal with the clock signal and outputs a phase difference signal. The first charge pump circuit outputs a charge pump current with a specified pulse width corresponding to the pulse width of the phase difference signal to the control voltage node. The current generation circuit includes: a current pulse generation circuit that allows a small bias current to flow through the control voltage node, generating intermittent current pulses based on the clock signal; and a smoothing circuit that generates a small bias current by smoothing the intermittent current pulses.

Description

Technical Field

[0001] This invention relates to synchronization circuits and communication interface circuits, etc. Background Technology

[0002] Previously, charge pump circuits were known to be included in PLL circuits and the like. Patent Document 1 discloses a method for using a transistor as a constant current source to draw current from the charge pump circuit.

[0003] Existing technical documents

[0004] Patent documents

[0005] Patent Document 1: Japanese Patent Application Publication No. 2021-093643 Summary of the Invention

[0006] While a single transistor can carry a constant current in the microampere range, in synchronous circuits composed of miniaturized semiconductor devices, from the viewpoint of suppressing increased jitter, a method is required to draw current from a specified node with a constant current in the nanoampere or picoampere range.

[0007] One aspect of this disclosure relates to a synchronization circuit comprising: a comparator circuit that compares the phase of an input signal with that of a clock signal and outputs a phase difference signal; a first charge pump circuit that outputs a charge pump current with a predetermined pulse width corresponding to the pulse width of the phase difference signal to a control voltage node; a loop filter that outputs a control voltage to the control voltage node based on the charge pump current with the predetermined pulse width; a voltage-controlled oscillator that generates the clock signal at a frequency corresponding to the control voltage; and a current generation circuit that allows a small bias current to flow through the control voltage node, the current generation circuit comprising: a current pulse generation circuit that generates intermittent current pulses based on the clock signal; and a smoothing circuit that generates the small bias current by smoothing the intermittent current pulses.

[0008] Furthermore, another aspect of this disclosure relates to a communication interface circuit that includes the aforementioned synchronization circuit, wherein the synchronization circuit comprises: a phase comparator; a second charge pump circuit that outputs a current corresponding to the comparison result of the phase comparator; and a switching circuit that switches between a frequency-locked loop and a phase-locked loop, wherein the frequency-locked loop comprises the comparator circuit, the first charge pump circuit, the loop filter, the current generation circuit, and the voltage-controlled oscillator to synchronize the frequency of the input signal with the clock signal, and the phase-locked loop comprises the phase comparator, the second charge pump circuit, the loop filter, the current generation circuit, and the voltage-controlled oscillator to synchronize the phase of the input signal with the clock signal. Attached Figure Description

[0009] Figure 1 This is a diagram illustrating the structure of a communication interface circuit.

[0010] Figure 2 This is a diagram illustrating the structure of a synchronous circuit.

[0011] Figure 3 This is a diagram illustrating the phase difference characteristics in the comparative example.

[0012] Figure 4 This is a diagram illustrating an example of the circuit structure involved in the operation of this embodiment.

[0013] Figure 5 This is a diagram illustrating an example of the phase difference characteristics in this embodiment.

[0014] Figure 6 This is a diagram illustrating examples of other circuit structures involved in the operation of this embodiment.

[0015] Figure 7 This is a diagram illustrating another example of phase difference characteristics in this embodiment.

[0016] Figure 8 This is a diagram illustrating a detailed structural example of a current generation circuit.

[0017] Figure 9 This is a diagram illustrating an example of how a current-generating circuit operates.

[0018] Figure 10 This is a diagram illustrating the structure of a frequency-locked loop.

[0019] Figure 11 This is a diagram illustrating the structure of a phase-locked loop.

[0020] Figure 12 This is a diagram illustrating a more detailed structural example of a switching circuit.

[0021] Figure 13 This is a diagram illustrating another structural example of a synchronous circuit.

[0022] Figure 14 This is a diagram illustrating an example of a voltage-controlled oscillator.

[0023] Figure 15 It is a diagram that conceptually illustrates the relationship between frequency locking and phase locking.

[0024] Figure 16 This is a diagram that conceptually illustrates an example of a phase comparator.

[0025] Figure 17 This is a diagram illustrating an example of how a phase comparator operates.

[0026] Label Explanation

[0027] 1…Communication interface circuit, 10…Synchronization circuit, 40…Comparison circuit, 50…Data recovery circuit, 100…Voltage controlled oscillator, 200…Loop filter, 300…Switching circuit, 310…First switching circuit, 311…First switch, 312…First second switch, 320…Second switching circuit, 321…Second first switch, 322…Second second switch, 330…Third switching circuit, 331…Third first switch, 332…Third second switch, 340…Fourth switching circuit, 341…Fourth first switch, 342…Fourth second switch, 4… 00… Frequency phase comparator, 500… Phase comparator, 510, 530… Master latch circuit, 520, 540… Slave latch circuit, 550, 560… XOR circuit, 570… Trigger circuit, 610… First charge pump circuit, 611… First specified switch, 612… Second specified switch, 613… Third specified switch, 614… Fourth specified switch, 615… Voltage follower, 620… Second charge pump circuit, 710… First frequency divider, 720… Second frequency divider, 900… Current generation circuit, 920… Current pulse generation circuit, 922… Counter, 924… N AND circuit, 940… smoothing circuit, 942… low-pass filter, 944… current mirror circuit, CA1, CA2, CA3… capacitors, CP… current pulse, DA1, DA1N, DA2, DA2N, DN, DNN, SGN, SGCLKN, SGRST, UP, UPN… signals, FLP… frequency-locked loop, N1… input node, N4… output node, N2, N3, N5, N6, N7, N41, N42, N51, N61, N62, N63, N64, N65, N71, N72, NA, NB… nodes, NCV… control circuit Phase-locked loop (PLP), resistors R1, R11, R12, SG, input signal, SGCLK, clock signal, T, interval, t0, t1, t2, t3, t4, t5, t6, t7, t8, t9, t10, t11, t12, t13, t14, t15, t16, t17, t18, t19, timing, transistor TR1, first transistor, transistor TR2, second transistor, transistors TR11, TR12, TR13, TR14, TR15, VA, VB, VC, VD, VE, VN71, VN72, voltage, voltage pulse VP. Detailed Implementation

[0028] The preferred embodiments of this disclosure will now be described in detail. Furthermore, the embodiments described below are not intended to unduly limit the scope of the claims, and the structures described in these embodiments are not necessarily all essential components.

[0029] Figure 1 This is a block diagram illustrating a structural example of the communication interface circuit 1, which includes the synchronization circuit 10 of this embodiment. The communication interface circuit 1 is included in a receiving device (not shown) and receives an input signal SG from an external device. The input signal SG is input to the synchronization circuit 10 via a buffer circuit (not shown). Details of the synchronization circuit 10 will be provided later. Figure 2 The explanation will follow.

[0030] Furthermore, the communication interface circuit 1 of this embodiment may also include a data recovery circuit 50. The data recovery circuit 50 recovers the data included in the input signal SG. Figure 1 For ease of explanation, the synchronization circuit 10 and the data recovery circuit 50 are shown separately, but the data recovery circuit 50 may be included in the synchronization circuit 10. More specifically, the phase comparator 500 included in the synchronization circuit 10 can also function as the data recovery circuit 50, as will be explained in detail later.

[0031] Although the input signal SG corresponds to the serial data signal during data communication, the input clock signal is used as the input signal SG during the locking period of the frequency-locked loop (FLP) and phase-locked loop (PLP) described later. This clock signal is a signal that alternately transmits 0s and 1s as a serial data signal, and refers to a clock signal that is assumed to be at half the transmission rate of the input signal SG.

[0032] use Figure 2 Here is an example of the structure of the synchronization circuit 10 in this embodiment. The synchronization circuit 10 includes a voltage-controlled oscillator 100, a comparator circuit 40, a first charge pump circuit 610, a loop filter 200, and a current generation circuit 900.

[0033] The voltage-controlled oscillator 100 generates a clock signal SGCLK, which is a clock signal with a frequency corresponding to the control voltage of the control voltage node NCV. A detailed structural example will be described later. Hereinafter, the clock signal output by the voltage-controlled oscillator 100 will be marked as "clock signal SGCLK". The output clock signal SGCLK is output to the comparator circuit 40. Alternatively, the clock signal SGCLK can also be output to the phase comparator 500 of the phase-locked loop (PLP), which will be described later.

[0034] Comparator circuit 40 compares the frequency and phase of clock signal SGCLK with input signal SG and outputs a phase difference signal, details of which will be explained later. The phase difference signal has a defined width, the size of which depends on the phase difference between clock signal SGCLK and input signal SG. First charge pump circuit 610 outputs a charge pump current with a defined pulse width corresponding to the pulse width of the phase difference signal to control voltage node NCV. The detailed structure of first charge pump circuit 610 will be explained later. By configuring a circuit including comparator circuit 40 and first charge pump circuit 610 in this way, the following relationship holds: when a phase difference is input, the output current corresponds to the input phase difference.

[0035] The loop filter 200 outputs a control voltage based on the charge pump current with a specified pulse width to the control voltage node NCV. For example, when the charge pump current output from the first charge pump circuit 610 is input to the loop filter 200, loop filtering is performed, and the loop filter 200 outputs a control voltage from the loop filter 200 to the control voltage node NCV to operate the voltage-controlled oscillator 100. The loop filter 200 is, for example, a low-pass filter, more specifically, a passive filter, but it can also be an active filter. The passive filter includes, for example, a lead filter, which is a filter in series with a resistor and a capacitor connected between the control voltage node NCV and the ground node.

[0036] The current generation circuit 900 is connected to the loop filter 200 and the control voltage node NCV. The current generation circuit 900 includes a current pulse generation circuit 920 and a smoothing circuit 940. The current pulse generation circuit 920 causes a bias current to flow through the control voltage node NCV and generates intermittent current pulses CP according to the clock signal SGCLK, details of which will be explained later. The smoothing circuit 940 generates a small bias current by smoothing the intermittent current pulses CP, details of which will be explained later. Specifically, the value of this small bias current is, for example, in the nanoampere or picoampere range. This embodiment relates to a method of operating a synchronization circuit 10 using a current generation circuit 900 configured in this way.

[0037] A conceptual explanation of the effects of applying the method of this embodiment will be provided. As a comparative example, Figure 3 The phase difference characteristics in the synchronization circuit 10, excluding the current generation circuit 900 of this embodiment, are shown. Specifically, Figure 3 F10 represents the input-output characteristics of the circuit including comparator circuit 40 and first charge pump circuit 610. In other words, Figure 3F10 shows the phase difference dependence of the charge pump current when the horizontal axis is the phase difference and the vertical axis is the charge pump current quantity, where the phase difference is the difference between the phase of the clock signal SGCLK input to the comparator circuit 40 and the phase of the input signal SG, and the charge pump current quantity is the current quantity output from the first charge pump circuit 610.

[0038] exist Figure 3 In the diagram, the right direction of the horizontal axis represents the positive direction of the phase difference. A larger positive direction indicates that the phase of the clock signal SGCLK input to the comparator circuit 40 is significantly delayed compared to the phase of the input signal SG input to the comparator circuit 40. Therefore, the comparator circuit 40 outputs a higher voltage rising signal to reduce the large phase difference. This results in a larger charge pump current being output from the first charge pump circuit 610. The first charge pump circuit 610 operates using a constant current source for charging and discharging, as described later; therefore, the charge pump current is proportional to the phase difference. That is, the dashed line F11 is an ideal straight line representing the phase difference dependence of the charge pump current with a defined slope. However, in reality, when the phase difference is small, no current is output from the first charge pump circuit 610; therefore, the actual phase difference dependence of the charge pump current is as shown by the solid line F12. That is, the charge pump current is zero when the phase difference is in the range shown in F13. This range shown in F13 is called the dead zone.

[0039] in addition, Figure 3 F20 illustrates the phase difference dependence of the control voltage difference when the horizontal axis represents the phase difference and the vertical axis represents the control voltage difference. This phase difference is the difference between the phase of the clock signal SGCLK input to the comparator circuit 40 and the phase of the input signal SG. The control voltage difference is the change in voltage at the control voltage node NCV, based on the amount of charge pump current with a defined pulse width output from the first charge pump circuit 610. The control voltage difference is proportional to the phase difference; therefore, the phase difference dependence of the control voltage difference is theoretically as shown by the dashed line in F21. However, the control voltage difference also depends on the amount of charge pump current; therefore, the actual phase difference dependence of the control voltage difference is shown by the solid line in F22. That is, the dead zone shown in F23 can also be considered regarding the phase difference dependence of the control voltage difference.

[0040] Next, the effects of the method in this embodiment will be explained. Figure 4 A detailed circuit structure example of the first charge pump circuit 610 and a circuit example including the first charge pump circuit 610 and the control voltage node NCV are conceptually shown. Figure 4In this circuit, the first charge pump circuit 610 includes a first transistor TR1, a first specified switch 611, a second specified switch 612, a third specified switch 613, a fourth specified switch 614, a voltage follower 615, an output node N4, and a second transistor TR2. The first transistor TR1 is a P-type MOS transistor. The source of the first transistor TR1 is connected to node N2, which serves as a high-potential side power supply node, and the drain of the first transistor TR1 is connected to node N3. The first transistor TR1 operates as a current source for a rising signal. The first specified switch 611 is positioned between node N3 and the output node N4. The output node N4 is connected to the control voltage node NCV. The second specified switch 612 is positioned between the output node N4 and node N6. The second transistor TR2 is an N-type MOS transistor. The drain of the second transistor TR2 is connected to node N6, and the source of the second transistor TR2 is connected to node N7, which serves as a low-potential side power supply node. The low-potential side power supply node is, for example, a ground node. The second transistor TR2 operates as a current source for the falling signal. Bias voltages are supplied to the gates of the first transistor TR1 and the second transistor TR2, respectively.

[0041] The first charge pump circuit 610 raises or lowers the voltage output to the loop filter 200, i.e., the voltage at the control voltage node NCV, based on the rising or falling signal output from the comparator circuit 40. More specifically, in the first charge pump circuit 610, when the rising signal output from the comparator circuit 40 is high, the first predetermined switch 611 is turned on, and the second predetermined switch 612 is turned off. Thus, the current based on the rising signal is introduced into the loop filter 200 as a pull-in current. On the other hand, when the falling signal output from the comparator circuit 40 is high, the first charge pump circuit 610 turns off the first predetermined switch 611 and turns on the second predetermined switch 612, thus introducing the current based on the falling signal as a sink current into the loop filter 200. Furthermore, in Figure 4 In this configuration, the third specified switch 613 is positioned between nodes N3 and N5, and the fourth specified switch 614 is positioned between nodes N5 and N6. The input node of the voltage follower 615 is connected to the output node N4, and the output node of the voltage follower 615 is connected to node N5. Therefore, the voltage at node N5 is equal to the voltage at the output node N4. Furthermore, when the first specified switch 611 is open, the third specified switch 613 is turned on, and when the second specified switch 612 is open, the fourth specified switch 614 is turned on. This ensures that the first transistor TR1 or the second transistor TR2, acting as a current source, always carries current, thus preventing delays or noise caused by the switching on and off of the current source.

[0042] In addition, Figure 4In the diagram, the current source shown in G10 is configured between the control voltage node NCV and node N7, and the capacitor shown in G11 is configured between the control voltage node NCV and node N7. The current source shown in G10 conceptually represents a current source of a small bias current generated by the current generation circuit 900; more specifically, it conceptually represents a current source in… Figure 8 The transistor TR15 is described in the description. The following will describe... Figure 6 The current source shown in G20 also conceptually represents a current source of a small bias current generated by the current generation circuit 900. Furthermore, Figure 4 The capacitor shown in G11 conceptually illustrates a composite capacitor of the capacitors included in the loop filter 200, as described later. Figure 6 The same applies to the capacitor shown in G21.

[0043] The current source shown in G10 is positioned between the control voltage node NCV and node N7, which serves as the low-potential side power supply voltage node. Therefore, the direction of the small bias current generated from the current source shown in G10 is the same as the direction of the sink current. Thus, including... Figure 4 The phase difference characteristics in the synchronization circuit 10 constructed in that way become as follows: Figure 5 As shown. More specifically, Figure 5 The phase difference dependence of the charge pump current shown in F30 is related to Figure 3 The phase difference dependence of the charge pump current shown in F10 is the same. That is, Figure 5 The dashed line shown in F31 and Figure 3 The dashed line shown in F11 is the same. Figure 5 The solid line shown in F32 and Figure 3 The solid line shown in F12 is the same. Figure 5 The dead zone shown by F33 and Figure 3 The dead zone shown by F13 is the same. On the other hand, the phase difference dependence of the control voltage difference is... Figure 3 and Figure 5 Different from China. Furthermore... Figure 5 The dashed line shown in F41 is an ideal concept, therefore it is consistent with... Figure 3 The dashed line shown in F21 is the same, but it is shown for ease of explanation. As mentioned above, by means of... Figure 4 The small bias current generated by the current source shown in G10 further introduces charge from the control voltage node NCV. This results in the same phenomenon as when the voltage-controlled oscillator 100 operates due to the control voltage generated by the apparently larger sink current flowing through it. Therefore, as... Figure 4 The phase difference dependence of the control voltage of such a circuit is as follows: Figure 5 The solid line at F42 is shown. Compare. Figure 3 The solid line of the F22 and Figure 5As can be seen from the solid line of F42, the phase difference dependence of the solid line of F42 is shifted in the positive direction by the magnitude shown in F43 relative to the phase difference dependence of F22.

[0044] Alternatively, in the synchronization circuit 10 of this embodiment, it can also be as follows: Figure 6 This constitutes the first charge pump circuit 610, the current generation circuit 900, and the loop filter 200. Figure 6 and Figure 4 The difference lies in the fact that the current source shown in G20 is configured between node N2 and the control voltage node NCV. That is, the current generation circuit 900 is configured between the high-potential side power supply node and the control voltage node NCV, which is different from... Figure 2 and Figure 4 Different. Furthermore... Figure 6 The first charge pump circuit 610 and Figure 4 The first charge pump circuit 610 is the same, so the description is omitted.

[0045] pass Figure 6 The current source G20 is shown, and the phase comparison characteristics of the synchronous circuit 10 are as follows: Figure 7 As shown. Figure 7 The phase difference dependence of the charge pump current shown by F50 and Figure 3 The phase difference dependence of the charge pump current shown in F10 is the same. That is, Figure 7 The dashed line shown in F51 and Figure 3 The dashed line shown in F11 is the same. Figure 7 The solid line shown in F52 and Figure 3 The solid line shown in F12 is the same. Figure 7 The dead zone shown by F53 and Figure 3 The dead zone shown by F13 is the same. On the other hand, the phase difference dependence of the control voltage difference is... Figure 3 and Figure 7 Different from China. Furthermore... Figure 7 The dashed line shown in F61 and Figure 3 The dashed line shown in F21 is the same. As mentioned above, by... Figure 6 The small bias current generated by the current source shown in G20 further introduces charge from the control voltage node NCV. This results in the same phenomenon as when the voltage-controlled oscillator 100 operates due to the control voltage generated by the apparently large spool current flowing through it. Therefore, as... Figure 6 The phase difference dependence of the control voltage of such a circuit is as follows: Figure 7 The solid line at F62 is shown. Compare. Figure 3 The solid line of the F22 and Figure 7 As can be seen from the solid line of F62, the phase difference dependence of the solid line of F62 is relative to... Figure 3The phase difference dependence of F22 shifts negatively by the magnitude shown in F63.

[0046] Figure 3 The size of the dead zone shown in F23 depends on the circuit's linewidth rules, etc., but as long as the dead zone is avoided and frequency locking and phase locking are performed by comparator circuit 40, it is not desirable to... Figure 5 The size of the F43 or Figure 7 The size of F63 becomes excessive. In this embodiment, by generating a small bias current through the current generation circuit 900, the size can be minimized. Figure 5 The size of the F43 or Figure 7 The size of F63.

[0047] Thus, the synchronization circuit 10 of this embodiment includes a comparator circuit 40, a first charge pump circuit 610, a loop filter 200, a voltage-controlled oscillator 100, and a current generation circuit 900. The comparator circuit 40 compares the phase of the input signal SG with the clock signal SGCLK and outputs a phase difference signal. The first charge pump circuit 610 outputs a charge pump current with a predetermined pulse width corresponding to the pulse width of the phase difference signal to the control voltage node NCV. The loop filter 200 outputs a control voltage to the control voltage node NCV based on the charge pump current with the predetermined pulse width. The voltage-controlled oscillator 100 generates a clock signal SGCLK with a frequency corresponding to the control voltage. The current generation circuit 900 includes: a current pulse generation circuit 920 that allows a small bias current to flow through the control voltage node NCV and generates intermittent current pulses according to the clock signal SGCLK; and a smoothing circuit 940 that generates a small bias current by smoothing the intermittent current pulses.

[0048] As described above, the synchronization circuit 10 of this embodiment includes a comparator circuit 40, a first charge pump circuit 610, a loop filter 200, and a voltage-controlled oscillator 100. Therefore, it is possible to compare the phases of the input signal SG and the clock signal SGCLK and adjust the phase difference. Furthermore, by including the current generation circuit 900, an offset can be applied to the pull-up or sink current output from the first charge pump circuit 610, thus avoiding dead time and locking the phases of the input signal SG and the clock signal SGCLK. Additionally, the current output from the current generation circuit 900 is a small bias current, thus avoiding dead time and minimizing the magnitude of the applied offset current. For example, when a single transistor is used as the current source, the offset can only be applied to the pull-up or sink current in the microampere range, requiring an increase in the charge pump current, which may increase jitter during locking. In this regard, by applying the method of this embodiment, the charge pump current can be offset based on a small bias current, thus enabling the construction of a synchronization circuit 10 that balances avoiding dead time, suppressing increased jitter, and locking the phase.

[0049] use Figure 8 To explain the current generation circuit 900 more specifically. Additionally, Figure 8 The current generation circuit 900 and Figure 4 The current source shown in G10 corresponds to this. The current pulse generation circuit 920 includes a counting circuit and a conversion circuit. The counting circuit generates a voltage pulse VP with a frequency lower than that of the clock signal SGCLK based on the clock signal SGCLK. The counting circuit includes a counter 922 and a NAND circuit 924. For ease of explanation, the counter 922 here uses N bits, i.e., 2^N, as the upper limit for counting.

[0050] Counter 922 is connected to NAND circuit 924. That is, counter 922 and NAND circuit 924 are connected through N signal lines. Thus, a voltage pulse VP is output from NAND circuit 924 only when counter 922 has counted to the upper limit value of 2^N. Therefore, it is possible to output a voltage pulse VP with a frequency lower than the clock signal SGCLK.

[0051] Furthermore, the output node of NAND circuit 924 is connected to the gate of transistor TR11, which is a P-type MOS transistor. The source of transistor TR11 is connected to node NA, which is a high-potential power supply node. The drain of transistor TR11 is connected to the source of transistor TR13, which is a P-type MOS transistor. Thus, transistor TR11 outputs a current pulse CP according to the voltage pulse VP. The drain of transistor TR13 is connected to node N71, which is a connection node connected to smoothing circuit 940. Furthermore, transistor TR13 and transistor TR12, which is a P-type MOS transistor, form a current mirror circuit. Specifically, the gate of transistor TR12 is connected to the gate of transistor TR13, the source of transistor TR12 is connected to node NA, and the drain of transistor TR12 is connected to node NB, which is a low-potential power supply node, via resistor R1. With this circuit structure, the current flowing through resistor R1 is mirrored from transistor TR12 to transistor TR13. That is, when the voltage pulse VP is high, transistor TR11 is turned off, and the drain current of transistor TR13 is zero. On the other hand, when the voltage pulse VP is low, transistor TR11 is turned on, and transistor TR13 flows through its drain current, i.e., the mirrored current. Thus, the voltage pulse VP is converted into a current pulse CP, which is output from transistor TR13 to the smoothing circuit 940. In other words, the circuit containing transistor TR11, the current mirror circuit composed of transistors TR12 and TR13, and resistor R1 is equivalent to a conversion circuit.

[0052] As described above, in the synchronization circuit 10 of this embodiment, the current pulse generation circuit 920 includes: a counting circuit that generates a voltage pulse VP with a frequency lower than that of the clock signal SGCLK; and a conversion circuit that converts the voltage pulse VP into a current pulse CP. Thus, a current pulse CP for generating a small bias current can be generated.

[0053] The smoothing circuit 940 includes a low-pass filter 942 and a current mirror circuit 944. The low-pass filter 942 includes resistors and capacitors. More specifically, Figure 8 The low-pass filter 942 shown is a passive filter including resistors R11 and R12, capacitors CA1, CA2, and CA3. However, this is only an example; the number of passive filters can be appropriately determined. The low-pass filter 942 is positioned between the drain of transistor TR13 and node NB, and is connected to the current mirror circuit 944 via node N72. The current mirror circuit 944 is composed of transistors TR14 and TR15, both N-type MOS transistors. The gate of transistor TR14 is connected to the gate of transistor TR15, the drain of transistor TR14 is connected to node N72, and the source of transistor TR14 is connected to node NB. The drain of transistor TR15 is connected to the control voltage node NCV, and the source of transistor TR15 is connected to node NB. That is, transistor TR15 operates as an output stage to the control voltage node NCV.

[0054] use Figure 9 To explain Figure 8 The operation of the current generation circuit 900. Figure 9 The upper part of the diagram is a timing diagram showing the time variation of the voltage pulse VP output from the NAND circuit 924. Figure 9 The middle section of the diagram is a timing diagram showing the time variation of voltage VN71, which is the voltage at node N71. Figure 9 The lower section of the diagram is a timing diagram showing the time variation of voltage VN72, which is the voltage at node N72. In the upper section, voltage VA is the voltage value of the high-potential side power node, and voltage VB is the voltage value of the low-potential side power node. When counter 922 counts the upper limit value 2^N, NAND circuit 924 outputs a voltage pulse VP as a low-level voltage VB. That is, assuming the clock signal frequency is f, Figure 9 The width shown in F81 is equivalent to 2^N / f, and the width shown in F82 is equivalent to 1 / f. The counting circuit generates a voltage pulse VP of 1 / 2^N as the duty cycle.

[0055] Therefore, during the period shown in F82, since the current pulse CP based on the voltage pulse VP flows from transistor TR13 to node N71, the voltage VN71 at node N71 rises, for example, from voltage VB to voltage VD. Regarding the magnitude of voltage VD, assuming that transistor TR11 is always on, the current output from the drain of transistor TR13 is set to I0, and the combined capacitance of low-pass filter 942 is set to C, the relationship "VD=I0 / Cf" holds true with voltage VB as a reference. Furthermore, voltage VN71 is gradually discharged by low-pass filter 942. In addition, voltage VN71 at node N71 is smoothed by low-pass filter 942, so that voltage VN72 at node N72 is maintained at approximately a fixed voltage, thus maintaining voltage VE. More specifically, with voltage VB as a reference, the value of voltage VE is "VE=I0 / (Cf(2^N))", which is lower than the value of voltage VD. That is, the voltage pulse VP is smoothed by the low-pass filter 942, resulting in a very low voltage value for voltage VE. Furthermore, a small bias current is generated from the transistor TR15 included in the current mirror circuit 944 based on voltage VE, thereby extracting a small amount of charge from the control voltage node NCV. C and N can be appropriately set in a manner that produces the desired small bias current at voltage VE.

[0056] As described above, in the synchronization circuit 10 of this embodiment, the smoothing circuit 940 includes: a low-pass filter 942, which includes a resistor and a capacitor; and a current mirror circuit 944, which mirrors the current based on the output voltage of the low-pass filter 942. Thus, a smoothing circuit 940 can be constructed that averages the current pulse CP and extracts its output as a small bias current. Furthermore, since a small bias current is generated through the low-pass filter 942, transistors TR14 and TR15, which are output stages, can be configured to operate in the subthreshold region.

[0057] Alternatively, the synchronization circuit 10 in this embodiment can also be configured as a frequency-locked loop (FLP). Specifically, as shown below... Figure 10 As shown, the comparator circuit 40 includes a frequency-phase comparator 400. In addition to this frequency-phase comparator 400, a frequency-locked loop (FLP) can be constructed by combining the first charge pump circuit 610, the loop filter 200, the current generation circuit 900, and the voltage-controlled oscillator 100. As described above, in the synchronization circuit 10 of this embodiment, the comparator circuit 40 includes a frequency-phase comparator 400. Therefore, the synchronization circuit 10 can operate as a frequency-locked loop (FLP).

[0058] Additionally, the synchronization circuit 10 of this embodiment may also include a first frequency divider 710 and a second frequency divider 720. Specifically, the first frequency divider 710 and the second frequency divider 720 may be included in a frequency-locked loop (FLP). Figure 10 As shown, the first frequency divider 710 is disposed between the voltage-controlled oscillator 100 and the frequency-phase comparator 400 to divide the clock signal SGCLK. The second frequency divider 720 is disposed between the input node N1, which is the input node of the input signal SG, and to divide the input signal SG. Furthermore, the division ratio of the first frequency divider 710 is the same as that of the second frequency divider 720. In addition, the first frequency divider 710 and the second frequency divider 720 can widely adopt well-known structures, so detailed illustrations are omitted. As described above, in the synchronization circuit 10 of this embodiment, the comparator circuit 40 also includes the first frequency divider 710 for dividing the clock signal SGCLK and the second frequency divider 720 for dividing the input signal SG. Thus, a synchronization circuit 10 corresponding to the higher speed of the input signal SG and the clock signal SGCLK can be constructed.

[0059] Alternatively, when the synchronization circuit 10 of this embodiment is included in the communication interface circuit 1, the synchronization circuit 10 may also be configured to further include Figure 11 The phase-locked loop (PLP) is shown. In this case, a half-rate clock signal is input to the synchronization circuit 10 as the original serial data signal, i.e., the input signal SG. Then, after frequency locking by the frequency-locked loop (FLP), the synchronization circuit 10 performs phase locking by the PLP. Afterward, a serial data signal with an embedded clock signal, such as an 8b or 10b, is input to the synchronization circuit 10 as the input signal SG, and the synchronization circuit 10 operates to recover the clock signal from the input signal SG through the PLP.

[0060] Furthermore, the synchronization circuit 10 may also include a switching circuit 300 for switching the frequency-locked loop (FLP) and the phase-locked loop (PLP). A specific example of the structure of the switching circuit 300 is shown in [the diagram / illustration]. Figure 12 , Figure 13 This will be explained in the following section. Additionally, the following will be explained... Figure 12 , Figure 13 The illustration of the switch circuit 300 is a conceptual illustration. Hereinafter, as the on / off control of the switch included in the switch circuit 300, an electrical on / off control based on a CMOS analog switch is illustrated. However, on / off control can also be achieved by a single transistor, for example.

[0061] For example, such as Figure 11As shown, the phase-locked loop (PLP) includes, for example, the voltage-controlled oscillator 100, loop filter 200, and current generation circuit 900, as described above, and also includes a phase comparator 500. The phase comparator 500 compares the phase of the frequency-locked input signal SG with that of the clock signal SGCLK. A detailed structural example of the phase comparator 500 will be described later, but the phase comparator 500 can be a half-rate type or a Bang-Bang type; a portion of the structure of the synchronization circuit 10 can be appropriately modified depending on the phase comparison method used. Furthermore, although not shown, the phase comparator 500 outputs a rising signal to advance the phase of the clock signal SGCLK or a falling signal to delay the phase of the clock signal SGCLK. The voltage-controlled oscillator 100 outputs a clock signal SGCLK based on the rising or falling signal output by the phase comparator 500.

[0062] Alternatively, for example, when the phase comparator 500 is a half-rate type, the synchronization circuit 10 can also be as follows: Figure 11 The configuration shown also includes a second charge pump circuit 620. The phase-locked loop (PLP) includes the phase comparator 500 and the second charge pump circuit 620. The second charge pump circuit 620 causes the voltage output to the loop filter 200 to rise or fall based on the rising or falling signal output from the phase comparator 500. The basic structure and operation of the second charge pump circuit 620 are the same as those of the first charge pump circuit 610, but the relationship between the magnitude of the current based on the rising signal and the magnitude of the current based on the falling signal is different from that of the first charge pump circuit 610. In other words, the circuit structure of the first charge pump circuit 610 is the same as that of the second charge pump circuit 620, but the specifications of the transistors included in the first charge pump circuit 610 are different from those of the transistors included in the second charge pump circuit 620.

[0063] As described above, the synchronization circuit 10 of this embodiment includes a phase comparator 500, a second charge pump circuit 620 that outputs a current corresponding to the comparison result of the phase comparator 500, and a switching circuit 300 that switches between a frequency-locked loop (FLP) and a phase-locked loop (PLP). Furthermore, the FLP includes a comparator circuit 40, a first charge pump circuit 610, a loop filter 200, a current generation circuit 900, and a voltage-controlled oscillator 100 to synchronize the frequency of the input signal SG and the clock signal SGCLK. Similarly, the PLP includes a phase comparator 500, a second charge pump circuit 620, a loop filter 200, a current generation circuit 900, and a voltage-controlled oscillator 100 to synchronize the phase of the input signal SG and the clock signal SGCLK. In this manner, a synchronization circuit 10 capable of switching between the FLP containing the first charge pump circuit 610 and the PLP containing the second charge pump circuit 620 can be constructed.

[0064] Alternatively, the method of this embodiment can also be implemented as a communication interface circuit 1 including the synchronization circuit 10 of the modified embodiment described above. That is, the communication interface circuit 1 of this embodiment includes a synchronization circuit 10. The synchronization circuit 10 includes a phase comparator 500, a second charge pump circuit 620 that outputs a current corresponding to the comparison result of the phase comparator 500, and a switching circuit 300 that switches between the frequency-locked loop (FLP) and the phase-locked loop (PLP). Furthermore, the frequency-locked loop (FLP) includes a comparator circuit 40, a first charge pump circuit 610, a loop filter 200, a current generation circuit 900, and a voltage-controlled oscillator 100 to synchronize the frequency of the input signal SG and the clock signal SGCLK. Furthermore, the phase-locked loop (PLP) includes a phase comparator 500, a second charge pump circuit 620, a loop filter 200, a current generation circuit 900, and a voltage-controlled oscillator 100 to synchronize the phase of the input signal SG and the clock signal SGCLK. Thus, the same effects as described above can be obtained.

[0065] A detailed structural example of the switching circuit 300 is provided. Figure 12 As shown, the switching circuit 300 includes, for example, a first switching circuit 310 and a second switching circuit 320. Additionally, as... Figure 12 As shown, the first switch circuit 310 includes a first switch 311 and a first switch 312, and the second switch circuit 320 includes a second first switch 321 and a second second switch 322.

[0066] like Figure 12 As shown, the first switch 311 is connected between the input node N1 and the comparator circuit 40, and the first switch 312 is connected between the input node N1 and the phase comparator 500. Additionally, the second switch 321 is connected between the first charge pump circuit 610 and the control voltage node NCV, and the second switch 322 is connected between the second charge pump circuit 620 and the control voltage node NCV.

[0067] For example, by turning on the first switch 311 and the second switch 321, and turning off the first switch 312 and the second switch 322, the input node N1, the comparator circuit 40, the first charge pump circuit 610, and the control voltage node NCV are connected. Thus, a frequency-locked loop (FLP) is formed. On the other hand, for example, by turning off the first switch 311 and the second switch 321, and turning on the first switch 312 and the second switch 322, the input node N1, the phase comparator 500, the second charge pump circuit 620, and the control voltage node NCV are connected. Thus, a phase-locked loop (PLP) is formed. Therefore, by controlling the turning on and off of the first switch 311, the first switch 312, the second switch 321, and the second switch 322, the switching between the frequency-locked loop (FLP) and the phase-locked loop (PLP) can be controlled.

[0068] Additionally, although the illustration is omitted, the synchronization circuit 10 may also include a control circuit for controlling the on / off state of the switch circuit 300. The control circuit may be a logic circuit that can be implemented using automatic configuration routing, such as a gate array, but is not limited to logic circuits. It can be implemented using a processor such as a CPU, and the operation of the control circuit can be performed by software. Alternatively, the control circuit may be located outside the synchronization circuit 10. For example, an input signal SG and a clock signal SGCLK are input to the control circuit, and a first control signal and a second control signal are output from the control circuit. The control circuit determines whether the frequency is locked based on the input signal SG and the clock signal SGCLK. Specifically, for example, the control circuit counts the number of pulses of the input signal SG and the number of pulses of the clock signal SGCLK, and calculates the difference between the number of pulses of the input signal SG and the number of pulses of the clock signal SGCLK counted within a certain period. This certain period is, for example, measured by counting a predetermined number of pulses of the input signal SG, and the difference between the predetermined number of pulses of the input signal SG and the number of pulses of the clock signal SGCLK is equivalent to the difference. Then, the control circuit determines that the frequency is locked if the calculated difference is within a certain value, and determines that the frequency is not locked if the calculated difference is greater than a certain value.

[0069] For example, assume that the first switch 311, the first second switch 312, the second first switch 321, and the second second switch 322 are all CMOS analog switches. In this case, a first control signal is input to the gate of the NMOS transistor of the first first switch 311, and a second control signal is input to the gate of the PMOS transistor of the first first switch 311. Similarly, a first control signal is input to the gate of the PMOS transistor of the first second switch 312, and a second control signal is input to the gate of the NMOS transistor of the first second switch 312. Likewise, a first control signal is input to the gate of the NMOS transistor of the second first switch 321, and a second control signal is input to the gate of the PMOS transistor of the second first switch 321. Finally, a first control signal is input to the gate of the PMOS transistor of the second second switch 322, and a second control signal is input to the gate of the NMOS transistor of the second second switch 322. Furthermore, the control circuit, by outputting a high-level first control signal and a low-level second control signal, turns on the first switch 311 and the second switch 321, and turns off the first switch 312 and the second switch 322, thereby selecting the frequency-locked loop (FLP). Conversely, the control circuit, by outputting a low-level first control signal and a high-level second control signal, turns off the first switch 311 and the second switch 321, and turns on the first switch 312 and the second switch 322, thereby selecting the phase-locked loop (PLP).

[0070] As described above, in the synchronization circuit 10 of this embodiment, the switching circuit 300 includes a first switching circuit 310 and a second switching circuit 320. The first switching circuit 310 includes: a first switch 311 connected between the input node N1 of the input signal SG and the comparator circuit 40; and a first switch 312 connected between the input node N1 and the phase comparator 500. The second switching circuit 320 includes: a second switch 321 connected between the first charge pump circuit 610 and the control voltage node NCV; and a second switch 322 connected between the second charge pump circuit 620 and the control voltage node NCV. Furthermore, a frequency-locked loop (FLP) is selected by turning on the first switch 311 and the second switch 321, and a phase-locked loop (PLP) is selected by turning on the first switch 312 and the second switch 322. Thus, a synchronization circuit 10 can be constructed that switches between the frequency-locked loop (FLP) and the phase-locked loop (PLP) by controlling the on / off state of the first switching circuit 310 and the second switching circuit 320.

[0071] Furthermore, for example, when the phase comparator 500 is a half-rate type phase comparator, even when a phase-locked loop (PLP) is selected, the synchronization circuit 10 can be operated by generating a small bias current in the current generation circuit 900. That is, in the synchronization circuit 10 of this embodiment, the phase comparator 500 is a half-rate type phase comparator, and the current generation circuit 900 flows a small bias current when a PLP is selected. As a result, the PLP can operate stably. For example, it is generally known in half-rate type phase comparators that the width of the rising signal changes while the width of the falling signal remains constant. Therefore, for example, when the rising signal fluctuates greatly due to manufacturing deviations of the phase comparator 500, it may exceed the capture range and shift to a higher frequency. In addition, phase locking is more sensitive to voltage fluctuations in the control voltage node NCV than frequency locking. In this regard, by applying the method of this embodiment, a small bias current can flow from the control voltage node NCV, thus appropriately maintaining the phase-locked state of the half-rate type phase comparator. Alternatively, when a phase-locked loop (PLP) is selected, control can be implemented that prevents the generation of a small bias current from the current generation circuit 900. For example, Figure 3 The counter 922 includes a reset terminal (not shown), to which the control circuit sends a signal SGRST. Then, when it is determined that the frequency is not locked, the control circuit outputs a low-level signal SGRST, releasing the reset of the counter 922. Thus, the counter 922 can perform... Figure 3 As described above, the current generation circuit 900 can generate a small bias current. On the other hand, when it is determined that the frequency is locked, the control circuit outputs a high-level signal SGRST to reset the counter 922. As a result, the count value counted by the counter 922 is reset to 0, and therefore no pulse voltage is output from the NAND circuit 924. Therefore, when the frequency is locked, that is, when the phase-locked loop (PLP) is selected, the current generation circuit 900 does not generate a small bias current. As described above, in the synchronization circuit 10 of this embodiment, the current generation circuit 900 flows a small bias current when the frequency-locked loop (FLP) is selected, and does not flow a small bias current when the phase-locked loop (PLP) is selected. Therefore, a synchronization circuit 10 can be constructed that generates a small bias current only when a loop that facilitates the generation of a small bias current is selected.

[0072] In addition, it was combined Figure 10 Structure Figure 11 Structure and Figure 12 The synchronization circuit 10 is configured such that the first charge pump circuit 610 and the second charge pump circuit 620 are different, but for example, under certain conditions, the synchronization circuit 10 can also be configured to... Figure 13 The structure example shown. Additionally, for ease of explanation, the following will combine [structures]. Figure 10Structure Figure 11 Structure and Figure 12 The synchronization circuit 10 with the structure is referred to as "synchronization circuit 10 of the first embodiment".

[0073] Figure 13 The synchronization circuit 10 is the same as the synchronization circuit 10 of the first embodiment in that it includes the aforementioned comparison circuit 40, voltage-controlled oscillator 100, loop filter 200, switching circuit 300, phase comparator 500, and current generation circuit 900. Furthermore, in Figure 13 The synchronization circuit 10, which switches between the frequency-locked loop (FLP) and the phase-locked loop (PLP) via the on / off control of the switching circuit 300, is also the same as the synchronization circuit 10 in the first embodiment. On the other hand, Figure 13 The difference between the synchronization circuit 10 in this embodiment and the synchronization circuit 10 in the first embodiment is that the frequency-locked loop FLP and the phase-locked loop PLP share the first charge pump circuit 610.

[0074] like Figure 7 As shown, the fact that the frequency-locked loop (FLP) and the phase-locked loop (PLP) share the first charge pump circuit 610 means that the operation of the first charge pump circuit 610 is the same in both the FLP and the PLP. That is, the specified condition is that the relationship between the magnitudes of the rising and falling signals output from the comparator circuit 40 is the same as the relationship between the magnitudes of the rising and falling signals output from the phase comparator 500. Illustrations of the operation are omitted in this embodiment, but the specified condition can be met, for example, when the phase comparator 500 is a Bang-Bang type. Thus, the synchronization circuit 10 of this embodiment includes the phase comparator 500 and a switching circuit 300 that switches between the FLP and the PLP. The FLP includes the comparator circuit 40, the first charge pump circuit 610, the loop filter 200, the current generation circuit 900, and the voltage-controlled oscillator 100, performing frequency synchronization between the input signal SG and the clock signal SGCLK. The phase-locked loop (PLP) includes a phase comparator 500, a first charge pump circuit 610, a loop filter 200, a current generation circuit 900, and a voltage-controlled oscillator 100, which synchronizes the input signal SG with the clock signal SGCLK. This allows for the construction of a synchronization circuit 10 that switches between the frequency-locked loop (FLP) and the phase-locked loop (PLP) with a simpler structure.

[0075] Additionally, although the illustrations are omitted, Figure 13 In the synchronization circuit 10, the frequency-locked loop (FLP) may further include a third frequency divider for dividing the clock signal SGCLK and a fourth frequency divider for dividing the input signal SG. Furthermore, the division ratio of the third frequency divider is the same as that of the fourth frequency divider. Therefore, the synchronization circuit 10 can handle situations where the frequency of the input signal SG and the frequency of the clock signal SGCLK are both relatively high.

[0076] In addition, more specifically, using Figure 13 In the case of the synchronization circuit 10, the switching circuit 300 is configured to include a third switching circuit 330 and a fourth switching circuit 340. The third switching circuit 330 includes a third first switch 331 and a third second switch 332, and the fourth switching circuit 340 includes a fourth first switch 341 and a fourth second switch 342. Figure 8 The synchronization circuit 10 is the same. Furthermore, Figure 13 The switch shown in A2 is the switch used for the rising signal in the fourth first switch 341, and the switch shown in A3 is the switch used for the falling signal in the fourth first switch 341. Similarly, Figure 13 The switch shown in A4 is the switch used for the rising signal in the fourth second switch 342, and the switch shown in A5 is the switch used for the falling signal in the fourth second switch 342.

[0077] The third first switch 331 is connected between input node N1 and comparator circuit 40, and the third second switch 332 is connected between input node N1 and phase comparator 500. Furthermore, the fourth first switch 341 is connected between comparator circuit 40 and first charge pump circuit 610, and the fourth second switch 342 is connected between phase comparator 500 and first charge pump circuit 610.

[0078] For example, by turning on the third first switch 331 and the fourth first switch 341, and turning off the third second switch 332 and the fourth second switch 342, the input node N1, the comparator circuit 40, the first charge pump circuit 610, and the control voltage node NCV are connected. This constitutes a frequency-locked loop (FLP). On the other hand, for example, by turning off the third first switch 331 and the fourth first switch 341, and turning on the third second switch 332 and the fourth second switch 342, the input node N1, the phase comparator 500, the first charge pump circuit 610, and the control voltage node NCV are connected. This constitutes a phase-locked loop (PLP). Therefore, by controlling the turning on and off of the third first switch 331, the third second switch 332, the fourth first switch 341, and the fourth second switch 342, it is possible to control... Figure 13 The switching between the frequency-locked loop FLP and the phase-locked loop PLP in the synchronization circuit 10.

[0079] Furthermore, the on / off control of the third switch circuit 330 and the fourth switch circuit 340 can be implemented using the same method as the on / off control of the first switch circuit 310 and the second switch circuit 320. That is, although the figures are omitted, the third first switch 331, the third second switch 332, the fourth first switch 341, and the fourth second switch 342 are all CMOS analog switches. In this case, a first control signal is input to the gate of the NMOS transistor of the third first switch 331, and a second control signal is input to the gate of the PMOS transistor of the third first switch 331. Similarly, a first control signal is input to the gate of the PMOS transistor of the third second switch 332, and a second control signal is input to the gate of the NMOS transistor of the third second switch 332. Likewise, a first control signal is input to the gate of the NMOS transistor of the fourth first switch 341, and a second control signal is input to the gate of the PMOS transistor of the fourth first switch 341. Furthermore, a first control signal is input to the gate of the PMOS transistor of the fourth second switch 342, and a second control signal is input to the gate of the NMOS transistor of the fourth second switch 342. The control circuit, by outputting a high-level first control signal and a low-level second control signal, turns on the third first switch 331 and the fourth first switch 341, and turns off the third second switch 332 and the fourth second switch 342, thereby achieving selection of the frequency-locked loop (FLP). Conversely, the control circuit, by outputting a low-level first control signal and a high-level second control signal, turns off the third first switch 331 and the fourth first switch 341, and turns on the third second switch 332 and the fourth second switch 342, thereby achieving selection of the phase-locked loop (PLP).

[0080] As described above, in the synchronization circuit 10 of this embodiment, the switching circuit 300 further includes a third switching circuit 330, which includes: a third first switch 331 connected between the input node N1, which receives the input signal SG, and the comparator circuit 40; and a third second switch 332 connected between the input node N1 and the phase comparator 500. Additionally, the switching circuit 300 also includes a fourth switching circuit 340, which includes: a fourth first switch 341 connected between the comparator circuit 40 and the first charge pump circuit 610; and a fourth second switch 342 connected between the phase comparator 500 and the first charge pump circuit 610. Furthermore, a frequency-locked loop (FLP) is selected by turning on the third first switch 331 and the fourth first switch 341, and a phase-locked loop (PLP) is selected by turning on the third second switch 332 and the fourth second switch 342. Therefore, the switching between the frequency-locked loop (FLP) and the phase-locked loop (PLP) can be controlled by turning on and off the third switch circuit 330 and the fourth switch circuit 340, and a synchronization circuit 10 based on a simple structure can be constructed.

[0081] Furthermore, although the illustration is omitted, the loop filter 200 can also perform first-loop filtering based on a first filtering characteristic and second-loop filtering based on a second filtering characteristic. The first filtering characteristic and the second filtering characteristic are different. Specifically, for example, the cutoff frequency involved in the first filtering characteristic is different from the cutoff frequency involved in the second filtering characteristic. More specifically, the time constant of the lead filter involved in the first filtering characteristic is different from the time constant of the lead filter involved in the second filtering characteristic. Additionally, the loop filter 200 can switch between the first filtering characteristic and the second filtering characteristic during the timing of switching from a frequency-locked loop (FLP) to a phase-locked loop (PLP). Thus, for example, in a frequency-locked loop (FLP), the loop filter 200 can perform first-loop filtering, and in a phase-locked loop (PLP), the loop filter 200 can perform second-loop filtering.

[0082] For example, although the illustration is omitted, the loop filter 200 includes multiple resistor circuits with different resistance values ​​and a fifth specified switch. By making the resistor circuits connected to the capacitors in the frequency-locked loop (FLP) and phase-locked loop (PLP) different, it is possible to make the first and second filtering characteristics different. Furthermore, the control circuit can control the fifth specified switch by switching the resistor circuits connected to the capacitors included in the loop filter 200, using the same method as the control of the switch circuit 300 described above.

[0083] As described above, in the synchronization circuit 10 of this embodiment, when the frequency-locked loop (FLP) is selected by the switching circuit 300, the loop filter 200 performs a first loop filtering process with a first filtering characteristic. When the phase-locked loop (PLP) is selected by the switching circuit 300, the loop filter 200 performs a second loop filtering process with a second filtering characteristic different from the first filtering characteristic. Therefore, different loop filtering processes are performed in the FLP and PLP, thus enabling the synchronization circuit 10 to operate more appropriately using only one loop filter 200. More specifically, according to... Figure 10 and Figure 11 Frequency-locked loops (FLPs) sometimes include a first divider 710 and a second divider 720, while phase-locked loops (PLPs) do not. Therefore, the frequency at which the input signal SG and the clock signal SGCLK are compared in the PLP is sometimes higher than the frequency at which they are compared in the FLP. To ensure the phase margin required for stable operation of both the FLP and PLP, it is desirable to minimize the cutoff frequency; however, when the cutoff frequency is too low, the tracking accuracy of the clock signal SGCLK deteriorates. Since the frequency of the clock signal SGCLK selected in the PLP is higher than that selected in the FLP, it is desirable to further improve the tracking accuracy of the clock signal SGCLK. Therefore, it is convenient to make the cutoff frequency of the second filter characteristic used in the PLP higher than the cutoff frequency of the first filter characteristic used in the FLP. Therefore, the resistance values ​​of each resistor circuit included in the loop filter 200 can be set in such a way that the time constant involved in the first filter characteristic is higher than the time constant involved in the second filter characteristic.

[0084] Next, the operation of the synchronization circuit 10 in this embodiment will be briefly described. Furthermore, the synchronization circuit 10 described below is the synchronization circuit 10 of the first embodiment. In other words, in the following description, the phase comparator 500 included in the phase-locked loop (PLP) will be described as a half-rate type.

[0085] Figure 14 A more detailed structural example of the voltage-controlled oscillator 100 according to this embodiment is shown below. The voltage-controlled oscillator 100 includes delay circuits shown in B1, B2, B3, B4, and B5. Furthermore, Figure 14Node N41 is the high-potential side power supply node, node N42 is the low-potential side power supply node, and node N51 is the node connected to the control voltage node NCV. That is, the voltage-controlled oscillator 100 is a 5-stage ring oscillator. The structure and operation of the ring oscillator are well-known and will not be described in detail here; however, clock signals SGCLK with different phases are output from each delay circuit. For example, based on the clock signal SGCLK output from node N61, a clock signal SGCLK with a phase delay of 72 degrees is output from node N63. Furthermore, using the same reference, a clock signal SGCLK with a phase delay of 144 degrees is output from node N65, a clock signal SGCLK with a phase delay of 216 degrees is output from node N62, and a clock signal SGCLK with a phase delay of 288 degrees is output from node N64.

[0086] In the synchronization circuit 10 of this embodiment, frequency locking is performed, for example, based on the clock signal SGCLK output from node N61, during the selection of the frequency-locked loop (FLP). Conceptually, in the process of selecting the frequency-locked loop (FLP), frequency locking is performed. Figure 15 When the signal shown in C10 is set as the input signal SG and the signal shown in C20 is set as the clock signal SGCLK, the rising edge of the input signal SG coincides with the rising edge of the clock signal SGCLK, thus achieving a frequency-locked state.

[0087] Furthermore, when the phase-locked loop (PLP) is selected, the clock signal SGCLK output from node N63 of the voltage-controlled oscillator 100 is input to the phase comparator 500. That is, the waveform of the input signal SG at the timing when the PLP is selected and phase synchronization between the input signal SG and the clock signal SGCLK begins is... Figure 15 In the case of the waveform shown in C10, the waveform of the clock signal SGCLK under the same timing becomes Figure 15 The waveform shown in C30. In the waveform shown in C30, the phase difference shown in C31 is from... Figure 13 The phase difference between the waveform output by node N61 and the waveform output by node N63 is equivalent to 72 degrees.

[0088] In the synchronization circuit 10 of the first embodiment, the phase is locked when the phase of the clock signal SGCLK is delayed by 90 degrees relative to the phase of the input signal SG. That is, the waveform of the input signal SG, when the phases of the input signal SG and the clock signal SGCLK are locked by the phase-locked loop (PLP), becomes... Figure 15 In the case of the waveform shown in C10, the waveform of the clock signal SGCLK under the same state becomes Figure 15The waveform shown in C40. In the waveform shown in C40, the phase difference shown in C41 is equivalent to 90 degrees. As mentioned above, compared to delaying the phase of the clock signal SGCLK by 90 degrees relative to the phase of the input signal SG from the state where the clock signal SGCLK and the input signal SG are in phase, delaying the phase of the clock signal SGCLK by 90 degrees relative to the phase of the input signal SG from the state where the phase of the clock signal SGCLK is delayed by 72 degrees relative to the phase of the input signal SG, it is more conducive to phase locking.

[0089] Figure 16 A more detailed structural example of the phase comparator 500 is shown. Additionally, Figure 16 An example of a differential circuit is shown. More specifically, for example, an input signal SG and a signal SGN, which is the logic inverted signal of the input signal SG, are shown being input to... Figure 15 The buffer shown is D1. Similarly, the signal SGCLKN is the logical inverted version of the clock signal SGCLK. Additionally, Figure 16 The signals UP and UPN, their logical inverses, are rising signals output from phase comparator 500, while DN and DNN, their logical inverses, are falling signals output from phase comparator 500. Details will be explained later. Furthermore, from... Figure 16 The signals DA1 and DA1N, which are the logical inverted signals of the buffer D11, are related to the data contained in the first data block described later. Similarly, the signals DA2 and DA2N, which are the logical inverted signals of the buffer D12, are related to the data contained in the second data block described later. Details will be explained later. Furthermore, for simplicity, only the positive terminal of the differential signal will sometimes be used in the following explanation. The phase comparator 500 includes a master latch circuit 510, a slave latch circuit 520, a master latch circuit 530, a slave latch circuit 540, an XOR circuit 550, and an XOR circuit 560. The input signal SG is transmitted via... Figure 16 The buffer shown in D1 is input to the main latch circuit 510 and the main latch circuit 530. Furthermore, the clock signal SGCLK is input to the main latch circuit 510, the slave latch circuit 520, the main latch circuit 530, and the slave latch circuit 540 via the buffer shown in D2. Additionally, the phase comparator 500 may also include a flip-flop circuit 570 to which the clock signal SGCLK can be input. The flip-flop circuit 570 will be described later.

[0090] exist Figure 16In the phase comparator 500, a falling-edge triggered master-slave flip-flop circuit is formed by the master latch circuit 510 and the slave latch circuit 520, and a rising-edge triggered master-slave flip-flop circuit is formed by the master latch circuit 530 and the slave latch circuit 540. Specifically, for example, the master latch circuit 510 takes in the input signal SG when the clock signal SGCLK is high and holds the taken-in input when the clock signal SGCLK is low. The slave latch circuit 520 holds the taken-in input when the clock signal SGCLK is high and takes in the input from the master latch circuit 510 when the clock signal SGCLK is low. The master latch circuit 530 takes in the input signal SG when the clock signal SGCLK is low and holds the taken-in input when the clock signal SGCLK is high. The slave latch circuit 540 takes in the input from the master latch circuit 530 when the clock signal SGCLK is high and holds the taken-in input when the clock signal SGCLK is low.

[0091] In addition, Figure 16 In the phase comparator 500, the XOR circuit 550 outputs the XOR result between the output of the main latch circuit 510 and the output of the main latch circuit 530. The XOR circuit 560 outputs the XOR result between the output of the slave latch circuit 520 and the output of the slave latch circuit 540. In this embodiment, the output signal of the XOR circuit 550 is a rising signal, and the output signal of the XOR circuit 560 is a falling signal. Furthermore, in this embodiment, the output signals of the slave latch circuit 520 and the trigger circuit 570 are obtained by deserializing the input signal SG, which is a serial data signal, into a 2-bit parallel signal. In other words, Figure 16 The phase comparator 500 includes Figure 1 The data recovery circuit 50 described herein.

[0092] Figure 17 This illustrates an example of the operation of a phase comparator 500 configured in this way. Figure 17 For ease of explanation, the horizontal axis is represented as time, with equal intervals t0, t1, t2, t3, t4, t5, t6, t7, t8, t9, t10, t11, t12, t13, t14, t15, t16, t17, t18, and t19 defined on the horizontal axis. Furthermore, for simplicity, these intervals are sometimes referred to as interval T. And, from... Figure 17Starting from the top section, the waveforms of the input signal SG, clock signal SGCLK, master latch circuit 510, slave latch circuit 520, master latch circuit 530, slave latch circuit 540, XOR circuit 550, and XOR circuit 560 are conceptually shown sequentially. Furthermore, for the sake of simplicity, the high-level output signal in the positive terminal of the differential signal is simplified to "1", and the low-level output signal is simplified to "0". Additionally, the input signal SG before timing t0 is "0", and the outputs of master latch circuit 510, slave latch circuit 520, master latch circuit 530, and slave latch circuit 540 are all "0".

[0093] in addition, Figure 17 The example shows an input signal SG that is phase-locked, undergoes the aforementioned 8b10b conversion, and contains data. For example, during the period from timing t1 to timing t3, the example shows a case where the voltage of the input signal SG is high, containing a "1" as binary data. That is, in Figure 17 In this context, the input signal SG contains binary data such as "110001100" at intervals of twice the interval T after timing t1.

[0094] At time t0, the input signal SG is "0", and the clock signal SGCLK drops from "1" to "0". Therefore, the main latch circuit 510 holds the input "0" and outputs "0". Additionally, it takes "0" as the output of the main latch circuit 510 from the latch circuit 520 and outputs "0". Furthermore, the main latch circuit 530 takes "0" as the input signal SG and outputs "0", while the latch circuit 540 outputs the held "0". Thus, the XOR circuit 550 outputs "0" based on the outputs of the main latch circuit 510 and 530. Furthermore, the XOR circuit 560 outputs "0" based on the outputs of the latch circuit 520 and 540.

[0095] At time t1, the input signal SG rises from "0" to "1", and the clock signal SGCLK is "0". Therefore, the main latch circuit 510 holds the input "0" and outputs "0". Additionally, it takes a "0" from the latch circuit 520 as the output of the main latch circuit 510 and outputs "0". Furthermore, the main latch circuit 530 takes a "1" as the input of the input signal SG and outputs "1". Furthermore, the latch circuit 540 outputs the held "0". Therefore, the XOR circuit 550 outputs "1" based on the output "0" of the main latch circuit 510 and the output "1" of the main latch circuit 530. Furthermore, the XOR circuit 560 outputs "0" based on the output "0" from the latch circuit 520 and the output "0" from the latch circuit 540.

[0096] At time t2, the input signal SG remains "1", and the clock signal SGCLK rises from "0" to "1". Therefore, the main latch circuit 510 takes in the "1" as input to the input signal SG. Meanwhile, the slave latch circuit 520 outputs "0" by holding the "0" taken from the main latch circuit 510. Furthermore, the main latch circuit 530 holds the taken "1" and therefore outputs "1". Additionally, the slave latch circuit 540 takes in the "1" as output of the main latch circuit 530 and therefore outputs "1". Thus, at time t2, the XOR circuit 550 outputs "0" based on the output "1" of the main latch circuit 510 and the output "1" of the main latch circuit 530. Furthermore, the XOR circuit 560 outputs "1" based on the output "0" of the slave latch circuit 520 and the output "1" of the slave latch circuit 540. The operation of the phase comparator 500 at time t3 is the same as that at time t2, so its description is omitted.

[0097] At time t4, the input signal SG remains "1", and the clock signal SGCLK drops from "1" to "0". Therefore, the main latch circuit 510 holds the fetched input "1" and outputs "1". Additionally, it fetches "1" from the latch circuit 520 as the output of the main latch circuit 510 and outputs "1". Furthermore, the main latch circuit 530 outputs "1" by fetching "1" as the input signal SG, and the latch circuit 540 outputs the held "1". Thus, at time t4, the XOR circuit 550 outputs "0" based on the output "1" of the main latch circuit 510 and the output "1" of the main latch circuit 530. Furthermore, the XOR circuit 560 outputs "0" based on the output "1" from the latch circuit 520 and the output "1" from the latch circuit 540.

[0098] At time t5, the input signal SG drops from "1" to "0", and the clock signal SGCLK outputs "0". Therefore, the main latch circuit 510 holds the input "1" and outputs "1". Additionally, the latch circuit 520 takes the "1" from the main latch circuit 510 and outputs "1". Furthermore, the main latch circuit 530 takes the "0" from the input signal SG and outputs "0". Additionally, the latch circuit 540 holds the "1" from the main latch circuit 530 and outputs "1". Therefore, the XOR circuit 550 outputs "1" based on the output "1" of the main latch circuit 510 and the output "0" of the main latch circuit 530. Furthermore, the XOR circuit 560 outputs "0" based on the output "1" of the latch circuit 520 and the output "1" of the latch circuit 540.

[0099] At time t6, the output of input signal SG is "0", and the output of clock signal SGCLK rises from "0" to "1". Therefore, main latch circuit 510 takes in the "0" as input from input signal SG and outputs "0". Meanwhile, slave latch circuit 520 holds the "1" taken from main latch circuit 510. Furthermore, main latch circuit 530 takes in the "0" as input from input signal SG and outputs "0". Furthermore, slave latch circuit 540 takes in the "0" as output from main latch circuit 530 and outputs "0". Therefore, XOR circuit 550 outputs "0" based on the outputs of main latch circuit 510 and main latch circuit 530. Additionally, XOR circuit 560 outputs "1" based on the outputs of slave latch circuit 520 and slave latch circuit 540. The operation of phase comparator 500 at time t7 is the same as that at time t6, so its description is omitted.

[0100] At time t8, the output of input signal SG is "0", and the output of clock signal SGCLK drops from "1" to "0". Therefore, main latch circuit 510 holds the fetched input "0" and outputs "0". Additionally, latch circuit 520 fetches "0" as the output of main latch circuit 510 and outputs "0". Furthermore, main latch circuit 530 outputs "0" by fetching "0" as the input of input signal SG, and latch circuit 540 outputs "0" by holding the fetched "0". Thus, at time t8, XOR circuit 550 outputs "0" based on the outputs of main latch circuit 510 and main latch circuit 530. Furthermore, XOR circuit 560 outputs "1" based on the outputs of latch circuit 520 and latch circuit 540. The operation of phase comparator 500 at time t9 is the same as that at time t8, so its description is omitted.

[0101] At time t10, the output of input signal SG is "0", and the output of clock signal SGCLK rises from "0" to "1". Therefore, main latch circuit 510 takes in "0" as input from input signal SG and outputs "0". Slave latch circuit 520 holds the "0" taken from main latch circuit 510. Main latch circuit 530 outputs "0" by taking in "0" as input from input signal SG. Slave latch circuit 540 outputs "0" by taking in "0" as output from main latch circuit 530. Therefore, at time t10, XOR circuit 550 outputs "0" based on the outputs of main latch circuit 510 and main latch circuit 530. Furthermore, XOR circuit 560 outputs "1" based on the outputs of slave latch circuit 520 and slave latch circuit 540.

[0102] At time t11, the output of the input signal SG rises from "0" to "1", and the output of the clock signal SGCLK remains "1". Therefore, the main latch circuit 510 takes in the "1" as input from the input signal SG and outputs "1". Meanwhile, the slave latch circuit 520 holds the "0" taken from the main latch circuit 510 and therefore outputs "0". Furthermore, the main latch circuit 530 holds the taken "0" and therefore outputs "0". Additionally, the slave latch circuit 540 takes in the "0" as output from the main latch circuit 530 and outputs "0". Thus, at time t11, the XOR circuit 550 outputs "1" based on the output "1" of the main latch circuit 510 and the output "0" of the main latch circuit 530. Furthermore, the XOR circuit 560 outputs "0" based on the output "0" of the slave latch circuit 520 and the output "0" of the slave latch circuit 540.

[0103] At time t12, the output of the input signal SG remains "1", and the output of the clock signal SGCLK drops from "1" to "0". Therefore, the main latch circuit 510 outputs "1" because it holds the fetched "1". Additionally, the latch circuit 520 fetches "1" as the output of the main latch circuit 510 and outputs "1". Furthermore, the main latch circuit 530 fetches "1" as the output of the input signal SG and outputs "1". The latch circuit 540 holds the "0" fetched from the main latch circuit 530 and therefore outputs "0". Thus, at time t12, the XOR circuit 550 outputs "0" based on the output "1" of the main latch circuit 510 and the output "1" of the main latch circuit 530. Furthermore, the XOR circuit 560 outputs "1" based on the output "1" of the latch circuit 520 and the output "0" of the latch circuit 540. In addition, the operation of phase comparator 500 under time t13 is the same as that under time t12, so the explanation is omitted.

[0104] At time t14, the output of the input signal SG remains "1", and the output of the clock signal SGCLK rises from "0" to "1". Therefore, the main latch circuit 510 takes in the "1" from the output of the input signal SG and outputs "1". Additionally, the slave latch circuit 520 holds the "1" taken from the main latch circuit 510 and therefore outputs "1". Furthermore, the main latch circuit 530 holds the taken "1" and therefore outputs "1". Additionally, the slave latch circuit 540 takes in the "1" from the output of the main latch circuit 530 and outputs "1". Therefore, at time t14, the XOR circuit 550 outputs "0" based on the outputs of the main latch circuit 510 and 530. Furthermore, the XOR circuit 560 outputs "0" based on the outputs of the slave latch circuit 520 and 540.

[0105] At time t15, the output of the input signal SG decreases from "1" to "0", while the output of the clock signal SGCLK remains "1". Therefore, the main latch circuit 510 takes in the "0" as input from the input signal SG and outputs "0". Meanwhile, the slave latch circuit 520 holds the "1" taken from the main latch circuit 510 and therefore outputs "1". Furthermore, the main latch circuit 530 holds the taken "1" and therefore outputs "1". Additionally, the slave latch circuit 540 takes in the "1" as output from the main latch circuit 530 and outputs "1". Thus, at time t15, the XOR circuit 550 outputs "1" based on the output "0" of the main latch circuit 510 and the output "1" of the main latch circuit 530. Furthermore, the XOR circuit 560 outputs "0" based on the output "1" of the slave latch circuit 520 and the output "1" of the slave latch circuit 540.

[0106] At timing t16, the output of the input signal SG remains "0", and the output of the clock signal SGCLK drops from "1" to "0". Therefore, the main latch circuit 510 holds the fetched "0" and outputs "0". The slave latch circuit 520 outputs "0" by fetching the input "0" from the main latch circuit 510. The main latch circuit 530 fetches the input "0" as part of the input signal SG and outputs "0". The slave latch circuit 540 holds the "1" fetched from the main latch circuit 530 and outputs "1". Thus, at timing t16, the XOR circuit 550 outputs "0" based on the outputs of the main latch circuit 510 and 530. Furthermore, the XOR circuit 560 outputs "1" based on the outputs of the slave latch circuit 520 and 540. In addition, the operation of phase comparator 500 under time t17 is the same as that under time t16, so the explanation is omitted.

[0107] At timing t18, the output of the input signal SG remains "0", and the output of the clock signal SGCLK rises from "0" to "1". Therefore, the main latch circuit 510 takes in the "0" from the output of the input signal SG and outputs "0". Additionally, the slave latch circuit 520 holds the "0" taken from the main latch circuit 510 and therefore outputs "0". Furthermore, the main latch circuit 530 holds the taken "0" and therefore outputs "0". Additionally, the slave latch circuit 540 takes in the "0" from the output of the main latch circuit 530 and outputs "0". Thus, at timing t18, the XOR circuit 550 outputs "0" based on the outputs of the main latch circuit 510 and 530. Furthermore, the XOR circuit 560 outputs "0" based on the outputs of the slave latch circuit 520 and 540. In addition, the operation of phase comparator 500 under time t19 is the same as that under time t18, so the explanation is omitted.

[0108] As described above, the phase comparator 500 operates, and the output from the XOR circuit 550 is... Figure 17 Following the pulse shown in D51, the XOR circuit 560 outputs the pulse shown in D61. The pulse shown in D51 has the pulse width shown in E1, and the pulse shown in D61 has the pulse width shown in E2, where the width shown in E2 is twice the width shown in E1. The relationship between the pulses shown in D52 and D62 is the same, as is the relationship between the pulses shown in D53 and D63, and the relationship between the pulses shown in D54 and D64. That is, regardless of the waveform of the input signal SG, when a pulse is output from the XOR circuit 550, a pulse with twice the pulse width will inevitably be output from the XOR circuit 560.

[0109] In addition, from Figure 17 It is known that when the timing of the rising or falling of the clock signal SGCLK is delayed relative to the timing of the rising or falling of the input signal SG, a pulse is generated from the XOR circuit 550. That is, the pulse generated from the XOR circuit 550 corresponds to the rising signal. Therefore, by making the pulse generated from the XOR circuit 560 correspond to the falling signal, the phase comparator 500 can be operated in a phase-locked manner.

[0110] That is, the rising and falling signals are output in a phase-locked state such that the clock signal SGCLK is phase-delayed by 90 degrees relative to the input signal SG. However, since the pulse width corresponding to the falling signal is twice the pulse width corresponding to the rising signal, the second charge pump circuit 620 needs to set the current value output based on the rising signal input from the phase comparator 500 to twice the current value output based on the falling signal input from the phase comparator 500. This allows the amount of charge from the second charge pump circuit 620 to the loop filter 200 to be equal to the amount of charge from the sinking current introduced from the control voltage node NCV, thus enabling phase locking.

[0111] Furthermore, the sink current value of the first charge pump circuit 610 based on the rising signal output from the frequency phase comparator 400 is equal to the current value of the first charge pump circuit 610 based on the falling signal output from the frequency phase comparator 400. Therefore, as described above, the first charge pump circuit 610 and the second charge pump circuit 620 have different specifications. Thus, in the case where the phase comparator 500 is a half-rate type, the synchronization circuit 10 of the first embodiment needs to be constructed. On the other hand, in the case where the phase comparator 500 is a Bang-Bang type, the pulse width involved in the rising signal is the same as the pulse width involved in the falling signal, therefore, as Figure 13 As shown, both the frequency-locked loop (FLP) and the phase-locked loop (PLP) can use the same first charge pump circuit 610.

[0112] Additionally, the phase comparator 500 can also recover data from the input signal SG. For example, the serial data associated with the input signal SG is divided into even-numbered data blocks and odd-numbered data blocks through deserialization. For instance, the data block related to the timing of the rising clock signal SGCLK is designated as the first data block, which is the odd-numbered data block, and the data block related to the timing of the falling clock signal SGCLK is designated as the second data block, which is the even-numbered data block. In this case, Figure 17 The outputs of latch circuit 540, represented by D41, D42, D43, D44, and D45, correspond to the data of the first data block. That is, D41 represents "1", D42 represents "0", D43 represents "0", D44 represents "1", and D45 represents "0", but these correspond to the data of the input signal SG mentioned above. Similarly, Figure 17 The outputs of latch circuit 520, represented by D21, D22, D23, D24, and D25, correspond to the data of the second data block. That is, D21 represents "0", D22 represents "1", D23 represents "0", D24 represents "1", and D25 represents "0", but these values ​​are consistent with the data of the input signal SG described above. Therefore, by inputting the outputs of latch circuit 520 and latch circuit 540 respectively to... Figure 16 The output stage of D10 (with a dashed box) outputs the data of the input signal SG. This recovers the data of the input signal SG. That is, Figure 16 The dashed box shown in D10 corresponds to Figure 1 The data recovery circuit 50. Additionally... Figure 16 The trigger circuit 570 within the dashed box of D10 is configured to synchronize the timing of the input and output of the buffer shown in D11 with the timing of the input and output of the buffer shown in D12.

[0113] As described above, the communication interface circuit 1 of this embodiment further includes a data recovery circuit 50, which recovers the data of the input signal SG based on the clock signal SGCLK generated by the phase-locked loop (PLP). Therefore, the device included in the communication interface circuit 1 can be operated based on the data contained in the input signal SG, whose phase is locked by the synchronization circuit 10.

[0114] As described above, the synchronization circuit of this embodiment includes a comparator circuit, a first charge pump circuit, a loop filter, a voltage-controlled oscillator, and a current generation circuit. The comparator circuit compares the phase of the input signal with that of the clock signal and outputs a phase difference signal. The first charge pump circuit outputs a charge pump current with a predetermined pulse width corresponding to the pulse width of the phase difference signal to the control voltage node. The loop filter outputs a control voltage based on the current pulses to the control voltage node. The voltage-controlled oscillator generates a clock signal with a frequency corresponding to the control voltage. The current generation circuit includes: a current pulse generation circuit that allows a small bias current to flow through the control voltage node, generating intermittent current pulses based on the clock signal; and a smoothing circuit that generates a small bias current by smoothing the intermittent current pulses.

[0115] As described above, since the charge pump current can be biased based on a small bias current, it is possible to construct a synchronization circuit that locks the phase while avoiding dead time and suppressing the increase of jitter.

[0116] Alternatively, the current pulse generation circuit may also include: a counting circuit that generates voltage pulses with a frequency lower than that of the clock signal based on the clock signal; and a conversion circuit that converts the voltage pulses into current pulses.

[0117] This enables the generation of current pulses used to generate minute bias currents.

[0118] Alternatively, the smoothing circuit may also include: a low-pass filter containing resistors and capacitors; and a current mirror circuit that mirrors the current based on the output voltage of the low-pass filter.

[0119] Therefore, it is possible to construct a smoothing circuit that averages current pulses and extracts their output as a small bias current.

[0120] Alternatively, the comparator circuit may also include a frequency-phase comparator.

[0121] Therefore, the synchronization circuit can be enabled to function as a frequency-locked loop.

[0122] In addition, the comparator circuit may also include a first frequency divider that divides the input signal and a second frequency divider that divides the clock signal.

[0123] Therefore, it is possible to construct synchronization circuits that correspond to higher speeds of input signals and clock signals.

[0124] Furthermore, the synchronization circuit may include a phase comparator, a second charge pump circuit whose output corresponds to the current of the phase comparator comparison result, and a switching circuit for switching between the frequency-locked loop (LLL) and the phase-locked loop (PLL). Additionally, the LLL may include a comparator circuit, a first charge pump circuit, a loop filter, a current generation circuit, and a voltage-controlled oscillator for frequency synchronization of the input signal and the clock signal. The PLL may include a phase comparator, a second charge pump circuit, a loop filter, a current generation circuit, and a voltage-controlled oscillator for phase synchronization of the input signal and the clock signal.

[0125] Therefore, it is possible to construct a synchronization circuit that can switch between a frequency-locked loop containing a first charge pump circuit and a phase-locked loop containing a second charge pump circuit.

[0126] Alternatively, the switching circuit may include a first switching circuit and a second switching circuit. The first switching circuit includes: a first switch connected between the input node receiving the input signal and the comparator circuit; and a first second switch connected between the input node and the phase comparator. The second switching circuit includes: a second first switch connected between the first charge pump circuit and the control voltage node; and a second second switch connected between the second charge pump circuit and the control voltage node. Furthermore, a frequency-locked loop can be selected by turning on both the first and second first switches, and a phase-locked loop can be selected by turning on both the first and second second switches.

[0127] Therefore, it is possible to construct a synchronization circuit that switches between the frequency-locked loop and the phase-locked loop by controlling the on / off state of the first and second switching circuits.

[0128] Alternatively, the phase comparator can also be a half-rate phase comparator, and the current generation circuit can also carry a small bias current when a phase-locked loop is selected.

[0129] Therefore, when selecting a phase-locked loop, the synchronization circuit containing a half-rate phase comparator can be appropriately activated.

[0130] In addition, the current generation circuit can either allow a small bias current to flow when selecting a frequency-locked loop or allow no small bias current to flow when selecting a phase-locked loop.

[0131] Therefore, it is possible to construct a synchronous circuit that generates a small bias current only when a loop that facilitates the generation of a small bias current is selected.

[0132] Alternatively, when the frequency-locked loop is selected by the switching circuit, the loop filter performs a first loop filtering process with the first filtering characteristic; when the phase-locked loop is selected by the switching circuit, it performs a second loop filtering process with the second filtering characteristic, which is different from the first filtering characteristic.

[0133] Therefore, different loop filtering processes are performed in the frequency-locked loop and the phase-locked loop, so that the synchronization circuit can operate more properly through a single loop filter.

[0134] Furthermore, this embodiment relates to a communication interface circuit that includes the aforementioned synchronization circuit. The synchronization circuit includes a phase comparator, a second charge pump circuit that outputs a current corresponding to the comparison result of the phase comparator, and a switching circuit that switches between a frequency-locked loop (LLL) and a phase-locked loop (PLL). The LLL includes a comparator circuit, a first charge pump circuit, a loop filter, a current generation circuit, and a voltage-controlled oscillator to synchronize the frequency of the input signal and the clock signal. The PLL includes a phase comparator, a second charge pump circuit, a loop filter, a current generation circuit, and a voltage-controlled oscillator to synchronize the phase of the input signal and the clock signal.

[0135] In addition, the communication interface circuit may also include a data recovery circuit, which recovers the data of the input signal based on the clock signal generated by the phase-locked loop.

[0136] Therefore, the device contained in the communication interface circuit 1 can be activated based on the data contained in the input signal whose phase is locked by the synchronization circuit.

[0137] Furthermore, while this embodiment has been described in detail above, those skilled in the art will readily understand that various modifications can be made without substantially departing from the new aspects and effects of this disclosure. Therefore, all such modifications are included within the scope of this disclosure. For example, a term described at least once in the specification or drawings along with a different, broader, or synonymous term can be replaced with that different term anywhere in the specification or drawings. Moreover, all combinations of this embodiment and its modifications are also included within the scope of this disclosure. Furthermore, the structure and operation of the synchronization circuit and communication interface circuit, etc., are not limited to those described in this embodiment, and various modifications can be implemented.

Claims

1. A synchronous circuit, characterized in that, The synchronization circuit includes: The comparator circuit compares the phase of the input signal with the clock signal and outputs a phase difference signal. The first charge pump circuit outputs a charge pump current with a predetermined pulse width corresponding to the pulse width of the phase difference signal to the control voltage node; A loop filter that outputs a control voltage to the control voltage node based on the charge pump current with the specified pulse width; A voltage-controlled oscillator that generates a clock signal with a frequency corresponding to the control voltage; and A current generating circuit that allows a small bias current to flow through the control voltage node. The current generation circuit includes: A current pulse generation circuit generates intermittent current pulses based on the clock signal; as well as A smoothing circuit generates the minute bias current by smoothing the intermittent current pulses.

2. The synchronization circuit according to claim 1, characterized in that, The current pulse generation circuit includes: A counting circuit that generates voltage pulses with a frequency lower than that of the clock signal, based on the clock signal; and A conversion circuit that converts the voltage pulse into the current pulse.

3. The synchronization circuit according to claim 1, characterized in that, The smoothing circuit includes: A low-pass filter, which includes resistors and capacitors; and A current mirror circuit that mirrors the current based on the output voltage of the low-pass filter.

4. The synchronization circuit according to claim 3, characterized in that, The comparison circuit includes a frequency-phase comparator.

5. The synchronization circuit according to claim 4, characterized in that, The comparison circuit further includes a first frequency divider for dividing the input signal and a second frequency divider for dividing the clock signal.

6. The synchronization circuit according to claim 1, characterized in that, The synchronization circuit includes: Phase comparator; The second charge pump circuit outputs a current corresponding to the comparison result of the phase comparator; and The switching circuit switches between the frequency-locked loop and the phase-locked loop. The frequency-locked loop includes the comparator circuit, the first charge pump circuit, the loop filter, the current generation circuit, and the voltage-controlled oscillator. The frequency-locked loop synchronizes the frequency of the input signal with that of the clock signal. The phase-locked loop includes the phase comparator, the second charge pump circuit, the loop filter, the current generation circuit, and the voltage-controlled oscillator. The phase-locked loop synchronizes the input signal with the clock signal.

7. The synchronization circuit according to claim 6, characterized in that, The switching circuit includes: The first switching circuit includes a first switch connected between the input node to which the input signal is input and the comparison circuit, and a first second switch connected between the input node and the phase comparator. as well as The second switching circuit includes a second first switch connected between the first charge pump circuit and the control voltage node, and a second second switch connected between the second charge pump circuit and the control voltage node. The switching circuit selects the frequency-locked loop by turning on the first switch and the second switch, and selects the phase-locked loop by turning on the first switch and the second switch.

8. The synchronization circuit according to claim 6, characterized in that, The phase comparator is a half-rate phase comparator. The current generation circuit flows through the tiny bias current when the phase-locked loop is selected.

9. The synchronization circuit according to claim 6, characterized in that, The current generation circuit flows through the small bias current when the frequency-locked loop is selected, and does not flow through the small bias current when the phase-locked loop is selected.

10. The synchronization circuit according to claim 6, characterized in that, When the frequency-locked loop is selected via the switching circuit, the loop filter performs a first loop filtering process, which is the first filtering characteristic. When the phase-locked loop is selected by the switching circuit, the loop filter performs a second loop filtering process, which is a second filtering process with a second filtering characteristic that is different from the first filtering characteristic.

11. A communication interface circuit, said communication interface circuit comprising the synchronization circuit of claim 1, characterized in that, The synchronization circuit includes: Phase comparator; The second charge pump circuit outputs a current corresponding to the comparison result of the phase comparator; and The switching circuit switches between the frequency-locked loop and the phase-locked loop. The frequency-locked loop includes the comparator circuit, the first charge pump circuit, the loop filter, the current generation circuit, and the voltage-controlled oscillator. The frequency-locked loop synchronizes the frequency of the input signal with that of the clock signal. The phase-locked loop includes the phase comparator, the second charge pump circuit, the loop filter, the current generation circuit, and the voltage-controlled oscillator. The phase-locked loop synchronizes the input signal with the clock signal.

12. The communication interface circuit according to claim 11, characterized in that, The communication interface circuit also includes a data recovery circuit, which recovers the data of the input signal based on the clock signal generated by the phase-locked loop.

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