Digital pre-distortion method, device and equipment for improving DAC linearity and medium

Abstract

The application provides a digital pre-distortion method, device, equipment and medium for improving DAC linearity, which comprises the following steps: collecting voltage fluctuation information of an analog power supply pin of a DAC; establishing a nonlinear distortion model describing the relationship between the output distortion of the DAC and the voltage fluctuation information; based on the nonlinear distortion model, performing pre-distortion processing on original digital signals input to the DAC to generate pre-distortion digital signals; collecting actual analog output of the DAC, comparing the actual analog output with expected output, and obtaining an error signal; updating parameters of the nonlinear distortion model according to the error signal, and continuously processing the DAC pre-distortion processing by using the updated nonlinear distortion model. The above method improves the DAC linearity and reduces the distortion of the DAC.

Description

Technical Field

[0001] This application relates to the field of digital predistortion technology, and in particular to a digital predistortion method, apparatus, device and medium for improving the linearity of a DAC. Background Technology

[0002] Digital-to-analog converters (DACs) are widely used in communication systems, audio equipment, precision instruments, and automatic control, and their linearity is a core indicator determining the accuracy of the output signal. In real-world operating environments, voltage fluctuations inevitably occur on the analog power supply pins and reference voltage pins of the DAC, introduced by switching power supply ripple, load surges, or external electromagnetic interference. These voltage fluctuations directly couple to the DAC's internal conversion circuitry, causing nonlinear changes in the switching behavior of the output stage current source or resistor ladder network, thereby generating additional harmonic distortion and integral nonlinearity errors.

[0003] Because power supply voltage fluctuations are time-varying and random, hardware filtering or fixed compensation schemes cannot track and counteract their dynamic impact on DAC linearity in real time, resulting in significant distortion and insufficient linearity in the output signal of existing DACs in high-precision application scenarios. Summary of the Invention

[0004] This application provides a digital predistortion method, apparatus, device, and medium for improving DAC linearity, thereby increasing DAC linearity and reducing DAC distortion.

[0005] In a first aspect, embodiments of this application provide a digital predistortion method for improving the linearity of a DAC, the method comprising: Collect voltage fluctuation information from the analog power supply pins of the DAC; A nonlinear distortion model is established to describe the relationship between the output distortion of the DAC and the voltage fluctuation information; Based on the aforementioned nonlinear distortion model, predistortion processing is applied to the original digital signal input to the DAC to generate a predistorted digital signal; The actual analog output of the DAC is acquired, and the actual analog output is compared with the expected output to obtain the error signal; The parameters of the nonlinear distortion model are updated based on the error signal, and the updated nonlinear distortion model is used to continuously process the DAC predistortion process.

[0006] In some embodiments, acquiring the voltage fluctuation information of the analog power supply pin of the DAC includes: The voltage waveform on the analog power supply pin is acquired at a sampling frequency higher than the input data rate of the DAC; Perform a fast Fourier transform on the voltage waveform to decompose the waveform time-domain data in the voltage waveform. The time-domain data includes: ripple fundamental frequency, harmonic components and power spectral density of random noise. The waveform time-domain data is filtered by moving average to extract instantaneous voltage fluctuation value, ripple amplitude and DC bias value, and output as voltage fluctuation information.

[0007] In some embodiments, establishing the nonlinear distortion model includes: Based on the voltage fluctuation information, a power modulation function is calculated, wherein the power modulation function is the ratio of the instantaneous voltage fluctuation value to a preset nominal reference voltage; A nonlinear error term in polynomial form is constructed based on the product of the higher power of the input code value and the instantaneous voltage fluctuation value. A set of pre-stored test sequences is output to the DAC, and the test output response is read. The coefficients of the polynomial are fitted using the least squares method to complete the establishment of the nonlinear distortion model.

[0008] In some embodiments, the predistortion processing includes: Based on the power supply modulation function in the nonlinear distortion model, the amplitude pre-compensation factor is calculated, and the digital signal is multiplied to complete the amplitude correction. The corrected digital signal and its powers are input to a finite impulse response filter, the coefficients of which are the polynomial coefficients in the nonlinear distortion model, and the nonlinear predistortion compensation signal is calculated. The amplitude-corrected signal is superimposed with the nonlinear predistortion compensation signal, and the superposition result is amplitude-limited to generate a predistortion digital signal.

[0009] In some embodiments, the step of collecting the actual simulation output and updating the model parameters includes: The feedback analog-to-digital converter is invoked to sample the actual analog output of the DAC at the same update rate as the DAC, and the feedback digital code is read. The desired digital code corresponding to the desired output is calculated based on the predistorted digital signal and the preset nominal reference voltage. The difference between the expected digital code and the feedback digital code is calculated as an error signal, and the error signal is sent to the adaptive algorithm module to update the parameters of the nonlinear distortion model.

[0010] In some embodiments, the adaptive algorithm is a proportional normalized least mean square algorithm with leakage terms, and its coefficient update formula is: β(n+1)=(1-ρλ)·β(n)+μ·P(n)·e(n)·X(n) / (γ+X(n) P(n)X(n)); Wherein, β(n) is the parameter vector of the nonlinear distortion model, e(n) is the error signal, X(n) is the input signal vector, μ is the step size factor, λ is the leakage coefficient, ρ is the proportional control factor, γ is the regularization constant, and P(n) is the proportional gain diagonal matrix, whose diagonal elements are dynamically allocated proportionally according to the magnitude of the absolute value of each component in β(n).

[0011] In some embodiments, the adaptive algorithm further includes a variable step size control mechanism, wherein the step size factor μ is dynamically adjusted to μ(n) based on the ratio of the short-time power to the high-frequency changing power of the error signal, and the adjustment formula is: μ(n) = μ max ·[1-σ e²(n) / (σ e²(n) +σ v²(n) )]; Where, σ e²(n) For the short-time power estimation of the error signal, σ v²(n) For the high-frequency power estimation of the error signal, μ max The maximum step size is preset; when the ratio is greater than the first threshold, a large step size is used to achieve rapid convergence, and when the ratio is less than the second threshold, a small step size is used to reduce steady-state error.

[0012] Secondly, embodiments of this application provide a digital predistortion device for improving DAC linearity, the digital predistortion device for improving DAC linearity includes: The fluctuation acquisition module is used to acquire voltage fluctuation information of the analog power supply pins of the DAC; The model building module is used to build a nonlinear distortion model that describes the relationship between the output distortion of the DAC and the voltage fluctuation information; The distortion compensation module is used to apply predistortion processing to the original digital signal input to the DAC based on the nonlinear distortion model to generate a predistorted digital signal. The error feedback module is used to acquire the actual analog output of the DAC and compare the actual analog output with the expected output to obtain an error signal; The parameter update module is used to update the parameters of the nonlinear distortion model according to the error signal, and to continuously process the DAC predistortion process using the updated nonlinear distortion model.

[0013] Thirdly, embodiments of this application provide an audio device, the audio device including a memory and a processor; The memory is used to store computer programs; The processor is configured to execute the computer program and, in executing the computer program, implement the digital predistortion method for improving DAC linearity as described in any of the embodiments of this application.

[0014] Fourthly, embodiments of this application provide a computer-readable storage medium storing a computer program that, when executed by a processor, causes the processor to implement a digital predistortion method for improving DAC linearity as described in any of the embodiments of this application.

[0015] This application provides a digital predistortion method to improve the linearity of a DAC. The method includes: acquiring voltage fluctuation information from the analog power supply pins of the DAC; establishing a nonlinear distortion model describing the relationship between the DAC's output distortion and the voltage fluctuation information; applying predistortion processing to the original digital signal input to the DAC based on the nonlinear distortion model to generate a predistorted digital signal; acquiring the actual analog output of the DAC and comparing it with the desired output to obtain an error signal; updating the parameters of the nonlinear distortion model based on the error signal, and continuously processing the DAC predistortion using the updated nonlinear distortion model. In this method, by acquiring voltage fluctuation information from the DAC's analog power supply pins in real time and establishing a nonlinear distortion model, predistortion processing is applied to the digital signal to actively cancel the dynamic distortion introduced by the power supply. Then, by adaptively updating the model parameters based on the error signals of the actual output and the desired output, the method can dynamically track changes in power supply fluctuations, continuously optimize the compensation effect, suppress nonlinear distortion caused by voltage fluctuations, and improve the output linearity of the DAC. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 A schematic flowchart illustrating a digital predistortion method for improving DAC linearity provided in an embodiment of this application; Figure 2 This is a schematic block diagram of a digital predistortion device for improving DAC linearity, provided as an embodiment of this application. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described below with reference to the accompanying drawings.

[0019] The terms "first" and "second," etc., used in the specification, claims, and drawings of this application are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or apparatuses.

[0020] The term "embodiment" as used herein means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0021] It should be understood that in this application, "at least one (item)" means one or more, "more than one" means two or more, "at least two (items)" means two or three or more, and "and / or" is used to describe the relationship between related objects, indicating that there can be three relationships. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist simultaneously, where A and B can be singular or plural. The character " / " generally indicates that the related objects before and after are in an "or" relationship. "At least one (item) of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one (item) of a, b, or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0022] Please see Figure 1 , Figure 1 This is a schematic flowchart illustrating a digital predistortion method for improving DAC linearity provided in an embodiment of this application. Figure 1 As shown, the specific steps of this digital predistortion method for improving DAC linearity include: S101-S105.

[0023] S101: Collect voltage fluctuation information of the analog power supply pin of the DAC.

[0024] For example, when acquiring voltage fluctuation information from the analog power supply pin of the DAC, the voltage waveform on the analog power supply pin is continuously sampled at a sampling frequency higher than the DAC input data rate. The sampled voltage data is processed by Fast Fourier Transform to decompose the ripple fundamental frequency, harmonic components, and power spectral density of random noise contained in the voltage waveform. Simultaneously, a moving average filter is used to smooth the time-domain data of the voltage waveform to extract the instantaneous voltage fluctuation value, ripple amplitude, and DC bias value. The sampling frequency can be set to more than eight times the DAC input data rate; for example, when the DAC input data rate is 48 kHz, the sampling frequency is set to... The frequency is 384 kHz, which ensures that the high-frequency switching noise component in the power supply ripple can be captured. The extracted instantaneous voltage fluctuation value characterizes the dynamic deviation of the power supply voltage over time. The ripple amplitude reflects the magnitude of the periodic disturbance introduced by the switching power supply or external interference. The DC bias value represents the average operating point of the power supply voltage. The above acquisition operation is realized by configuring and reading data from the auxiliary analog-to-digital converter through digital logic. In order to eliminate the aliasing effect in the sampling process, an anti-aliasing filter can be added to the input of the auxiliary analog-to-digital converter to retain the voltage fluctuation component in the effective frequency band. The voltage fluctuation information obtained in this way is used as the input parameters for subsequent modeling steps.

[0025] S102. Establish a nonlinear distortion model to describe the relationship between the output distortion of the DAC and voltage fluctuation information.

[0026] For example, a power modulation function is calculated based on the instantaneous voltage fluctuation value and DC bias value in the voltage fluctuation information. This power modulation function is defined as the ratio of the instantaneous voltage value to the nominal reference voltage. For instance, when the nominal reference voltage is 2.5 volts and the instantaneous voltage value is 2.52 volts, the power modulation function value is 1.008. This ratio reflects the real-time modulation effect of power fluctuation on the DAC output gain. Then, a nonlinear error term in polynomial form is constructed. This polynomial contains the product of the higher powers of the input code value and the instantaneous voltage fluctuation deviation. The input code value is the decimal value corresponding to the digital input word length of the DAC. The higher powers are typically second, third, up to fourth or fifth powers. The instantaneous voltage fluctuation deviation is defined as the instantaneous voltage fluctuation value minus its time average. To determine the coefficients of each term in the polynomial, a set of pre-stored test sequences is output to the DAC. These test sequences can be ramp signals from zero to full scale or pseudo-random sequences with wide-spectrum characteristics. Simultaneously, the actual output response of the DAC is read through a high-precision analog-to-digital converter. The residual between the actual output response and the theoretical output value is used as the fitting target, and the coefficients of the polynomial are solved using the least squares method. This allows the polynomial model to approximate the true power-dependent distortion characteristics with the minimum mean square error. The coefficients obtained through the above fitting process are stored in non-volatile memory, thus completing the establishment of the nonlinear distortion model.

[0027] S103. Based on the nonlinear distortion model, predistortion processing is applied to the original digital signal input to the DAC to generate a predistorted digital signal.

[0028] For example, based on an established nonlinear distortion model, during the process of applying predistortion processing to the original digital signal input to the DAC to generate a predistorted digital signal, the reciprocal of the real-time power modulation ratio is calculated according to the power modulation function in the nonlinear distortion model. This reciprocal is equal to the nominal reference voltage divided by the sum of the instantaneous voltage value and the DC bias value. This reciprocal is used as an amplitude pre-compensation factor to perform a multiplication operation on the original digital signal to complete the first-level amplitude correction. That is, the original digital codeword is multiplied by this reciprocal and then rounded to obtain the corrected codeword. Then, the corrected codeword and its powers (including second power, third power, and up to the power with the same order as the highest order in the nonlinear error term) are fed as input vectors into a finite impulse response filter. The tap coefficients of this filter are the polynomial coefficients stored in the nonlinear distortion model. The filter performs a weighted summation of the input vector according to the convolution operation rules and outputs a nonlinear predistortion compensation signal. The codeword after the first-stage amplitude correction is then superimposed on the nonlinear predistortion compensation signal. The superposition result reflects the nonlinear component that is added to the original signal, which is opposite to the power supply fluctuation. In order to ensure that the superimposed codeword does not exceed the digital input range of the DAC, the superposition result is subjected to amplitude limiting processing. That is, when the superposition result is greater than the maximum input codeword of the DAC, it is clamped to the maximum codeword, and when it is less than the minimum input codeword, it is clamped to the minimum codeword. The value obtained after amplitude limiting processing is the predistortion digital signal, which is sent to the digital input terminal of the DAC in real time for conversion.

[0029] S104. Acquire the actual analog output of the DAC and compare it with the expected output to obtain the error signal.

[0030] For example, while the predistorted digital signal is fed into the DAC for conversion, the operation of acquiring the actual analog output of the DAC and comparing it with the desired output to obtain the error signal is implemented through a feedback analog-to-digital converter (ADC). This feedback ADC is configured to sample the analog output voltage of the DAC at the same update rate as the DAC, and its quantization accuracy is at least two bits higher than that of the DAC. For example, an 18-bit or higher resolution feedback ADC is used for a 16-bit DAC to ensure that the error signal can truly reflect the residual distortion in the DAC output rather than quantization noise. The calculation of the desired output is accomplished through a software-implemented ideal DAC model. This ideal DAC model assumes that the DAC has perfect linear conversion characteristics at the nominal reference voltage, that is, the desired digital code is equal to the decimal value corresponding to the predistorted digital signal multiplied by the nominal reference voltage, divided by 2 raised to the power of the DAC bit width, and then rounded to the same bit width as the DAC. The difference between the actual acquired feedback digital code and the expected digital code calculated by the ideal DAC model is the error signal. The sign and magnitude of the error signal indicate whether the actual output of the DAC is too high or too low relative to the expected output, and the degree of deviation. For example, when the expected digital code is 32768 and the feedback digital code is 32800, the error signal is +32, indicating that the actual output is about 0.1% higher than the expected output. This error signal is the core basis for subsequent parameter updates.

[0031] S105. Update the parameters of the nonlinear distortion model based on the error signal, and use the updated nonlinear distortion model to continuously process the DAC predistortion.

[0032] For example, the process of updating the parameters of the nonlinear distortion model based on the aforementioned error signal and continuously processing the DAC predistortion using the updated nonlinear distortion model employs a proportionally normalized least mean square adaptive algorithm with a leakage term. The coefficient update formula of this algorithm includes the current filter coefficient vector, the error signal, the input signal vector, and a proportional gain diagonal matrix. The diagonal elements of the proportional gain diagonal matrix are dynamically allocated to the update step size proportionally to the absolute value of each coefficient, allowing coefficients with larger amplitudes to receive greater update weights to accelerate the convergence of the dominant nonlinear term. The leakage term is introduced to suppress slow coefficient drift caused by numerical ill-conditioning when the system enters steady state. Specifically, during the update, the product of the error signal and the input signal vector is divided by the energy estimate of the input signal vector to obtain a normalized update direction. This direction is then multiplied by the global step size factor and the proportional gain matrix and superimposed onto the current coefficient vector, while simultaneously subtracting the product of the leakage term and the current coefficient vector. After each update, the new coefficient vector is immediately written back to the tap coefficient register of the finite impulse response filter for use in the predistortion calculation at the next time step. In addition, the adaptive algorithm also includes a variable step size control mechanism based on the ratio of short-time power of the error signal to high-frequency changing power. When the ratio is large, it indicates that the system is in a mismatch state with large signal or power supply fluctuations. A larger step size factor is used to quickly approximate the optimal coefficient. When the ratio is small, it indicates that the system has entered the noise-dominated steady-state region. A smaller step size factor is used to reduce steady-state fluctuations. Through this continuous adaptive iteration, the parameters of the nonlinear distortion model can track the model drift caused by power supply fluctuations, temperature changes, and device aging in real time, thereby ensuring that the pre-distortion processing is always in the optimal compensation state.

[0033] This application provides a digital predistortion method to improve the linearity of a DAC. The method includes: acquiring voltage fluctuation information from the analog power supply pins of the DAC; establishing a nonlinear distortion model describing the relationship between the DAC's output distortion and the voltage fluctuation information; applying predistortion processing to the original digital signal input to the DAC based on the nonlinear distortion model to generate a predistorted digital signal; acquiring the actual analog output of the DAC and comparing it with the desired output to obtain an error signal; updating the parameters of the nonlinear distortion model based on the error signal, and continuously processing the DAC predistortion using the updated nonlinear distortion model. In this method, by acquiring voltage fluctuation information from the DAC's analog power supply pins in real time and establishing a nonlinear distortion model, predistortion processing is applied to the digital signal to actively cancel the dynamic distortion introduced by the power supply. Then, by adaptively updating the model parameters based on the error signals of the actual output and the desired output, the method can dynamically track changes in power supply fluctuations, continuously optimize the compensation effect, suppress nonlinear distortion caused by voltage fluctuations, and improve the output linearity of the DAC.

[0034] To more clearly illustrate the technical solution of this application, the technical solution of this application will be described below through specific embodiments. It should be noted that the specific embodiments are used to expand the description of the technical solution of this application, and are not intended to limit this application.

[0035] In some embodiments, acquiring voltage fluctuation information of the analog power supply pin of the DAC includes: acquiring the voltage waveform on the analog power supply pin at a sampling frequency higher than the input data rate of the DAC; performing a fast Fourier transform on the voltage waveform to decompose the waveform time-domain data, the time-domain data including: ripple fundamental frequency, harmonic components and power spectral density of random noise; applying a moving average filter to the waveform time-domain data to extract the instantaneous voltage fluctuation value, ripple amplitude and DC bias value, and outputting it as voltage fluctuation information.

[0036] For example, the voltage waveform on the analog power supply pin is continuously acquired at a sampling frequency higher than the DAC input data rate (e.g., setting the sampling frequency to eight times the DAC input data rate; when the DAC input data rate is 192 kHz, the sampling frequency is 1.536 MHz). The obtained raw voltage data is then processed by a Fast Fourier Transform to decompose the waveform into time-domain data. This time-domain data specifically includes the ripple fundamental frequency (reflecting the main frequency component of the switching power supply or external periodic interference), each harmonic component (characterizing the degree of non-sinusoidal distortion of the ripple), and the power spectral density of random noise (used for evaluation). The broadband noise level of the power supply is determined, and then the above waveform time-domain data is smoothed using a moving average filter (the window length can be set to 16 sampling points). This effectively filters out high-frequency random jitter and extracts instantaneous voltage fluctuation values, ripple amplitude, and DC bias values. The instantaneous voltage fluctuation value represents the dynamic deviation of the power supply voltage from the average value at each sampling moment, the ripple amplitude reflects the peak variation range of the periodic disturbance, and the DC bias value determines the static operating point of the power supply voltage. The above extraction results are integrated into voltage fluctuation information output, providing accurate power supply state input for subsequent nonlinear distortion modeling.

[0037] In some embodiments, establishing the nonlinear distortion model includes: calculating a power modulation function based on the voltage fluctuation information, wherein the power modulation function is the ratio of the instantaneous voltage fluctuation value to a preset nominal reference voltage; constructing a nonlinear error term in polynomial form based on the product of the higher-order power of the input code value and the instantaneous voltage fluctuation value; outputting a set of pre-stored test sequences to the DAC, reading the test output response, fitting the coefficients of the polynomial using the least squares method, and completing the establishment of the nonlinear distortion model.

[0038] For example, a power modulation function is calculated based on the instantaneous voltage fluctuation value and DC bias value from the collected voltage fluctuation information. This power modulation function is defined as the ratio of the instantaneous voltage fluctuation value to a preset nominal reference voltage (for example, if the nominal reference voltage is 3.3 volts, and the instantaneous voltage fluctuation value is 3.333 volts, then the power modulation function value is 1.01). This ratio intuitively quantifies the real-time modulation degree of power supply fluctuation on the DAC conversion gain. Then, a polynomial-form nonlinear error term is constructed based on the product of the higher-order powers of the input code value (usually the second, third, and fourth powers) and the deviation of the instantaneous voltage fluctuation value from its average value. This polynomial can fit the nonlinear changes in the DAC's internal switch on-resistance and current source output impedance caused by power supply variations. To determine the coefficients of each order in the polynomial, a set of pre-stored test sequences (such as a ramp signal linearly increasing from zero code value to full-scale code value, or a pseudo-random sequence with wide spectrum characteristics) is output to the DAC. The corresponding test output response is read through a high-precision analog-to-digital converter. The residual between the actual output response and the ideal linear response is used as the objective function, and the coefficients of each order of the polynomial are fitted using the least squares method, thereby completing the establishment of the nonlinear distortion model. This model can describe the DAC output distortion characteristics under specific power fluctuation conditions with high accuracy.

[0039] In some embodiments, the predistortion processing includes: calculating an amplitude pre-compensation factor based on the power modulation function in the nonlinear distortion model, and performing a multiplication operation on the digital signal to complete amplitude correction; inputting the corrected digital signal and its powers to a finite impulse response filter, wherein the coefficients of the finite impulse response filter are the polynomial coefficients in the nonlinear distortion model, to calculate a nonlinear predistortion compensation signal; superimposing the amplitude-corrected signal with the nonlinear predistortion compensation signal, and performing amplitude limiting processing on the superposition result to generate a predistorted digital signal.

[0040] For example, an amplitude pre-compensation factor is calculated based on the power modulation function in the nonlinear distortion model. This amplitude pre-compensation factor is the reciprocal of the power modulation function (i.e., the nominal reference voltage divided by the sum of the instantaneous voltage fluctuation value and the DC bias value). A multiplication operation is then performed on the original digital signal to achieve amplitude correction. For instance, when the original digital codeword is 20000 and the amplitude pre-compensation factor is 0.99, the corrected codeword is 19800. This operation cancels out the overall gain change caused by power fluctuations. The corrected digital signal and its powers (including second, third, and up to powers identical to the nonlinear model's order) are used as input vectors and fed into a finite impulse response filter. The tap coefficients of this filter are the polynomial coefficients fitted in the nonlinear distortion model. The filter calculates the nonlinear pre-distortion compensation signal using a weighted summation method. This signal reflects the additional nonlinear component, opposite to the power fluctuation, that needs to be added on top of the amplitude correction. After the above process, the amplitude-corrected signal is superimposed with the nonlinear predistortion compensation signal, and the superposition result is subjected to amplitude limiting processing (for example, when the superposition result exceeds the DAC input codeword range of 0 to 65535, it is clamped to 0 or 65535 respectively), thereby generating the final predistortion digital signal. This signal can actively cancel the nonlinear distortion caused by power supply fluctuations after being sent to the DAC.

[0041] In some embodiments, the step of acquiring the actual analog output and updating the model parameters includes: calling a feedback analog-to-digital converter to sample the actual analog output of the DAC at the same update rate as the DAC, and reading the feedback digital code; calculating the expected digital code corresponding to the expected output based on the predistorted digital signal and a preset nominal reference voltage; calculating the difference between the expected digital code and the feedback digital code as an error signal, and sending the error signal to an adaptive algorithm module to update the parameters of the nonlinear distortion model.

[0042] For example, in a specific embodiment of acquiring the actual analog output and updating the model parameters, a feedback analog-to-digital converter (ADC) working in conjunction with a DAC is invoked. This ADC is configured to have the same update rate as the DAC (e.g., when the DAC update rate is 192 kHz, the feedback ADC also uses a sampling rate of 192 kHz) to sample the actual analog output of the DAC and read the quantized feedback digital code. To ensure that the error signal accurately reflects the distortion component rather than quantization noise, the accuracy of this feedback ADC is typically set to be at least two bits higher than the DAC's accuracy (e.g., a 16-bit DAC paired with an 18-bit feedback ADC). Simultaneously, based on the currently generated predistorted digital signal and a preset nominal reference voltage, an ideal DAC model implemented in software calculates the desired digital code corresponding to the expected output. This ideal DAC model assumes a strictly linear relationship between the output and input under conditions of no power fluctuations and infinite errors. The difference between the desired digital code and the feedback digital code is calculated as the error signal. The sign and absolute value of this error signal indicate the direction and degree of deviation of the actual output from the desired output, respectively. The error signal is then sent to the adaptive algorithm module to update the parameters of the nonlinear distortion model, thereby forming a closed-loop calibration system that enables the model parameters to track power fluctuations and environmental changes in real time.

[0043] In some embodiments, the adaptive algorithm is a proportional normalized least mean square algorithm with leakage terms, and its coefficient update formula is: β(n+1)=(1-ρλ)·β(n)+μ·P(n)·e(n)·X(n) / (γ+X(n) P(n)X(n)); Wherein, β(n) is the parameter vector of the nonlinear distortion model, e(n) is the error signal, X(n) is the input signal vector, μ is the step size factor, λ is the leakage coefficient, ρ is the proportional control factor, γ is the regularization constant, and P(n) is the proportional gain diagonal matrix, whose diagonal elements are dynamically allocated proportionally according to the magnitude of the absolute value of each component in β(n).

[0044] In a specific implementation of the adaptive algorithm, a proportional normalized least mean square algorithm with a leakage term is used to iteratively update the parameters of the nonlinear distortion model. The introduction of the leakage term (1-ρλ)·β(n) causes the parameter vector to slowly shrink towards zero when the error signal is small, effectively suppressing the coefficient drift problem caused by the correlation of the input signal.

[0045] The proportional gain matrix P(n) allows coefficients with larger amplitudes (usually corresponding to lower-order terms that dominate nonlinear distortion) to have larger update step sizes, while coefficients with smaller amplitudes (corresponding to higher-order terms that have a weak impact) to have smaller update step sizes. This concentrates limited computational resources on the main distortion components and significantly accelerates the convergence speed.

[0046] It should also be noted that X(n) in the denominator... P(n)X(n) normalizes the power of the input signal, making the algorithm insensitive to changes in the amplitude of the input signal and ensuring stable update performance under different signal strengths.

[0047] In some embodiments, the adaptive algorithm further includes a variable step size control mechanism, wherein the step size factor μ is dynamically adjusted to μ(n) based on the ratio of the short-time power to the high-frequency changing power of the error signal, and the adjustment formula is: μ(n) = μ max ·[1-σ e²(n) / (σ e²(n) +σ v²(n) )]; Where, σ e²(n) For the short-time power estimation of the error signal, σ v²(n) For the high-frequency power estimation of the error signal, μ max The maximum step size is preset; when the ratio is greater than the first threshold, a large step size is used to achieve rapid convergence, and when the ratio is less than the second threshold, a small step size is used to reduce steady-state error.

[0048] Ratio σ e²(n) / (σ e²(n) +σ v²(n) This actually reflects the proportion of systematic mismatch energy in the error signal. When this ratio is large (e.g., greater than 0.7), it indicates that the error mainly comes from model mismatch rather than random noise. In this case, the step size factor μ(n) is close to μ. max A large step size is used to quickly converge to the optimal coefficients. When this ratio is small (e.g., less than 0.3), it indicates that the error has entered the noise-dominated steady-state region. At this point, the step size factor approaches zero, and a small step size is used to reduce steady-state parameter fluctuations and output residuals. Compared with traditional variable step size methods based on the absolute value of instantaneous error or a fixed threshold, this mechanism can more accurately identify the convergence stage and adaptively adjust the update intensity, thus achieving a better balance between fast tracking capability and steady-state accuracy.

[0049] Please see Figure 2 , Figure 2 This is a schematic block diagram of a digital predistortion device 200 for improving DAC linearity, provided in an embodiment of this application. This digital predistortion device 200 is used to perform the aforementioned digital predistortion method for improving DAC linearity. The digital predistortion device 200 can be configured in a server.

[0050] The server can be a standalone server, a server cluster, or a cloud server that provides basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communication, middleware services, domain name services, security services, content delivery networks (CDN), and big data and artificial intelligence platforms.

[0051] like Figure 2 As shown, the digital predistortion device 200 for improving DAC linearity includes: a fluctuation acquisition module 201, a model building module 202, a distortion compensation module 203, an error feedback module 204, and a parameter update module 205.

[0052] The fluctuation acquisition module 201 is used to acquire voltage fluctuation information of the analog power supply pins of the DAC.

[0053] Model building module 202 is used to build a nonlinear distortion model that describes the relationship between the output distortion of the DAC and voltage fluctuation information.

[0054] The distortion compensation module 203 is used to apply predistortion processing to the original digital signal input to the DAC based on a nonlinear distortion model to generate a predistorted digital signal.

[0055] The error feedback module 204 is used to acquire the actual analog output of the DAC and compare the actual analog output with the expected output to obtain the error signal.

[0056] The parameter update module 205 is used to update the parameters of the nonlinear distortion model according to the error signal, and to continuously process the DAC predistortion processing using the updated nonlinear distortion model.

[0057] This application provides an audio device, which includes a memory and a processor; the memory is used to store a computer program; the processor is used to execute the computer program and, when executing the computer program, implement a digital predistortion method for improving DAC linearity as described in any of the embodiments of this application.

[0058] This application provides a computer-readable storage medium storing a computer program that, when executed by a processor, causes the processor to implement a digital predistortion method for improving DAC linearity as described in any of the embodiments of this application.

[0059] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A digital predistortion method for improving the linearity of a DAC, characterized in that, The method is performed by a digital processor coupled to the DAC, and the method includes: Collect voltage fluctuation information from the analog power supply pins of the DAC; A nonlinear distortion model is established to describe the relationship between the output distortion of the DAC and the voltage fluctuation information; Based on the aforementioned nonlinear distortion model, predistortion processing is applied to the original digital signal input to the DAC to generate a predistorted digital signal; The actual analog output of the DAC is acquired, and the actual analog output is compared with the expected output to obtain the error signal; The parameters of the nonlinear distortion model are updated based on the error signal, and the updated nonlinear distortion model is used to continuously process the DAC predistortion process.

2. The digital predistortion method for improving DAC linearity as described in claim 1, characterized in that, The voltage fluctuation information of the analog power supply pin of the DAC is acquired, including: The voltage waveform on the analog power supply pin is acquired at a sampling frequency higher than the input data rate of the DAC; Perform a fast Fourier transform on the voltage waveform to decompose the waveform time-domain data in the voltage waveform. The time-domain data includes: ripple fundamental frequency, harmonic components and power spectral density of random noise. The waveform time-domain data is filtered by moving average to extract instantaneous voltage fluctuation value, ripple amplitude and DC bias value, and output as voltage fluctuation information.

3. The digital predistortion method for improving DAC linearity as described in claim 2, characterized in that, The establishment of the nonlinear distortion model includes: Based on the voltage fluctuation information, a power modulation function is calculated, wherein the power modulation function is the ratio of the instantaneous voltage fluctuation value to a preset nominal reference voltage; A nonlinear error term in polynomial form is constructed based on the product of the higher power of the input code value and the instantaneous voltage fluctuation value. A set of pre-stored test sequences is output to the DAC, and the test output response is read. The coefficients of the polynomial are fitted using the least squares method to complete the establishment of the nonlinear distortion model.

4. The digital predistortion method for improving DAC linearity as described in claim 3, characterized in that, The pre-distortion processing includes: Based on the power supply modulation function in the nonlinear distortion model, the amplitude pre-compensation factor is calculated, and the digital signal is multiplied to complete the amplitude correction. The corrected digital signal and its powers are input to a finite impulse response filter, the coefficients of which are the polynomial coefficients in the nonlinear distortion model, and the nonlinear predistortion compensation signal is calculated. The amplitude-corrected signal is superimposed with the nonlinear predistortion compensation signal, and the superposition result is subjected to amplitude limiting to generate a predistortion digital signal.

5. The digital predistortion method for improving DAC linearity as described in claim 1, characterized in that, The process of collecting actual simulation output and updating model parameters includes: The feedback analog-to-digital converter is invoked to sample the actual analog output of the DAC at the same update rate as the DAC, and the feedback digital code is read. The desired digital code corresponding to the desired output is calculated based on the predistorted digital signal and the preset nominal reference voltage. The difference between the expected digital code and the feedback digital code is calculated as an error signal, and the error signal is sent to the adaptive algorithm module to update the parameters of the nonlinear distortion model.

6. The digital predistortion method for improving DAC linearity according to claim 5, characterized in that, The adaptive algorithm is a proportional normalized least mean square algorithm with leakage terms, and its coefficient update formula is as follows: β(n+1)=(1-ρλ)·β(n)+μ·P(n)·e(n)·X(n) / (γ+X(n) P(n)X(n); Wherein, β(n) is the parameter vector of the nonlinear distortion model, e(n) is the error signal, X(n) is the input signal vector, μ is the step size factor, λ is the leakage coefficient, ρ is the proportional control factor, γ is the regularization constant, and P(n) is the proportional gain diagonal matrix, whose diagonal elements are dynamically allocated proportionally according to the magnitude of the absolute value of each component in β(n).

7. The digital predistortion method for improving DAC linearity according to claim 6, characterized in that, The adaptive algorithm also includes a variable step size control mechanism, wherein the step size factor μ is dynamically adjusted to μ(n) based on the ratio of the short-time power to the high-frequency changing power of the error signal, and the adjustment formula is: μ(n)=μ max ·[1-s e²(n) / (s e²(n )+s v²(n) )]; Where, σ e²(n) For the short-time power estimation of the error signal, σ v²(n) For the high-frequency power estimation of the error signal, μ max The maximum step size is preset; when the ratio is greater than the first threshold, a large step size is used to achieve rapid convergence, and when the ratio is less than the second threshold, a small step size is used to reduce steady-state error.

8. A digital predistortion device for improving the linearity of a DAC, characterized in that, The digital predistortion device for improving DAC linearity is used to perform the digital predistortion method for improving DAC linearity as described in any one of claims 1-7, wherein the digital predistortion device for improving DAC linearity comprises: The fluctuation acquisition module is used to acquire voltage fluctuation information of the analog power supply pins of the DAC; The model building module is used to build a nonlinear distortion model that describes the relationship between the output distortion of the DAC and the voltage fluctuation information. The distortion compensation module is used to apply predistortion processing to the original digital signal input to the DAC based on the nonlinear distortion model to generate a predistorted digital signal. The error feedback module is used to acquire the actual analog output of the DAC and compare the actual analog output with the expected output to obtain an error signal; The parameter update module is used to update the parameters of the nonlinear distortion model according to the error signal, and to continuously process the DAC predistortion process using the updated nonlinear distortion model.

9. An audio device, characterized in that, The audio device includes a memory and a processor; The memory is used to store computer programs; The processor is configured to execute the computer program and, in executing the computer program, implement the digital predistortion method for improving DAC linearity as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, causes the processor to implement the digital predistortion method for improving DAC linearity as described in any one of claims 1 to 7.

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