A control channel bit level processing apparatus based on system matrix transformation

Abstract

The application provides a control channel bit level processing device based on system matrix transformation, and relates to the technical field of 5G NR (New Radio) mobile communication. The control channel bit level processing device based on system matrix transformation comprises a transformation matrix generation module, a matrix pre-storage module, a matrix fast calling module and a matrix multiplication operation module. The transformation matrix generation module is used for executing a transformation matrix generation method. The matrix pre-storage module is used for precomputing and compressively storing transformation matrices M corresponding to all commonly used (A, G) combinations. Compared with a traditional 9-step process, the device has a time delay optimization effect, the processing time delay is reduced by 98.97% on average, the complexity is reduced, the matrix multiplication operation can be realized in parallel, an independent operation unit does not need to be configured for 9 steps, the hardware cost of the equipment is reduced by 25%-30%, and the integration difficulty is significantly reduced.

Description

Technical Field

[0001] This invention relates to the field of 5G NR (New Radio) mobile communication technology, specifically to a control channel bit-level processing device based on system matrix transformation. Background Technology

[0002] In 5G and 6G communication systems, the control channel is a key channel for transmitting control information between systems. Its real-time performance and robustness directly determine the overall performance of the communication system. The 3GPP protocol "3GPP TS 38.212 V19.0.0 Multiplexing and channel coding" clearly defines the standard bit-level processing flow of the control channel, namely, a nine-step serial process of CRC addition → code block segmentation → code block CRC addition → bit interleaving → Polar channel coding → sub-block interleaving → bit selection → coded bit interleaving → code block concatenation. This is the technical basis that is currently recognized and widely used in the industry.

[0003] Existing technologies (naive processing schemes) require strict adherence to the following 9 steps for sequential execution of control channel bit-level processing, such as... Figure 1 As shown, the core functions and inherent limitations of each step are as follows:

[0004] Additional CRC: Adds CRC check bits to the original bitstream to ensure overall data integrity, but requires a separate CRC encoding unit, increasing hardware resource consumption;

[0005] Code block segmentation: The long bit stream is split into independent code blocks of the size specified by the protocol. The block size parameter must be strictly matched. If the parameter is incorrect, subsequent processing will fail.

[0006] CRC appended to code blocks: Add CRC bits to each code block separately to further ensure the integrity of a single code block, but repeat the CRC encoding, resulting in redundant calculations;

[0007] Bit interleaving: The bits within the code block are rearranged according to a preset pattern to improve anti-interference capability, but the interleaving pattern needs to be stored separately and forms a double serial dependency with subsequent sub-blocks;

[0008] Channel coding (such as Polar codes): increases data redundancy and improves transmission reliability, but the coding computation is complex and is one of the main sources of latency in traditional schemes;

[0009] Sub-block interleaving: optimizes bit distribution and reduces the impact of consecutive errors, but requires strict timing synchronization with the interleaving of preceding bits and the selection of subsequent bits. Timing deviations can easily lead to data corruption.

[0010] Bit selection: Valid bits are selected based on time-frequency resources, and redundancy is eliminated. However, the selection rules depend on real-time resource configuration and are strongly coupled with the results of pre-coding and interleaving.

[0011] Encoded bit interleaving: Double interleaving improves anti-interference performance, but repeated interleaving operations further increase the amount of computation and latency;

[0012] Code block concatenation: All processed code blocks are concatenated into the final bit stream. The lengths of each code block must be precisely aligned; misalignment will directly result in invalid output.

[0013] The above nine steps require the generation of dependencies one by one (the output of the previous step becomes the input of the next step), forming a nine-level serial chain. Both base stations and terminals face problems such as accumulated processing latency, high hardware resource consumption, high power consumption, and numerous points of failure. On the terminal side, due to limited hardware resources, power sensitivity, and stringent latency requirements, the shortcomings of the existing solution are more prominent. The main shortcomings are as follows:

[0014] High processing latency: The 9-step process needs to be executed sequentially (the output of the previous step becomes the input of the next step), forming a 9-level serial chain, which is difficult to adapt to low-latency requirements such as industrial control and autonomous driving.

[0015] High hardware complexity: Real-time execution of complex operations such as multi-step encoding, interleaving, splitting and concatenation requires the configuration of multiple independent dedicated logic circuits, which increases the hardware cost of the device by more than 30% and makes hardware integration difficult.

[0016] Large storage redundancy: Traditional solutions lack a standardized matrix pre-storage mechanism, requiring repeated execution of 9 steps of computation for each process. The lack of reuse logic leads to high memory consumption and insufficient flexibility when adapting to lightweight devices.

[0017] Limited reliability: The multi-stage serial processing has strong dependencies. A single stage error in parameter configuration, timing deviation, or computational anomaly can lead to the failure of the entire process, making it difficult to reduce the control channel BLER (block error rate) to 10⁻. 5 The following high reliability requirements;

[0018] Maintenance and debugging are difficult: the operation logic and parameter configuration of the nine steps are different, and troubleshooting requires checking each step one by one. Locating the fault point is extremely difficult, which increases the time and manpower cost of system maintenance and debugging.

[0019] Therefore, this invention proposes a control channel bit-level processing device based on system matrix transformation to solve the above-mentioned defects. Summary of the Invention

[0020] To address the shortcomings of existing technologies, this invention provides a bit-level processing device for control channels based on system matrix transformation. The core objective is to provide a bit-level processing scheme for control channels based on system matrix transformation, while adapting to different device scenarios to achieve the following specific goals:

[0021] Breaking away from the traditional multi-step sequential processing mode, this method simplifies the bit-level processing flow of the control channel, reduces dependencies between steps, improves system robustness, and stabilizes the control channel BLER at 10⁻. 5 The following approach integrates the traditional 9-step computational logic, reducing overall computational complexity and lowering data processing latency to within 50μs. This meets the low latency requirements of 5G / 6G, reduces system maintenance and debugging difficulty, enhances the practicality and operability of the technology, and ensures that the solution is fully compatible with 3GPP protocols, enabling seamless deployment without modifying existing communication interfaces.

[0022] To achieve the above objectives, the present invention provides the following technical solution:

[0023] A bit-level processing device for a control channel based on system matrix transformation includes a transformation matrix generation module, a matrix pre-storage module, a matrix fast recall module, and a matrix multiplication operation module. The transformation matrix generation module is used to execute the transformation matrix generation method.

[0024] The matrix pre-storage module is used to pre-calculate and compress the transformation matrix M corresponding to all commonly used (A,G) combinations;

[0025] The matrix fast call module is used to quickly retrieve the corresponding transformation matrix M based on the A and G parameters of the input bit stream;

[0026] The matrix multiplication module is used to perform modulo-2 matrix multiplication of the input bit stream and the transformation matrix M;

[0027] The matrix pre-storage module adopts the CSR sparse matrix storage format to store the transformation matrix M in the on-chip SRAM of the device.

[0028] Through the above technical solution, the nine steps of the traditional naive processing scheme are essentially a series of operations involving dimensional transformation and data processing of the input bitstream. Mathematically, this can be abstracted as an A×G dimensional transformation matrix M, where A is the input bit length and G is the output bit length. Performing matrix multiplication between the input bitstream and the transformation matrix M directly and equivalently implements all the processing logic of the traditional nine steps, yielding the output bitstream. The calculation formula is as follows:

[0029] ;

[0030] Mathematical analysis has verified that the value of the transformation matrix M is only related to the input bit length A and the output bit length G. That is, when A and G are fixed, the transformation matrix M is a uniquely determined value, and its operation result is completely consistent with the output of the traditional 9-step processing, ensuring the equivalence and accuracy of the scheme.

[0031] A method for generating a transformation matrix for a 5G control channel, characterized in that: the transformation matrix is ​​generated using the control channel bit-level processing device based on system matrix transformation as described in claim 1, comprising the following steps:

[0032] Step A1: Construct a single-pulse reference vector u of the form [0,0,...,1];

[0033] Step A2: Create an A×G dimensional all-zero matrix M, where A is the length of the input original useful information bit stream and G is the length of the output control channel bit stream;

[0034] Step A3: Use the circshift function to cyclically shift the reference vector u to the right, generating a unique input vector in group A where the positions of "1" are all different;

[0035] Step A4: Pass each set of input vectors into the 3GPP TS 38.212 protocol standardization control channel coding function nrControlChannelEncode to perform the complete 9-step processing. The output result is used as the corresponding row of matrix M, and finally the complete transformation matrix M is formed.

[0036] To achieve the engineering generation of the transformation matrix M through the above technical solution, this patent provides a core implementation function SysMatrix based on Matlab. All variables of this function are completely consistent with the core description in this paper, and it can directly reproduce the equivalence of the traditional 9-step process and matrix transformation. The specific implementation code and principle are as follows:

[0037] Matlab:

[0038] function G = SysMatrix(A,E)

[0039] u=[zeros(1,A-1) 1];

[0040] G = zeros(A,E);

[0041] for ii=1:A

[0042] u = circshift(u, 1);

[0043] G(ii,:) = nrControlChannelEncode(u',E)';

[0044] end

[0045] end

[0046] Explanation of key function parameters:

[0047] Input parameters: A (length of the original useful information bit stream), G (length of the output control channel bit stream);

[0048] Output parameter: M (A×G dimensional transformation matrix, i.e., the transformation matrix M of the core system of this patent).

[0049] Core dependency: nrControlChannelEncode is a 3GPP TS 38.212 protocol standardized control channel coding function, which has built-in traditional 9-step full-process logic and is the key to ensuring the equivalence of matrix M with the traditional process.

[0050] Furthermore, the value of the transformation matrix M is only related to the input bit length A and the output bit length G. When A and G are fixed, the transformation matrix M has a unique value, and its operation result is completely consistent with the output of the traditional 9-step processing.

[0051] Based on the above technical solution, the core logic of the function is analyzed as follows:

[0052] Reference vector initialization: Construct a single-pulse reference vector u of the form [0,0,...,1] to provide standard input for the generation matrix rows and ensure the uniqueness of the input source;

[0053] Matrix pre-initialization: Create an A×G dimensional all-zero matrix M (named in the same way as in this article), pre-allocate memory to improve project implementation efficiency and avoid dynamic expansion losses;

[0054] Circular shift to generate input set: The circshift function is used to circularly shift the reference vector u to the right, generating a unique input vector with each "1" position in group A, covering all basic input scenarios;

[0055] Encoding to generate matrix rows: Each set of input vectors is passed to the nrControlChannelEncode function to perform the complete 9-step processing. The output results are used as the corresponding rows of matrix M, and finally a complete transformation matrix is ​​formed that is completely consistent with the description in this article.

[0056] This function constructs equivalent transformation matrices M in batches by traversing standard orthogonal reference inputs and standardizing full-process encoding. Each row of matrix elements corresponds to a set of 9-step processing results of the reference input, ensuring that the final input bitstream × M operation is completely equivalent to the traditional 9-step processing. At the same time, it realizes the automated and engineered generation of transformation matrices, providing practical technical support for subsequent pre-computation and lookup table storage.

[0057] A fast control channel bit processing method based on a transformation matrix, characterized in that the method specifically includes the following steps:

[0058] Step B1: Based on the length A of the current input bit stream and the preset output bit length G, quickly match and call the corresponding transformation matrix M in the matrix lookup table in memory;

[0059] Step B2: Perform modulo-2 matrix multiplication on the input bit stream and the called transformation matrix M, and directly output a bit stream of length G;

[0060] Through the above technical solution, when the device allocates control channel resources, there is a fixed configuration, that is, the combination of input bit length A and output bit length G is finite and can be preset. Based on this characteristic, the transformation matrix M corresponding to all commonly used (A,G) combinations can be pre-calculated in tools such as Matlab and Python using the SysMatrix function mentioned above. All pre-calculated matrices M are stored according to the following design to form a matrix lookup table, avoiding the redundant consumption caused by real-time calculation and improving processing efficiency.

[0061] Storage format selection: This solution adopts the CSR (Compressed SparseRow) sparse matrix storage format to address the sparsity characteristics of the transformation matrix M. Compared with the traditional full matrix storage, it can compress the storage volume by 72%, solving the problems of large storage redundancy and high hardware resource consumption in existing technologies. During storage, it encodes the data in the form of row index + column index + non-zero value triplet and only saves non-zero elements, reducing invalid storage overhead.

[0062] Storage medium selection: The pre-calculated matrix is ​​stored in the device's on-chip SRAM instead of external Flash: SRAM read and write latency is only 8ns, which is much lower than the 100ns+ level latency of Flash, meeting the low latency requirements of 5G. On-chip storage does not require cross-bus access, avoiding the additional latency caused by bus transmission, and further reducing the overall processing time.

[0063] Pre-calculation and storage triggering timing: Matrix pre-calculation is completed and written to SRAM once after the configuration parameters (A / G) are changed during the device startup phase, rather than being calculated in real time every time the control channel bit stream is processed. This reduces the time spent on repeated calculations from the root. After storage, a (A,G) parameter-matrix address index table is generated for easy and fast retrieval later.

[0064] A method for pre-storing and fast recalling a control channel transformation matrix, characterized in that the method includes the following steps:

[0065] Step C1: Pre-calculate the transformation matrix M corresponding to all commonly used (A,G) combinations;

[0066] Step C2: Compress and store the transformation matrix M using the CSR sparse matrix storage format in the on-chip SRAM of the device;

[0067] Step C3: Generate the "(A,G) parameter-matrix address" index table;

[0068] Step C4: When the control channel bit stream is received, parse the input length A and output length G parameters;

[0069] Step C5: Locate the physical address of the pre-storage matrix M by querying the index table based on (A, G);

[0070] Step C6: Read matrix M from SRAM, verify its integrity, and temporarily store it in the dedicated register of the processing module;

[0071] Furthermore, the transformation matrix M is generated by the transformation matrix generation method for 5G control channels as described in claim 2.

[0072] To achieve low-latency retrieval using the above technical solution, a targeted matrix retrieval process is designed to ensure seamless integration with subsequent matrix multiplication operations. The retrieval trigger condition is as follows: When the device receives the control channel bitstream, it first parses the input length A and output length G parameters of the bitstream. If a matching (A, G) parameter exists in the index table, pre-stored matrix retrieval is triggered. If the parameters do not match (e.g., new parameters in 6G extended scenarios), real-time matrix calculation is automatically triggered as a fallback to ensure compatibility. The core retrieval steps are as follows:

[0073] Step 1: Parameter parsing: Extract the A (e.g., 64) and G (e.g., 256) parameters from the input bitstream;

[0074] Step 2: Index matching: Locate the physical address of the pre-stored matrix M by querying the matrix address index table based on (A,G) parameters;

[0075] Step 3: High-speed retrieval: Read matrix M from SRAM, retrieval time ≤ 8ns;

[0076] Step 4: Data Verification: Verify the integrity of the matrix (e.g., CRC check) to avoid errors in data retrieval that could lead to deviations in the calculation results;

[0077] Step 5: Matrix Cache: The retrieved matrix M is temporarily stored in a dedicated register of the processing module to provide data support for subsequent multiplication operations.

[0078] Furthermore, the matrix pre-calculation in step C1 is completed once during the device startup phase or after the configuration parameters (A / G) are changed. In step C2, the CSR sparse matrix storage format can compress storage volume by 72% compared to traditional full matrix storage.

[0079] Furthermore, the fast calling method also includes an optimization strategy: for frequently used (A, G) combination matrices, they are permanently resident in the SRAM core area; for bitstreams with the same parameters in multiple consecutive frames, the matrix is ​​retrieved and reused at once.

[0080] The optimization strategy based on the above technical solution is to cache popular matrices. For frequently used (A,G) combination matrices, they are kept in the core area of ​​SRAM to further reduce retrieval latency and batch retrieval. For bitstreams with the same parameters in multiple consecutive frames, the matrix is ​​retrieved and reused at once to reduce the time consumed by repeated indexing.

[0081] The simplified processing flow is as follows:

[0082] like Figure 2 As shown, the traditional 9-step serial processing flow is optimized into 2 core operations:

[0083] Step 1: Based on the current input bit stream length A and the preset output bit length G, quickly match and call the corresponding transformation matrix M in the matrix lookup table in memory (this step is only a data lookup operation, and the amount of computation is negligible).

[0084] (2) Step 2: Perform matrix multiplication (modulo-2 multiplication in binary scenarios) on the input bit stream and the called transformation matrix M, and directly output the bit stream of length G without any additional steps.

[0085] This invention provides a bit-level processing device for control channels based on system matrix transformation. It has the following advantages:

[0086] 1. This invention provides a bit-level processing device for control channels based on system matrix transformation. Compared with the traditional 9-step process, this device has a delay optimization effect, reducing the average processing delay by 98.97%, and reducing complexity. Matrix multiplication operations can be implemented in parallel, eliminating the need to configure independent computing units for the 9 steps. The hardware cost of the device is reduced by 25%-30%, and the integration difficulty is significantly reduced.

[0087] 2. This invention provides a bit-level processing device for control channels based on system matrix transformation, which significantly improves reliability, reduces the traditional nine potential fault points to two, breaks the strong dependencies between steps, meets the high reliability requirements of industrial control, autonomous driving and other scenarios, and reduces maintenance costs. The simplified two-step process has clear logic, and fault diagnosis only needs to focus on two core links: table lookup matching and matrix multiplication, improving the diagnosis efficiency by 80% and greatly reducing the time and manpower costs of system maintenance and debugging.

[0088] 3. This invention provides a control channel bit-level processing device based on system matrix transformation, which has advantages in compatibility and scalability. It is developed based on 3GPP standards, is fully compatible with existing 5G NR protocols and subsequent upgrades, can be seamlessly deployed without modifying the device communication interface, supports offline pre-updates and online incremental updates, and can flexibly adapt to new (A, G) combinations to meet the expansion needs of 6G communication systems. Attached Figure Description

[0089] Figure 1 This is a traditional, rudimentary bit-level processing flow for the control channel;

[0090] The traditional 9-step processing flowchart illustrates the serial processing steps of control channel bits from input to output in existing technologies. The steps are: additional CRC, code block segmentation, code block additional CRC, bit interleaving, Polar channel coding, sub-block interleaving, bit selection, coded bit interleaving, and code block concatenation, clearly showing the serial relationship between the steps.

[0091] Figure 2 This is the bit-level processing flow of the control channel based on system matrix transformation according to the present invention;

[0092] This solution demonstrates the two-step core process of matrix lookup and matrix multiplication. Module 1 is the matrix lookup table, which includes index matching, matrix retrieval, and three-level caching functions. Module 2 is the modulo-2 matrix multiplication unit, which takes the original bit stream and transformation matrix M as input and outputs the final control channel bit stream.

[0093] Figure 3 This is a comparison chart showing the consistency of outputs from two schemes for 18 typical coding lengths of the present invention.

[0094] Each square represents a coding length, and a Hamming distance of 0 indicates that the outputs of the two schemes are completely identical, providing a direct verification of the scheme's correctness.

[0095] Figure 4 This is a comparison chart showing the processing time of two schemes for 18 typical encoding lengths of the present invention;

[0096] The horizontal axis represents the combination of (A, G), and the vertical axis represents the processing delay (s). Two curves are used to display the delay data of the traditional solution and the solution of this patent, clearly showing the delay advantage of this solution. Detailed Implementation

[0097] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0098] Example 1:

[0099] This invention provides a bit-level processing device for control channels based on system matrix transformation. The specific bit-level processing flow for control channels based on system matrix transformation is as follows:

[0100] Taking control channel transmission with A=64 (input bit length) and G=256 (output bit length) as an example, the specific implementation steps are as follows:

[0101] Transformation matrix pre-calculation: Call the SysMatrix(64,256) function to generate a 64×256 dimensional transformation matrix M. The matrix elements are 0 / 1 binary values. It has been verified that this matrix is ​​completely equivalent to the traditional 9-step processing flow.

[0102] Matrix storage: The matrix M is compressed and stored using the CSR sparse matrix format. The original storage size is 64×256=16384 bits, and the storage size is reduced to 4580 bits after compression (compression rate 72%). The compressed matrix is ​​stored in the high-frequency cache area of ​​the device's SRAM, and the corresponding AG index code is 64_256. The time-frequency resource parameters → AG index mapping table are also entered.

[0103] Matrix call: After the device allocates control channel resources (configures 8 RBs and 30kHz subcarrier spacing), it quickly matches AG index 64_256 through the mapping table, directly addresses and retrieves matrix M from the SRAM high-frequency buffer, with a retrieval delay of 8ns. After retrieval, it is temporarily stored in the dedicated register of the processing module.

[0104] Matrix multiplication: Input a 64-bit raw useful information bitstream and perform a modulo-2 matrix multiplication operation with matrix M in the register. The operation takes 5μs.

[0105] Results and Verification: The output is a 256-bit control channel bitstream, which is completely consistent with the output of the traditional 9-step process. Transmitted in an AWGN channel (signal-to-noise ratio 10dB), the BLER is 7.3 × 10⁻⁻⁶. 6 The total processing latency (call and operation) is 10μs, which meets the 1ms latency budget and high reliability requirements.

[0106] Example 2:

[0107] like Figure 3-4 As shown, the transformation matrix generation method of the present invention has the following verification data:

[0108] Output consistency verification: The specific scheme involves selecting 18 typical (A,G) code length combinations (including commonly used combinations such as 64_128, 64_256, 128_256, and 128_512), and comparing the proposed scheme (based on the SysMatrix function to generate matrix M) with the naive processing scheme. The results show that the output bitstream consistency rate of all combinations is 100%, verifying the correctness of the proposed scheme. Specific comparison data is as follows: Figure 3 As shown;

[0109] Processing latency verification: The processing time of the above 18 combinations (A,G) was compared and tested. The traditional solution took 50 to 300 times longer than this solution, while the processing time of this solution was significantly lower than that of the traditional solution. Specific comparison data are as follows. Figure 4 As shown.

[0110] The following points should be noted in this article:

[0111] 1. The accompanying drawings of the embodiments disclosed herein only relate to the structures involved in the embodiments disclosed herein; other structures can be referred to in general design.

[0112] 2. Where there is no conflict, the embodiments of this disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0113] Although embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions, and variations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

Claims

1. A bit-level processing device for a control channel based on system matrix transformation, comprising a transformation matrix generation module, a matrix pre-storage module, a matrix fast retrieval module, and a matrix multiplication operation module, characterized in that: The transformation matrix generation module is used to execute the transformation matrix generation method; The matrix pre-storage module is used to pre-calculate and compress the transformation matrix M corresponding to all commonly used (A,G) combinations; The matrix fast call module is used to quickly retrieve the corresponding transformation matrix M based on the A and G parameters of the input bit stream; The matrix multiplication module is used to perform modulo-2 matrix multiplication of the input bit stream and the transformation matrix M; The matrix pre-storage module adopts the CSR sparse matrix storage format to store the transformation matrix M in the on-chip SRAM of the device.

2. A method for generating a transformation matrix for a 5G control channel, characterized in that: The transformation matrix generation is achieved through the control channel bit-level processing device based on system matrix transformation as described in claim 1, comprising the following steps: Step A1: Construct a single-pulse reference vector u of the form [0,0,...,1]; Step A2: Create an A×G dimensional all-zero matrix M, where A is the length of the input original useful information bit stream and G is the length of the output control channel bit stream; Step A3: Use the circshift function to cyclically shift the reference vector u to the right, generating a unique input vector in group A where the positions of the "1"s are all different; Step A4: Pass each set of input vectors into the 3GPP TS 38.212 protocol standardization control channel coding function nrControlChannelEncode to perform the complete 9-step processing. The output result is used as the corresponding row of matrix M, and finally the complete transformation matrix M is formed.

3. The transformation matrix generation method for 5G control channels according to claim 2, characterized in that: The value of the transformation matrix M is only related to the input bit length A and the output bit length G. When A and G are fixed, the transformation matrix M has a unique value, and its operation result is completely consistent with the output of the traditional 9-step processing.

4. A fast bit processing method for control channel based on a transformation matrix, characterized in that: The method specifically includes the following steps: Step B1: Based on the length A of the current input bit stream and the preset output bit length G, quickly match and call the corresponding transformation matrix M in the matrix lookup table in memory; Step B2: Perform a modulo-2 matrix multiplication operation on the input bit stream and the called transformation matrix M, and directly output a bit stream of length G.

5. The fast bit processing method for control channel based on a transformation matrix as described in claim 4, characterized in that: The transformation matrix M is generated by the transformation matrix generation method for 5G control channels as described in claim 2.

6. A method for pre-storing and fast recalling a control channel transformation matrix, characterized in that: The method includes the following steps: Step C1: Pre-calculate the transformation matrix M corresponding to all commonly used (A,G) combinations; Step C2: Compress and store the transformation matrix M using the CSR sparse matrix storage format in the on-chip SRAM of the device; Step C3: Generate the "(A,G) parameter - matrix address" index table; Step C4: When the control channel bit stream is received, parse the input length A and output length G parameters; Step C5: Locate the physical address of the pre-storage matrix M by querying the index table based on (A, G); Step C6: Read matrix M from SRAM, verify its integrity, and temporarily store it in the dedicated register of the processing module.

7. The method for pre-storing and fast recalling of a control channel transformation matrix according to claim 6, characterized in that: In step C1, the matrix pre-calculation is completed once during the device startup phase or after the configuration parameters (A / G) are changed. In step C2, the CSR sparse matrix storage format can compress storage volume by 72% compared with traditional full matrix storage.

8. The method for pre-storing and fast recalling of a control channel transformation matrix according to claim 6, characterized in that: The fast call method also includes optimization strategies, such as keeping the (A, G) combination matrix, which is used frequently, permanently in the SRAM core area, and retrieving and reusing the matrix in one go for bit streams with the same parameters in multiple consecutive frames.

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