An integrated time delay sip module based on ltcc

Abstract

This invention discloses an integrated time-delay SIP module based on LTCC (Low Temperature Co-fired Ceramic), comprising a first switch chip, a second switch chip, an attenuator chip, and a ceramic housing formed by integral sintering of multiple layers of low temperature co-fired ceramic. The top of the ceramic housing has a chip mounting cavity to accommodate the chips. Microstrip lines are arranged on the surface of the housing, and at least two layers of strip-shaped time-delay lines are embedded internally. The strip-shaped time-delay lines are electrically connected across layers via coaxial metal vias, forming a three-dimensional time-delay transmission path. A direct link and a time-delay link are formed within the module. The two switch chips switch synchronously to select one to conduct the corresponding link, and the attenuator is used to compensate for the amplitude difference between the two links. This invention integrates time-delay and switching functions into a single package. The three-dimensional wiring structure effectively improves the time delay per unit area while ensuring impedance continuity and shielding performance of RF transmission, adapting to the miniaturization requirements of phased array antennas.

Description

Technical Field

[0001] This invention relates to the field of phased array antenna technology, and in particular to an integrated time-delay SIP module based on LTCC. Background Technology

[0002] When phased array antennas operate in broadband signal and large scan angle scenarios, there are path differences in the signal transmission paths of array elements at different locations. The larger the array size and the more array elements there are, the more significant the time difference between the transmit and receive links becomes. The delay module improves beamforming efficiency by compensating for the time difference between each link and is an indispensable core component in large phased array technology.

[0003] Currently, most delay modules on the market adopt a discrete design architecture, with the delay transmission unit and the switching unit being independent devices that need to be deployed separately and cascaded through external lines. In addition to the space occupied by the delay transmission section itself, additional space needs to be reserved for the installation of the switching module and interconnection wiring, resulting in a large overall board area and significantly increasing the difficulty of layout for the transmission network. At the same time, existing delay lines mostly use a single-layer planar wiring structure, which limits the delay that can be achieved per unit area. To achieve the corresponding delay targets, it is often necessary to further increase the physical size of the module, making it difficult to adapt to the development trend of high density and miniaturization in phased array systems.

[0004] In summary, existing delay modules suffer from drawbacks such as low integration, large size, poor space utilization, and weak layout adaptability. Summary of the Invention

[0005] The purpose of this invention is to provide an integrated delay SIP module based on LTCC, which solves the aforementioned technical problems in the prior art by integrating delay and switching functions into a single package. The specific technical solution is as follows: An integrated time-delay SiP module based on LTCC includes a first switch chip, a second switch chip, an attenuator chip, and a ceramic housing. The first switch chip, second switch chip, and attenuator chip are all housed within a chip mounting cavity at the top of the ceramic housing. The surface of the ceramic housing is covered with microstrip lines, and at least two layers of strip-shaped time-delay lines are embedded internally. These strip-shaped time-delay lines are electrically connected across layers via coaxial metal vias to form a three-dimensional time-delay transmission path. The bottom of the ceramic housing has external pads electrically connected to the internal circuitry. The first switch chip, microstrip lines, attenuator chip, and second switch chip are sequentially electrically connected to form a direct link. The attenuator chip is connected in series in the direct link to compensate for the amplitude difference between the direct link and the time-delay link. The first switch chip is connected to one end of the time-delay transmission path via a microstrip line and a coaxial metal via. The other end of the time-delay transmission path is connected to the second switch chip via a coaxial metal via and a microstrip line to form a time-delay link. The first and second switch chips are used for synchronous switching, selectively activating either the direct link or the time-delay link.

[0006] Furthermore, the ceramic tube shell is provided with multiple layers of grounding metal planes, and grounding metal planes are provided on the upper and lower sides of each layer of strip-shaped time delay line.

[0007] Furthermore, a matching slot is provided on the grounding metal plane at the position corresponding to the path of the strip delay line. The extension path of the matching slot is consistent with the routing of the strip delay line, and the width of the matching slot is 5 times the width of the strip delay line.

[0008] Furthermore, at least two strip-shaped delay lines include a first strip-shaped delay line and a second strip-shaped delay line, which are respectively located in different dielectric layers inside the ceramic tube shell; both the first strip-shaped delay line and the second strip-shaped delay line adopt a reciprocating bending routing layout, and the corners of the routing lines are rounded transition structures.

[0009] Furthermore, a first RF matching terminal is provided between the first switching chip and the input terminal of the strip delay line, a second RF matching terminal is provided between the second switching chip and the output terminal of the strip delay line, and a third RF matching terminal is provided in the through link; each RF matching terminal is arranged on the surface of the ceramic tube shell, wherein the first RF matching terminal and the second RF matching terminal are connected in series between the microstrip line and the coaxial metal via.

[0010] Furthermore, the first RF matching terminal, the second RF matching terminal, and the third RF matching terminal are all T-shaped structures.

[0011] Furthermore, the external pads at the bottom of the ceramic housing are QFN pads, which contain at least two RF ports, at least two functional ports, and multiple reference ground ports.

[0012] Furthermore, the first switch chip and the second switch chip are arranged as mirror images of each other, and each switch chip is equipped with multiple radio frequency ports and multiple functional ports.

[0013] Furthermore, the right-angle bends of the microstrip lines that form the straight-through link are provided with chamfered structures.

[0014] Furthermore, the chip mounting cavity includes a lower chip placement cavity and an upper bonding working cavity. The depth of the chip placement cavity is less than the depth of the bonding working cavity, and the bottom of the chip placement cavity is a ground plane.

[0015] The integrated delay SIP module based on LTCC of this invention has the following advantages: 1. Using a sintered LTCC ceramic housing as the core carrier, the switching, amplitude compensation, and time delay transmission functions are integrated into a single package, eliminating the structural redundancy of the discrete substrate and additional metal shell of traditional time delay modules, and significantly reducing the physical size and assembly process of the module. At the same time, multi-layer strip delay lines are connected across layers through coaxial metal vias to construct a three-dimensional time delay transmission path, breaking the area bottleneck of planar wiring, effectively improving the time delay per unit area, and the shielding structure of the coaxial vias can ensure the impedance continuity of the interlayer transition and reduce signal crosstalk, achieving a balance between miniaturization and high RF performance.

[0016] 2. By setting ground metal planes on the upper and lower sides of each layer of strip-shaped delay lines, a closed strip-shaped transmission structure can be formed, which confines the electromagnetic field inside the medium, effectively reducing radiation loss and improving the module's anti-electromagnetic interference capability. At the same time, multiple independent ground planes can form reliable electromagnetic isolation between delay lines of different layers, weaken the signal coupling of the bent traces between upper and lower layers, reduce the dispersion characteristics of the delay lines, and ensure the delay accuracy and signal stability in broadband working scenarios.

[0017] 3. A matching slot is made along the path of the strip delay line on the ground metal plane, and the slot width is 5 times the line width. This can optimize the electromagnetic field distribution at the point where the coaxial metal via crosses the ground plane, compensate for the impedance change in the via region, improve the impedance matching state of the transition region between the microstrip line, coaxial via and strip delay line, reduce signal reflection and insertion loss, and effectively improve the transmission performance of the delay link and the performance consistency of mass production.

[0018] 4. The strip delay line adopts a reciprocating bending routing layout, which can make full use of the planar space of the ceramic layer, maximize the transmission line length per unit area, and improve the delay capacity of a single layer; at the same time, the routing corners adopt a rounded transition structure, which can smooth the transmission line impedance changes at the corners, weaken the parasitic discontinuity capacitance caused by right-angle corners, reduce signal reflection and phase distortion, and enable the densely bent delay line to maintain good transmission characteristics.

[0019] 5. By setting an RF matching terminal in series between the microstrip line and the coaxial via between the switching chip and the strip delay line, an impedance transition section can be formed between the chip port and the internal transmission line of the ceramic, improving the impedance matching state at the interconnection point and reducing signal reflection and insertion loss at the connection node. At the same time, the independent matching terminal structure facilitates targeted debugging according to the port characteristics of different chips, improving the compatibility of the solution with different chip models and also helping to optimize the performance yield of mass production.

[0020] 6. The RF matching terminal adopts a T-shaped structure, which can flexibly adjust the impedance transformation characteristics by adjusting the size parameters of the wide and narrow ends, so as to achieve good matching between the chip and the internal circuit of the package. The structure is simple, compatible with the planar processing technology of LTCC, requires no additional process, and is easy to debug. It can reduce the cost of circuit design and processing debugging while ensuring the matching effect. Attached Figure Description

[0021] Figure 1 This is an overall schematic diagram of the integrated delay SIP module based on LTCC of the present invention.

[0022] Figure 2 This is a cross-sectional schematic diagram of the ceramic tube shell structure in the integrated delay SIP module based on LTCC of the present invention.

[0023] Figure 3 This is a cross-sectional schematic diagram of the strip delay line path in the integrated delay SIP module based on LTCC of the present invention.

[0024] Figure 4 This is an exploded view of the integrated delay SIP module based on LTCC of the present invention.

[0025] Figure 5 This is an assembly diagram of the integrated delay SIP module based on LTCC of the present invention.

[0026] Figure 6 This is a schematic diagram of the CO3 layer in the integrated delay SIP module based on LTCC of this invention.

[0027] Figure 7 This is a schematic diagram of the C07 layer in the integrated delay SIP module based on LTCC of this invention.

[0028] Figure 8 This is a schematic diagram of the pads in the integrated delay SIP module based on LTCC of this invention.

[0029] Figure 9 This is a schematic diagram of the through link in the integrated delay SIP module based on LTCC of this invention.

[0030] Figure 10This is a graph showing the S-parameter performance of the delay link in the integrated delay SIP module based on LTCC of this invention.

[0031] Figure 11 This is a graph showing the latency performance (minus the pass-through latency) of the latency link in the integrated latency SIP module based on LTCC of this invention. Detailed Implementation

[0032] To better understand the purpose, structure, and function of this invention, the integrated time-delay SIP (System-in-Package) module based on LTCC (Low Temperature Co-fired Ceramic) of this invention will be described in detail below with reference to the accompanying drawings.

[0033] like Figures 1 to 11 As shown, this invention provides an integrated time-delay SIP module based on LTCC, mainly used in phased array antenna systems to compensate for path delay differences between different array elements during beam scanning, thereby improving beamforming efficiency under broadband signals. The module's core carrier is a ceramic tube shell 1 formed by the integral sintering of multiple layers of low-temperature co-fired ceramic. Switching, amplitude compensation, and time-delay transmission functions are all integrated into a single package, eliminating the need for separate substrates and metal casings. This significantly reduces the physical volume while ensuring RF transmission performance and environmental reliability. In this embodiment, the dielectric constant of the ceramic substrate is 7.3, and the thickness of the single-layer green ceramic after sintering is 0.108 mm. The entire module is composed of 15 layers of green ceramic stacked and fired, defined from bottom to top as C00 to C15 layers, with an overall shape of a 5 mm × 5 mm square structure.

[0034] The ceramic housing 1 is integrally formed by high-temperature co-firing of multiple layers of green ceramic, serving four functions: encapsulation shell, transmission medium, grounding shield, and external interconnection. The top of the ceramic housing 1 has a recessed chip mounting cavity 2, which adopts a layered recessed structure: layers C11 to C15 are reserved to form the upper bonding working cavity, with a depth corresponding to the thickness of four layers of green ceramic, approximately 0.404 mm; layers C09 to C11 are recessed to form three independent lower chip placement cavities, with a depth corresponding to the thickness of two layers of green ceramic, approximately 0.202 mm. The bottom of each chip placement cavity is a complete grounding plane. The first switch chip 3, the second switch chip 4, and the attenuator chip 5 are all fixed inside the chip mounting cavity 2 using surface mount technology. After the chips are mounted, each port is electrically connected to the corresponding bonding pads on the surface of the housing via gold wire bonding, completing the cascading of the chips and internal circuitry. This arrangement, which embeds the active chip within the ceramic housing 1 cavity, significantly reduces the overall height of the module and minimizes lateral assembly space compared to the traditional discrete structure of substrate, external chip, and metal casing. Furthermore, the shielding properties of the ceramic substrate itself reduce the impact of external electromagnetic interference on the internal chip. After chip mounting and gold wire bonding processes are completed, a metal cover plate 7 can be welded to the solder ring 6 pre-reserved at the top of the C15 layer to completely seal the chip mounting cavity 2, creating an airtight space inside the module and meeting the environmental protection requirements of high-reliability applications.

[0035] The surface of the ceramic housing 1 is covered with microstrip lines 15 for short-distance interconnection between chip ports. Inside the housing, at least two layers of strip-shaped delay lines are embedded: a first strip-shaped delay line 8 located on layer C03 and a second strip-shaped delay line 9 located on layer C07. Layers C01, C05, and C09 are ground metal planes, corresponding to the first ground metal plane 10, the fifth ground metal plane 12, and the ninth ground metal plane 14, respectively. Layer C03 corresponds to the third metal layer 11, and layer C07 corresponds to the seventh metal layer 13; these two layers are signal routing layers for the strip-shaped delay lines and do not serve a grounding function. The strip-shaped delay lines are distributed at different dielectric depths, and cross-layer electrical connections are achieved between layers through coaxial metal vias, collectively forming a three-dimensional delay transmission path. In traditional planar routing schemes, the total length of the delay line is limited by the planar area of ​​the package, and the delay achievable per unit area is limited. This embodiment splits the delay line into different dielectric layers and completes the interlayer signal transfer with the help of coaxial metal vias. The specific transmission path is as follows: after being led out from the first RF matching terminal 17 of the C11 layer, it passes down through four layers of LTCC dielectric and one layer of metal ground plane through the coaxial metal via below the matching terminal, and reaches the input terminal of the second strip delay line 9 of the C07 layer. The signal extends through multiple bends and loops in the second strip delay line 9 to the position below the second switch chip 4, and then passes down through four layers of LTCC dielectric and one layer of metal ground plane through the coaxial metal via to reach the C03 layer, where it is connected to the first strip delay line 8. It extends along the same bend routing logic to the position below the corresponding second RF matching terminal 18, and finally passes up through eight layers of LTCC dielectric and two layers of ground metal plane through the coaxial metal via, returning to the bonding area plane of the C11 layer. This three-dimensional routing effectively expands the wiring space multiple times within the same footprint, significantly improving the latency capacity per unit package area. In this embodiment, this structure achieves an equivalent latency relative to an 85mm air path, corresponding to a phase of approximately 1867 degrees, with a relative latency of 0.28ns, while maintaining a very small overall package size of 5mm × 5mm. Furthermore, unlike ordinary metallized vias, the shielded coaxial metal vias have a surrounding grounding structure that confines the signal field within the via, reducing impedance abrupt changes and electromagnetic radiation during interlayer transitions. This ensures impedance continuity throughout the RF transmission process and avoids interlayer crosstalk issues caused by multilayer routing, resulting in more stable latency performance.

[0036] The bottom of the ceramic housing 1 is provided with an external solder pad 16 that is electrically connected to the internal circuitry. This serves as the interconnection interface between the module and the external circuit board. All radio frequency signals, control signals, and grounding connections are completed through the external solder pad 16, eliminating the need for additional side pins or connectors and further reducing the overall size of the module.

[0037] The module internally forms two switchable signal paths: a direct link and a time-delay link. The direct link is constructed by sequentially connecting a first switch chip 3, a microstrip line 15, an attenuator chip 5, and a second switch chip 4. In this embodiment, the microstrip line 15 of the direct link corresponds to two dielectric layers with a linewidth of 0.26 mm. The signal is transmitted along the surface microstrip line 15, resulting in a short path and low inherent time delay, suitable for operating scenarios where no time delay compensation is required, such as normal radiation from a phased array antenna. The attenuator chip 5 is connected in series in the direct link, primarily used to compensate for the amplitude difference between the two links. The time-delay link traverses a long strip-shaped time-delay line, naturally resulting in higher insertion loss than the shorter direct link. By adding an attenuator chip 5 with matching attenuation in the direct link, the output signal amplitudes of the two links can be kept consistent, preventing signal amplitude jumps during link switching and ensuring the stability of phased array beamforming.

[0038] The time-delay link is led out from the first switch chip 3, passing through the surface microstrip line 15 and coaxial metal vias into the inner time-delay transmission path. The signal sequentially passes through the second strip-shaped time-delay line 9 and the first strip-shaped time-delay line 8 to complete long-distance transmission, and then returns to the surface microstrip line 15 through the coaxial metal via at the other end, finally connecting to the second switch chip 4. Most of the entire time-delay transmission path is embedded inside the ceramic dielectric, wrapped by ground planes on the top and bottom, providing excellent electromagnetic shielding. It is far less affected by the external environment and cavity resonance than the open microstrip line 15 structure, maintaining excellent time-delay linearity and signal integrity in a small volume. The first switch chip 3 and the second switch chip 4 operate synchronously, selecting one to conduct the direct-through link or the time-delay link according to the external control signal, which can quickly complete the switching of the module's working mode and meet the time-delay requirements of the phased array antenna under different scanning states. The three-dimensional delay wiring structure, formed by cascading multiple strip delay lines across coaxial metal vias, can effectively improve the delay per unit area within a limited package area, while ensuring the impedance continuity and electromagnetic shielding performance of RF transmission. It is the core structure for achieving both module miniaturization and high performance.

[0039] To further optimize the transmission performance of the stripline delay line, multiple grounding metal planes are arranged inside the ceramic housing 1. Each stripline delay line has corresponding grounding metal planes on both its upper and lower sides. The fifth grounding metal plane 12, located in layer C05, serves as a shared intermediate shielding layer for both stripline delay lines. The stripline structure relies on the enclosed space formed by the upper and lower grounding planes to confine the electromagnetic field. Compared to the semi-open microstrip line 15 structure, it exhibits lower radiation loss and stronger anti-interference capabilities. The shared intermediate grounding plane effectively isolates the two delay lines, preventing signal coupling caused by bending in the upper and lower layers, thereby reducing the dispersion characteristics of the delay line and ensuring delay accuracy for broadband signals.

[0040] On the grounded metal plane, a matching slot is provided at the position corresponding to the path of the strip delay line. The extension path of the slot is consistent with the routing of the strip delay line, and the width of the slot is set to 5 times the linewidth of the strip delay line. This setting is mainly used to optimize the impedance matching of the transition region between the coaxial via and the strip line: when the coaxial metal via crosses the grounded plane, the field distribution in the via region will be distorted, which can easily cause impedance discontinuities and signal reflections. By setting a matching slot of corresponding width along the line path, the equivalent dielectric constant and field distribution of the transition region can be adjusted, so that the impedance transition between the microstrip line 15, the coaxial metal via, and the strip delay line can be smoothed. Simulation verification shows that when the slot width is 5 times the linewidth, the return loss of this transition structure is optimal, which can effectively reduce insertion loss and improve the consistency of delay performance.

[0041] Both the first strip delay line 8 and the second strip delay line 9 employ a reciprocating bending routing layout to maximize the total length of the transmission line within the limited ceramic layer plane, thereby achieving the target delay and maximizing the use of planar routing space. All corners of the two strip delay lines utilize rounded corner transitions. This is because right-angle corners cause abrupt changes in the equivalent width of the transmission line, generating parasitic discontinuities at the corners, leading to signal reflection and phase distortion. Rounded corner transitions smooth out impedance changes at the corners, weakening the impact of discontinuities, reducing transmission line performance degradation, and ensuring good transmission characteristics even with bent routing.

[0042] A first RF matching terminal 17 is provided between the first switching chip 3 and the input terminal of the stripline delay line, a second RF matching terminal 18 is provided between the second switching chip 4 and the output terminal of the stripline delay line, and a third RF matching terminal 19 is provided in the direct link; all terminals are arranged on the surface of the ceramic housing 1, wherein the first RF matching terminal 17 and the second RF matching terminal 18 are connected in series between the microstrip line 15 and the coaxial metal via. Since the impedance characteristics of the chip port differ from the impedance characteristics of the transmission line inside the ceramic housing 1, direct interconnection is prone to impedance mismatch, increasing signal reflection; the three types of RF matching terminals are all equivalent to impedance transformation structures, which can improve the matching effect between the chip and the internal circuit of the housing and reduce transition loss. In this embodiment, the first RF matching terminal 17, the second RF matching terminal 18, and the third RF matching terminal 19 all adopt a T-shaped structure. The first and second RF matching terminals 17 and 18 are used to connect the switching chip and the strip delay line, with an overall size of 0.65mm × 0.6mm, a narrower end size of 0.2mm × 0.435mm, and a wider end size of 0.185mm × 0.6mm. The third RF matching terminal 19 adapts to the impedance matching requirements of a through-link, with an overall size of 0.58mm × 0.35mm, a narrower end size of 0.2mm × 0.3mm, and a wider end size of 0.35mm × 0.28mm. By adjusting the dimensional parameters of the wide and narrow ends of the terminals, the matching performance can be flexibly adjusted to adapt to different models of switching chips, reducing the difficulty of circuit debugging and improving performance consistency during mass production.

[0043] The external pads 16 at the bottom of the ceramic housing 1 adopt a QFN (Quad Flat No-Leader) pad structure, containing at least two RF ports, at least two functional ports, and multiple reference ground ports. In this embodiment, it is specifically configured with two RF ports, two functional ports, and twenty-five reference ground ports. The definition of each port can be flexibly adjusted according to the actual project requirements. The QFN package is a surface mount technology that can reduce the assembly difficulty of downstream users' SMT (Surface Mount Technology) and improve the soldering yield. It can also enhance the grounding performance and heat dissipation capacity of the module through the large area of ​​the external pads 16 and reference ground ports. All external ports are concentrated at the bottom of the housing, eliminating the need for side leads, further compressing the lateral size of the module, and also making it easier to achieve overall hermetic packaging, improving the module's adaptability in complex environments.

[0044] The first switch chip 3 and the second switch chip 4 are arranged in a mirror image of each other within the cavity. Each switch chip has multiple RF ports and multiple functional ports. The RF ports include a common terminal RFc and two path terminals RF1 and RF2. The functional ports include voltage control terminals VS and VC. This mirrored layout allows for more symmetrical routing of the two links, reducing additional phase and amplitude differences introduced by asymmetrical routing. It also facilitates routing planning within the cavity, improving layout efficiency within a limited space. By applying different bias voltages to the two control ports, the conduction state of the internal paths of the switches can be controlled, enabling rapid switching of link states. The control logic is simple and reliable.

[0045] The microstrip line 15, which constitutes the straight-through link, has a chamfered structure at its right-angle bend. When the microstrip line 15 makes a right-angle bend, the electric field concentrates in the corner region, generating a parasitic capacitance effect, which leads to a decrease in local impedance and forms an impedance discontinuity point. By chamfering at the right angle, the impedance change at the corner can be effectively compensated, signal reflection can be reduced, the return loss and insertion loss performance of the straight-through link can be optimized, and the signal transmission quality in the straight-through state can be guaranteed.

[0046] Furthermore, the chip mounting cavity 2 adopts a layered structure, including a lower chip placement cavity and an upper bonding working cavity. The depth of the chip placement cavity is less than the depth of the bonding working cavity, and the bottom of the chip placement cavity is a ground plane. Placing the chip in the shallower chip placement cavity reduces the height difference between the chip pads and the surface bonding pads, shortens the gold wire bonding span, and reduces parasitic inductance and transmission loss introduced by bonding. The deeper upper bonding working cavity provides ample operating space for the gold wire bonding process, preventing the bonding wires from touching the cavity sidewalls, and also provides the necessary air gap for chip operation, ensuring the long-term reliability of the device.

[0047] The working principle of this delay SIP module directly corresponds to the working mode of the phased array antenna. When the phased array antenna is operating in normal radiation mode, the propagation path length of the signal emitted by each array element is consistent, and no delay compensation is required. At this time, the module switches to a direct link through the switching chip: the radio frequency signal is input from the common port of the first switching chip 3, led out through the direct path inside the switch to the surface microstrip line 15, passes through the attenuator chip 5 to complete amplitude calibration, and then enters the corresponding path of the second switching chip 4 and is finally output. The entire path has a short transmission distance and a small inherent delay, ensuring that the signal passes through the module with minimal loss.

[0048] When a phased array antenna performs beam scanning, the path lengths from different array elements to the target direction differ, causing time differences in the arrival times of the signals from each element and reducing beam combining efficiency. In this case, the module switches to a time-delay link: the RF signal is input from the common port of the first switch chip 3, enters the first RF matching terminal 17 through a corresponding path to complete impedance transition, then penetrates deep into the ceramic through a coaxial metal via, sequentially passing through the second strip-shaped time-delay line 9 and the first strip-shaped time-delay line 8. After multiple bends and loops in the C03 and C07 wiring layers, following a preset delay path, it returns to the surface through the coaxial via and is output through the second switch chip 4. The signal receives a fixed time delay increment after traveling a long distance along the strip-shaped time-delay line, thus offsetting the path difference caused by the phased array scanning, enabling the signals from each element to be synthesized in phase, improving antenna performance in wideband, large-scan-angle scenarios. Switching between the two links can be completed simply by changing the voltage at the control port of the switch chip, resulting in a fast response and adapting to the beam agility requirements of the phased array antenna.

[0049] In summary, this embodiment uses an LTCC-integrated sintered ceramic housing 1 as the integration carrier, combined with multi-layer three-dimensional delay wiring, coaxial via transition, impedance matching optimization, and layered cavity structures, to achieve complete functions of switching, amplitude compensation, and delay transmission within a very small package size. This effectively solves the problems of large size, low integration, and performance susceptibility to environmental influences of traditional delay modules, and can well adapt to the development trend of miniaturization and high density of phased array antennas.

[0050] The present invention has been further described above with reference to specific embodiments. However, it should be understood that the specific descriptions herein should not be construed as limiting the substance and scope of the present invention. Various modifications made to the above embodiments by those skilled in the art after reading this specification are all within the scope of protection of the present invention. The various specific technical features described in the above embodiments can be combined in any suitable manner without contradiction. To avoid unnecessary repetition, the embodiments of the present invention will not further describe various possible combinations.

[0051] If the embodiments of the present invention involve directional indicators (such as up, down, left, right, front, back, etc.), the directional indicators are only used to explain the relative positional relationship and movement of the components in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicators will also change accordingly.

Claims

1. An integrated delay SIP module based on LTCC, characterized in that, The device includes a first switch chip, a second switch chip, an attenuator chip, and a ceramic housing. The first switch chip, second switch chip, and attenuator chip are all housed within a chip mounting cavity at the top of the ceramic housing. The surface of the ceramic housing is covered with microstrip lines, and at least two layers of strip-shaped time delay lines are embedded internally. These strip-shaped time delay lines are electrically connected across layers via coaxial metal vias to form a three-dimensional time delay transmission path. The bottom of the ceramic housing has external pads electrically connected to the internal circuitry. The first switch chip, the microstrip lines, the attenuator chip, and the second switch chip are sequentially electrically connected to form a direct link. The attenuator chip is connected in series in the direct link to compensate for the amplitude difference between the direct link and the time delay link. The first switch chip is connected to one end of the time delay transmission path via the microstrip lines and coaxial metal vias, and the other end of the time delay transmission path is connected to the second switch chip via coaxial metal vias and the microstrip lines to form the time delay link. The first switch chip and the second switch chip are used for synchronous switching, selectively activating either the direct link or the time delay link.

2. The integrated delay SIP module based on LTCC according to claim 1, characterized in that, The ceramic tube shell is provided with multiple layers of grounding metal planes inside, and the grounding metal planes are provided on the upper and lower sides of each layer of strip-shaped time delay line.

3. The integrated delay SIP module based on LTCC according to claim 2, characterized in that, A matching slot is provided on the grounding metal plane at a position corresponding to the path of the strip delay line. The extension path of the matching slot is consistent with the routing of the strip delay line, and the width of the matching slot is 5 times the width of the strip delay line.

4. The integrated delay SIP module based on LTCC according to claim 1, characterized in that, The at least two strip-shaped delay lines include a first strip-shaped delay line and a second strip-shaped delay line, which are respectively located in different dielectric layers inside the ceramic tube shell; both the first strip-shaped delay line and the second strip-shaped delay line adopt a reciprocating bending routing layout, and the corners of the routing lines are rounded transition structures.

5. The integrated delay SIP module based on LTCC according to claim 1, characterized in that, A first RF matching terminal is provided between the first switching chip and the input terminal of the strip delay line, a second RF matching terminal is provided between the second switching chip and the output terminal of the strip delay line, and a third RF matching terminal is provided in the through link; each RF matching terminal is disposed on the surface of the ceramic tube shell, wherein the first RF matching terminal and the second RF matching terminal are connected in series between the microstrip line and the coaxial metal via.

6. The integrated delay SIP module based on LTCC according to claim 5, characterized in that, The first RF matching terminal, the second RF matching terminal, and the third RF matching terminal are all T-shaped structures.

7. The integrated delay SIP module based on LTCC according to any one of claims 1 to 6, characterized in that, The external pads at the bottom of the ceramic housing are QFN pads, which include at least two RF ports, at least two functional ports, and multiple reference ground ports.

8. The integrated delay SIP module based on LTCC according to any one of claims 1 to 6, characterized in that, The first switch chip and the second switch chip are arranged as mirror images of each other, and each switch chip is provided with multiple radio frequency ports and multiple functional ports.

9. The integrated delay SIP module based on LTCC according to any one of claims 1 to 6, characterized in that, The right-angle bends of the microstrip lines that constitute the straight-through link are provided with chamfered structures.

10. The integrated delay SIP module based on LTCC according to any one of claims 1 to 6, characterized in that, The chip mounting cavity includes a lower chip placement cavity and an upper bonding working cavity. The depth of the chip placement cavity is less than the depth of the bonding working cavity, and the bottom of the chip placement cavity is a ground plane.

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