Radio frequency communication circuit and method

Abstract

The present invention relates to radio frequency communication circuits and methods. An apparatus can include a digital power amplifier (DPA) comprising a plurality of amplifier cells configured to provide an output signal based on amplitude control information, wherein each amplifier cell is switchable to contribute to the output signal; and a controller configured to enable a subset of the plurality of amplifier cells according to an activation sequence, wherein the subset comprises enabled amplifier cells arranged in a non-adjacent manner, wherein at least one non-enabled amplifier cell of the plurality of amplifier cells is placed between adjacent enabled amplifier cells.

Description

Background Technology

[0001] In wireless communication networks based on numerous wireless communication technologies, such as Wireless Local Area Networks (WLAN or Wi-Fi), Bluetooth, 4th Generation Long Term Evolution (LTE), and 5th Generation (5G) New Radio (NR), various methods are employed to provide wireless data delivery with desired efficiency, speed, and reliability. These networks require robust design and implementation of radio frequency (RF) components to achieve desired performance characteristics, including low power consumption, high bandwidth, and minimal interference. As wireless communication technologies evolve to meet the ever-growing demands for data and mobile applications, the need for efficient and scalable RF solutions has become critical.

[0002] Digital transmit (DTX) architecture represents a paradigm shift from traditional analog transmit architectures, offering enhanced integration and efficiency in wireless communication systems. Employing digital signal processing techniques, DTX architectures enable compact design and scalability in advanced complementary metal-oxide-semiconductor (CMOS) processes, addressing the ever-increasing demands for wider bandwidth and more sophisticated modulation schemes. Unlike analog transmit architectures that utilize Class AB CMOS power amplifiers (PAs) and quadrature modulation, such as Quadrature Analog Transmit (Q-ATX) systems, DTX architectures rely on digital signal operation, enabling improved power efficiency through switching power amplifiers and compact die areas. Many DTX architectures, such as the Digital Polar Transmitter (DPTX) architecture, can comprise two main functional blocks: a digital time converter (DTC) and a digital power amplifier (DPA). The DTC modulates the local oscillator (LO) signal using phase information, while the DPA modulates the amplitude of the signal onto a phase-modulated LO (MOLO) signal to generate a radio frequency (RF) communication signal. Attached Figure Description

[0003] In the accompanying drawings, similar reference numerals typically refer to the same parts in different views. The drawings are not necessarily to scale, but rather focus on illustrating the principles described herein. In the following description, various aspects are described with reference to the following drawings, in which:

[0004] Figure 1 and Figure 2 Describe a general network and device architecture for wireless communication and / or sensing operations;

[0005] Figure 3 Example illustrations showing various communication elements for a device used in a wireless communication apparatus;

[0006] Figure 4 An example illustration showing the transmit path of an RF transceiver;

[0007] Figure 5A block diagram showing an example of a communication circuit;

[0008] Figure 6 An illustrative example of a digital power amplifier unit is shown;

[0009] Figure 7 An illustrative example of digital power amplifier operation is shown;

[0010] Figure 8 An illustrative example of digital power amplifier operation is shown;

[0011] Figure 9 An illustrative example of digital power amplifier operation is shown;

[0012] Figure 10 Examples of complementary cumulative distribution functions based on the aspects described in this paper are shown;

[0013] Figure 11 An example of one method is shown. Detailed Implementation

[0014] The following detailed description refers to the accompanying drawings, which illustrate exemplary details and aspects by way of illustration that can be put into practice the aspects described herein.

[0015] Transmitter architectures have evolved to include various RF transmitter designs, including digital transmitter architectures. These architectures can incorporate digital signal processing for enhanced efficiency and scalability. Unlike traditional analog transmitters that can rely on quadrature modulation and analog power amplifiers, digital polarity transmitters can utilize components such as digital time converters and digital power amplifiers. These components enable precise modulation of phase and amplitude, making them particularly suitable for broadband applications with stringent performance requirements.

[0016] Wireless communication systems rely on efficient signal transmission and amplification to ensure high performance, reliability, and cost-effectiveness. As devices become more compact and energy-efficient, the demand for optimized digital power amplifiers has increased significantly. Digital power amplifiers play a crucial role in wireless transmitters by amplifying signals while maintaining signal integrity and efficiency. Given the widespread deployment of wireless technologies in mobile devices, base stations, and Internet of Things (IoT) applications, there is an ongoing need to improve the performance of digital power amplifiers while addressing fundamental challenges such as heat dissipation, power efficiency, and component lifetime.

[0017] Challenges in designing digital power amplifiers can include managing the heat generated during operation. As a byproduct of electronic switching and power amplification, semiconductor devices, including those in digital power amplifiers, generate heat. If this heat is not effectively dissipated, it can accumulate within the device, leading to elevated operating temperatures. Elevated temperatures, in turn, cause semiconductor component performance degradation, reduced efficiency, and accelerated aging. These effects ultimately impact the amplifier's reliability and lifespan, making thermal management a critical consideration in digital power amplifier design. Maintaining thermal stability is paramount in high-performance wireless applications, as overheating can cause signal distortion, variations in output power, and ultimately, device failure.

[0018] Various approaches exist to alleviate the thermal challenges of digital power amplifiers. One common approach involves reducing the density of circuit components, thereby enabling better heat dissipation. However, reducing circuit density comes at the cost of increased chip area and manufacturing costs, making it an impractical solution for cost-sensitive applications. Another approach relies on external thermal management solutions, such as heat sinks, fans, or dedicated cooling systems. While effective in temperature control, these solutions introduce additional costs, increase system complexity, and may not be suitable for compact and integrated wireless devices.

[0019] Strategies to improve the lifespan of digital power amplifiers can include operating the amplifier at reduced power levels and avoiding situations where excessive heat buildup occurs. By limiting the maximum operating power, thermal stress on the device can be reduced, thereby extending its operational lifespan. However, this approach may sacrifice overall performance, as reducing the amplifier's output power directly affects signal strength and transmission efficiency. In competitive wireless applications requiring high power efficiency and signal integrity, this trade-off may be considered undesirable.

[0020] Accordingly, a method remains needed to enhance the thermal performance and reliability of digital power amplifiers without compromising power efficiency, chip size, or overall performance. The aspects described in this paper address these challenges by introducing a configuration that optimally distributes heat dissipation across the digital power amplifier. Instead of relying on external cooling systems or reducing circuit density, the aspects described employ an advanced control mechanism that dynamically selects and activates amplifier units in a manner that reduces or minimizes localized heat buildup.

[0021] Digital power amplifiers typically comprise arrays or multiple arrays of amplifier units, each contributing to the overall output signal. The aspect described herein may include an activation scheme that activates only a subset of amplifier units at a given time, while ensuring that the activated units are distributed in a non-adjacent manner. By placing at least one inactive amplifier unit between adjacent activated units, particularly when the desired power level (e.g., indicated by amplitude control information) is below the power level capacity of the digital power amplifier, the aspect described herein can effectively distribute heat dissipation over a larger area to reduce peak silicon temperature. This approach addresses a fundamental design limitation in conventional digital power amplifiers where clusters of active units generate concentrated hotspots, leading to non-uniform heating and localized performance degradation.

[0022] Furthermore, by merging multiple predefined activation sequences, the aspects described in this paper can improve the lifetime of digital power amplifiers. These sequences enable adaptive operation, where the distribution of activation units can be dynamically adjusted based on operating conditions. By alternating between different activation sequences, wear on individual amplifier units can be distributed more evenly, mitigating long-term degradation effects. This technique can provide a significant improvement in device lifetime while maintaining optimal performance under changing load conditions.

[0023] The benefits of the aspects described in this paper extend beyond thermal management and reliability. Some aspects enable highly efficient configurations without compromising power consumption, signal quality, or chip size. Unlike prior solutions that require additional cooling components or performance trade-offs, the aspects described in this paper employ an inherent operating strategy to optimize heat dissipation. The ability to dynamically adjust activation modes based on real-time feedback, such as amplitude control information or thermal measurements, also improves adaptability and efficiency.

[0024] The aspects described herein may include a device comprising a digital power amplifier having multiple switchable amplifier units and control circuitry for activating a subset of these units according to an activation sequence. Specifically, when the desired output level is below a certain threshold, the activation sequence ensures that the activated amplifier units are arranged in a non-adjacent manner, wherein at least one inactive amplifier unit is placed between adjacent activated units. This spatial distribution mitigates localized heat buildup, thereby reducing thermal stress and improving the amplifier's reliability and lifespan.

[0025] In some respects, the device can combine multiple activation sequences, each representing a different mode that selectively enables amplifier units. By storing multiple activation sequences and dynamically selecting from them, the device enables adaptive operation based on operating conditions, such as thermal feedback from temperature sensors or amplitude control information. This dynamic adjustment ensures optimal performance under varying thermal and power conditions, thereby preventing overheating in any particular region of the amplifier array.

[0026] In some respects, the arrangement of amplifier units can be facilitated by a two-dimensional matrix, which can further promote efficient heat dissipation. The activation sequence can be defined in a corresponding configuration, in which the enabled amplifier units are distributed across specific rows or columns, ensuring a structured pattern that enhances heat dissipation. Furthermore, the activation sequence can be designed to achieve a uniform distribution of enabled units, ensuring balanced heat distribution and preventing localized performance degradation.

[0027] Beyond thermal management, the device ensures that the number of activated amplifier units directly corresponds to the desired output power level at the digital power amplifier's output. The control circuitry can determine which amplifier units to activate based on amplitude control information and generate switching signals accordingly. By ensuring that only activated amplifier units contribute to the output signal, the device improves power efficiency while maintaining signal integrity. Furthermore, the inclusion of a digital time converter and a processor providing amplitude and phase control information facilitates seamless integration into advanced communication systems, such as in digital transmission architectures, enabling high-performance wireless transmissions with precise power and phase modulation control.

[0028] As described herein, a digital time converter may include a circuit structure comprising: a first node configured for signal processing; a second node configured to receive a reference signal; a digital-to-analog signal converter section configured to process a digital control word; a configurable impedance network selectively coupled to the first node; a switching circuit arrangement (having a first switch coupled to the reference signal and a second switch coupled to a reset voltage level); a comparator circuit coupled to an output stage; a capacitor element configured for timing control; and a current source configured for edge timing control. The described structure is configured to receive a digital control word representing desired phase modulation parameters, process a reference clock signal from a local oscillator, convert a digital input code into a corresponding time delay, generate an output signal with a timing adjustment having controlled edge transitions, and provide a phase-modulated output suitable for driving an RF stage, such that the structure performs a time-domain conversion of the timing variations from the digital input signal to the output signal with precise control.

[0029] Digital power amplifiers can include circuit structures comprising switching elements arranged for RF signal amplification. Common implementations may include RF-DAC (RF digital-to-analog converter) configurations utilizing a switched capacitor array with binary weighted capacitors and digital control logic for capacitor switching, and / or switched capacitor power amplifier (SCPA) implementations (characterized by a bridged configuration of semiconductor switches coupled to the capacitor array for charge domain signal processing) and digital decoder / encoder blocks for switch control. Further architectural variations may include Class G implementations with dual supply voltages, quadrature switched capacitor power amplifier structures combining in-phase / quadrature-phase (I / Q) signals on a shared capacitor array, digital polarity architectures incorporating envelope and phase processing, and Doherty configurations utilizing carrier and peak amplifiers. These structures may typically incorporate protection circuitry and can be integrated with digital control circuitry implemented in a field-programmable gate array (FPGA) or dedicated silicon for enhanced functionality and control.

[0030] The devices and methods described herein may utilize or be related to wireless communication technologies. While some examples may relate to specific wireless communication technologies, the examples provided herein can be similarly applied to a variety of other wireless communication technologies (existing and undeveloped), especially where such wireless communication technologies share similar features disclosed with respect to the examples below. The various example wireless communication technologies that the devices and methods described herein may utilize include, but are not limited to: Global System for Mobile Communications (“GSM”) wireless communication technology, General Packet Radio Service (“GPRS”) wireless communication technology, GSM Evolution with Enhanced Data Rate (“EDGE”) wireless communication technology and / or 3GPP (“3GPP”) wireless communication technologies, such as Universal Mobile Telecommunications System (“UMTS”), Freedom of Multimedia Access (“FOMA”), 3GPP Long Term Evolution (“LTE”), 3GPP Advanced Long Term Evolution (“Advanced LTE”), Code Division Multiple Access 2000 (“CDMA2000”), Cellular Digital Packet Data (“CDPD”), Mobitex, and other third-generation wireless communication technologies. (3G), Circuit Switched Data (“CSD”), High-Speed ​​Circuit Switched Data (“HSCSD”), Universal Mobile Telecommunications System (“3G”) (“UMTS(3G)”), Wideband Code Division Multiple Access (Universal Mobile Telecommunications System) (“W-CDMA(UMTS)”), High-Speed ​​Packet Access (“HSPA”), High-Speed ​​Downlink Packet Access (“HSDPA”), High-Speed ​​Uplink Packet Access (“HSUPA”), High-Speed ​​Packet Access+ (“HSPA+”), Universal Mobile Telecommunications System-Time Division Duplex (“UMTS-TDD”), Time Division-Code Division Multiple Access (“TD-CDMA”), Time Division-Synchronous Code Division Multiple Access (“TD-CDMA”), 3G Partner Program Version 8 (quasi-4G) (“3GPP”) Release 8 (Pre-4G), 3GPP Release 9 (3rd Generation Partnership Project Version 9), 3GPP Release 10 (3rd Generation Partnership Project Version 10), 3GPP Release 11 (3rd Generation Partnership Project Version 11), 3GPP Release 12 (3rd Generation Partnership Project Version 12), 3GPP Release 13 (3rd Generation Partnership Project Version 13), 3GPP Release 14 (3rd Generation Partnership Project Version 14), 3GPP Release 15 (3rd Generation Partnership Project Version 15), 3GPP Release 16 (3rd Generation Partnership Project Version 16), 3GPP Release 17 (3rd Generation Partnership Project Version 17), 3GPP Release 1...18 (3rd Generation Partner Program Version 18), 3GPP 4G, 3GPP LTE Enhanced, Advanced LTE Pro, LTE Licensed Assisted Access (“LAA”), MuLTEfire, UMTS Terrestrial Radio Access (“UTRA”), Evolved UMTS Terrestrial Radio Access (“E-UTRA”), Advanced Long Term Evolution (4th Generation) (“Advanced LTE (4G)”), cdmaOne (“2G”), Code Division Multiple Access 2000 (3rd Generation) (“CDMA2000 (3G)”), Evolved Data Optimized or Evolved Data Only (“EV-DO”), Advanced Mobile Telephone Systems (1st Generation) (“AMPS (1G)”), Total Access Communication Protocol Scheme / Extended Access Communication Protocol Scheme (“TACS / ETACS”), Digital AMPS (2nd Generation) (“D-AMPS (2G)”), Push-to-Talk (“PTT”), Mobile Telephone System (“MTS”), Improved Mobile Telephone System (“IMTS”), Advanced Mobile Telephone System (“AMTS”), OLT (Norwegian: Finnish for Autoradiopuhelin (public land mobile phone), MTD (an abbreviation of Swedish Mobiltelefonisystem D or mobile phone system D), Public Automated Land Mobile System (“Autotel / PALM”), ARP (Finnish Autoradiopuhelin, “vehicle radiophone”), NMT (Nordic Mobile Telephone), NTT High Capacity Version (“Hicap”), Cellular Digital Packet Data (“CDPD”), Mobitex, DataTAC, Integrated Digital Enhanced Network (“iDEN”), Personal Digital Cellular (“PDC”), Circuit Switched Data (“CSD”), Personal Handheld Telephone System (“PHS”), Broadband Integrated Digital Enhanced Network (“WiDEN”), iBurst, Unlicensed Mobile Access (“UMA”, also known as 3GPP Universal Access Network or GAN standard), Zigbee, etc. The Wireless Gigabit Alliance (“WiGig”) standard, mmWave standards in general (wireless systems operating in the 10-300 GHz and above, such as WiGig, IEEE 802.11ad, IEEE 802.11ay, etc.), technologies operating in the 300 GHz and THz bands and above, vehicle-to-vehicle (“V2V”) and vehicle-to-the-world (“V2X”) and vehicle-to-infrastructure (“V2I”) and infrastructure-to-vehicle (“I2V”) communication technologies (based on 3GPP / LTE or IEEE 802.11p and others), 3GPP cellular V2X, DSRC (Dedicated Short Range Communication) communication schemes such as intelligent transmission systems, and other existing, developing or future wireless communication technologies.

[0031] The devices and methods described herein can utilize such wireless communication technologies according to various spectrum management schemes (including, but not limited to, dedicated licensed spectrum, unlicensed spectrum, (licensed) shared spectrum (such as licensed shared access in LSA = 2.3–2.4 GHz, 3.4–3.6 GHz, 3.6–3.8 GHz and other frequencies, and spectrum access systems in SAS = 3.55–3.7 GHz and other frequencies)) and can use various spectrum bands, including but not limited to IMT (International Mobile Telecommunications) spectrum (including 450–470 MHz, 69 The spectrum includes 0-960MHz, 1710-2025MHz, 2110-2200MHz, 2300–2400MHz, 2500–2690MHz, 698-790MHz, 610-790MHz, 3400-3600MHz, etc. (some of which may be restricted to specific regions (multiple) and / or countries), IMT Advanced Spectrum, and IMT-2020 Spectrum (expected to include 3600-3800MHz, 3.5GHz band, 600MHz band, and bands in the 24.25-86GHz range, etc.). The FCC's "Frontier Spectrum" 4G initiative includes available spectrum (including 27.5–28.35 GHz, 29.1–29.25 GHz, 31–31.3 GHz, 37–38.6 GHz, 38.6–40 GHz, 42–42.5 GHz, 47–64 GHz, 64–71 GHz, 61–76 GHz, 81–86 GHz, and 92–94 GHz, etc.), 4.9 GHz (typically 4.85–5.925 GHz) and 63–64 GHz ITS (Intelligent Transport System) bands, and bands such as WiGig. The bands currently allocated to WiGig, such as band 1 (57.24–59.40 GHz), WiGig band 2 (59.40–61.56 GHz), WiGig band 3 (61.56–63.72 GHz), and WiGig band 4 (63.72–65.88 GHz), the 60.2 GHz–71 GHz band, any band between 65.88 GHz and 61 GHz, bands currently allocated to automotive radar applications such as 66–81 GHz, and future bands including 94–300 GHz and above, are included. Furthermore, the devices and methods described herein can also be used, in a secondary manner, on wireless communication technologies such as TV white space bands (typically below 690 MHz), in which the 400 MHz and 600 MHz bands are potential candidates. In addition to cellular applications, specific applications in vertical markets can be addressed, such as PMSE (Programming for Special Events), medical, health, surgical, automotive, low-latency, and drone applications.Furthermore, the devices and methods described herein can also utilize wireless communication technologies with hierarchical applications, such as by introducing hierarchical usage priority ordering (e.g., low / medium / high priority, etc.) for different types of users based on priority access to the spectrum (e.g., where layer 1 users are given the highest priority, followed by layer 2, then layer 3, etc.). The devices and methods described herein can also utilize wireless communication technologies that leverage different single-carrier or OFDM variants (CP OFDM, SC FDMA, SC OFDM, filter bank-based multicarrier (FBMC), OFDMA, etc.), and, for example, 3GPP NR (New Radio), which may include allocating OFDM carrier data bit vectors to corresponding symbol resources.

[0032] The wireless communication technologies described herein can be categorized as either short-range wireless communication technologies or cellular wide-area wireless communication technologies. Short-range wireless communication technologies may include Bluetooth, WLAN (e.g., in accordance with any IEEE 802.11 standard), and other similar wireless communication technologies. Cellular wide-area wireless communication technologies may include Global System for Mobile Communications (“GSM”), Code Division Multiple Access 2000 (“CDMA2000”), Universal Mobile Telecommunications System (“UMTS”), Long Term Evolution (“LTE”), General Packet Radio Service (“GPRS”), Evolved Data Optimized (“EV-DO”), GSM Evolution with Enhanced Data Rate (“EDGE”), High Speed ​​Packet Access (HSPA; including High Speed ​​Downlink Packet Access (“HSDPA”), High Speed ​​Uplink Packet Access (“HSUPA”), HSDPA+ (“HSDPA+”), and HSUPA+ (“HSUPA+”)), Global Microwave Access Interoperability (“WiMax”) (e.g., in accordance with the IEEE 802.16 wireless communication standard, such as Fixed WiMax or Mobile WiMax), and other similar wireless communication technologies. Cellular wide-area wireless communication technology also includes "small cells" of this type of technology, such as microcells, femtocells, and picocells. Cellular wide-area wireless communication technology can generally be referred to as "cellular" communication technology in this document.

[0033] In the context of WLAN, the devices and methods described herein can be used in a variety of wireless devices, including access points (APs) and radio station devices (STAs), each of which may be equipped with RF communication capabilities. These devices may combine transmitting and receiving components designed to process RF signals within a specified bandwidth and channel, as described herein. The communication components typically include both hardware elements and software implementations for signal processing, enabling modulation and demodulation according to a specified communication protocol. These devices may be specifically configured to operate under various wireless communication standards, including those developed by the Institute of Electrical and Electronics Engineers (IEEE) for Wi-Fi applications. The RF components, in conjunction with an antenna system, enable communication across multiple frequency bands. These frequency bands may include the 2.4 GHz band supporting protocols such as IEEE 802.11b / g / n / ax, the 5 GHz band supporting IEEE 802.11n / ac / ax / be, and the 6 GHz band supporting newer standards such as IEEE 802.11ax / be, and so on. Additional operating frequencies can be extended to 60 GHz (supporting IEEE 802.11ad / ay) and 800 MHz (supporting IEEE 802.11ah), where the antenna system can operate at frequencies such as 28 GHz and 40 GHz. Beyond these specified standards, the device can support emerging Wi-Fi protocols and alternative wireless communication technologies. These alternatives may include, but are not limited to, Bluetooth technology, dedicated short-range communication systems, UHF applications (including IEEE 802.11af and IEEE 802.22), and white-band frequency utilization. The RF receive chain can typically incorporate necessary components such as low-noise amplifiers, signal amplification stages, analog-to-digital conversion systems, data buffering mechanisms, and digital baseband processing units, all configured to ensure effective wireless communication capabilities.

[0034] Figure 1 and Figure 2 Describe a general network and device architecture for wireless communication and / or sensing operations. Specifically, Figure 1An example wireless communication network 100 is illustrated according to some aspects, which may include terminal devices 102 and 104 and network access nodes 110 and 120 (e.g., wireless access nodes). The wireless communication network 100 can communicate with terminal devices 102 and 104 via a wireless access network through network access nodes 110 and 120. Each of terminal devices 102 and 104 or network access nodes 110 and 120 may be a sensing communication device capable of performing sensing operations as described herein. While some examples described herein may refer to a specific wireless access network context (e.g., 6G, 5G NR, LTE, UMTS, GSM, other 3GPP networks, WLAN / WiFi, Bluetooth, millimeter wave, etc.), these examples are exemplary and can therefore be readily applied to any other type or configuration of wireless access network. The number of network access nodes and terminal devices in the wireless communication network 100 is exemplary and scalable to any quantity.

[0035] In the example cellular context, network access nodes 110 and 120 can be base stations (e.g., eNodeB, NodeB, Base Transceiver Station (BTS), gNodeB, or any other type of base station), while terminal devices 102 and 104 can be cellular terminal devices (e.g., mobile station (MS), user equipment (UE), or any type of cellular terminal device). Network access nodes 110 and 120 can therefore (e.g., via a backhaul interface) interface with a cellular core network (such as an evolved packet core (EPC, for LTE), a core network (CN, for UMTS)) or other cellular core networks (which can also be considered part of the wireless communication network 100). The cellular core network can interface with one or more external data networks. In the example short-range context, network access nodes 110 and 120 can be access points (APs, such as WLAN or WiFi APs), while terminal devices 102 and 104 can be short-range terminal devices (e.g., stations (STAs)). Network access nodes 110 and 120 can (e.g., via internal or external routers) interface with one or more external data networks. Network access nodes 110 and 120 and terminal devices 102 and 104 may include one or more transmit / receive points (TRPs).

[0036] Network access nodes 110 and 120 (and optionally, Figure 1 Other network access nodes of the wireless communication network 100 (not explicitly shown in the text) can therefore provide information to terminal devices 102 and 104 (and optionally, Figure 1Other terminal devices in the wireless communication network 100 (not explicitly shown) are provided with a wireless access network. In the example cellular context, the wireless access network provided by network access nodes 110 and 120 enables terminal devices 102 and 104 to wirelessly access the core network via wireless communication. The core network can provide the exchange, routing, and transmission of traffic data related to terminal devices 102 and 104, and can also provide access to various internal data networks (e.g., control nodes, routing nodes that transmit information between other terminal devices on the wireless communication network 100, etc.) and external data networks (e.g., data networks that provide voice, text, multimedia (audio, video, images), and other Internet and application data). Furthermore, terminal devices 102 and 104, as well as network access nodes 110 and 120, can perform sensing operations, particularly radar sensing, according to the JCAS architecture. In the example short-range context, the wireless access network provided by network access nodes 110 and 120 can provide access to internal data networks (e.g., for transmitting data between terminal devices connected to wireless communication network 100) and external data networks (e.g., data networks providing voice, text, multimedia (audio, video, images) and other Internet and application data).

[0037] According to the various aspects described herein, network access nodes 110 and 120 and terminal devices 102 and 104 can perform their respective sensing operations in a manner that allows each device to perform its respective sensing operation according to its respective sensing signal configuration. Therefore, each of these devices can generate and transmit its respective sensing signal according to a corresponding configuration, which may include at least one of frequency resources for transmitting the sensing signal, bandwidth of the sensing signal, transmit power of the sensing signal, and waveform shape of the sensing signal, which the respective device may determine before generating and / or transmitting the sensing signal. In some examples, a central orchestrator (e.g., a sensing orchestrator) can determine the respective sensing signal configuration for each device and transmit information representing the respective sensing signal configuration to the respective device.

[0038] The radio access network and core network of wireless communication network 100 (if applicable, such as for cellular context) can be governed by communication protocols that may vary according to the details of wireless communication network 100. Such communication protocols can define the scheduling, formatting, and routing of both user traffic and control data traffic through wireless communication network 100, including the transmission and reception of such data through both the radio access network domain and the core network domain of wireless communication network 100. Therefore, terminal devices 102 and 104, as well as network access nodes 110 and 120, can follow the defined communication protocols to transmit and receive data through the radio access network domain of wireless communication network 100, while the core network can follow the defined communication protocols to route data both within and outside the core network. Example communication protocols include 6G, 5G NR, LTE, UMTS, GSM, WiMAX, Bluetooth, WiFi, mmWave, etc., any of which may be applicable to wireless communication network 100.

[0039] Figure 2 An example internal configuration of a communication device (e.g., a sensing communication device) according to various aspects described herein is shown. The communication device may include aspects of a wireless communication device (e.g., network access nodes 110, 120) or also aspects of a mobile wireless communication device (e.g., terminal devices 102, 104). Communication device 200 may include an antenna system 202, a radio frequency (RF) transceiver 204, a baseband modem 206 (including a digital signal processor 208 and a protocol controller 210), an application processor 212, and a memory 214. Although in Figure 2 Not explicitly shown, in some respects, the communication device 200 may include one or more additional hardware and / or software components, such as processors / microprocessors, controllers / microcontrollers, other dedicated or general-purpose hardware / processors / circuits, peripheral devices (multiple), memory, power supply, external device interfaces (multiple), user identity modules (multiple) (SIM), user input / output devices (multiple displays, multiple keypads, multiple touchscreens, multiple speakers, multiple external buttons, multiple cameras, multiple microphones, etc.) or other related components.

[0040] Communication device 200 can transmit and receive wireless signals on one or more wireless access networks. Baseband modem 206 can direct such communication functions of communication device 200 according to the communication protocol associated with each wireless access network, and can perform control over antenna system 202 and RF transceiver 204 to transmit and receive wireless signals according to formatting and scheduling parameters defined by each communication protocol. Although various practical designs may include separate communication components (e.g., separate antennas, RF transceivers, digital signal processors, and controllers) for each supported wireless communication technology, for the sake of simplicity, Figure 2 The configuration of the communication device 200 shown is only a single instance of such a component.

[0041] Communication device 200 can transmit and receive wireless signals using antenna system 202. Antenna system 202 can be a single antenna or can include one or more antenna arrays, each comprising multiple antenna elements. For example, antenna system 202 can include an antenna array located at the top of communication device 200 and a second antenna array located at the bottom of communication device 200. In some aspects, antenna system 202 may additionally include analog antenna combination and / or beamforming circuitry. In the receive (RX) path, RF transceiver 204 can receive analog radio frequency signals from antenna system 202 and perform analog and digital RF front-end processing on the analog radio frequency signals to generate digital baseband samples (e.g., in-phase / quadrature (IQ) samples) provided to baseband modem 206. RF transceiver 204 can include analog and digital receiving components, including amplifiers (e.g., low-noise amplifiers (LNAs)), filters, RF demodulators (e.g., RF IQ demodulators), and analog-to-digital converters (ADCs), which RF transceiver 204 can utilize to convert the received radio frequency signals into digital baseband samples.

[0042] In the transmit (TX) path, RF transceiver 204 can receive digital baseband samples from baseband modem 206 and perform analog and digital RF front-end processing on the digital baseband samples to generate an analog radio frequency signal for wireless transmission to antenna system 202. RF transceiver 204 may therefore include analog and digital transmission components, including amplifiers (e.g., power amplifiers (PA)), filters, RF modulators (e.g., RF IQ modulators), and digital-to-analog converters (DACs), which RF transceiver 204 can utilize to mix the digital baseband samples received from baseband modem 206 and generate the analog radio frequency signal for wireless transmission by antenna system 202. In some aspects, baseband modem 206 can control the wireless transmission and reception of RF transceiver 204, including specifying the transmit and receive radio frequencies for the operation of RF transceiver 204.

[0043] Based on the various aspects provided herein, the communication device 200 can perform sensing operations within the wireless communication network 100. For example, in addition to conventional communication processing, the baseband modem 206 (e.g., digital signal processor 208) can be configured to perform sensing-related signal processing. For instance, the baseband modem 206 can be configured to implement techniques such as radar waveform generation, matched filtering for target detection, parameter estimation (e.g., range, velocity, angle) of detected targets, and environmental mapping. In some examples, the baseband modem 206 (e.g., digital signal processor 208) can utilize its hardware accelerators and parallel processing capabilities to efficiently handle computationally intensive sensing algorithms during communication tasks.

[0044] Furthermore, the baseband modem 206 (e.g., protocol controller 210) can be configured to coordinate and / or manage the joint operation of communication and sensing functions. For example, the baseband modem 206 can schedule sensing and communication operations, allocate resources (e.g., time / frequency resources, antenna beams), and manage interference between them. The baseband modem (e.g., protocol controller 210) can also implement sensing control protocols and interfaces to coordinate with other network entities for the distributed sensing operations described herein.

[0045] In some examples, application processor 212 can be configured to act as both a source and destination for sensed data, similar to its role with communication data. Application processor 212 can execute sensing applications configured to process and interpret sensed data received from baseband modem 206. For example, application processor 212 can use the sensed data to perform at least one object detection and tracking, environment mapping, and / or situational awareness service. In some examples, application processor 212 can interface with external sensors (e.g., cameras, LiDAR) to fuse data from multiple sensing modalities to enhance sensing capabilities.

[0046] Accordingly, in addition to transmitting and receiving communication signals, RF transceiver 204 can also support the transmission and reception of sensed waveforms. For example, RF transceiver 204 can generate and transmit sensed signals (e.g., frequency-modulated continuous waveforms for radar) and can process received sensed signals to extract target information. In some examples, RF transceiver 204 can use the same analog and digital components (e.g., amplifiers, filters, modulators / demodulators, ADCs / DACs) for both sensing and communication operations, and may also have additional hardware accelerators for sensing-specific tasks. For example, antenna system 202 can also support both communication and sensing functions, and in some examples, it has a separate antenna array or a shared array with beamforming capabilities. Depending on various aspects, and depending on sensing requirements and resource constraints, antenna system 202 can form a narrow beam for extending sensing range or a wide beam for faster coverage. Techniques such as MIMO and beamforming can be employed to enhance sensing performance and achieve features such as high-resolution target parameter estimation and interference mitigation.

[0047] like Figure 2As shown, the baseband modem 206 may include a digital signal processor 208, which can perform physical layer (PHY, Layer 1) transmit and receive processing to: prepare outgoing transmit data provided by the protocol controller 210 for transmission via the RF transceiver 204 in the transmit path, and prepare incoming receive data provided by the RF transceiver 204 for processing by the protocol controller 210 in the receive path. The digital signal processor 208 may be configured to perform one or more of the following: error detection, forward error correction coding / decoding, channel coding and interleaving, channel modulation / demodulation, physical channel mapping, radio measurement and search, frequency and time synchronization, antenna diversity processing, power control and weighting, rate matching / dematching, retransmission processing, interference cancellation, and any other physical layer processing functions. Digital signal processor 208 may be implemented structurally as a hardware component (e.g., implemented as one or more digitally configured hardware circuits or field-programmable gate arrays (FPGAs)), as a software-defined component (e.g., one or more processors configured to execute program code defining arithmetic, control, and I / O instructions (e.g., software and / or firmware) stored in a non-transitory computer-readable storage medium), or as a combination of hardware and software components. In some aspects, digital signal processor 208 may include one or more processors configured to invoke and execute program code defining control and processing logic for physical layer processing operations. In some aspects, digital signal processor 208 may utilize software execution processing functions via the execution of executable instructions. In some aspects, digital signal processor 208 may include one or more dedicated hardware circuits (e.g., application-specific integrated circuits (ASICs), field-programmable gate arrays, and other hardware) digitally configured for specific execution processing functions, wherein one or more processors of digital signal processor 208 may offload certain processing tasks to these dedicated hardware circuits (referred to as hardware accelerators). Example hardware accelerators may include Fast Fourier Transform (FFT) circuitry and encoder / decoder circuitry. In some respects, the processor and hardware accelerator components of the digital signal processor 208 may be implemented as coupled integrated circuits.

[0048] The communication device 200 can be configured to operate according to one or more wireless communication technologies. The digital signal processor 208 can handle the lower-layer processing functions of the wireless communication technology (e.g., layer 1 / PHY), while the protocol controller 210 can handle the upper-layer protocol stack functions (e.g., data link layer / layer 2 and / or network layer / layer 3). The protocol controller 210 can therefore be responsible for controlling the wireless communication components of the communication device 200 (antenna system 202, RF transceiver 204, and digital signal processor 208) according to the communication protocol of each supported wireless communication technology, and can accordingly represent the access layer (AS) and non-access layer (NAS) of each supported wireless communication technology (also including layers 2 and 3). The protocol controller 210 can be structurally implemented as a protocol processor configured to execute protocol stack software (retrieved from controller memory) and subsequently control the wireless communication components of the communication device 200 to transmit and receive communication signals according to the corresponding protocol stack control logic defined in the protocol software. Protocol controller 210 may include one or more processors configured to invoke and execute program code defining upper-layer protocol stack logic for one or more wireless communication technologies, which may include data link layer / layer 2 functions and network layer / layer 3 functions. Protocol controller 210 may be configured to perform both user plane functions and control plane functions according to the specific protocol of the supported wireless communication technology to facilitate the transmission of application layer data to and from wireless communication device 200. User plane functions may include header compression and encapsulation, security, error checking and correction, channel multiplexing, scheduling and prioritization, while control plane functions may include the establishment and maintenance of radio bearers. The program code invoked and executed by protocol controller 210 may include executable instructions defining the logic of such functions.

[0049] The communication device 200 may further include an application processor 212 and a memory 214. The application processor 212 may be a CPU and may be configured to process layers above the protocol stack, including the transport layer and the application layer. The application processor 212 may be configured to execute various applications and / or programs of the communication device 200 at the application layer of the communication device 200, such as an operating system (OS), a user interface (UI) supporting user interaction with the communication device 200, and / or various user applications. The application processor may interface with the baseband modem 206 and act as both a source (in the transmission path) and a destination (in the reception path) for user data, such as voice data, audio / video / image data, message transmission and reception data, application data, basic Internet / web access data, etc. In the transmission path, the protocol controller 210 may therefore receive and process the outgoing data provided by the application processor 212 according to the layer-specific functions of the protocol stack, and provide the resulting data to the digital signal processor 208. Digital signal processor 208 can then perform physical layer processing on the received data to generate a digital baseband sample, which it can then provide to RF transceiver 204. RF transceiver 204 can then process the digital baseband sample to convert it into an analog RF signal, which it can then wirelessly transmit via antenna system 202. In the receiving path, RF transceiver 204 can receive and process the analog RF signal from antenna system 202 to obtain a digital baseband sample. RF transceiver 204 can provide the digital baseband sample to digital signal processor 208, which can then perform physical layer processing on the digital baseband sample. Digital signal processor 208 can then provide the resulting data to protocol controller 210, which can process the resulting data according to layer-specific functions of the protocol stack and provide the resulting incoming data to application processor 212. Application processor 212 can then process the incoming data at the application layer, which may include using the data to execute one or more applications and / or presenting the data to a user via a user interface.

[0050] Memory 214 can implement a memory component of communication device 200, such as a hard disk drive or another similar permanent storage device. Although Figure 2 Not clearly depicted in the text. Figure 2 Each of the various other components of the communication device 200 shown may additionally include integrated permanent and non-permanent memory components, such as those for storing software program code, buffered data, etc.

[0051] According to some wireless communication networks, terminal devices 102 and 104 can perform mobility procedures to connect to, disconnect from, and switch between available network access nodes of the wireless access network of wireless communication network 100. Since each network access node of wireless communication network 100 may have a specific coverage area, terminal devices 102 and 104 can be configured to select and reselect available network access nodes to maintain a strong wireless access connection with the wireless access network of wireless communication network 100. For example, terminal device 102 can establish a wireless access connection with network access node 110, while terminal device 104 can establish a wireless access connection with network access node 112.

[0052] In the event of a degraded wireless access connection, terminal device 102 or 104 can seek a new wireless access connection with another network access node of the wireless communication network 100. For example, terminal device 104 can move from the coverage area of ​​network access node 112 to the coverage area of ​​network access node 110. Therefore, the wireless access connection with network access node 112 may have degraded, and terminal device 104 can detect this via wireless measurements such as signal strength or signal quality measurements of network access node 112.

[0053] According to a movement process defined in a suitable network protocol for the wireless communication network 100, such as performing wireless measurements on nearby network access nodes to determine whether any nearby network access node can provide a suitable wireless access connection, the terminal device 104 can seek a new wireless access connection (which may be triggered, for example, by the terminal device 104 or by the wireless access network). Since the terminal device 104 may have moved into the coverage area of ​​the network access node 110, the terminal device 104 can identify the network access node 110 (which may be selected by the terminal device 104 or by the wireless access network) and transition to a new wireless access connection with the network access node 110. Such movement processes, including wireless measurements, cell selection / reselection, and handover, are established in various network protocols and can be adopted by the terminal device and the wireless access network to maintain a strong wireless access connection between each terminal device and the wireless access network in any number of different wireless access network scenarios.

[0054] Figure 3Example illustrations of various communication elements for a device used in a wireless communication apparatus (e.g., communication apparatus 200). Apparatus 300 may include processing circuitry 310 (e.g., baseband modem 206, application processor 212) that can bootstrap and manage the communication operation of apparatus 300 according to one or more wireless communication protocols, and can control the transmission / reception of communication signals through at least one or more antennas 322a-b via one or more RF transceivers 320a-b. Processing circuitry 310 may include interfaces to RF transceivers 320a-b. In this example, two RF transceivers are shown, namely a first RF transceiver 320a and a second RF transceiver 320b, but apparatus 300 may include more than two RF transceivers. In the example, each RF transceiver depicted herein may be implemented using a corresponding integrated circuit (i.e., a transceiver integrated circuit). Depending on the aspects described herein, apparatus 300 may include the communication circuitry described herein, which may include RF transceivers 320a-b.

[0055] Each RF transceiver 320a-b may include at least one RF chain to process communication signals associated with antennas 322a-b respectively. Device 300 may include a first antenna and a second antenna 322a-b, or device 300 may include antenna interfaces that can be coupled to these antennas 322a-b. It should be noted that device 300 is depicted as being coupled to antennas 322a-b, but device 300 may be coupled to more than two antennas, and therefore each RF transceiver 320a-b may include multiple RF chains, each RF chain capable of processing communication signals from a corresponding antenna. Device 300 can transmit and receive wireless communication signals using antennas 322a-b. Device 300 can act as an RF transmitter (e.g., an RF transmitting circuit) to transmit wireless communication signals, and it can also act as an RF receiver (e.g., an RF receiving circuit) to receive wireless communication signals.

[0056] Processing circuitry 310 may include circuitry and / or logic, or may be partially or entirely implemented by circuitry and / or logic. For example, a processor may include circuitry and / or logic, memory circuitry, and / or logic that may be configured to manage wireless communication operations. Processing circuitry 310 may be configured to communicate with an external main processor (e.g., a host processor, central processing unit, system-on-a-chip) of the wireless communication device including device 300 via a designated interface coupled to a main processor. In some examples, processing circuitry 310 may be the main processor of the wireless communication device. Processing circuitry 310 may also access the main memory of the corresponding wireless communication device via a designated interface. Processing circuitry 310 may also include an interface to RF transceivers 320a-b.

[0057] Processing circuitry 310 may include a digital signal processor (e.g., digital signal processor 208). Digital signal processor 208 may be configured to perform one or more of the following: error detection, forward error correction coding / decoding, channel coding and interleaving, channel modulation / demodulation, physical channel mapping, radio measurement and search, frequency and time synchronization, antenna diversity processing, power control and weighting, rate matching / dematching, retransmission processing, interference cancellation, and any other physical layer processing functions.

[0058] Processing circuitry 310 may include a modem configured to process baseband signals received from / transmitted to antennas 322a-b via corresponding communication paths 325a-b including corresponding RF chains. In various examples, the interface of processing circuitry 310 to RF transceivers 320a-b may be configured to couple processing circuitry 310 to communication paths 325a-b. Therefore, processing circuitry 310 may include media access control (MAC) circuitry and / or logic, physical layer (PHY) circuitry and / or logic, baseband (BB) circuitry and / or logic, baseband processor, baseband memory, application processor circuitry and / or logic, application processor, application processor memory, and / or any other circuitry and / or logic. As an example, processing circuitry 310 may perform baseband processing on digital baseband signals to recover data included in wireless data transmission.

[0059] Processing circuitry 310 can control and / or arbitrate the transmit and / or receive functions of device 300, and perform one or more baseband processing functions (e.g., MAC, encoding / decoding, modulation / demodulation, data symbol mapping, error correction, etc.). Processing circuitry 310 can be configured to provide control functions to RF transceivers 320a-b (e.g., to the RF chain) to control and / or arbitrate the transmission and / or reception of wireless communication signals. In some aspects, the functionality of processing circuitry 310 can be implemented in software and / or firmware executing on one or more suitable programmable processors, and can be implemented, for example, in field-programmable gate arrays, application-specific integrated circuits, etc. In various examples, the interface of processing circuitry 310 to RF transceivers 320a-b can be configured to couple the processing circuitry to the RF transceivers 320a-b to provide communication between them.

[0060] Each RF transceiver 320a-b can provide RF processing of communication signals transmitted via corresponding communication paths 325a-b within a corresponding RF chain, based on signals (e.g., baseband communication signals, digital signals) received from processing circuitry 310 via a communication path, to transmit wireless communication signals via a corresponding antenna. Each RF transceiver 320a-b can provide RF processing of communication signals transmitted via corresponding communication paths 325a-b that receive wireless communication signals via corresponding antennas 322a-b, and provide signals to processing circuitry 310 via corresponding communication paths 325a-b. Processing circuitry 310 can be configured to control the operation of RF transceivers 320a-b. Each RF transceiver 320a-b may include a receive path to provide RF processing for receiving wireless communication signals received from corresponding antennas 322a-b, and may include a transmit path to provide RF processing for transmitting wireless communication signals transmitted via corresponding antennas 322a-b.

[0061] In the receive (RX) path, each RF transceiver 320a-b can receive analog radio frequency signals from a corresponding antenna 322a-b via a corresponding communication path 325a-b, and perform analog and digital RF front-end processing on the analog radio frequency signals to generate digital baseband samples (e.g., in-phase / quadrature (IQ) samples) to be provided to the processing circuitry 310. In various examples, each RF transceiver 320a-b may include two RF chains for each antenna element, and each RF chain can be specified for a particular polarization. Each RF transceiver 320a-b may include analog and digital receiving components, including amplifiers (e.g., low-noise amplifiers (LNAs)), filters, RF demodulators (e.g., RF IQ demodulators), and analog-to-digital converters, which the RF transceiver 320 can utilize to convert the received radio frequency signals into digital baseband samples.

[0062] In the transmit (TX) path, each RF transceiver 320a-b may receive digital baseband samples from processing circuitry 310 and perform analog and digital RF front-end processing on the digital baseband samples to generate analog radio frequency signals to be provided to corresponding antennas 322a-b via corresponding communication paths 325a-b for wireless transmission. Each RF transceiver 320a-b may therefore include analog and digital transmission components, including amplifiers (e.g., power amplifiers), filters, RF modulators (e.g., RF IQ modulators), and digital-to-analog converters. The RF transceiver 320 may utilize these analog and digital transmission components to mix the digital baseband samples received from processing circuitry 310 and generate corresponding analog radio frequency signals to be wirelessly transmitted by the corresponding antennas 322a-b. In some aspects, processing circuitry 310 may control the wireless transmission and reception of RF transceivers 320a-b, including specifying transmit and receive radio frequencies for the operation of each RF transceiver 320a-b. In some examples, at least one amplifier may be included in the amplifier circuitry provided herein.

[0063] Figure 4 This diagram illustrates an example of the transmit path of an RF transceiver. The RF transceiver is referred to herein as RF transceiver 320, and may be based on... Figure 3 The first RF transceiver 320a or the second RF transceiver 320b is described. The RF transceiver 320, whose transmission path is shown in the figure, may be configured for a digital polarity transmitter. The RF transceiver 320 can be coupled to processing circuitry (e.g., processing circuitry 310, modem) via an interface. The interface may include a communication path specifying a communication signal 410 to be carried between the processing circuitry and the antenna. In some examples, the interface may include additional circuitry paths to provide communication between the RF transceiver 320 and the processing circuitry for operational control. The RF transceiver 320 may also include additional components and / or circuitry not depicted herein, such as additional filtering circuitry, synthesizer circuitry, etc. The RF transceiver 320 may include various circuitry and components deployed on the respective transmission paths.

[0064] RF transceiver 320 may include various circuits and components deployed to process and transmit communication signals on two frequency bands. These components may include a digital front end (DFE) 420, digital time converters (DTC) 430a and 430b, digital power amplifiers (DPA) 440a and 440b, a combiner 450, and a duplexer 460.

[0065] Digital front-end 420 can receive communication signal 410 via an interface to which processing circuitry is coupled. Digital front-end 420 may include digital front-end processing circuitry and additional components. Digital front-end 420 can be configured to convert communication signal 410 (e.g., in-phase / quadrature signal) into polarized signals, which include: amplitude modulation (AM) signals (e.g., amplitude control codes), which may herein be referred to as amplitude modulation command or amplitude control information (sometimes bit) signals; and phase modulation (PM) signals (e.g., phase control codes), which may herein be referred to as phase modulation command signals or phase control information (sometimes bit) signals. The generated AM and PM signals can be provided to corresponding transmit chains for further processing.

[0066] For example, in the first transmit signal path, the RF transceiver 320 may include a first digital time converter 430a. The first digital time converter 430a may be coupled to the digital front end 420. The first digital time converter 430a may receive a corresponding phase modulation signal. The first digital time converter 430a may be further coupled to a local oscillator (LO) 435. The first digital time converter 430a may adjust polarity modulation parameters (e.g., the phase of the oscillator signal) based on the phase modulation signal provided by the digital front end 420 to generate a first modulated local oscillator signal. The first digital time converter 430a may output a first modulated local oscillator (MOLO) signal. In the first transmit signal path, the RF transceiver 320 may additionally include a first digital power amplifier 440a. The first digital power amplifier 440a may receive an amplitude modulation signal that sets the desired power of its output. The first digital power amplifier 440a may additionally receive the modulated local oscillator signal and provide a first output RF signal based on the received modulated local oscillator signal and the amplitude modulation signal. The first digital power amplifier 440a may include dynamic power control or an RF capacitor digital-to-analog converter (RF-CDAC).

[0067] In the second transmit signal path, the RF transceiver 320 may include a second digital time converter 430b. The second digital time converter 430b may be coupled to the digital front end 420. The second digital time converter 430b may receive a corresponding phase modulation signal. The second digital time converter 430b may be further coupled to a local oscillator 435. The second digital time converter 430b may adjust polarity modulation parameters (e.g., the phase of the oscillator signal) based on the phase modulation signal provided by the digital front end 420 to generate a second modulated local oscillator signal. The second digital time converter 430a may output the second modulated local oscillator signal. In the second transmit signal path, the RF transceiver 320 may additionally include a second digital power amplifier 440b. The second digital power amplifier 440b may receive an amplitude modulation signal that sets the desired power of its output. The second digital power amplifier 440b may additionally receive the second modulated local oscillator signal in a second frequency band and provide a second output RF signal based on the received second modulated local oscillator signal and the amplitude modulation signal. The second digital power amplifier 440b may include dynamic power control or an RF capacitor digital-to-analog converter.

[0068] Local oscillator 435 may include various components to generate one or more stable and continuous signals of a specified frequency and may be used as a reference for frequency conversion, mixing, and other signal processing tasks. In this example, local oscillator 435 may include an oscillator core. The oscillator core can generate signals of a specified frequency. The oscillator core may include one or more voltage-controlled oscillators, which may include adjustable oscillators whose frequency can be adjusted by changing a control voltage. The oscillator core may include a crystal oscillator that relies on the mechanical resonance of a quartz crystal. The oscillator core may include a dielectric resonator oscillator (DRO).

[0069] In some examples, the local oscillator 435 may include a resonator to determine or stabilize the oscillation frequency. The resonator may include a quartz crystal in a crystal oscillator, an LC circuit, or a dielectric resonator in a voltage-controlled oscillator. In some examples, the local oscillator 435 may also include a phase-locked loop (PLL) to synchronize the output of the local oscillator 435 with a reference signal to promote high accuracy and stability with low phase noise. For example, the PLL may include a reference oscillator, a phase detector, a low-pass filter, and a voltage-controlled oscillator or an adjustable oscillator. The local oscillator 435 may additionally include frequency control circuitry configured to adjust the output frequency of the local oscillator 435 by various methods such as manual tuning (e.g., potentiometer), automatic frequency control (AFC), or digital control by means of a microcontroller, or a DSP (e.g., by means of a digital front-end 420). According to the various aspects described herein, the local oscillator 435 may operate using a resonator shared with another RF transceiver. For example, return to reference. Figure 4 In the example where RF transceiver 320 is the first RF transceiver 320a, the second RF transceiver 320b can also be the same as or similar to RF transceiver 320. The common resonator can be shared by the local oscillator of these RF transceivers (e.g., local oscillator 435).

[0070] RF transceiver 320 may also include a combiner 450 to combine the RF signals provided by digital power amplifiers 440a-b. Combiner 450 can be configured to combine RF signals from a first transmit signal path and a second transmit signal path. Specifically, combiner 450 can couple RF signals received through a first terminal (e.g., input) of combiner 450, output by digital power amplifiers 440a and 440b, to a second terminal (e.g., output) of combiner 450, thereby coupling to additional components of RF transceiver 320, which are coupled to the second terminal of the combiner. Combiner 450 (e.g., a converter) can facilitate appropriate impedance matching between the two frequency bands to optimize power delivery and minimize signal reflections.

[0071] Figure 5A block diagram of a communication circuit according to the aspects described herein is shown. The communication circuit may be an RF transceiver (e.g., RF transceiver 320). It may include a phase-locked loop (DPLL) 535 (e.g., LO 435), a digital time converter (DTC) 530 (e.g., DTC 430a), a digital signal processor (DSP) 521, and a digital power amplifier 440 (e.g., digital power amplifier 440a) depicted as a switched-capacitor digital power amplifier circuit (SC-DPA), which are combined into a single transmit path. In such a configuration, the PLL 535 can provide a reference clock or timing signal that can serve as a frequency or phase reference for the digital time converter 530. Typically, in response to phase information derived from the digital signal processor 521, the digital time converter 530 can then use this reference to adjust the phase or timing characteristics of one or more signals it generates. The digital signal processor 521 can receive digital data, possibly in in-phase (I) and quadrature (Q) format, from a modem, and it can be configured to generate amplitude control information indicated as K bits and phase control information indicated as N bits. These bits can be used to define the amplitude of the output signal or to define a specific timing requirement that the digital time converter 530 can achieve. In the example, a signal of a specific frequency or phase is provided to the digital power amplifier 440 for amplification and then fed to an output coupling device (such as a transformer or balun) to drive an antenna.

[0072] Digital signal processor 521 can be configured to process I / Q data from a modem and generate amplitude and phase control information for transmission. In the example, digital signal processor 521 can be included in a digital front end (e.g., DFE 420). In the example, digital signal processor 521 can transform the I / Q data into polar coordinates, generate a phase-modulated component used by digital time converter 530, and an amplitude-modulated component sent to digital power amplifier 440 in digital bits. Digital time converter 530 can receive phase-modulation information (such as N bits) together with a reference clock from phase-locked loop 535. Phase-locked loop 535 can be a digitally controlled phase-locked loop that is locked to a stable frequency reference and generates an output clock at the desired frequency. Digital time converter 530 can then adjust the timing or phase of this clock to generate a phase-adjusted signal used by digital power amplifier 440 or by additional components in the transmission path. Although only one digital time converter 530 is labeled in this figure, there may be scenarios where multiple digital time converters are deployed in parallel or series for multiple modulation formats or for multi-band operation.

[0073] Digital power amplifier 440 may include multiple digital power amplifier arrays 441, 442. Each array may include multiple digital power amplifier units. For example, digital power amplifier array 441 may include a first plurality of digital power amplifier units (including digital power amplifier unit 445a), and digital power amplifier array 442 may include a second plurality of digital power amplifier units (including digital power amplifier unit 446a). The first array 441 may be located near the top of the digital power amplifier block 440, and the second array 442 may be located below it, but the arrangement of these arrays may vary depending on the design. In some embodiments, digital power amplifier 440 may include more than two arrays, each containing a different number of units based on performance or power requirements. In some examples, the arrays may be logically or physically partitioned, for example, to handle different ranges of output power, different transmission frequency bands, or to provide redundancy to enhance reliability.

[0074] Figure 6 Show Figure 5 The illustration shows a digital power amplifier unit (e.g., digital power amplifier unit 445a). Digital power amplifier unit 445a may include several sub-blocks, including selection logic 601, level shifter 602, and driver 603. Selection logic 601 may be configured to determine when a particular unit is enabled or disabled based on amplitude control bits received from digital signal processor 521 or from other control logic described herein. In some implementations, selection logic 601 may interpret certain received bits that indicate whether the amplifier unit should be activated in a given modulation state. Selection logic 601 may be implemented using logic gates, multiplexers, or small control finite state machines, although other techniques such as lookup tables in memory or configuration registers storing the states of a particular transmit power level may also be employed.

[0075] When selection logic 601 indicates that the amplifier unit should be enabled, selection logic 601 can transmit a control signal to level shifter 602. Level shifter 602 may be necessary when there is a voltage difference between the logic domain in which selection logic 601 operates and the drive domain in which high-power amplifier operation occurs. In some scenarios, the logic domain may be at a lower supply voltage, such as VDDL, while the amplifier drive domain may be at a higher supply voltage, such as VDDH. By appropriately shifting the voltage level, level shifter 602 can ensure that the drive signal has sufficient amplitude to effectively activate or deactivate driver 603. Level shifter 602 may include transistors configured in designs that boost or reduce input signals to appropriate voltage levels to ensure reliable switching without damaging the transistors. Depending on the semiconductor process and voltage range used, alternatives may include stacked MOS transistors or charge pump arrangements.

[0076] Driver 603 may include one or more stages of transistors configured to amplify or buffer signals, typically driving the output node coupled to one or more capacitors. The capacitors may be part of a switched-capacitor network forming a power delivery path to a load. In some designs, these capacitors may be arranged in parallel segments, each segment being engaged or disengaged by driver 603 depending on whether an amplifier unit is enabled. Driver 603 can thus contribute a certain amount of charge with each switching, effectively shaping the output RF waveform. The capacitors immediately adjacent to driver 603 shown in the figure may represent a load or portion of the overall switched network determining the power delivered to the antenna. In some implementations, these capacitors may be physically located at the output of driver 603, forming part of a switched-capacitor digital-to-analog converter (DAC) arrangement that converts digital signals to analog waveforms for radio frequency. By varying the number of activated units and thus the effective capacitance contributing to the output signal, this switched-capacitor DAC approach allows for precise control of the output power.

[0077] Digital power amplifier 440 can therefore be operated by receiving amplitude control bits (indicated as K bits) from digital signal processor 521. These bits can indicate how many or which specific units among digital power amplifier units 445a, 446a, etc., should be enabled at any given time. According to the various aspects described herein, especially when the desired transmit power is below the amplifier's maximum value, by distributing these enabled units, digital power amplifier 440 can dissipate the thermal load and reduce localized heating. Controller 541 can facilitate this distribution. For example, a processor (e.g., processor 310) or digital front end (e.g., DFE 420) may include controller 541. Digital power amplifier 440 can also incorporate timing or phase adjustments provided by digital time converter 530 to process individual phases of the signal. In the case of using two arrays 441 and 442, controller 541 can decide to enable a portion of the first array and a portion of the second array to distribute the thermal load and control the overall output amplitude.

[0078] In one embodiment, arrays 441 and 442 may each have a nominal capacity to provide a portion of the total output power, such that operating them together can produce a higher maximum output power. Controller 541 can selectively enable only array 441 at lower power levels, then gradually enable units in array 442 as power demand increases. Alternatively, for efficient thermal balancing, controller 541 can toggle units from both arrays by keeping the hottest units inactive while cooling units become active, thereby extending the overall lifespan of the amplifier. Digital power amplifier 440 may also incorporate an internal thermal sensor or sensing line that can interface with digital signal processor 521, or a separate management system that notifies controller 541 of temperature distribution maps.

[0079] In this example, depending on the implementation details, the digital signal processor 521, digital time converter 530, and phase-locked loop 535 can reside on the same integrated circuit or on different dies. The digital signal processor 521 can, for example, be located within a baseband processor or a separate transceiver chip, while the digital time converter 530 can be positioned close to the digital power amplifier 440 to minimize jitter or wiring complexity. The phase-locked loop 535 can be integrated with other clock generation circuitry or can be a separate module. Various supply voltages can be introduced, such as VDDL for lower voltage logic domains and VDDH for the drive domain of the digital power amplifier 440, ensuring that each stage operates optimally according to its power requirements. Depending on the overall power management strategy, intermediate or additional tracks may also exist.

[0080] In some implementations, the digital signal processor 521 may include a polarity modulator that decomposes the baseband data into amplitude and phase components. This polarity approach is particularly well-suited for digital power amplifier designs because phase modulation can be performed by adjusting the clock edge or timing in the digital time converter 530, while amplitude modulation can be achieved by enabling or disabling units within the digital power amplifier 440. This separation of amplitude and phase can result in efficient transmitter architectures for various communication standards such as 5G NR, Wi-Fi, or Bluetooth, but this does not mean being limited to these specific protocols. The architecture can also support legacy systems, multi-band operation, or dynamic spectrum management.

[0081] In digital power amplifier unit 445a, selection logic 601 can receive one or more control bits from a higher-level management block within digital power amplifier 440. This block can interpret combinations of amplitude control bits, thermal management bits, or other signals. The output of selection logic 601 can be fed to level shifter 602, which boosts or reduces the voltage to the appropriate level for driver 603. Driver 603 can then actively drive a capacitor load. In some variations, driver 603 can be a CMOS inverter stage, sized to deliver the appropriate current for a predetermined RF operation. Depending on the fabrication technology, one or more capacitors or capacitors attached to the driver output can be physically implemented as metal-oxide-semiconductor (MOM) capacitors, metal-insulator-metal (MIM) capacitors, or even transistor-based capacitors. This arrangement can be repeated for each unit, and each unit can have slightly different transistors sized such that each contributes a fraction of the total possible power. This fractional contribution can be calibrated or tuned during manufacturing testing to ensure uniform amplitude steps when more units are enabled.

[0082] Figure 5 The design shown is an example of how a digital signal processor 521, a digital time converter 530, and a phase-locked loop 535 can be integrated with a digital power amplifier 440 to form a complete transmit chain. It should be recognized that the number of digital power amplifier arrays 441, 442 and the number of units (e.g., 445a, 446a, etc.) in each array can vary depending on the desired peak output power, target bandwidth, and manufacturing constraints. The digital power amplifier 440 can receive at least two supply voltages, designated VDDL and VDDH. VDDL can be dedicated to the lower voltage domain, such as logic within the digital signal processor 521, the digital time converter 530, or internal gating logic within the digital power amplifier. VDDH can be a higher supply voltage powering the final drive stage of the digital power amplifier unit.

[0083] Digital power amplifier arrays 441 and 442 can be arranged such that each array can provide an incremental portion of the total power indicated by amplitude control information. By combining multiple arrays, the circuitry can be adjusted from a low-power mode to a high-power mode, potentially corresponding to different coverage scenarios in wireless standards. For example, in a mobile device scenario, the system might primarily operate in a low-power mode to conserve battery life, thus activating only a small portion of the units of digital power amplifier 440 at any given time. On the other hand, in a base station scenario, all arrays can be combined simultaneously to achieve higher power coverage.

[0084] The digital time converter 530 can incorporate a phase interpolator or digitally controlled delay line that modulates the phase of a clock signal derived from the phase-locked loop 535. By providing the adjusted phase signal to the digital power amplifier 440, the overall transmitter can achieve phase modulation in the RF domain, while amplitude modulation is handled digitally by switching power amplifier units on or off. The digital time converter 530 can also process fractional phase increments to enable fractional-N synthesis or advanced modulation schemes. The data path (labeled N bits) from the digital signal processor 521 to the digital time converter 530 can define the resolution or precision of the phase step, for example, supporting a specific number of bits for phase control. Simultaneously, the path (labeled K bits) from the digital signal processor 521 to the digital power amplifier 440 can define the amplitude resolution, indicating how many or which units to enable. In some scenarios, the system can incorporate jitter or dynamic bit weighting to improve spectral purity or reduce spurious output.

[0085] In some examples, driver 603 may include a Class D, Class E, or Class F topology, where capacitors at the output can be selected or deselected to shape the RF waveform. This figure only shows a general representation of the capacitors; however, in practice, multiple parallel capacitor segments can exist, each corresponding to a bit of amplitude control. For example, 5-bit amplitude control could correspond to 32 capacitor segments, each toggled in or out by its corresponding digital power amplifier unit. The combination of selection logic 601 and level shifter 602 thus ensures that each segment is activated only when necessary, mitigating unintended current leakage and heat generation.

[0086] In summary, the communication circuitry can correspond to a digital transmitter architecture that integrates a phase-locked loop 535, a digital time converter 530, and a digital signal processor 521 to generate digital signals, which are then amplified by a switched-capacitor digital power amplifier block 440. The digital power amplifier 440 may include multiple digital power amplifier arrays 441 and 442, each array including multiple digital power amplifier units such as 445a and 446a, wherein each unit includes selection logic 601, a level shifter 602, and a driver 603 for driving capacitors to produce a final RF output. Figure 6 A more detailed view of a single representative digital power amplifier unit can be shown, illustrating how selection logic 601 can receive control bits to enable or disable the amplifier unit, how level shifter 602 can convert the signal to the appropriate voltage domain, and how driver 603 can dock with capacitors that contribute to the RF output signal.

[0087] In the example, a digital power amplifier 440 comprising multiple amplifier units 445a, 446a can provide an output signal based on amplitude control information as described herein, wherein each amplifier unit 445a, 446a can be switched to contribute to the output signal. The communication circuitry may include control circuitry (e.g., controller 541) configured to enable a subset of the multiple amplifier units 445a, 446a according to an activation sequence.

[0088] When controller 541 enables a subset, the subset may include enabled amplifier units arranged in a non-adjacent manner, wherein at least one inactive amplifier unit among a plurality of amplifier units is placed between adjacent enabled amplifier units. An inactive amplifier unit may refer to a digital power amplifier unit that is not activated to contribute to the output signal of digital power amplifier 440 for a given amplitude control information. For example, each amplifier unit 445a, 446a in digital power amplifier 440 may be configured to operate according to amplitude control information reflecting a desired power level or output magnitude, such that the communication circuitry utilizes a plurality of identical or nearly identical amplifier units distributed in a physical layout. Each unit may include other components such as selection logic and driver arrangement that cause the amplifier unit to switch to conduction or to switch out of conduction. For example, controller 541 may arrange a subset of enabled amplifier units in such a manner that no two adjacent units are simultaneously enabled. Because of this, the communication circuitry can guarantee that at least one inactive unit is distributed between any two enabled units, creating a non-adjacent mode. This addresses the problem of localized overheating by activating the unit distribution over the available die area.

[0089] To achieve this distribution, in the example, controller 541 may maintain an internal mapping between each amplifier unit and amplitude control information. It can interpret the amplitude control bits to determine how many units should be turned on for a given output level. Instead of any random or sequential set of turned-on units, controller 541 may instruct the digital power amplifier 440 to operate in a non-adjacent configuration to provide an output signal, where the output signal is generated based on the amplitude control information. For example, the mapping between each amplifier unit and the amplitude control information may represent an activation sequence. This mapping may be stored in memory. Based on the received amplitude control information and the internal mapping, controller 541 may enable the amplifier units indicated by the internal mapping, which includes a mapping representing the amplitude control information to a pattern of enabled units in the non-adjacent configuration. Enabled units in the non-adjacent configuration may include at least one inactive amplifier unit placed between at least two adjacent enabled amplifier units.

[0090] The communication circuitry can implement several such patterns. In one example, the controller 541 can arrange the cells in a checkerboard pattern, such that any cell identified as "on" (i.e., enabled) is diagonally adjacent to other enabled cells, but never horizontally or vertically adjacent. Another example could include the controller 541 positioning each enabled cell such that at least one adjacent cell on each side remains active, resulting in a linear or striped pattern that keeps the active cells spaced apart. Because digital power amplifiers often rely on multiple cells sharing a common underlying power rail or reference voltage, simultaneously enabling many adjacent cells can create the risk of high current density in this small area. The aspects described herein can also help avoid this by indicating that a subset of cells are "spread out" or interleaved with inactive cells.

[0091] Each amplifier unit can be switched to contribute to the output signal, which may include a localized gating function that blocks or enables conduction. An amplitude control bit can be passed through controller 541, which can determine which units are part of a subset. Controller 541 can then signal to drive charge or current into the load. Non-adjacent configuration ensures that even when many units are turned on to achieve higher output power, there is no localized clustering of activated units.

[0092] In the example, controller 541 can acquire information representing the layout geometry of digital power amplifier 440 to identify which units are adjacent. This information can be stored in memory. For example, the adjacency definition can be row-based, column-based, or even diagonal-based, depending on how strictly the active units are to be separated. Second, controller 541 can convert amplitude control bits to satisfy a non-adjacent selection mode (e.g., an activation sequence). If the amplitude control bits request greater power, controller 541 can enable more units in a non-adjacent configuration, provided the desired output level and / or amplitude control information allows for conversion to a non-adjacent configuration. Controller 541 can thus instruct digital power amplifier 440 to provide a corresponding gating signal that physically turns each unit on or off. Controller 541 can also facilitate the generation of correct voltage levels and timing signals.

[0093] In the example, by maintaining a stored list of subsets of units whose amplitude levels can be indicated by amplitude control information, controller 541 can facilitate operation in non-adjacent configurations. For instance, each of the multiple amplitude levels indicated by the amplitude control information can be mapped to a corresponding predefined subset of units to be enabled, each subset having a corresponding non-adjacent configuration. The multiple amplitude levels mentioned in the previous sentence can refer to all amplitude levels that allow non-adjacent configurations or only some amplitude levels.

[0094] As an illustrative example, when the amplitude control bit indicates that 10 cells should be enabled, controller 541 can retrieve a "10-cell pattern" from memory. In this example, controller 541 can verify that no two cells among these 10 cells are physically adjacent in the circuit layout. If the amplitude request increases to 11, controller 541 can retrieve an "11-cell pattern" from memory that also satisfies the non-adjacent configuration. Alternatively, controller 541 can dynamically calculate which cells should be placed in the subset by scanning the bitmask and skipping positions adjacent to enabled cells.

[0095] Controller 541 can define adjacency in various ways. For example, adjacency can refer to adjacency along only one dimension, meaning that two cells in the same row are considered adjacent, while two cells in adjacent rows are not. In another example, adjacency can refer to adjacency along both row and column directions to ensure that each active cell is surrounded by inactive cells in all basic directions (and possibly diagonal directions). Non-adjacency configurations can include any configuration that leaves at least one inactive cell between two active cells (two cells that are turned on).

[0096] In some examples, a non-adjacent configuration can be advantageous even if the amplitude control bits rarely request higher power. For instance, in a mobile device that typically transmits at moderate levels, there may be occasional bursts of maximum power. Controller 541 can guarantee that even during those bursts, the digital power amplifier 440 applies a non-adjacent configuration. This approach extends the device's operational life by preventing repetitive thermal stress in a single region of the chip. This also allows manufacturers to produce more compact integrated circuits knowing that adjacency rules will be followed, as localized locations do not necessitate larger thermal tolerances around each cell.

[0097] In the example, controller 541 can enable a subset of multiple amplifier units based on multiple activation sequences, each activation sequence representing a different mode of selectively enabling amplifier units. Each different mode can represent a unique distribution of activation units that satisfies non-adjacency based on given amplitude control information. For example, one mode might enable units every other position along a row, while another mode might enable them in a chessboard arrangement. In some examples, multiple sequences can be arranged such that each activation sequence serves a corresponding performance objective that balances and differs from other performance objectives associated with other activation sequences. For example, memory could store these activation sequences, or controller 541 could compute them based on a stored algorithm.

[0098] In the example, controller 541 can select an activation sequence from a plurality of activation sequences based on predetermined operating conditions. Accordingly, controller 541 can select which activation sequence to employ at a given time. Predetermined operating conditions may be, for example, a specific power level threshold, battery voltage, or an operating mode indicated by a device including communication circuitry. For instance, if the device, communication circuitry, or controller 541 is in a low-power state, controller 541 can select the minimum activation sequence that may involve low-power non-adjacent configurations. If it transitions to a high-power state, controller 541 can select a more aggressive sequence that may involve higher-power non-adjacent configurations, which can respond to user needs or environmental conditions without manual intervention. For example, controller 541 may include a comparator that monitors whether a register exceeds a threshold, thereby triggering a change in the selected mode.

[0099] In the example, controller 541 can select an activation sequence from a plurality of activation sequences based on thermal feedback received from a temperature sensor. The thermal feedback may include real-time thermal data. If the temperature sensor indicates an excessively high local temperature, controller 541 can select a more dispersed mode that activates units across multiple regions to reduce the temperature in any single region.

[0100] For example, the communication circuitry may include one or more temperature sensors disposed in or near the digital power amplifier 440. The temperature sensors may be located very close to the digital power amplifier arrays 441 and 442, allowing real-time monitoring of the thermal conditions of the digital power amplifiers 440. Alternatively, where heat accumulation is known to occur, the sensors may be located in the central or peripheral area of ​​the die. The controller 541 may receive temperature sensor data and may determine the need for different sequences. For example, the controller 541 may acquire the sensor data via a bus or analog-to-digital interface, and the controller 541 may then select from a library of its active sequences.

[0101] In the example, there may be progressive threshold levels for selecting the activation sequence. For example, if the temperature exceeds a first threshold, controller 541 may select a first activation sequence corresponding to a first mode. If it exceeds a second threshold, controller 541 may select a second activation sequence corresponding to a second mode. In the example, controller 541 may read the output of the temperature sensor and trigger the application of a non-adjacent configuration when the temperature exceeds a predefined threshold (e.g., when digital power amplifier 440 was previously configured for an adjacent or random configuration). Once the temperature falls below the threshold, controller 541 may revert to a less conservative mode, disable certain non-adjacent requirements, and / or revert to an adjacent or random configuration.

[0102] In the example, controller 541 can select an activation sequence based on amplitude control information. For example, the amplitude control bits can be selected directly from a stored mode, or controller 541 can select an activation sequence that takes into account amplitude and possibly other metrics. If the received amplitude control information corresponds to medium power, controller 541 can select the corresponding medium mode. If the amplitude control information corresponds to high power (e.g., above a certain threshold), controller 541 can select a mode that enables many units while still retaining a non-adjacent configuration.

[0103] In the example, controller 541 can adaptively switch from a first active sequence to a second active sequence among multiple active sequences. The selection is not a one-time event; controller 541 can continuously re-evaluate and switch sequences if specified conditions change. For example, if the device changes from a medium load to a heavy load, or if the temperature unexpectedly rises, controller 541 can abandon the previously selected first sequence and adopt another sequence. In the example, controller 541 can assign multiple modes in memory, each labeled with an identifier indicating when it should be used.

[0104] For example, controller 541 can cyclically alternate between activation sequences to change which amplifier units are enabled. For instance, even if operating conditions or amplitude control remain constant, controller 541 can facilitate such alternation, allowing the device to cycle through multiple specified sequences to distribute usage across different sets of units over time. Functionally, this can reduce wear on specific units that might otherwise remain active too frequently. In this example, controller 541 can track time or usage cycles and periodically switch from one mode to another.

[0105] In another example, controller 541 can observe multiple input parameters, such as recent communication circuit usage history, measured temperature trends over time, or predicted future load demands, and dynamically determine when to switch between activation sequences. For example, controller 541 can compare the cumulative heat exposure of individual amplifier units or evaluate performance metrics such as linearity or efficiency. Controller 541 can, for example, employ a weighted usage scheme, where units that have been activated more frequently are given a temporary "rest" period in the next sequence cycle. In the example, controller 541 can cyclically alternate between activation sequences to change which amplifier units are enabled.

[0106] In the example, the amplifier units can be arranged on the substrate in a two-dimensional matrix comprising multiple rows and columns. In other words, the digital power amplifier 440 can be implemented as a grid of amplifier units, each located at a unique row-column intersection. The controller 541 can assign a corresponding identifier to each amplifier unit (which may represent the position of the amplifier unit in row and column coordinates) and enable amplifier units to be enabled in a non-adjacent configuration by providing control signals to the corresponding units.

[0107] In the example, controller 541 can enable a subset of amplifier units such that a first row of a plurality of rows includes enabled amplifier units, and at least one second row of a plurality of rows includes a plurality of inactive units, wherein at least one second row can be positioned between adjacent rows in the first row. In the example, controller 541 can designate an entire row as "active" or "inactive." For example, row 0 may contain active units, row 1 may remain inactive, row 2 may again contain active units, and so on. By sandwiching inactive rows between two active rows, the provided pattern guarantees that there is no direct adjacency between two active rows. For example, controller 541 can process row-based gating lines such that rows 0 and 2 receive gating signals, while row 1 remains inactive. This approach is particularly simple when each row shares a specific power line or control line, making it easy for the device to skip entire rows. In the example, active and inactive units can be defined by certain segments within a row rather than the entire row, wherein said segments include at least two adjacent amplifier units.

[0108] In the example, a first column of a plurality of columns may include enabled amplifier units, and at least one second column of a plurality of columns may include a plurality of inactive units, with the at least one second column positioned between adjacent columns in the first column. Similar to a row-based approach, this activation sequence can facilitate keeping the entire column off between active columns. An example could be enabling columns 0, 2, and 4, while columns 1 and 3 remain inactive, thus ensuring that no two enabled columns appear side-by-side. For instance, the communication circuitry could have a column-based gating line driven by a controller 541 for switching the entire column to an active or inactive state. In the example, active and inactive units can be defined by segments within the column rather than the entire column, wherein the segments include at least two adjacent amplifier units.

[0109] In the example, the activation sequence can cause the digital power amplifier 440 to uniformly distribute the enabled amplifier units among multiple amplifier units, such that the enabled amplifier units are placed at regular intervals, with multiple inactive amplifier units inserted between adjacent enabled amplifier units along at least one dimension of the matrix. This can produce finer patterns where the distribution does not simply skip rows or columns, but rather places the activated units at consistent intervals. For example, the activation sequence could produce a pattern that places enabled units at every other position in a row, or a pattern that leaves a consistent gap of two inactive units between any two activated units.

[0110] Figure 7 An illustrative example of the operation of a digital power amplifier is shown. The digital power amplifier may be the digital power amplifier 440 described herein. In this illustrative example, each amplifier unit in a given row and column, indicated by the numbers shown in the figure, is activated sequentially and adjacently. The figure depicts two digital power amplifier arrays (e.g., digital power amplifier arrays 441 and 442), labeled “Array 1” and “Array 2”, each containing 8 columns and 16 rows of units. The numbering in each unit indicates an exemplary order in which the amplifier units can operate as the output power increases. For example, as amplitude control information (e.g., from digital signal processor 521) requests increasingly higher power levels, controller 541 can activate units based on their assigned sequential indices. By referencing columns and rows in a linear progression, this scheme allows newly activated units to be placed adjacent to already activated units, thereby forming a continuous block of activated units in each row.

[0111] For example, controller 541 can interpret amplitude control information as a direct instruction to activate an integer number of units in ascending order. If the amplitude bit indicates that a certain power level corresponds to activating the first X units, controller 541 can activate units in the actual equivalent numerical order: column 1 row 16, then column 2 row 16, column 3 row 16, and so on, up to the row, until the desired total number for that amplitude setting is met. If further increments are needed, controller 541 can continue down the table or across columns, activating adjacent units. Accordingly, each power increment corresponds to activating the next immediately adjacent unit in the array. Thus, if the amplitude control information corresponds to the specified value 128, it can be seen that all amplifier units from column 1 row 16 to column 8 row 16 are activated in a consecutive block.

[0112] To summarize some of the aspects mentioned above, controller 541 can enable a subset of multiple amplifier units according to an activation sequence, where the activation sequence indicates the order in which the amplifier units are enabled. Controller 541 can enable the subset according to the order indicated by the activation sequence based on amplitude control information. The order is determined based on the amplitude control information. For example, controller 541 can enable a subset of amplifier units such that, for a given amplitude control value, a corresponding number of amplifier units are enabled in the order defined by the activation sequence, where the activation sequence specifies a predefined arrangement of the amplifier units, and controller 541 selects and enables amplifier units in the prescribed order until the number of enabled amplifier units corresponds to the amplitude control information. In this particular example, for a given amplitude control value, a corresponding number of amplifier units are activated sequentially according to the activation sequence corresponding to adjacent configurations. Controller 541 can maintain a lookup table or algorithm that interprets the amplitude as a request to activate the first N units based on a strict sequence described by the numbers in the table. Each unit may include hardware such as selection logic 601, level shifter 602, and driver 603, which together determine whether the amplifier unit is activated.

[0113] Figure 8 An illustrative example of the operation of a digital power amplifier is shown. The digital power amplifier may be the digital power amplifier 440 described herein. Each amplifier unit in two digital power amplifier arrays (e.g., digital power amplifier arrays 441, 442) denoted as "Array 1" and "Array 2" is shown as having a specific number indicating an illustrative activation order. Instead of proceeding row by row or column by column in a sequential pattern, these numberings have been arranged such that physically adjacent units are assigned different numbers.

[0114] Two digital power amplifier arrays are depicted, each with 8 columns and 16 rows, totaling 128 cells per array. The number within each cell identifies its position in a non-adjacent activation sequence. Because the arrays are arranged in a two-dimensional grid on the substrate, adjacent cells (in both the row and column directions) could potentially lead to localized heat build-up if activated simultaneously. By assigning these cells numbers that are far apart in a sequence of 1–256 as shown, the corresponding activation sequence ensures that, at intermediate amplitude levels (e.g., 32, 64, 128), any newly activated cell is physically distant from those already activated in operation. Therefore, controller 541 can obtain amplitude control bits from, for example, digital signal processor 521 and interpret them as a request for a certain number of activated cells. The controller can then continue activating cells numbered from 1 up to the target count, based on the arrangement shown in the figure.

[0115] For example, each cell in the array may include sub-blocks such as selection logic 601, level shifter 602, and driver 603. Controller 541 may send a strobe signal to the selection logic of a cell based on an activation sequence representing an identifier (e.g., an assigned label) for each cell. Thus, if 64 cells are enabled, amplifier cells numbered 1 through 64 can receive an "on" signal, while higher-numbered cells remain off. When 96 cells are required at the amplitude level, controller 541 may extend the range of enabled labels to 1 through 96, allowing more spatially separated cells to be online. Through this process, the progressing steps do not produce blocks of spatially close active cells because a numbering scheme assigning widely spaced labels to physically adjacent cells is used.

[0116] As an illustrative result, when the amplitude control bit specifies that 32 units should be enabled, the controller 541 can activate amplifier units numbered 1 to 32, and because these units are physically spaced apart, no two adjacent amplifier units are turned on in the same step. If the amplitude control bit requests that 64 units be enabled, the controller 541 can activate units numbered 1 to 64, redistributing the activated units so that no local areas experience excessive heat concentration.

[0117] In practice, the sequential numbering of the amplifier units depicted can be viewed as a lookup table index for the controller 541. When the amplitude control bit indicates the desired number (N) of active units, the controller 541 can reference amplifier units numbered 1 to N in ascending order. Each label can indicate a physical location in one of two arrays—array 1 or array 2—and can be assigned to ensure that physically adjacent units have non-contiguous numbering along at least one axis.

[0118] To summarize this illustrative example, controller 541 can enable a subset of multiple amplifier units according to an activation sequence, where the activation sequence indicates the order in which the amplifier units are enabled. Controller 541 can enable the subset based on amplitude control information according to the order indicated by the activation sequence. The order is determined based on the amplitude control information. For example, controller 541 can implement a subset of amplifier units such that, for a given amplitude control value, a corresponding number of amplifier units are activated in an ascending order specified by the activation sequence.

[0119] For example, when the amplitude control bit corresponds to a requested amplitude level for a certain number of units (e.g., 32, 64, or 128), controller 541 can activate an appropriate number of units by referring to an activation sequence defined by assigned numbers. Starting with the first activated amplifier unit, units can be activated in the order of their assigned numbers, and this activation sequence continues until the desired number of units is reached. Generally, for example, if 32 activated units are requested, the first 32 units in the sequence (1 to 32 in the label map) are activated. If the request increases to 64, the next 32 units in the activation sequence (from 33 to 64) are activated, while no physically adjacent units are activated.

[0120] In some cases, depending on the amplitude request, controller 541 can progressively increase the number of activated cells by the number of the next set in the reference sequence to ensure that cells physically spaced far apart are activated to prevent overheating. These activation instructions can be systematically implemented by controller 541, which sends control signals to the selection logic of each cell to trigger this activation.

[0121] In this illustrative example, controller 541 may refer to an activation sequence in which each amplifier unit is assigned a specific position in an ordered list. Amplitude control information indicates how many units should be activated to achieve the desired output power. Therefore, when the amplitude control value corresponds to enabling N units, controller 541 can iterate through the activation sequence and enable those units numbered from 1 to N in the specified list. Because each amplifier unit occupies a predefined position in the activation sequence, controller 541 can simply select and enable the first N items of the sequence to achieve the target output level. Once the necessary number of units have been enabled, any remaining units in the sequence beyond position N remain inactive until a higher amplitude control value is requested. Thus, for each amplitude control value, different subsets of amplifier units can be enabled in the order determined by the activation sequence.

[0122] Figure 9An illustrative example of digital power amplifier operation is shown. The digital power amplifier can be the digital power amplifier 440 described herein. In this figure, two digital power amplifier arrays labeled "Array 1" and "Array 2" (e.g., digital power amplifier arrays 441, 442) again show amplifier units in an eight-column by sixteen-row matrix, where each unit is labeled with a unique number from 1 to 256. As with other non-adjacent configurations, these numbers specify a predetermined activation order aimed at separating the activation of physically adjacent units. Although the overall concept is similar... Figure 8 The concept shown is different, but the new drawing presents a different labeling scheme, reflecting the existing... Figure 8 Different activation sequences are possible. If the amplitude control bit requires many units, the label of each unit can identify the point in the sequence where that unit is activated. When the amplitude control bit requests N units, the controller 541 can enable the amplifier units corresponding to the labels from 1 to N in ascending order, and can ensure that units assigned to indices exceeding N remain inactive.

[0123] By comparing which rows and columns receive lower-numbered labels, it can be observed that... Figure 8 The difference lies in the early sequences. In the previous figure, it can be noted that certain rows or corners systematically receive the earliest indices. Here, the labeling pattern is changed so that the distribution of lower-numbered cells is spread out in a new way. However, the principle remains the same: by distributing the earliest labels (those enabled at lower amplitude levels) in physically distant locations, this arrangement avoids adjacent enabled cells, at least on the axes of the matrix provided by the amplifier units.

[0124] Controller 541 can address each row and column in both arrays via dedicated or shared strobe signals. Each amplifier unit at the row-column intersection can have local components such as selection logic 601, level shifter 602, and driver 603. Selection logic 601 can determine whether driver 603 is enabled based on a signal of the assigned label of the referenced unit regarding the amplitude control bit. If amplitude control requires, for example, 96 active units, controller 541 can examine a stored or computed sequence of active units representing an order to identify units labeled 1 through 96. Each of those units can then receive an "enable" command via its selection logic 601, which may be passed through level shifter 602 if a shift from a low-voltage logic domain (e.g., VDDL) to a high-voltage supply (e.g., VDDH) powering driver 603 is required.

[0125] Controller 541 can store or dynamically generate this labeling structure in internal memory. When the amplitude control bits come from digital signal processor 521 or a similar source, controller 541 can look up how many units must be turned on, and thus can select amplifier units from label 1 to label N for non-adjacent configurations. In the example, the communication circuitry can further refine which arrays are engaged at low power levels, perhaps enabling only a small portion of the amplifier units in array 1 if the requested amplitude is moderate, but as long as the communication circuitry requires a higher amplitude output, controller 541 can move up the numerical sequence, also enabling units in the labels of array 2. An important difference from the sequential numbering method is that lower numbers in array 2 can often be selected to be physically farthest from lower numbers in array 1, so that, for example, turning on units labeled 1 to 80 does not create a cluster in one corner.

[0126] Because each unit can be physically identical from an operational standpoint, the identifier (i.e., label) can simply be a matter of controlling the order in which the activation selection logic 601 is executed. Once the controller 541 can command a unit to turn on, the driver 603 of that unit can contribute to the total output power. The difference lies in how the identifier ensures that units at physically close coordinates do not share consecutive or near-consecutive labels, preventing them from switching on and off together at the same amplitude step. It is worth noting that if the amplitude request is large enough to eventually enable all 256 units, the final scenario is the same—every unit is active. The advantage of a non-adjacent configuration lies primarily in all intermediate steps, which actually represent most of the normal operation, since peak power is not continuously used. Because each asymptotic step from 1 to N is widely distributed across the array, the digital power amplifier can experience a slower, more uniform thermal gradient.

[0127] In the example, the activation sequence represents a mapping of amplitude control information to binary patterns indicating the enabled and disabled states of amplifier units. For example, amplitude control bits can directly select which units are ultimately turned on or off. If the device has a 10-bit amplitude control code, this code can correspond to a 1024-entry table encoding the binary mask used for the digital power amplifier units. Adjacency rules can be satisfied by arranging the activation sequence to ensure that the corresponding binary mask does not allow two adjacent units to both be set to enabled. Based on the received amplitude control information, the controller 541 can retrieve the corresponding binary pattern from memory and apply that pattern to the gating of each unit.

[0128] In the example, controller 541 can determine which amplifier units to enable for generating the output signal based on the selected activation sequence. For example, this could include setting certain strobe signals to "active" for those units to be enabled, and setting certain strobe signals to "deactivated" for other units.

[0129] In the example, controller 541 may generate switching signals to selectively switch each amplifier unit to an enabled state when a selected activation sequence indicates activation of each amplifier unit, and to switch it to an inactive state when the selected activation sequence indicates deactivation of each amplifier unit. In the example, controller 541 may couple selection logic for each unit, which then triggers a level shifter for that unit. Controller 541 may include logic circuitry or a smaller processor that generates different strobe signals for each amplifier unit. An internal address decoder or multiplexing stage may route these signals to the correct subset of units indicated by the selected activation sequence. For example, controller 541 may include a memory register or lookup table that stores which units to enable for each amplitude code or operating state.

[0130] Each amplifier unit may include selection logic 601, a level shifter 602, and a driver 603, arranged such that a gating signal from controller 541 can propagate to the drive domain of the amplifier unit. Selection logic 601 may receive a digital enable signal corresponding to an assigned index and activation state of the amplifier unit. This logic may then drive level shifter 602, which converts a lower voltage control signal to a higher voltage domain (e.g., VDDH) suitable for switching driver 603. Driver 603 itself may include one or more transistor and capacitor elements that couple power to the output node of the digital power amplifier. When controller 541 asserts a gating signal to the amplifier unit, the amplifier unit can transition from a off state (where it does not contribute charge or current) to an on state (actively transferring a share of the overall output power).

[0131] The amplitude control information described herein indicates the desired output power level. Each active unit can contribute an incremental portion of the power, so if a high level is requested, the controller 541 can activate more units. Because the adjacency rule is in effect, the controller 541 can determine which subset best achieves that power. Accordingly, activated amplifier units can contribute to the output signal, and inactive amplifier units can be excluded from contributing to the output signal. Thus, only the activated units actually drive current or charge into the load, while the inactive units are effectively decoupled. Each amplifier unit may include a gating transistor or driver stage that remains off if the controller 541 specifies that the unit is inactive.

[0132] As illustrated herein, the digital power amplifier 440 may include multiple unit arrays, which may be two unit arrays as described herein or any integer number of unit arrays, such as 3, 4, 5, 10, etc. Furthermore, the controller 541 may enable a specific number of units within the multiple arrays, indicated by amplitude control information, such that the amplitude of the output signal is proportional to the number of amplifier units enabled. For example, in a digital power amplifier, the output voltage signal may be linearly proportional to the number of operating units. This means that operating two full arrays will produce twice the output signal value (or increase the output power by 6 dB).

[0133] Figure 10 An example of the complementary cumulative distribution function (CCDF) according to the various aspects described herein is shown. This figure depicts the complementary cumulative distribution function (CCDF) of the transmitted signal under MCS7 modulation, illustrating the statistical probability of various output power levels occurring over time. Specifically, the curve represents the occurrence of power levels corresponding to a 6 dB backoff from the maximum output (which could require activating two digital power amplifier arrays to double the power) under operating conditions below 5%. Therefore, for approximately 95% of the transmission time, the transmitter operates in a lower power state, meaning that only about half of the available amplifier units are activated. This observation stems from the linear relationship between the number of activated units and the output voltage amplitude, where doubling the amplifier units produces an approximately 6 dB increase in output power.

[0134] For example, in a communication circuit comprising a substrate on which a first pair of digital power amplifier arrays are arranged around one corner and a second pair of digital power amplifier arrays are arranged around the other corner, the core temperature of these arrays is simulated to be approximately 130-131 degrees Celsius when each pair of digital power amplifier arrays operates in a configuration in which one digital power amplifier array operates in an adjacent configuration. On the other hand, when these pairs are instructed to operate in a non-adjacent configuration to distribute enable cells within the pair, the core temperature is simulated to be approximately 120-123 degrees Celsius, representing an average temperature reduction of 8.4 degrees Celsius. For example, the application of non-adjacent configurations can be identified by thermal detection of digital power amplifiers operating in BO (backoff) mode. In this scenario, sweeping the output signal from low power to high power can generate thermal temperature points visible at several locations on the digital power amplifier arrays.

[0135] Figure 11 An example of a method is shown. The method may include: providing an output signal 1101 using a digital power amplifier (DPA) comprising multiple amplifier units based on amplitude control information, wherein each amplifier unit is switchable to contribute to the output signal; and activating a subset of the multiple amplifier units 1102 according to an activation sequence, wherein the subset includes activated amplifier units arranged in a non-adjacent manner, wherein at least one inactive amplifier unit among the multiple amplifier units is placed between adjacent activated amplifier units. A computer-readable medium may store instructions that, if executed, cause a processor to perform the method.

[0136] The following examples relate to other aspects described in this article.

[0137] Example 1 may include the subject of a device comprising: a digital power amplifier (DPA) including a plurality of amplifier units configured to provide an output signal based on amplitude control information, wherein each amplifier unit is switchable to contribute to the output signal; and control circuitry (i.e., a controller) configured to enable a subset of the plurality of amplifier units according to an activation sequence, wherein the subset includes enabled amplifier units arranged in a non-adjacent manner, wherein at least one inactive amplifier unit of the plurality of amplifier units is placed between adjacent enabled amplifier units.

[0138] Example 2 may include the subject of Example 1, wherein the control circuitry is further configured to enable a subset of multiple amplifier units based on a plurality of activation sequences, each activation sequence representing a different mode for selectively enabling amplifier units.

[0139] Example 3 may include the subject of Example 2, wherein the control circuit is configured to select an activation sequence from a plurality of activation sequences based on predetermined operating conditions.

[0140] Example 4 may include the subject of Example 2 or Example 3, wherein the control circuit is configured to select an activation sequence from a plurality of activation sequences based on thermal feedback received from a temperature sensor.

[0141] Example 5 may include the subject of any of Examples 2 to 4, wherein the control circuitry is further configured to select an activation sequence based on amplitude control information.

[0142] Example 6 may include the subject of any one of Examples 2 to 5, wherein the control circuit is configured to adaptively switch from a first activation sequence among a plurality of activation sequences to a second activation sequence among a plurality of activation sequences.

[0143] Example 7 may include the subject of any of Examples 2 through 6, wherein the control circuitry is also configured to cyclically alternate between activation sequences to change which amplifier units are enabled.

[0144] Example 8 may include the subject of any of Examples 1 to 7, wherein the amplifier units are arranged on the substrate in a two-dimensional matrix comprising multiple rows and multiple columns.

[0145] Example 9 may include the subject of Example 8, wherein a first row of a plurality of rows includes an enabled amplifier unit, and at least one second row of a plurality of rows includes a plurality of inactive units, the plurality of inactive units including at least one inactive amplifier unit, wherein at least one second row is positioned between adjacent rows in the first row.

[0146] Example 10 may include the subject of Example 8 or Example 9, wherein a first column of a plurality of columns includes an enabled amplifier unit, and at least one second column of a plurality of columns includes a plurality of inactive units, the plurality of inactive units including at least one inactive amplifier unit, wherein at least one second column is positioned between adjacent columns in the first column.

[0147] Example 11 may include the subject of any of Examples 8 to 10, wherein the activation sequence is configured to uniformly distribute enabled amplifier units among a plurality of amplifier units, wherein the enabled amplifier units are placed at regular intervals, and wherein a plurality of inactive amplifier units are inserted between adjacent enabled amplifier units along at least one dimension of the matrix.

[0148] Example 12 may include the subject of any of Examples 1 to 11, wherein the activation sequence represents a mapping of amplitude control information to binary patterns representing the enabled and inactive states of amplifier units.

[0149] Example 13 may include the subject of any of Examples 1 to 12, wherein the control circuitry is configured to determine which amplifier units to enable to generate the output signal based on a selected activation sequence.

[0150] Example 14 may include the subject matter of Example 13, wherein the control circuitry is configured to generate switching signals to selectively switch each amplifier unit to an enabled state when a selected activation sequence indicates activation, and to switch each amplifier unit to an inactive state when a selected activation sequence indicates deactivation.

[0151] Example 15 may include the subject of any of Examples 1 to 14, wherein amplitude control information indicates the desired output power level.

[0152] Example 16 may include the subject of any of Examples 1 to 15, wherein an enabled amplifier unit is configured to contribute to the output signal, and at least one inactive amplifier unit is excluded from the contribution to the output signal.

[0153] Example 17 may include the subject of any of Examples 1 to 16, wherein the DPA includes a plurality of unit arrays, the plurality of unit arrays including a plurality of amplifier units.

[0154] Example 18 may include the subject of any of Examples 1 to 17, wherein the enabled amplifier includes a certain number of amplifier units of a plurality of amplifier units, wherein the number is based on amplitude control information.

[0155] Example 19 may include the subject of Example 18, wherein the amplitude of the output signal is proportional to the number of amplifier units enabled.

[0156] Example 20 may include a communication circuit comprising: a device of any one of Examples 1 to 19; and a digital time converter configured to provide a phase modulation signal to the device.

[0157] Example 21 may include the communication circuitry of Example 20, which may additionally include a processor configured to provide amplitude control information to the device and phase control information to the digital time converter.

[0158] Example 22 may include the subject of a method comprising: providing an output signal based on amplitude control information using a digital power amplifier (DPA) comprising a plurality of amplifier units, wherein each amplifier unit is switchable to contribute to the output signal; and enabling a subset of the plurality of amplifier units according to an activation sequence, wherein the subset comprises enabled amplifier units arranged in a non-adjacent manner, wherein at least one inactive amplifier unit of the plurality of amplifier units is placed between adjacent enabled amplifier units.

[0159] Example 23 may include the subject of Example 22, and may also include a subset of multiple amplifier units enabled based on multiple activation sequences, each activation sequence representing a different mode for selectively enabling amplifier units.

[0160] Example 24 may include the subject of Example 23, and may also include selecting an activation sequence from a plurality of activation sequences based on predetermined operating conditions.

[0161] Example 25 may include the subject of Example 23 or Example 24, and may also include selecting an activation sequence from a plurality of activation sequences based on thermal feedback received from a temperature sensor.

[0162] Example 26 may include the subject of any of Examples 23 to 25, and may also include selecting an activation sequence based on amplitude control information.

[0163] Example 27 may include the subject of any of Examples 23 to 26, and may also include adaptively switching from a first activation sequence among a plurality of activation sequences to a second activation sequence among a plurality of activation sequences.

[0164] Example 28 may include the subject of any of Examples 23 through 27, and may also include cyclically alternating between activation sequences to change which amplifier units are enabled.

[0165] Example 29 may include the subject of any of Examples 22 to 28, wherein the amplifier units are arranged on the substrate in a two-dimensional matrix comprising multiple rows and multiple columns.

[0166] Example 30 may include the subject of Example 29, and may also include enabling amplifier units in a first row of a plurality of rows, while at least one second row of the plurality of rows includes a plurality of inactive units, the plurality of inactive units including at least one inactive amplifier unit, wherein at least one second row is disposed between adjacent rows in the first row.

[0167] Example 31 may include the subject of Example 29 or Example 30, and may also include enabling amplifier units in a first column of a plurality of columns, while at least one second column of the plurality of columns includes a plurality of inactive units, the plurality of inactive units including at least one inactive amplifier unit, wherein at least one second column is disposed between adjacent columns in the first column.

[0168] Example 32 may include the subject of any of Examples 29 to 31, wherein the activation sequence is used to uniformly distribute enabled amplifier units among a plurality of amplifier units, wherein the enabled amplifier units are placed at regular intervals, and wherein a plurality of inactive amplifier units are inserted between adjacent enabled amplifier units along at least one dimension of the matrix.

[0169] Example 33 may include the subject of any of Examples 22 to 32, wherein the activation sequence represents a mapping of amplitude control information to binary patterns representing the enabled and inactive states of amplifier units.

[0170] Example 34 may include the subject of any of Examples 22 to 33, and may also include determining which amplifier units to enable to generate the output signal based on the selected activation sequence.

[0171] 35 may include the subject matter of Example 34, and may also include generating switch signals to selectively switch each amplifier unit to an enabled state when the selected activation sequence indicates activation, and to switch each amplifier unit to an inactive state when the selected activation sequence indicates deactivation.

[0172] Example 36 may include the subject of any of Examples 22 to 35, wherein amplitude control information indicates the desired output power level.

[0173] Example 37 may include the subject of any of Examples 22 to 36, wherein an enabled amplifier unit contributes to the output signal, and at least one inactive amplifier unit is excluded from the contribution to the output signal.

[0174] Example 38 may include the subject of any of Examples 22 to 37, wherein the DPA includes a plurality of unit arrays, the plurality of unit arrays including a plurality of amplifier units.

[0175] Example 39 may include the subject of any of Examples 22 to 38, and may also include enabling a certain number of amplifier units among a plurality of amplifier units, wherein the number is based on amplitude control information.

[0176] Example 40 may include the subject of Example 39, wherein the amplitude of the output signal is proportional to the number of amplifier units enabled.

[0177] Example 41 may include the subject matter of a non-transitory computer-readable medium storing instructions that, when executed by a processor, cause the processor to: control a digital power amplifier (DPA) comprising a plurality of amplifier units, wherein each amplifier unit is switchable to contribute to an output signal; and enable a subset of the plurality of amplifier units according to an activation sequence, wherein the subset comprises enabled amplifier units arranged in a non-adjacent manner, wherein at least one inactive amplifier unit of the plurality of amplifier units is placed between adjacent enabled amplifier units.

[0178] Example 42 may include the subject of Example 41, wherein the instructions further enable the processor to enable a subset of multiple amplifier units based on a plurality of activation sequences, each activation sequence representing a different mode for selectively enabling amplifier units.

[0179] Example 43 may include the subject of Example 42, wherein the instructions further cause the processor to select an activation sequence from a plurality of activation sequences based on predetermined operating conditions.

[0180] Example 44 may include the subject of Example 42 or Example 43, wherein the instructions further enable the processor to select an activation sequence from a plurality of activation sequences based on thermal feedback received from a temperature sensor.

[0181] Example 45 may include the subject of any of Examples 42 to 44, wherein the instructions further enable the processor to select an activation sequence based on amplitude control information.

[0182] Example 46 may include the subject of any one of Examples 42 to 45, wherein the instructions further enable the processor to adaptively switch from a first activation sequence among a plurality of activation sequences to a second activation sequence among a plurality of activation sequences.

[0183] Example 47 may include the subject of any of Examples 42 to 46, wherein the instructions further cause the processor to cyclically alternate between activation sequences to change which amplifier units are enabled.

[0184] Example 48 may include the subject of any of Examples 41 to 47, wherein the amplifier units are arranged on the substrate in a two-dimensional matrix comprising multiple rows and multiple columns.

[0185] Example 49 may include the subject of Example 48, wherein the instructions further cause the processor to enable amplifier units in a first row of a plurality of rows, while at least one second row of the plurality of rows includes a plurality of inactive units, the plurality of inactive units including at least one inactive amplifier unit, wherein at least one second row is disposed between adjacent rows in the first row.

[0186] Example 50 may include the subject of Example 48 or Example 49, wherein the instructions further cause the processor to enable the amplifier unit in a first column of a plurality of columns, while at least one second column of the plurality of columns includes a plurality of inactive units, the plurality of inactive units including at least one inactive amplifier unit, wherein at least one second column is disposed between adjacent columns in the first column.

[0187] Example 51 may include the subject of any of Examples 48 to 50, wherein the activation sequence is configured to uniformly distribute enabled amplifier unit elements among a plurality of amplifier units, wherein the enabled amplifier units are placed at regular intervals, and wherein a plurality of inactive amplifier units are inserted between adjacent enabled amplifier units along at least one dimension of the matrix.

[0188] Example 52 may include the subject of any of Examples 41 to 51, wherein the activation sequence represents a mapping of amplitude control information to binary patterns representing the enabled and inactive states of amplifier units.

[0189] Example 53 may include the subject of any of Examples 41 to 52, wherein the instructions further enable the processor to determine which amplifier units to enable to generate the output signal based on the selected activation sequence.

[0190] Example 54 may include the subject matter of Example 53, wherein the instructions further cause the processor to generate switch signals to selectively switch each amplifier unit to an enabled state when a selected activation sequence indicates activation, and to switch each amplifier unit to an inactive state when a selected activation sequence indicates deactivation.

[0191] Example 55 may include the subject of any of Examples 41 to 54, wherein amplitude control information indicates the desired output power level.

[0192] Example 56 may include the subject of any of Examples 41 to 55, wherein an enabled amplifier unit contributes to the output signal, and at least one inactive amplifier unit is excluded from the contribution to the output signal.

[0193] Example 57 may include the subject of any of Examples 41 to 56, wherein the DPA includes a plurality of unit arrays, the plurality of unit arrays including a plurality of amplifier units.

[0194] Example 58 may include the subject of any of Examples 41 to 57, wherein the instructions further cause the processor to enable a certain number of amplifier units among a plurality of amplifier units, wherein the number is based on amplitude control information.

[0195] Example 59 may include the subject of Example 58, wherein the amplitude of the output signal is proportional to the number of amplifier units enabled.

[0196] The term “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any embodiment or design described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments or designs.

[0197] The terms "plural" and "multiple" in the specification or claims explicitly refer to a quantity greater than one. The terms "group," "set," "aggregate," "series," "sequence," "grouping," etc., in the specification or claims refer to a quantity equal to or greater than one, i.e., one or more. Any term expressed in plural form that does not explicitly state "plural" or "multiple" similarly refers to a quantity equal to or greater than one.

[0198] Any vector and / or matrix representations used herein are exemplary in nature and are for illustrative purposes only. Therefore, the devices and methods described herein with accompanying vector and / or matrix representations are not limited to implementation using only vectors and / or matrices, and the associated processing and computations can be performed in an equivalent manner for sets, sequences, groups, etc., of data, observations, information, signals, samples, symbols, elements, etc.

[0199] As used herein, “memory” is understood to be a non-transitory computer-readable medium in which data or information can be stored for retrieval. References to “memory” as used herein can therefore be understood to refer to volatile or non-volatile memory, including random access memory (“RAM”), read-only memory (“ROM”), flash memory, solid-state memory, magnetic tape, hard disk drive, optical drive, etc., or any combination thereof. Furthermore, registers, shift registers, processor registers, data buffers, etc., are also included herein by the term “memory.” A single component referred to as “memory” may consist of more than one different type of memory, and therefore may refer to a centralized component comprising one or more types of memory. Any single memory component can be separated into multiple common equivalent memory components, and vice versa. Furthermore, although memory may be depicted as separate from one or more other components (as in the figures), memory may also be integrated with other components, such as integrated on a common integrated chip, or in a controller with embedded memory.

[0200] The term "software" refers to any type of executable instructions, including firmware.

[0201] In the context of this description, the term "process" may be used, for example, to denote a method. For instance, any process described herein can be implemented as a method (e.g., a channel estimation process can be understood as a channel estimation method). Any process described herein can be implemented as a non-transitory computer-readable medium comprising instructions that, when executed, cause one or more processors to perform the process (e.g., execute a method).

[0202] Throughout the accompanying drawings, it should be noted that the same reference numerals are used to depict the same or similar elements, features, and structures, unless otherwise stated. It should be noted that certain components may be omitted for simplicity. It should be noted that in drawings including electronic circuit diagrams, nodes (points) are provided to identify intersections of circuit lines.

[0203] The phrases “at least one” and “one or more” can be understood to include a numerical quantity greater than or equal to one (e.g., one, two, three, four, [...] etc.). In this document, the phrase “at least one of” relative to a group of elements may be used to mean at least one element in a group of elements. For example, in this document, the phrase “at least one of” relative to a group of elements may be used to mean a selection of: one of the listed elements, a plurality of listed elements, a plurality of separately listed elements, or a plurality of a plurality of separately listed elements.

[0204] The terms “plural” and “multiple” in the specification and claims explicitly refer to a quantity greater than one. Therefore, any phrase that explicitly uses the foregoing terms referring to a large number of elements (e.g., “plural [elements]”, “multiple [elements]”) explicitly refers to more than one of the stated elements. For example, the phrase “multiple” can be understood to include a quantity greater than or equal to two (e.g., two, three, four, five, [...] etc.).

[0205] As used herein, a signal or information that “indicates,” “represents,” “represents,” or “indicates” a value or other information can be a digital or analog signal that encodes or transmits the value or other information in a manner that can be decoded in a receiving component and / or cause a responsive action in that component. The signal may be stored or buffered in a computer-readable storage medium before being received by the receiving component, and the receiving component may retrieve the signal from the storage medium. Furthermore, a “value” that “indicates” or “represents” certain quantities, states, or parameters can be physically implemented as a digital signal, analog signal, or storage bit that encodes or transmits the value.

[0206] As used herein, signals can be transmitted or conducted through signal chains, where they can be processed to alter characteristics such as phase, amplitude, and frequency. Even with these modifications, the signal can still be referred to as the same signal. Generally, a signal can be considered the same signal as long as it continues to encode the same information. For example, a transmitted signal can be considered to refer to a transmitted signal in baseband, intermediate frequency, and radio frequency.

[0207] For example, the terms "processor" or "controller" as used herein can be understood as any kind of technical entity that allows data processing. Data can be processed according to one or more specific functions performed by the processor. Furthermore, the processor or controller as used herein can be understood as any kind of circuit, such as any kind of analog or digital circuit. A processor or controller can therefore be or include analog circuits, digital circuits, mixed-signal circuits, logic circuits, processors, microprocessors, central processing units (CPUs), graphics processing units (GPUs), digital signal processors (DSPs), field-programmable gate arrays (FPGAs), integrated circuits, application-specific integrated circuits (ASICs), etc., or any combination thereof. Any other kind of implementation of the corresponding functions, which will be described in more detail below, can also be understood as a processor, controller, or logic circuit. It should be understood that any two (or more) of the processors, controllers, or logic circuits detailed herein can be implemented as a single entity with equivalent functionality, and conversely, any single processor, controller, or logic circuit detailed herein can be implemented as two (or more) separate entities with equivalent functionality.

[0208] The term "one or more processors" is intended to refer to either a processor or a controller. One or more processors may include a processor or multiple processors. These terms are used only as alternatives to "processor" or "controller".

[0209] The term "user device" is intended to refer to a device belonging to a user (e.g., an owner) that can be configured to provide information relevant to the user. Exemplary user devices may include mobile phones, smartphones, wearable devices (e.g., smartwatches, smart wristbands), computers, and the like.

[0210] As used herein, the terms “module,” “component,” “system,” “circuit,” “element,” “slice,” “circuit,” etc., are intended to refer to a collection of one or more electronic components, a computer-related entity, hardware, software (e.g., running), and / or firmware. For example, a circuit or similar term can be a processor, a process running on a processor, a controller, an object, an executable program, a storage device, and / or a computer having processing power. For illustration, an application running on a server and a server can also be a circuit. One or more circuits may exist within the same circuit, and circuits may be located on one computer and / or distributed among two or more computers. In this document, a collection of elements or other collections of circuits may be described, where the term “collection” can be interpreted as “one or more.”

[0211] As used herein, the term "data" can be understood to include information in any suitable analog or digital form, such as information provided as a file, a portion of a file, a collection of files, a signal or stream, a portion of a signal or stream, a collection of signals or streams, and so on. Furthermore, the term "data" can also be used to indicate a reference to information, for example, in the form of a pointer. However, the term "data" is not limited to the examples above and can take various forms and represent any information understood in the prior art. The term "data item" can include data or a portion of data.

[0212] It will be understood that when a component is referred to as being "connected" or "coupled" to another component, it can be physically connected or coupled to the other component such that current and / or electromagnetic radiation (e.g., signals) can flow along a conductive path formed through the component. Essentially, such components can be connected or coupled to another component. When components are described as being coupled or connected to each other, an intermediate conductive element, inductive element, or capacitive element can be present between the component and the other component. Additionally, when coupled or connected to each other, a component can be able to sense voltage or current or electromagnetic wave propagation in the other component without physical contact or intermediate components. Furthermore, when voltage, current, or signal is referred to as being "provided" to a component, the voltage, current, or signal can be transmitted to the component through a physical connection or through capacitive, electromagnetic, or inductive coupling that does not involve a physical connection.

[0213] Unless explicitly stated otherwise, the term "time instance" refers to the time of a specific event or situation, depending on the context. A time instance can refer to a point in time or a period of time involving a specific event or situation.

[0214] Unless explicitly stated otherwise, the term “transmit” includes both direct transmission (point-to-point) and indirect transmission (via one or more intermediate points). Similarly, the term “receive” includes both direct reception and indirect reception. Furthermore, the terms “transmit,” “receive,” “transmit,” and other similar terms include both physical transmission (e.g., transmission of wireless signals) and logical transmission (e.g., transmission of digital data via a logical software-level connection). For example, a processor or controller may transmit or receive data in the form of wireless signals with another processor or controller via a software-level connection, where physical transmission and reception are handled by wireless layer components such as RF transceivers and antennas, and logical transmission and reception via a software-level connection are performed by the processor or controller. The term “transmit” includes one or both of transmission and reception, i.e., one-way or two-way communication in one or both of the incoming and outgoing directions. The term “computation” includes both types of computation: “direct” computation via mathematical expressions / equations / relations, and “indirect” computation via lookup tables or hash tables and other array indexing or search operations.

[0215] While the above description and related figures may depict electronic device components as individual elements, those skilled in the art will understand the various possibilities of combining or integrating discrete components into a single element. This may include combining two or more circuits to form a single circuit, mounting two or more circuits onto a common chip or chassis to form an integrated element, running discrete software components on a common processor core, and so on. Conversely, those skilled in the art will recognize the possibility of separating a single element into two or more discrete elements, such as splitting a single circuit into two or more separate circuits, separating a chip or chassis into discrete elements disposed thereon, separating software components into two or more parts and running them on separate processor cores, and so on.

[0216] It should be understood that the implementation of the method detailed herein is exemplary in nature and is therefore to be understood as being implementable in the corresponding apparatus. Similarly, it is to be understood that the implementation of the apparatus detailed herein is to be understood as being implementable as the corresponding method. Therefore, it is to be understood that the apparatus corresponding to the method detailed herein may include one or more components configured to perform each aspect of the relevant method. All acronyms defined in the above description also apply in all claims included herein.

Claims

1. An apparatus, the apparatus comprising: A digital power amplifier (DPA) comprising multiple amplifier units configured to provide an output signal based on amplitude control information, wherein each amplifier unit is switchable to contribute to the output signal; and A controller configured to enable a subset of the plurality of amplifier units according to an activation sequence, wherein the subset includes enabled amplifier units arranged in a non-adjacent manner, wherein at least one inactive amplifier unit of the plurality of amplifier units is placed between adjacent enabled amplifier units.

2. The device according to claim 1, wherein, The controller is also configured to enable a subset of the plurality of amplifier units based on a plurality of activation sequences, including the activation sequence, which represent different modes of selectively enabling the amplifier units.

3. The device according to claim 2, wherein, The controller is configured to select an activation sequence from the plurality of activation sequences based on predetermined operating conditions.

4. The device according to claim 2, wherein, The controller is configured to select an activation sequence from the plurality of activation sequences based on thermal feedback received from a temperature sensor.

5. The device according to claim 2, wherein, The controller is also configured to select the activation sequence based on the amplitude control information.

6. The device according to claim 2, wherein, The controller is also configured to adaptively switch from a first activation sequence to a second activation sequence among the plurality of activation sequences.

7. The device according to claim 2, wherein, The controller is also configured to cyclically alternate between the activation sequences to change which amplifier units are enabled.

8. The device according to any one of claims 1 to 7, wherein, The amplifier units are arranged on the substrate in a two-dimensional matrix comprising multiple rows and multiple columns.

9. The device according to claim 8, wherein, The first row of the plurality of rows includes the enabled amplifier unit, and at least one second row of the plurality of rows includes a plurality of inactive units, the plurality of inactive units including the at least one inactive amplifier unit, wherein the at least one second row is disposed between adjacent rows in the first row.

10. The device according to claim 8, wherein, The first column of the plurality of columns includes the enabled amplifier unit, and at least one second column of the plurality of columns includes a plurality of inactive units, the plurality of inactive units including the at least one inactive amplifier unit, wherein the at least one second column is disposed between adjacent columns in the first column.

11. The device according to claim 8, wherein, The activation sequence is configured to uniformly distribute the enabled amplifier units among the plurality of amplifier units, wherein the enabled amplifier units are placed at regular intervals, and wherein a plurality of inactive amplifier units are inserted between adjacent enabled amplifier units along at least one dimension of the matrix.

12. The device according to any one of claims 1 to 7, wherein, The activation sequence represents the mapping of the amplitude control information to a binary pattern representing the enabled and inactive states of the amplifier unit.

13. The device according to any one of claims 1 to 7, wherein, The controller is configured to determine which amplifier units to activate to generate the output signal based on the selected activation sequence.

14. The device according to claim 13, wherein, The controller is configured to generate switching signals to selectively switch each amplifier unit to an enabled state when a selected activation sequence indicates activation, and to switch each amplifier unit to an inactive state when a selected activation sequence indicates deactivation.

15. The device according to any one of claims 1 to 7, wherein, The amplitude control information indicates the desired output power level.

16. The device according to any one of claims 1 to 7, wherein, The activated amplifier unit is configured to contribute to the output signal, and the at least one inactive amplifier unit is excluded from contributing to the output signal.

17. The device according to any one of claims 1 to 7, wherein, The DPA includes multiple unit arrays, and the multiple unit arrays include the multiple amplifier units.

18. The device according to any one of claims 1 to 7, wherein, The activated amplifier includes a certain number of amplifier units from the plurality of amplifier units, wherein the number is based on amplitude control information.

19. The device according to claim 18, wherein, The amplitude of the output signal is proportional to the number of the activated amplifier units.

20. A communication circuit, the communication circuit comprising: The device includes: A digital power amplifier (DPA) comprising multiple amplifier units configured to provide an output signal based on amplitude control information, wherein each amplifier unit is switchable to contribute to the output signal; and A controller configured to enable sub-amplifier units according to an activation sequence. A subset comprising enabled amplifier units arranged in a non-adjacent manner, wherein at least one inactive amplifier unit of the plurality of amplifier units is placed adjacent to the enabled amplifier unit. Between; and A digital time converter configured to provide a phase modulation signal to the device.

21. The communication circuit of claim 20, further comprising a processor configured to provide the amplitude control information to the device and the phase control information to the digital time converter.

22. A non-transitory computer-readable medium storing instructions that, when executed by a processor, cause the processor to perform the following operations: Controlling a digital power amplifier (DPA) comprising multiple amplifier units, wherein, At least some of the amplifier units can be switched to contribute to the output signal; as well as A subset of the plurality of amplifier units is activated according to an activation sequence, wherein the subset includes activated amplifier units arranged in a non-adjacent manner, wherein at least one inactive amplifier unit of the plurality of amplifier units is placed between adjacent activated amplifier units.

23. The non-transitory computer-readable medium according to claim 22, wherein, The instructions also cause the processor to enable the subset of the plurality of amplifier units based on a plurality of activation sequences, including the activation sequence, the activation sequence representing different modes of selectively enabling the amplifier units.

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