An adaptive DC offset cancellation method for UWB receivers

Abstract

This application discloses an adaptive DC offset cancellation method for a UWB receiver, comprising: processing multi-channel ADC sampled data through a first path to obtain first sampled data, the first path processing including directly entering the DC estimation loop, sequentially passing through multi-channel summation and downsampling, a first-order differential, a leakage integrator, and a ΣΔ error feedback truncation; processing multi-channel ADC sampled data through a second path to obtain second sampled data, the second path processing including delaying the multi-channel ADC sampled data by one clock cycle through a delay register to compensate for the pipeline delay of the DC estimation loop; subtracting the first sampled data and the second sampled data in a subtractor to obtain a DC-corrected clean signal. This application provides an adaptive DC offset cancellation method for a UWB receiver, which effectively adaptively cancels DC offset by processing ADC sampled data through two paths.

Description

Technical Field

[0001] This application relates to the field of ultra-wideband technology, and in particular to an adaptive DC offset cancellation method for UWB receivers. Background Technology

[0002] UWB (Ultra-Wideband) communication systems use nanosecond-level narrow pulses for data transmission, featuring high-precision positioning and low power consumption. They are widely used in indoor positioning, digital keys, smart homes, and other scenarios. Typical UWB receivers employ direct down-conversion (Zero-IF) or low-IF architectures to reduce chip area and power consumption.

[0003] In direct downconversion receivers, DC (Direct Current) offset is an inherent and prominent technical problem. The main sources of DC offset include: (1) Local oscillator leakage self-mixing - the local oscillator signal is coupled to the LNA input through a parasitic path and mixed with itself in the mixer, generating a DC component in the baseband; (2) Circuit mismatch - process deviations of various devices such as mixers, filters, and ADCs (Analog-to-Digital Converters) introduce static DC offset; (3) Dynamic DC drift - factors such as chip temperature changes, power supply voltage fluctuations, and channel environment changes cause DC offset to change slowly over time; (4) Antenna diversity switching - in multi-antenna receivers, the DC bias characteristics of different antenna links are different, and the original DC estimate is no longer valid when switching antennas.

[0004] If DC offset is not properly eliminated, it will lead to the following serious consequences: DC component occupies the ADC range, error vector amplitude deteriorates, automatic gain control loop converges to the wrong operating point, and the received signal strength indication measurement is inaccurate.

[0005] Therefore, it is necessary to provide an adaptive DC offset cancellation method for UWB receivers to solve the above problems. Summary of the Invention

[0006] This application provides an adaptive DC offset cancellation method for UWB receivers, which effectively and adaptively cancels DC offset by processing ADC sampled data through two paths.

[0007] This application provides an adaptive DC offset cancellation method for a UWB receiver, the method comprising:

[0008] After performing a first path processing on the multi-channel ADC sampling data, the first sampling data is obtained. This first path processing includes directly entering the DC estimation loop, sequentially passing through multi-channel summation and downsampling, a first-order differential, a leakage integrator, and a ΣΔ error feedback cutoff. The channel summation and downsampling are used to merge the multi-channel ADC sampling data and reduce the data rate to save dynamic power consumption in subsequent modules. The transfer function of the first-order differential is... The system is used to extract low-frequency components near DC and filter out high-frequency components in the signal to avoid useful signals interfering with DC estimation; the leakage integrator is a first-order IIR low-pass filter used to smooth the integration of the difference results to extract a stable DC estimate; the ΣΔ error feedback truncation is used to maintain high accuracy under narrow output bit width constraints.

[0009] The second sampling data is obtained by performing a second path processing on the multi-channel ADC sampling data. The second path processing includes delaying the multi-channel ADC sampling data by one clock cycle through a delay register to compensate for the pipeline delay of the DC estimation loop.

[0010] The first sampled data and the second sampled data are subtracted in the subtractor to obtain a clean signal after DC correction.

[0011] Preferably, the clean signal after DC correction enters the AGC path, the Sync path, and the RSSI path;

[0012] The AGC path is used for high 7-bit truncation for automatic gain control, discarding LSBs to suppress irrelevant noise;

[0013] The Sync path is used for the main receiving data demodulation path, and IQ amplitude mismatch compensation is superimposed.

[0014] The RSSI path is used to receive signal strength measurements and is updated only when rssi_work_flag is valid.

[0015] Preferably, the leakage integrator provides a dynamically adjustable α parameter value through a first control signal and a second control signal;

[0016] The first control signal is used to control three parameters: α_start, α_step, and α_stop. The value of the α parameter starts from a preset initial value α_start and increases by a fixed step size α_step every clock cycle until it reaches a preset final value α_stop and remains unchanged.

[0017] Preferably, when the second control signal is enabled, α is immediately and unconditionally reset to α_start, and the incrementing process of α_start→α_stop restarts on the new antenna link.

[0018] Preferably, when the current lead code detection is not completed, the DC estimation loop operates normally, performing real-time DC estimation and tracking on the multi-channel ADC sampling data;

[0019] Once the current preamble detection is successful, the behavior of the DC estimation loop is determined by a configurable register;

[0020] If the register is enabled, the DC estimation loop continues to receive the multi-channel ADC sampling data and track normally;

[0021] If the register is deenabled, the input path of the DC estimation loop is closed, and the leakage integrator maintains the currently converged DC estimate and no longer updates it.

[0022] Preferably, the non-AOA angle measurement mode is entered when there is only one antenna or the antenna is not switched.

[0023] When the current preamble detection is not completed, the DC estimation loop operates normally, performing real-time DC estimation and tracking on the multi-channel ADC sampling data; the first control signal is used to control three parameters: α_start, α_step, and α_stop. The value of the α parameter starts from the preset initial value α_start and increases by a fixed step size α_step in each clock cycle until it reaches the preset final value α_stop and remains unchanged.

[0024] After the current preamble detection is successful, the behavior of the DC estimation loop is determined by a configurable register. If the register is enabled, the DC estimation loop continues to receive the multi-channel ADC sampling data and track normally. If the register is deenabled, the input path of the DC estimation loop is closed, and the leakage integrator maintains the currently converged DC estimate and no longer updates.

[0025] Preferably, the AOA angle measurement mode is entered during rapid switching of multiple antennas;

[0026] When the current preamble detection is not completed, the DC estimation loop operates normally, performing real-time DC estimation and tracking on the multi-channel ADC sampling data; the first control signal is used to control three parameters: α_start, α_step, and α_stop. The value of the α parameter starts from the preset initial value α_start and increases by a fixed step size α_step in each clock cycle until it reaches the preset final value α_stop and remains unchanged.

[0027] After the current preamble detection is successful, the behavior of the DC estimation loop is determined by a configurable register. If the register is enabled, the DC estimation loop continues to receive the multi-channel ADC sampling data and track normally. If the register is deenabled, the input path of the DC estimation loop is closed, and the leakage integrator maintains the currently converged DC estimate value and no longer updates.

[0028] When the second control signal is enabled, α is immediately and unconditionally reset to α_start, and the incrementing process of α_start→α_stop restarts on the new antenna link.

[0029] Preferably, the final output value of the ΣΔ error feedback cutoff is calculated using the following formula:

[0030] y[n] = Q{u[n]},

[0031] Where y[n] is the final output value of the ΣΔ error feedback truncation, and Q{u[n]} is the superposition result u[n] fed into the truncation unit Q for bit width reduction;

[0032] The superposition result u[n] is calculated using the following formula:

[0033] u[n] = x[n] + e[n-1],

[0034] Where x[n] is the input of the ΣΔ truncation module, e[n-1] is the truncation error of the previous step, and u[n] is the result of e[n-1] being fed back to the input after a one-step delay and superimposed on x[n] at the adder Σ.

[0035] Preferably, the truncation unit Q is first biased by half an LSB before truncation, so that the mean value of the truncation error is zero.

[0036] Preferably, the output terminal is equipped with saturation protection logic. When the truncation result exceeds the representable range of the target bit width, the output is clamped to the maximum / minimum value to prevent overflow propagation from affecting subsequent paths.

[0037] This application offers the following advantages over existing technologies: It provides an adaptive DC offset cancellation method for a UWB receiver. The method includes: performing a first path processing on multi-channel ADC sampling data to obtain first sampled data. The first path processing includes directly entering a DC estimation loop, sequentially passing through multi-channel summation and downsampling, a first-order differential, a leakage integrator, and a ΣΔ error feedback truncation. The channel summation and downsampling are used to merge the multi-channel ADC sampling data and reduce the data rate to save dynamic power consumption in subsequent modules. The transfer function of the first-order differential is... The system extracts low-frequency components near DC and filters out high-frequency components in the signal to avoid useful signals interfering with DC estimation. The leakage integrator is a first-order IIR low-pass filter used to smooth the integration of the differential result to extract a stable DC estimate. The ΣΔ error feedback cutoff is used to maintain high accuracy under narrow output bit width constraints. The second sampling data is obtained after the multi-channel ADC sampling data is processed by a second path. The second path processing includes delaying the multi-channel ADC sampling data by one clock cycle through a delay register to compensate for the pipeline delay of the DC estimation loop. The first sampling data and the second sampling data are subtracted in a subtractor to obtain a clean signal after DC correction. By processing the ADC sampling data through two paths, DC offset is effectively and adaptively eliminated.

[0038] Furthermore, the leakage integrator provides dynamically adjustable α parameter values ​​through a first control signal and a second control signal; the first control signal is used to control three parameters: α_start, α_step, and α_stop. The α parameter value starts from a preset initial value α_start and increases by a fixed step size α_step each clock cycle until it reaches a preset final value α_stop and remains unchanged. Through the automatic increment strategy of α, it is equivalent to fast convergence with small α in the initial stage and high-precision tracking with large α in steady state. The convergence curve is predictable and no DC amplitude detection circuit is required.

[0039] Furthermore, when the second control signal is set to valid, α is immediately and unconditionally reset to α_start, and the increment process of α_start→α_stop is restarted on the new antenna link. At the moment of antenna switching, α is immediately reset to α_start, and re-convergence is completed in conjunction with the guard interval in the frame structure, thus eliminating the demodulation blind zone introduced by antenna switching.

[0040] Furthermore, when the current preamble detection is not completed, the DC estimation loop operates normally, performing real-time DC estimation and tracking of the multi-channel ADC sampling data; after the current preamble detection is successful, the behavior of the DC estimation loop is determined by a configurable register; if the register is enabled, the DC estimation loop continues to receive the multi-channel ADC sampling data and track normally; if the register is deenabled, the input path of the DC estimation loop is closed, and the leakage integrator maintains the currently converged DC estimation value and no longer updates, allowing for flexible selection of power-saving mode or dynamic tracking mode. Attached Figure Description

[0041] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0042] Figure 1This is a flowchart illustrating an adaptive DC offset cancellation method for a UWB receiver in an embodiment of this application.

[0043] Figure 2 This is the overall architecture of the DC offset cancellation module in an adaptive DC offset cancellation method for a UWB receiver according to an embodiment of this application;

[0044] Figure 3 This is a schematic diagram of the adaptive α parameter profile in an adaptive DC offset cancellation method for a UWB receiver according to an embodiment of this application.

[0045] Figure 4 This is a timing diagram illustrating the linkage between DC estimation and UWB frame structure in an adaptive DC offset cancellation method for a UWB receiver according to an embodiment of this application.

[0046] Figure 5 This is a schematic diagram of the ΣΔ error feedback truncation structure in an adaptive DC offset cancellation method for a UWB receiver according to an embodiment of this application.

[0047] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0048] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0049] To address the aforementioned issues, this application provides an adaptive DC offset cancellation method for UWB receivers, which effectively and adaptively eliminates DC offset by processing ADC sampled data through two paths.

[0050] Figure 1 This is a flowchart illustrating an adaptive DC offset cancellation method for a UWB receiver according to an embodiment of this application. Figure 2 This is the overall architecture of the DC offset cancellation module in an adaptive DC offset cancellation method for a UWB receiver, as described in an embodiment of this application. Now refer to... Figure 1 and Figure 2 This invention provides an adaptive DC offset cancellation method for a UWB receiver, the method comprising:

[0051] Step S101: After performing first path processing on the multi-channel ADC sampling data, first sampling data is obtained. The first path processing includes directly entering the DC estimation loop, sequentially passing through multi-channel summation and downsampling, a first-order differential, a leakage integrator, and a ΣΔ error feedback cutoff. The channel summation and downsampling are used to merge the multi-channel ADC sampling data and reduce the data rate to save dynamic power consumption of subsequent modules. The transfer function of the first-order differential is... The system is used to extract low-frequency components near DC and filter out high-frequency components in the signal to avoid useful signals interfering with DC estimation; the leakage integrator is a first-order IIR low-pass filter used to smooth the integration of the difference results to extract a stable DC estimate; the ΣΔ error feedback truncation is used to maintain high accuracy under narrow output bit width constraints.

[0052] Step S102: The multi-channel ADC sampling data is processed by the second path to obtain the second sampling data. The second path processing includes delaying the multi-channel ADC sampling data by one clock cycle through the delay register to compensate for the pipeline delay of the DC estimation loop.

[0053] Step S103: The first sampled data and the second sampled data are subtracted in the subtractor to obtain a clean signal after DC correction.

[0054] Specifically, the DC offset cancellation module includes a multi-channel ADC input interface, a delay register, a DC estimation loop, an adaptive α control module, a subtraction correction circuit, and three parallel output paths. The DC estimation loop includes multi-channel summation and downsampling, a differential converter, a leakage integrator, and a ΣΔ error feedback truncation module. The three parallel output paths include AGC, Sync, and RSSI.

[0055] The multi-channel ADC sampled data is processed through two paths: the first path directly enters the DC estimation loop, sequentially passing through multi-channel summation and downsampling, a first-order differential, a leakage integrator, and a ΣΔ error feedback truncation; the second path delays the ADC data by one clock cycle through a delay register to compensate for the pipeline delay of the DC estimation loop, ensuring strict alignment with dc_est. The aligned delayed data is subtracted from dc_est in a subtractor to obtain the DC-corrected clean signal, which is then fed into the AGC path, Sync path, and RSSI path, respectively.

[0056] The adaptive α control module receives two external control signals, α_cfg and ant_switch, to provide the leakage integrator with dynamically adjustable α parameter values ​​in real time.

[0057] In practice, the clean signal after DC correction enters the AGC path, the Sync path, and the RSSI path;

[0058] The AGC path is used for high 7-bit truncation for automatic gain control, discarding LSBs to suppress irrelevant noise;

[0059] The Sync path is used for the main receiving data demodulation path, and IQ amplitude mismatch compensation is superimposed.

[0060] The RSSI path is used to receive signal strength measurements and is updated only when rssi_work_flag is valid.

[0061] In specific implementation, the leakage integrator provides a dynamically adjustable α parameter value through a first control signal and a second control signal;

[0062] The first control signal is used to control three parameters: α_start, α_step, and α_stop. The value of the α parameter starts from a preset initial value α_start and increases by a fixed step size α_step every clock cycle until it reaches a preset final value α_stop and remains unchanged.

[0063] Specifically, the z-domain transfer function of the leakage integrator is: The parameter α is the core factor determining the loop's dynamic characteristics. When α is close to 0, the poles are near the origin of the unit circle, resulting in a wide loop passband and fast DC estimation that tracks input changes, but insufficient noise suppression in steady state. When α is close to 1, the poles are near the edge of the unit circle, resulting in an extremely narrow passband and very smooth steady-state estimate, but an extremely slow response. An open-loop control strategy with a fixed step size and automatic increment is employed. Because the step size is fixed, the curve of α changing over time is completely predictable, eliminating the need for any additional DC amplitude detection circuitry and minimizing hardware overhead.

[0064] In practice, when the second control signal is enabled, α is immediately and unconditionally reset to α_start, and the incrementing process of α_start→α_stop restarts on the new antenna link.

[0065] Specifically, the three parameters α_start, α_step, and α_stop can all be set in registers through the α_cfg configuration interface, flexibly adapting to different numbers of antennas and different chip process deviation ranges.

[0066] Figure 3 This is a schematic diagram of the adaptive α parameter profile in an adaptive DC offset cancellation method for a UWB receiver according to an embodiment of this application, as shown below. Figure 3As shown, during the Preamble phase, α increases rapidly from α_start, converging and stabilizing near the α_stop value before successful Preamble Detection (PD). During the SFD (Start of Frame Delimiter) and DATA (Data Payload) phases, α remains at α_stop, and the DC loop is equivalent to an extremely narrow-band fixed-parameter filter, providing optimal steady-state estimation accuracy. When antenna switching occurs, α drops sharply to α_start, and then rapidly reconverges within the subsequent guard interval (gap), ensuring that the data demodulation of the new antenna link is unaffected by the DC offset.

[0067] In practice, when the current lead code detection is not completed, the DC estimation loop operates normally, performing real-time DC estimation and tracking on the multi-channel ADC sampling data;

[0068] Once the current preamble detection is successful, the behavior of the DC estimation loop is determined by a configurable register;

[0069] If the register is enabled, the DC estimation loop continues to receive the multi-channel ADC sampling data and track normally;

[0070] If this register is deenabled, the input path of the DC estimation loop is closed, and the leakage integrator maintains the currently converged DC estimate and no longer updates. This mechanism allows the same hardware to be flexibly switched between different application scenarios, including short / long packets and low power / high tracking accuracy.

[0071] Figure 4 This is a timing diagram illustrating the linkage between DC estimation and UWB frame structure in an adaptive DC offset cancellation method for a UWB receiver according to an embodiment of this application. (See now) Figure 4 In practice, when there is only one antenna or the antenna is not switched, it enters a non-AOA angle measurement mode.

[0072] When the current preamble detection is not completed, the DC estimation loop operates normally, performing real-time DC estimation and tracking on the multi-channel ADC sampling data; the first control signal is used to control three parameters: α_start, α_step, and α_stop. The value of the α parameter starts from the preset initial value α_start and increases by a fixed step size α_step in each clock cycle until it reaches the preset final value α_stop and remains unchanged.

[0073] After the current preamble detection is successful, the behavior of the DC estimation loop is determined by a configurable register. If the register is enabled, the DC estimation loop continues to receive the multi-channel ADC sampling data and track normally. If the register is deenabled, the input path of the DC estimation loop is closed, and the leakage integrator maintains the currently converged DC estimate and no longer updates.

[0074] In the SFD and DATA phases, if the freeze mode is used, the DC correction value remains fixed to minimize dynamic power consumption; if the dynamic tracking mode is used, the slow drift is continuously tracked with an extremely narrow bandwidth of α_stop.

[0075] In practice, the AOA angle measurement mode is entered when multiple antennas switch rapidly.

[0076] When the current preamble detection is not completed, the DC estimation loop operates normally, performing real-time DC estimation and tracking on the multi-channel ADC sampling data; the first control signal is used to control three parameters: α_start, α_step, and α_stop. The value of the α parameter starts from the preset initial value α_start and increases by a fixed step size α_step in each clock cycle until it reaches the preset final value α_stop and remains unchanged.

[0077] After the current preamble detection is successful, the behavior of the DC estimation loop is determined by a configurable register. If the register is enabled, the DC estimation loop continues to receive the multi-channel ADC sampling data and track normally. If the register is deenabled, the input path of the DC estimation loop is closed, and the leakage integrator maintains the currently converged DC estimate value and no longer updates.

[0078] When the second control signal is enabled, α is immediately and unconditionally reset to α_start, and the incrementing process of α_start→α_stop restarts on the new antenna link.

[0079] In the STS (Secure Training Sequence) and subsequent DATA phases, configurable registers are enabled, and the DC loop maintains dynamic tracking mode throughout, ensuring that DC correction remains accurate during demodulation of each antenna link.

[0080] Figure 5 This is a schematic diagram of the ΣΔ error feedback truncation structure in an adaptive DC offset cancellation method for a UWB receiver according to an embodiment of this application. See now. Figure 5 In specific implementation, the final output value of the ΣΔ error feedback cutoff is calculated using the following formula:

[0081] y[n] = Q{u[n]},

[0082] Where y[n] is the final output value of the ΣΔ error feedback truncation, and Q{u[n]} is the superposition result u[n] fed into the truncation unit Q for bit width reduction;

[0083] The superposition result u[n] is calculated using the following formula:

[0084] u[n] = x[n] + e[n-1],

[0085] Where x[n] is the input of the ΣΔ truncation module, e[n-1] is the truncation error of the previous step, and u[n] is the result of e[n-1] being fed back to the input after a one-step delay and superimposed on x[n] at the adder Σ.

[0086] By introducing a first-order ΣΔ error feedback structure between the output of the full-precision leakage integrator and the final output of the narrow-bit-width DC estimation, the quantization noise generated by the truncation is pushed from the low-frequency region to the high-frequency region using the principle of noise shaping. This maintains high precision at low frequencies (near DC) under the constraint of a narrow output bit width. The typical bit width of the full-precision leakage integrator output is on the order of 24 bits, and the typical target bit width of the final output of the narrow-bit-width DC estimation is on the order of 10 bits.

[0087] The input x[n] of the ΣΔ truncation module is the raw output of the leakage integrator, carrying complete DC estimation information. e[n-1] is the truncation error (full precision) of the previous cycle, which is fed back to the input after a one-cycle delay and superimposed on x[n] at the adder Σ. The superposition result u[n] is fed into the truncation module Q for bit width reduction, outputting the final value y[n]. At the same time, the truncation module Q generates the error signal e[n] = u[n] - y[n] for the current cycle, which is stored in the delay unit for use in the next cycle. Among them, the input x[n], i.e. s_filt_out, is the full precision bit width, typically 24-bit, and the output final value y[n], i.e. s_dc_corr / dc_est, is the narrow bit width, typically 10-bit.

[0088] In practice, the truncation unit Q is first biased by half an LSB before truncation, so that the mean value of the truncation error is zero.

[0089] In practical implementation, the output is equipped with saturation protection logic. When the truncation result exceeds the representable range of the target bit width, the output is clamped to the maximum / minimum value to prevent overflow propagation from affecting subsequent paths.

[0090] A z-transform analysis of the system yields the following results: The noise transfer function It exhibits first-order high-pass characteristics—the NTF is zero at DC (z=1), and the quantization error is completely suppressed; as the frequency increases, the NTF gradually increases, and the quantization noise is pushed to higher frequencies. In DC estimation applications, the effective bandwidth of the leakage integrator is located in a very low frequency range near DC, so first-order ΣΔ shaping is sufficient to suppress the quantization noise in this frequency band to a level far below that of the direct truncation. The effective bandwidth of the leakage integrator is determined by α_stop.

[0091] First-order ΣΔ truncation can increase the effective number of bits near DC by about 3-4 bits compared to direct truncation. Compared to directly using full-precision paths, the bit width of both the accumulator and multiplier can be reduced, resulting in area and power savings of about 30%-40%.

[0092] In summary, this application provides an adaptive DC offset cancellation method for a UWB receiver. The method includes: performing a first path processing on multi-channel ADC sampled data to obtain first sampled data. The first path processing includes directly entering a DC estimation loop, sequentially passing through multi-channel summation and downsampling, a first-order differential, a leakage integrator, and a ΣΔ error feedback truncation. The channel summation and downsampling are used to merge the multi-channel ADC sampled data and reduce the data rate to save dynamic power consumption in subsequent modules. The transfer function of the first-order differential is... The system extracts low-frequency components near DC and filters out high-frequency components in the signal to avoid useful signals interfering with DC estimation. The leakage integrator is a first-order IIR low-pass filter used to smooth the integration of the differential result to extract a stable DC estimate. The ΣΔ error feedback cutoff is used to maintain high accuracy under narrow output bit width constraints. The second sampling data is obtained after the multi-channel ADC sampling data is processed by a second path. The second path processing includes delaying the multi-channel ADC sampling data by one clock cycle through a delay register to compensate for the pipeline delay of the DC estimation loop. The first sampling data and the second sampling data are subtracted in a subtractor to obtain a clean signal after DC correction. By processing the ADC sampling data through two paths, DC offset is effectively and adaptively eliminated.

[0093] Furthermore, the leakage integrator provides dynamically adjustable α parameter values ​​through a first control signal and a second control signal; the first control signal is used to control three parameters: α_start, α_step, and α_stop. The α parameter value starts from a preset initial value α_start and increases by a fixed step size α_step each clock cycle until it reaches a preset final value α_stop and remains unchanged. Through the automatic increment strategy of α, it is equivalent to fast convergence with small α in the initial stage and high-precision tracking with large α in steady state. The convergence curve is predictable and no DC amplitude detection circuit is required.

[0094] Furthermore, when the second control signal is set to valid, α is immediately and unconditionally reset to α_start, and the increment process of α_start→α_stop is restarted on the new antenna link. At the moment of antenna switching, α is immediately reset to α_start, and re-convergence is completed in conjunction with the guard interval in the frame structure, thus eliminating the demodulation blind zone introduced by antenna switching.

[0095] Furthermore, when the current preamble detection is not completed, the DC estimation loop operates normally, performing real-time DC estimation and tracking of the multi-channel ADC sampling data; after the current preamble detection is successful, the behavior of the DC estimation loop is determined by a configurable register; if the register is enabled, the DC estimation loop continues to receive the multi-channel ADC sampling data and track normally; if the register is deenabled, the input path of the DC estimation loop is closed, and the leakage integrator maintains the currently converged DC estimation value and no longer updates, allowing for flexible selection of power-saving mode or dynamic tracking mode.

[0096] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the claims.

[0097] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. An adaptive DC offset cancellation method for a UWB receiver, characterized in that, The method includes: After performing a first path processing on the multi-channel ADC sampling data, the first sampling data is obtained. This first path processing includes directly entering the DC estimation loop, sequentially passing through multi-channel summation and downsampling, a first-order differential, a leakage integrator, and a ΣΔ error feedback cutoff. The channel summation and downsampling are used to merge the multi-channel ADC sampling data and reduce the data rate to save dynamic power consumption in subsequent modules. The transfer function of the first-order differential is... The system is used to extract low-frequency components near DC and filter out high-frequency components in the signal to avoid useful signals interfering with DC estimation; the leakage integrator is a first-order IIR low-pass filter used to smooth the integration of the difference results to extract a stable DC estimate; the ΣΔ error feedback truncation is used to maintain high accuracy under narrow output bit width constraints. The second sampling data is obtained by performing a second path processing on the multi-channel ADC sampling data. The second path processing includes delaying the multi-channel ADC sampling data by one clock cycle through a delay register to compensate for the pipeline delay of the DC estimation loop. The first sampled data and the second sampled data are subtracted in the subtractor to obtain a clean signal after DC correction.

2. The adaptive DC offset cancellation method for a UWB receiver according to claim 1, characterized in that, The clean signal after DC correction enters the AGC path, Sync path, and RSSI path; The AGC path is used for high 7-bit truncation for automatic gain control, discarding LSBs to suppress irrelevant noise; The Sync path is used for the main receiving data demodulation path, and IQ amplitude mismatch compensation is superimposed. The RSSI path is used to receive signal strength measurements and is updated only when rssi_work_flag is valid.

3. The adaptive DC offset cancellation method for a UWB receiver according to claim 1, characterized in that, The leakage integrator provides a dynamically adjustable α parameter value through a first control signal and a second control signal; The first control signal is used to control three parameters: α_start, α_step, and α_stop. The value of the α parameter starts from a preset initial value α_start and increases by a fixed step size α_step every clock cycle until it reaches a preset final value α_stop and remains unchanged.

4. The adaptive DC offset cancellation method for a UWB receiver according to claim 3, characterized in that, When the second control signal is enabled, α is immediately and unconditionally reset to α_start, and the incrementing process of α_start→α_stop restarts on the new antenna link.

5. The adaptive DC offset cancellation method for a UWB receiver according to claim 1, characterized in that, While the current lead code detection is not complete, the DC estimation loop operates normally, performing real-time DC estimation and tracking on the multi-channel ADC sampled data; Once the current preamble detection is successful, the behavior of the DC estimation loop is determined by a configurable register; If the register is enabled, the DC estimation loop continues to receive the multi-channel ADC sampling data and track normally; If the register is deenabled, the input path of the DC estimation loop is closed, and the leakage integrator maintains the currently converged DC estimate and no longer updates it.

6. The adaptive DC offset cancellation method for a UWB receiver according to claim 1, characterized in that, Enter non-AOA angle measurement mode when using a single antenna or without switching antennas; When the current preamble detection is not completed, the DC estimation loop operates normally, performing real-time DC estimation and tracking on the multi-channel ADC sampling data; the first control signal is used to control three parameters: α_start, α_step, and α_stop. The value of the α parameter starts from the preset initial value α_start and increases by a fixed step size α_step in each clock cycle until it reaches the preset final value α_stop and remains unchanged. After the current preamble detection is successful, the behavior of the DC estimation loop is determined by a configurable register; if the register is enabled, the DC estimation loop continues to receive the multi-channel ADC sampling data and track normally. If the register is deenabled, the input path of the DC estimation loop is closed, and the leakage integrator maintains the currently converged DC estimate and no longer updates it.

7. The adaptive DC offset cancellation method for a UWB receiver according to claim 1, characterized in that, Enter AOA angle measurement mode during rapid switching of multiple antennas; When the current preamble detection is not completed, the DC estimation loop operates normally, performing real-time DC estimation and tracking on the multi-channel ADC sampling data; the first control signal is used to control three parameters: α_start, α_step, and α_stop. The value of the α parameter starts from the preset initial value α_start and increases by a fixed step size α_step in each clock cycle until it reaches the preset final value α_stop and remains unchanged. After the current preamble detection is successful, the behavior of the DC estimation loop is determined by a configurable register; if the register is enabled, the DC estimation loop continues to receive the multi-channel ADC sampling data and track normally. If the register is deenabled, the input path of the DC estimation loop is closed, and the leakage integrator maintains the currently converged DC estimate and does not update it. When the second control signal is enabled, α is immediately and unconditionally reset to α_start, and the incrementing process of α_start→α_stop restarts on the new antenna link.

8. The adaptive DC offset cancellation method for a UWB receiver according to claim 1, characterized in that, The final output value of the ΣΔ error feedback cutoff is calculated using the following formula: y[n] = Q{u[n]}, Where y[n] is the final output value of the ΣΔ error feedback truncation, and Q{u[n]} is the superposition result u[n] fed into the truncation unit Q for bit width reduction; The superposition result u[n] is calculated using the following formula: u[n] = x[n] + e[n-1], Where x[n] is the input of the ΣΔ truncation module, e[n-1] is the truncation error of the previous step, and u[n] is the result of e[n-1] being fed back to the input after a one-step delay and superimposed on x[n] at the adder Σ.

9. The adaptive DC offset cancellation method for a UWB receiver according to claim 8, characterized in that, Before truncation, the truncation unit Q is first biased by half an LSB to make the mean value of the truncation error zero.

10. The adaptive DC offset cancellation method for a UWB receiver according to claim 9, characterized in that, The output is equipped with saturation protection logic. When the truncation result exceeds the representable range of the target bit width, the output is clamped to the maximum / minimum value to prevent overflow propagation from affecting subsequent paths.

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