A multi-station phase-by-phase automatic testing method and system for power communication modules

Abstract

The application relates to the technical field of power communication module testing, and discloses a multi-station phase-dividing automatic testing method and system for a power communication module, which comprises the following steps: a main control module searches a function pointer array according to a module type and a testing stage, and divides a time sequence in combination with a separator; an effective station is tested simultaneously in one time during a parallel section, and the effective station is serially traversed during a serial single-station section and a serial phase-dividing section; if a station fault is detected, corresponding bit positions are reset, and a disconnection instruction is issued to cut off the power supply of a sub-control module and a relay matrix; the application constructs an impedance isolation environment by controlling a switch matrix topology to switch through a bitmap register, effectively eliminates the conductive coupling crosstalk of a high-frequency carrier in a line, blocks the superposition of same-frequency radiation in space, improves the accuracy of a telecommunication signal strength indication measurement, and eliminates the cascade damage of abnormal current to adjacent measurement loops.

Description

Technical Field

[0001] This invention relates to an automated testing method and system for multi-station phase-separated testing of power communication modules, belonging to the field of power communication module testing technology. Background Technology

[0002] In the field of production line testing of dual-mode communication modules for low-voltage power distribution networks, low-voltage carrier communication, and wireless communication, the mainstream approach is to use an industrial control computer in conjunction with a multi-station fixture baseboard and a phase-splitting switch matrix to build a test topology. By loading high-frequency modulation signals onto AC conductors, the actual network coupling state is reproduced. The accuracy of electrical parameter acquisition and the stability of received signal strength indication depend on the physical isolation boundary maintained by each test circuit when high-voltage power is connected. Therefore, ensuring the discrete transmission of multi-channel signals in time and space constitutes the physical premise for obtaining a reliable measurement benchmark. As production lines evolve towards multi-channel, the circuit density increases due to multiple workstations being deployed within the same fixture. Each module generates electromagnetic intermodulation crosstalk due to sharing the low-voltage AC power supply network. At the same time, the disordered signal superposition occurs due to multiple wireless high-frequency radiations in a limited space. This electrical coupling interference causes waveform sampling distortion and time-varying deviations in the measurement benchmark. In particular, when an abnormal short circuit occurs at a workstation, the inrush current spreads along the shared line to the adjacent normal path, causing cascading burnout of the main control sampling board and adjacent modules, resulting in high maintenance costs and widespread timing deadlock.

[0003] To address carrier interference and fault propagation issues, conventional approaches typically involve adding isolation transformers or filters, or widening the spacing between workstations to reduce spatial radiation. However, adding magnetic components not only increases equipment costs and size, but their inherent inductive characteristics also cause signal phase lag, deteriorating the timing alignment accuracy required for precise phase-by-phase measurements. Furthermore, they cannot adaptively switch faulty loops, resulting in the following limitations of existing test paths: 1. Circuit coupling of multiple carrier signals in a shared loop and the radiation superposition of wireless signals in space lead to measurement distortion; 2. In multi-channel concurrent testing, the lack of real-time protection and physical isolation for sudden short-circuit modules easily leads to cascading damage to adjacent measurement workstations and the main control circuit; 3. The lack of a logical decoupling mechanism in the timing arrangement of multi-workstation measurement processes causes deadlock in the control state machine.

[0004] Therefore, the technical problem to be solved by this invention is how to eliminate carrier electromagnetic crosstalk in a shared distribution network through spatiotemporal collaborative isolation of software state variables and hardware relay matrices, and complete millisecond-level physical shutdown and bitmap removal of faulty workstations under analog dynamic monitoring feedback, thereby establishing a multi-channel phase-sequence measurement environment with high timing stability and all-time online self-healing. Summary of the Invention

[0005] To address the problems mentioned in the background art, the technical solution of the present invention is as follows: A multi-station phase-separated automated testing method for power communication modules, comprising the following steps: Step S101: The motherboard microprocessor obtains the type code of the module under test and the test stage flag, retrieves the target function pointer array based on the dual index of the type code of the module under test and the test stage flag, and divides the overall test timing into parallel segment, serial single-station segment and serial phase segment by embedding a stage separator in the address space of the target function pointer array. In step S102, the motherboard microprocessor initializes the workstation bitmap variable in memory, with each data bit of the workstation bitmap variable corresponding one-to-one with each workstation to be tested. In the parallel segment, the scheduling engine running by the motherboard microprocessor tests the valid workstations in the workstation bitmap variable simultaneously. In the serial single-workstation segment and the serial phase segment, the scheduling engine running by the motherboard microprocessor serially traverses the valid workstations in the workstation bitmap variable according to the workstation index. Step S103: When a short circuit, overcurrent, or communication timeout fault is detected in any of the above stages at the target workstation, the scheduling engine drives the target workstation to independently exit all subsequent test steps. The motherboard microprocessor resets the data bit in the workstation bitmap variable corresponding to the target workstation to an invalid state and sends a disconnect control word to the sub-board corresponding to the target workstation through the communication bus, driving the sub-board to shut down the independent power supply path and capacitor charging enable switch. The subsequent electrical variable acquisition process automatically skips the invalid workstation based on the updated workstation bitmap variable.

[0006] Preferably, when the overall test timing is in the serial single-station segment, step S101 includes the following sub-steps: Step S1011: Before entering the serial single-station segment, disconnect all phase relays of all valid stations in the test station bitmap variable at the end of the parallel segment; Step S1012: Direct the process pointer to the single-station functional test start mark and close all phase relays of the current station; Step S1013: Call the independent test step for the current station to carry out external version read / write comparison and extended function check. If the test result is a failure, the scheduling engine disconnects all phase relays and power supply path of the current station, updates the data bit corresponding to the current station in the station bitmap variable to an invalid state, and skips all tests of the current station in the serial phase segment. If the test is successful, proceed to the serial phase segment for the current station and complete the test steps for the serial phase segment; Step S1014: Regardless of whether the test result of the current station is successful or not, first disconnect all phase line relays of the current station, and then return to step S1012 to start traversing the next valid station until all valid stations have been traversed.

[0007] Preferably, in step S102, when the overall test timing is switched to the serial phase segment, for each target station that is valid in the station bitmap variable, the following sub-steps are included: Step S1021: The scheduling engine reads the phase enable mask and sequentially traverses the A phase line, B phase line, and C phase line. If the phase being traversed is in an inactive state in the phase enable mask, the phase being traversed is skipped directly; Step S1022: If the phase being traversed is in an active state in the phase enable mask, the relay group is controlled to switch, only the phase line relay and the common neutral line relay being engaged, and the remaining phase line relays being disengaged, so as to energize the current single-phase test circuit.

[0008] Preferably, after the motherboard microprocessor resets the data bit corresponding to the target workstation in the workstation bitmap variable to an invalid state, the following steps are also included: Step S104: The motherboard microprocessor establishes a topology communication link with the multi-channel daughterboard and the baseboard through the communication bus, and integrates the multi-channel analog quantity return, relay on / off status and transparent meter reading data into a unified discrete logic state stream.

[0009] Preferably, it also includes the following steps: Step S105: Equip each test station pin with an independent LED indicator path. When the corresponding channel is triggered to remove the station due to short circuit, overcurrent, or communication timeout, drive the LED indicator path to present optical status feedback.

[0010] Preferably, after the electrical variable acquisition process is completed, the following steps are also included: Step S106: Automatically extract the structured physical parameters of each channel and combine them to generate a formatted discrete test report, thereby realizing the recording of the interaction status between the electrical variable quantization parameters and the communication protocol.

[0011] Preferably, when the overall test timing is in the parallel segment in step S101, the following sub-steps are included: Step S1013: The motherboard microprocessor sends basic firmware data and broadcasts calibration instructions to all test stations that are valid in the workstation bitmap variables in parallel, driving the power communication modules on each test station to synchronously perform basic electrical quantity burning and calibration.

[0012] Preferably, step S103 for communication timeout fault includes the following steps: when the scheduling engine initiates a communication request, it starts a high-frequency timer and introduces a communication compensation factor to correct the processor context switching delay. If no response data packet from the power communication module is received when the timeout period reaches the timeout threshold corrected by the communication compensation factor, it is determined that a communication timeout fault has occurred at the current workstation.

[0013] Preferably, step S102 in the serial phase segment includes the following sub-steps: Step S1023: If all data bits in the workstation bitmap variable are reset to an invalid state, the scheduling engine disconnects the main power supply circuit of the base plate and outputs a process end command indicating that there are no valid workstations.

[0014] A multi-station phase-separated automated testing system for power communication modules includes a main control microprocessor module, a bus data transmission module, and a multi-channel sub-control sub-module. The main control microprocessor module is connected to the bus data transmission module, and the multi-channel sub-control module is connected to the main control microprocessor module through the bus data transmission module. The main control microprocessor module is used to obtain the type code of the module under test and the test phase flag, and retrieve the target function pointer array based on the dual index of the type code of the module under test and the test phase flag. By embedding a phase separator in the address space of the target function pointer array, the overall test timing is divided into parallel segments, serial single-station segments, and serial phase segments. The main control microprocessor module is also used to initialize station bitmap variables in memory, with each data bit of the station bitmap variable corresponding one-to-one with each station under test. The scheduling engine run by the main control microprocessor module is used to test the valid stations in the station bitmap variables simultaneously in the parallel segment. In the serial single-station segment and the serial phase segment, the valid stations in the station bitmap variables are traversed serially according to the station index. When a short circuit, overcurrent, or communication timeout fault is detected at any of the above stages at the target workstation, the scheduling engine is used to drive the target workstation to independently exit all subsequent test steps. The main control microprocessor module is used to reset the data bit corresponding to the target workstation in the workstation bitmap variable to an invalid state and send a disconnection control word to the sub-control sub-module corresponding to the target workstation through the bus data transmission module. The sub-control module corresponding to the target workstation is used to receive the disconnect control word and, in response to the disconnect control word, shut down the independent power supply branch and the capacitor charging enable path. The subsequent electrical variable acquisition process is automatically skipped by the main control microprocessor module based on the updated workstation bitmap variables.

[0015] Compared with the prior art, the beneficial effects of the present invention are: 1. The top plate relay matrix only engages the single-phase line relay and neutral line relay corresponding to the current test station within a specific time window, while the other two-phase line relays and all relays in other stations remain in the open state. This works in conjunction with the synchronous switching of the transmitting phase and wireless channel of the bottom plate controller. This spatiotemporal discrete control mechanism cuts off the conduction path of the shared live and neutral wire circuit, suppresses the circuit coupling of multi-channel high-frequency carrier signals in the shared electrical circuit, and blocks the superposition of co-frequency radiation in space. This ensures that the acquisition process of received signal strength indication, dynamic current, and topology parameters is within mutually independent physical boundaries, and the acquisition result corresponds to a unique test object, eliminating the intermodulation distortion caused by concurrent measurement at multiple stations.

[0016] 2. The motherboard microprocessor continuously collects the power-on short-circuit current and charging current of the module under test via analog sensors. When the software determines that the current exceeds the set safety threshold, the scheduling engine rewrites the corresponding bit in the bitmap variable, resets it to an invalid state, and sends a disconnect control word to the corresponding workstation's daughterboard via the communication bus. The daughterboard receives the disconnect control word and completely shuts down the independent power supply path and the capacitor charging enable switch, so that the local circuit with the electrical short-circuit fault is physically isolated in the measurement process. Subsequent electrical variable acquisition processes automatically skip the failed workstation based on the updated bitmap variable, preventing abnormal current from causing cascading damage to adjacent measurement circuits.

[0017] 3. Based on the dual indexing of the module under test type code and the test phase flag, the target function pointer array is located. A segmentation isolation separator is embedded in a specific address space of the array. The scheduling engine is driven to divide the overall test sequence into parallel segments, serial single-station segments, and serial phase segments on the time axis. This timing arrangement architecture decouples the static basic electrical quantity burning and calibration from the high-frequency phase communication test in terms of control logic. When a phase test step of a certain station fails partially, the scheduling engine drives the station to independently exit the phase loop and sends a control word to the sub-board to set all relays to the open state at once. This effectively prevents the measurement state machine from deadlocking and maintains the determinism of the multi-channel measurement process. Attached Figure Description

[0018] Figure 1 This is a flowchart of the dual-index timing control and fault station removal process of the present invention; Figure 2 This is a schematic diagram of the topology of the main control and sub-control modules of the present invention.

[0019] The objectives, features, and advantages of this invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0020] The technical solutions of the embodiments of this application will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of this application are within the scope of protection of this application.

[0021] A multi-station phase-separated automated testing method for power communication modules includes the following steps: Step S101: The motherboard microprocessor obtains the type code of the module under test and the test stage flag, retrieves the target function pointer array based on the dual index of the type code of the module under test and the test stage flag, and divides the overall test timing into parallel segment, serial single-station segment and serial phase segment by embedding a stage separator in the address space of the target function pointer array. In step S102, the motherboard microprocessor initializes the workstation bitmap variable in memory, with each data bit of the workstation bitmap variable corresponding one-to-one with each workstation to be tested. In the parallel segment, the scheduling engine running by the motherboard microprocessor tests the valid workstations in the workstation bitmap variable simultaneously. In the serial single-workstation segment and the serial phase segment, the scheduling engine running by the motherboard microprocessor serially traverses the valid workstations in the workstation bitmap variable according to the workstation index. Step S103: When a short circuit, overcurrent, or communication timeout fault is detected in any of the above stages at the target workstation, the scheduling engine drives the target workstation to independently exit all subsequent test steps. The motherboard microprocessor resets the data bit in the workstation bitmap variable corresponding to the target workstation to an invalid state and sends a disconnect control word to the sub-board corresponding to the target workstation through the communication bus, driving the sub-board to shut down the independent power supply path and capacitor charging enable switch. The subsequent electrical variable acquisition process automatically skips the invalid workstation based on the updated workstation bitmap variable.

[0022] Preferably, when the overall test timing is in the serial single-station segment, step S101 includes the following sub-steps: Step S1011: Before entering the serial single-station segment, disconnect all phase relays of all valid stations in the test station bitmap variable at the end of the parallel segment; Step S1012: Direct the process pointer to the single-station functional test start mark and close all phase relays of the current station; Step S1013: Call the independent test step for the current station to carry out external version read / write comparison and extended function check. If the test result is a failure, the scheduling engine disconnects all phase relays and power supply path of the current station, updates the data bit corresponding to the current station in the station bitmap variable to an invalid state, and skips all tests of the current station in the serial phase segment. If the test is successful, proceed to the serial phase segment for the current station and complete the test steps for the serial phase segment; Step S1014: Regardless of whether the test result of the current station is successful or not, first disconnect all phase line relays of the current station, and then return to step S1012 to start traversing the next valid station until all valid stations have been traversed.

[0023] Preferably, in step S102, when the overall test timing is switched to the serial phase segment, for each target station that is valid in the station bitmap variable, the following sub-steps are included: Step S1021: The scheduling engine reads the phase enable mask and sequentially traverses the A phase line, B phase line, and C phase line. If the phase being traversed is in an inactive state in the phase enable mask, the phase being traversed is skipped directly; Step S1022: If the phase being traversed is in an active state in the phase enable mask, the relay group is controlled to switch, only the phase line relay and the common neutral line relay being engaged, and the remaining phase line relays being disengaged, so as to energize the current single-phase test circuit.

[0024] Preferably, after the motherboard microprocessor resets the data bit corresponding to the target workstation in the workstation bitmap variable to an invalid state, the following steps are also included: Step S104: The motherboard microprocessor establishes a topology communication link with the multi-channel daughterboard and the baseboard through the communication bus, and integrates the multi-channel analog quantity return, relay on / off status and transparent meter reading data into a unified discrete logic state stream.

[0025] Preferably, it also includes the following steps: Step S105: Equip each test station pin with an independent LED indicator path. When the corresponding channel is triggered to remove the station due to short circuit, overcurrent, or communication timeout, drive the LED indicator path to present optical status feedback.

[0026] Preferably, after the electrical variable acquisition process is completed, the following steps are also included: Step S106: Automatically extract the structured physical parameters of each channel and combine them to generate a formatted discrete test report, thereby realizing the recording of the interaction status between the electrical variable quantization parameters and the communication protocol.

[0027] Preferably, when the overall test timing is in the parallel segment in step S101, the following sub-steps are included: Step S1013: The motherboard microprocessor sends basic firmware data and broadcasts calibration instructions to all test stations that are valid in the workstation bitmap variables in parallel, driving the power communication modules on each test station to synchronously perform basic electrical quantity burning and calibration.

[0028] Preferably, step S103 for communication timeout fault includes the following steps: when the scheduling engine initiates a communication request, it starts a high-frequency timer and introduces a communication compensation factor to correct the processor context switching delay. If no response data packet from the power communication module is received when the timeout period reaches the timeout threshold corrected by the communication compensation factor, it is determined that a communication timeout fault has occurred at the current workstation.

[0029] Preferably, step S102 in the serial phase segment includes the following sub-steps: Step S1023: If all data bits in the workstation bitmap variable are reset to an invalid state, the scheduling engine disconnects the main power supply circuit of the base plate and outputs a process end command indicating that there are no valid workstations.

[0030] A multi-station phase-separated automated testing system for power communication modules includes a main control microprocessor module, a bus data transmission module, and a multi-channel sub-control sub-module. The main control microprocessor module is connected to the bus data transmission module, and the multi-channel sub-control module is connected to the main control microprocessor module through the bus data transmission module. The main control microprocessor module is used to obtain the type code of the module under test and the test phase flag, and retrieve the target function pointer array based on the dual index of the type code of the module under test and the test phase flag. By embedding a phase separator in the address space of the target function pointer array, the overall test timing is divided into parallel segments, serial single-station segments, and serial phase segments. The main control microprocessor module is also used to initialize station bitmap variables in memory, with each data bit of the station bitmap variable corresponding one-to-one with each station under test. The scheduling engine run by the main control microprocessor module is used to test the valid stations in the station bitmap variables simultaneously in the parallel segment. In the serial single-station segment and the serial phase segment, the valid stations in the station bitmap variables are traversed serially according to the station index. When a short circuit, overcurrent, or communication timeout fault is detected at any of the above stages at the target workstation, the scheduling engine is used to drive the target workstation to independently exit all subsequent test steps. The main control microprocessor module is used to reset the data bit corresponding to the target workstation in the workstation bitmap variable to an invalid state and send a disconnection control word to the sub-control sub-module corresponding to the target workstation through the bus data transmission module. The sub-control module corresponding to the target workstation is used to receive the disconnect control word and, in response to the disconnect control word, shut down the independent power supply branch and the capacitor charging enable path. The subsequent electrical variable acquisition process is automatically skipped by the main control microprocessor module based on the updated workstation bitmap variables.

[0031] Example 1: This example combines Figures 1 to 2 This document describes a multi-station phase-separated automated testing method and system for power communication modules, such as... Figure 1 As shown, in the automated testing method flow, in step S101, the motherboard microprocessor obtains the type code of the module under test and the test stage flag, retrieves the target function pointer array based on the dual index of the type code of the module under test and the test stage flag, and divides the overall test timing into parallel segments, serial single-station segments and serial phase segments by embedding stage separators in the address space of the target function pointer array. Then, in step S102, the motherboard microprocessor initializes the station bitmap variable in memory, and each data bit of the station bitmap variable corresponds one-to-one with each station under test. In the parallel segment, the scheduling engine, run by the motherboard microprocessor, tests the valid workstations in the workstation bitmap variable simultaneously. In the serial single-workstation segment and the serial phase segment, the scheduling engine, run by the motherboard microprocessor, serially traverses the valid workstations in the workstation bitmap variable according to the workstation index. Then, in step S103, when a short circuit, overcurrent, or communication timeout fault is detected in any of the above stages of the target workstation, the scheduling engine drives the target workstation to independently exit all subsequent test steps. The motherboard microprocessor resets the corresponding data bit to an invalid state and sends a disconnect control word to the corresponding daughterboard through the communication bus, driving the daughterboard to shut down the independent power supply path and capacitor charging enable switch, so that the subsequent process automatically skips invalid workstations based on the updated bitmap variable.

[0032] like Figure 2 As shown, in the overall module topology and data flow of the system, the test phase flag is input to the motherboard microprocessor and the target function pointer array, respectively. The motherboard microprocessor points to the code of the module under test, and the code of the module under test is input to the target function pointer array. The motherboard microprocessor also points to the station bitmap variable. The station bitmap variable, the target function pointer array, and the phase enable mask are input to the scheduling engine, respectively. The motherboard microprocessor and the scheduling engine transmit control instructions and status data to the bus data transmission module. The bus data transmission module distributes the received signals to the multi-channel control sub-module. The multi-channel control sub-module is connected to the independent power supply path, the capacitor charging enable switch, and the relay matrix, respectively, and implements control. The output terminals of the independent power supply path and the capacitor charging enable switch are connected to the station under test. The output terminals of the station under test and the relay matrix work together in the impedance isolation environment. Finally, the impedance isolation environment outputs a formatted discrete test report.

[0033] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the present invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the present invention.

[0034] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention.

Claims

1. A multi-station phase-separated automated testing method for power communication modules, characterized in that, Includes the following steps: Step S101: The motherboard microprocessor obtains the type code of the module under test and the test stage flag, retrieves the target function pointer array based on the dual index of the type code of the module under test and the test stage flag, and divides the overall test timing into parallel segment, serial single-station segment and serial phase segment by embedding a stage separator in the address space of the target function pointer array. In step S102, the motherboard microprocessor initializes the workstation bitmap variable in memory, with each data bit of the workstation bitmap variable corresponding one-to-one with each workstation to be tested. In the parallel segment, the scheduling engine running by the motherboard microprocessor tests the valid workstations in the workstation bitmap variable simultaneously. In the serial single-workstation segment and the serial phase segment, the scheduling engine running by the motherboard microprocessor serially traverses the valid workstations in the workstation bitmap variable according to the workstation index. Step S103: When a short circuit, overcurrent, or communication timeout fault is detected in any of the above stages at the target workstation, the scheduling engine drives the target workstation to independently exit all subsequent test steps. The motherboard microprocessor resets the data bit in the workstation bitmap variable corresponding to the target workstation to an invalid state and sends a disconnect control word to the sub-board corresponding to the target workstation through the communication bus, driving the sub-board to shut down the independent power supply path and capacitor charging enable switch. The subsequent electrical variable acquisition process automatically skips the invalid workstation based on the updated workstation bitmap variable.

2. The automated multi-station phase-separated testing method for power communication modules according to claim 1, characterized in that, In step S101, when the overall test timing is in the serial single-station segment, the following sub-steps are included: Step S1011: Before entering the serial single-station segment, disconnect all phase line relays of all valid stations in the test station bitmap variable at the end of the parallel segment; Step S1012: Direct the flow pointer to the single-station functional test start mark and close all phase line relays of the current station; Step S1013: Call the independent test step for the current station to carry out external version read / write comparison and extended function check. If the test result is a failure, the scheduling engine disconnects all phase line relays and power supply path of the current station, updates the data bit corresponding to the current station in the station bitmap variable to an invalid state, and skips all tests of the current station in the serial phase segment. If the test is successful, proceed to the serial phase segment for the current station and complete the test steps for the serial phase segment; Step S1014: Regardless of whether the test result of the current station is successful or not, first disconnect all phase line relays of the current station, and then return to step S1012 to start traversing the next valid station until all valid stations have been traversed.

3. The automated multi-station phase-separated testing method for power communication modules according to claim 1, characterized in that, In step S102, when the overall test timing is switched to the serial phase segment, for each target station that is valid in the station bitmap variable, the following sub-steps are included: Step S1021: The scheduling engine reads the phase enable mask and sequentially traverses the A phase line, B phase line, and C phase line. If the phase being traversed is in an inactive state in the phase enable mask, the phase being traversed is skipped directly; Step S1022: If the phase being traversed is in an active state in the phase enable mask, the control switches the relay group, only engaging the phase line relay and the common neutral line relay being traversed, and disengaging the remaining phase line relays to energize the current single-phase test circuit.

4. The automated multi-station phase-separated testing method for power communication modules according to claim 1, characterized in that, After the motherboard microprocessor resets the data bit corresponding to the target workstation in the workstation bitmap variable to an invalid state, the following steps are also included: Step S104: The motherboard microprocessor establishes a topology communication link with the multi-channel daughterboard and the baseboard through the communication bus, and integrates the multi-channel analog quantity return, relay on / off status and transparent meter reading data into a unified discrete logic state stream.

5. The automated multi-station phase-separated testing method for power communication modules according to claim 4, characterized in that, It also includes the following steps: Step S105: Equip each test station pin with an independent LED indicator path. When the corresponding channel is triggered to remove the station due to short circuit, overcurrent, or communication timeout, drive the LED indicator path to present optical status feedback.

6. The automated multi-station phase-separated testing method for power communication modules according to claim 1, characterized in that, After the electrical variable acquisition process is completed, the following steps are also included: Step S106: Automatically extract the structured physical parameters of each channel and combine them to generate a formatted discrete test report, thereby realizing the recording of the interaction status between the electrical variable quantization parameters and the communication protocol.

7. The automated multi-station phase-separated testing method for power communication modules according to claim 1, characterized in that, When the overall test timing is in the parallel segment in step S101, the following sub-steps are included: Step S1013: The motherboard microprocessor sends basic firmware data and broadcasts calibration instructions to all test stations that are valid in the workstation bitmap variables in parallel, driving the power communication modules on each test station to synchronously perform basic electrical quantity burning and calibration.

8. The automated multi-station phase-separated testing method for power communication modules according to claim 1, characterized in that, Step S103 for communication timeout fault includes the following steps: When the scheduling engine initiates a communication request, it starts a high-frequency timer and introduces a communication compensation factor to correct the processor context switching delay. If no response data packet is received from the power communication module when the timeout period reaches the timeout threshold corrected by the communication compensation factor, it is determined that a communication timeout fault has occurred at the current workstation.

9. The automated multi-station phase-separated testing method for power communication modules according to claim 1, characterized in that, Step S102 in the serial phase segment includes the following sub-steps: Step S1023: If all data bits in the workstation bitmap variable are reset to an invalid state, the scheduling engine disconnects the main power supply circuit of the base plate and outputs a process end command indicating that there are no valid workstations.

10. A multi-station phase-separated automated testing system for power communication modules, used to implement the multi-station phase-separated automated testing method for power communication modules as described in claim 1, characterized in that, It includes a main control microprocessor module, a bus data transmission module, and a multi-channel distributed control submodule: The main control microprocessor module is connected to the bus data transmission module, and the multi-channel sub-control module is connected to the main control microprocessor module through the bus data transmission module. The main control microprocessor module is used to obtain the type code of the module under test and the test phase flag, and retrieve the target function pointer array based on the dual index of the type code of the module under test and the test phase flag. By embedding a phase separator in the address space of the target function pointer array, the overall test timing is divided into parallel segments, serial single-station segments, and serial phase segments. The main control microprocessor module is also used to initialize station bitmap variables in memory, with each data bit of the station bitmap variable corresponding one-to-one with each station under test. The scheduling engine run by the main control microprocessor module is used to test the valid stations in the station bitmap variables simultaneously in the parallel segment. In the serial single-station segment and the serial phase segment, the valid stations in the station bitmap variables are traversed serially according to the station index. When a short circuit, overcurrent, or communication timeout fault is detected at any of the above stages at the target workstation, the scheduling engine is used to drive the target workstation to independently exit all subsequent test steps. The main control microprocessor module is used to reset the data bit corresponding to the target workstation in the workstation bitmap variable to an invalid state and send a disconnection control word to the sub-control sub-module corresponding to the target workstation through the bus data transmission module. The sub-control module corresponding to the target workstation is used to receive the disconnect control word and, in response to the disconnect control word, shut down the independent power supply branch and the capacitor charging enable path. The subsequent electrical variable acquisition process is automatically skipped by the main control microprocessor module based on the updated workstation bitmap variables.

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