Embedded satellite TT&C and data transmission integrated baseband

Abstract

The application discloses an embedded satellite TT&C (Telemetry, Tracking and Command) data transmission integrated baseband, and relates to the technical field of satellite communication.The baseband comprises a ZYNQ SoC core module, an intermediate frequency interface module, a storage module, a network interface module, a digital / analog conversion module, a baseband processing module and a power module.The digital / analog conversion module is connected with the intermediate frequency interface module and the baseband processing module; the ZYNQ SoC core module integrates a PS end and a PL end, and the baseband processing module interacts with the PL end through an LVDS bus.The PS end is responsible for control and network processing, the baseband processing module performs modulation and demodulation processing of multi-system signals, and the PL end constructs a high-speed data channel and performs serial-parallel conversion and frequency reduction.The application has high integration, small volume and low power consumption, solves the problems of low data interaction efficiency and poor compatibility of a traditional baseband, and is suitable for portable ground stations and miniaturized scenes such as satellites.

Description

Technical Field

[0001] This invention belongs to the field of satellite communication and aerospace telemetry and control technology, and in particular relates to an embedded satellite telemetry and control integrated baseband. Background Technology

[0002] In the field of aerospace telemetry, tracking, and command (TT&C) and data transmission baseband is a core device of satellite communication systems, primarily used for telemetry reception, remote command transmission, and high-speed data transmission and demodulation. Traditional TT&C and data transmission basebands often employ a discrete architecture, integrating communication function boards such as FPGAs, DSPs, ADCs, DACs, intermediate frequency channels, and power management, configured with a PCI or VME dedicated bus chassis architecture. Additionally, some existing technologies attempt to implement baseband functionality using a single FPGA.

[0003] However, the aforementioned existing technologies have the following drawbacks and shortcomings in achieving miniaturization, lightweight design, and efficient data interaction: First, it suffers from low integration, large size, and high power consumption. Traditional discrete architectures have a large number of boards and complex connections, resulting in large chassis size and high power consumption, which cannot meet the needs of miniaturized and low-power applications such as small satellites, portable ground stations, field testing, and on-orbit commissioning.

[0004] Secondly, the parameter configuration is complex and the real-time performance is poor. The parameter configuration and data interaction of the existing system often rely on external dedicated control boards or independent host computers for relay. The configuration link has multiple layers, resulting in high latency in parameter distribution and difficulty in guaranteeing real-time performance.

[0005] Third, data interaction is inefficient and unreliable. Data transmission between the baseband processing module and the control module relies on an external bus, which has limited bandwidth and a high error rate. When performing high-speed data transmission (e.g., at a rate ≥900Mbps), data needs to be processed and exchanged with the host before being forwarded over the network, which can easily lead to problems such as data packet loss and frame synchronization anomalies.

[0006] Fourth, it suffers from poor functional compatibility and low flexibility. A single FPGA has limited resources, making it difficult to simultaneously handle the signal processing needs of multiple systems, such as PCM-CDMA-BPSK spread spectrum measurement and control, and BPSK / QPSK / 8PSK high-speed data transmission. Furthermore, algorithm upgrades require reprogramming the firmware, resulting in high maintenance costs. In addition, a single FPGA lacks an independent processor core; tasks such as parameter configuration, network protocol stack processing, and data cache management still rely on external processors, preventing true embedded integrated design. This leads to low resource scheduling flexibility and large data interaction latency when multiple modules are processed in parallel.

[0007] Fifth, the status monitoring capability is weak. The existing system cannot monitor the operating status of multiple modules such as carrier synchronization, frame synchronization, signal level, and signal-to-noise ratio (Eb / No) in real time and uniformly. The log records are scattered, making fault location difficult.

[0008] Therefore, those skilled in the art urgently need an embedded satellite telemetry and data transmission integrated baseband that is highly integrated, small in size, low in power consumption, and capable of supporting multi-system telemetry and control and data transmission signal processing, and realizing high-speed and reliable data interaction. Summary of the Invention

[0009] In view of this, the present invention aims to propose an embedded satellite telemetry, tracking, and command (TT&C) data transmission integrated baseband to solve the technical problems of existing satellite TT&C data transmission basebands, such as low integration, large size and power consumption, complex parameter configuration and poor real-time performance, low data interaction efficiency and insufficient reliability, poor compatibility with multiple systems, and weak status monitoring capabilities.

[0010] To achieve the above objectives, the technical solution of the present invention is implemented as follows: This invention provides an embedded satellite telemetry, tracking, and command (TT&C) integrated baseband, comprising: a ZYNQ SoC core module, an intermediate frequency interface module, a storage module, a network interface module, a digital-to-analog / analog-to-digital converter module, a baseband processing module, and a power supply module; The ZYNQ SoC core module integrates a PS terminal and a PL terminal. The PS terminal and the PL terminal achieve high-speed data interaction through the on-chip AXI bus. The PS terminal is used to run the embedded operating system for parameter configuration management, network protocol stack processing, and data cache scheduling, while the PL terminal is used to build a high-speed data path. The baseband processing module is implemented using independent FPGA logic and is used to perform multi-mode baseband signal processing. The baseband processing module and the PL terminal interact with each other for data and parameters through the LVDS bus. The intermediate frequency interface module is connected to the digital-to-analog / analog-to-digital converter module, and the digital-to-analog / analog-to-digital converter module is connected to the baseband processing module. It is used to convert the intermediate frequency signal into a digital signal and send it to the baseband processing module. Both the storage module and the network interface module are connected to the PS end; The power module is used to supply power to each module; During downlink data processing, the demodulated data from the baseband processing module is transmitted to the PL end via the LVDS bus. The PL end then moves the data to the PS end via the on-chip AXI bus. The PS end caches the data in the storage module and outputs it through the network interface module.

[0011] Furthermore, the PS side is an ARM Cortex-A9 dual-core processor, and the PL side is an FPGA logic array; the on-chip AXI bus includes the AXI HP bus, and the PS side is connected to the DDR3 SDRAM in the storage module through the AXI HP bus.

[0012] Furthermore, the baseband processing module supports high-speed data transmission processing, with a code rate range of [missing information]. to ; The PL end is configured to receive data from the baseband processing module. The data stream undergoes a 1:8 or 1:16 serial-to-parallel conversion process, reducing the parallel data stream rate to [a lower frequency]. or It operates using multiple phase-locked loops corresponding to the serial-to-parallel conversion ratio; the PL terminal uses a DMA mechanism to move parallel data to the PS terminal via the on-chip AXI bus.

[0013] Furthermore, the embedded operating system on the PS is Linux, which is used to implement status monitoring, logging, and remote interactive control. Parameter configuration management sends commands directly to the PL terminal via the on-chip AXI bus, with a latency of less than [time value missing]. .

[0014] Furthermore, the intermediate frequency interface module includes a 70MHz intermediate frequency interface, a 1.2GHz intermediate frequency interface, and an X-band inverter interface, supporting AGC control with a control range greater than or equal to... ; The digital-to-analog / analog-to-digital conversion module includes an intermediate frequency (IF) AD / DA chip, and the baseband processing module is connected to the IF AD / DA chip via an I / O interface.

[0015] Furthermore, the storage module includes SPI FLASH, DDR3 SDRAM, and EEPROM; SPI FLASH is used to store firmware and configuration parameters, and EEPROM is used to retain parameters even when power is off. The network interface module uses dual gigabit Ethernet interfaces, one for remote configuration and control, and the other for telemetry and data transmission output.

[0016] Furthermore, the power module supports AC220V or DC12V power supply, and uses SCT2460 and LMZ14203 power chips for output. , , , Voltage, total power consumption less than or equal to .

[0017] Based on the same concept, the present invention also provides a data interaction method for an embedded satellite telemetry, tracking, and command (TT&C) integrated baseband, which includes the following steps: Parameter configuration steps: The PS terminal receives the configuration command sent by the remote host computer through the network interface module, parses it, and sends the command to the PL terminal through the on-chip AXI bus. The PL terminal completes parameter loading and mode configuration. Data uplink steps: The PS end frames the data and sends it to the PL end through the on-chip AXI bus. The PL end sends the data to the baseband processing module. The baseband processing module encodes, scrambles, and modulates the data. After that, the data is output to the X-band frequency converter to transmit radio frequency signals through the digital-to-analog / analog-to-digital converter module and the intermediate frequency interface module. Downlink data steps: The intermediate frequency signal is sent to the baseband processing module via the digital-to-analog / analog-to-digital converter module to complete demodulation, decoding and descrambling. Then it is transmitted to the PL end via the LVDS bus. The PL end sends it to the PS end via the on-chip AXI bus. The PS end performs buffering and unpacking processing and outputs it through the network interface module. Status monitoring steps: The baseband processing module collects operating parameters in real time and sends them to the PS terminal via the PL terminal and the on-chip AXI bus. The PS terminal then summarizes the data and outputs it through the network interface module.

[0018] Furthermore, in the data uplink step, the PS end frames the remote control commands or uploaded data; During the data downlink step, after receiving telemetry data, the PS terminal sends it to the remote host computer for display via the network interface module, and generates a log file via the other channel.

[0019] Furthermore, it also includes a self-closed-loop detection step: the transmitted signal is directly looped back to the receiving end through an internal loop composed of intermediate frequency output and intermediate frequency input to perform remote control loop detection and telemetry simulation detection, so as to verify link connectivity and data integrity; Remote control loop detection includes: looping the modulated remote control signal back to the detection channel; telemetry simulation detection includes: looping back to the telemetry receiving channel through the telemetry simulation channel.

[0020] Compared with the prior art, the present invention has the following beneficial effects: First, it is highly integrated, miniaturized, and low-power. This invention adopts a ZYNQ SoC (ARM+FPGA) integrated architecture, which highly integrates the processor and FPGA logic, eliminating the need for external control boards and complex dedicated bus chassis. Compared with conventional industrial control chassis-type basebands, it significantly reduces the overall size and weight of the device and greatly reduces system power consumption, fully meeting the needs of miniaturized and lightweight applications such as portable ground stations and spaceborne systems.

[0021] Secondly, parameter configuration is highly efficient, flexible, and real-time. This invention manages parameter configuration directly through the PS terminal, and configuration commands are sent directly to the PL terminal via the on-chip AXI bus, eliminating the need for an external bus relay and achieving a latency of less than 50ms throughout the process. It also supports one-click macro configuration, configuration file import / export, and remote online modification, significantly improving the flexibility and efficiency of parameter configuration.

[0022] Third, the data interaction is high-speed, reliable, and has sufficient bandwidth. This invention achieves data interaction between the PS and PL ends through an on-chip AXI bus, with a bus bandwidth of over 10Gbps. This on-chip interconnection mechanism completely solves the problems of limited bandwidth and high error rate of traditional external buses, and can support packet loss-free transmission of high-speed data transmission at 600Mbps and above, significantly improving the reliability of data interaction.

[0023] Fourth, it is compatible with multiple systems, flexible in function, and scalable. The PL terminal of this invention integrates a multi-system baseband processing IP core, which can simultaneously meet the processing needs of various signal systems such as spread spectrum measurement and control, medium and low speed data transmission, and high speed data transmission (such as BPSK / QPSK / 8PSK). When upgrading the algorithm, only the PL terminal firmware needs to be updated without modifying the hardware structure, effectively reducing the maintenance cost of the equipment.

[0024] Fifth, comprehensive status monitoring and convenient fault location. This invention collects operating parameters from multiple modules uniformly through the PS terminal, and can display key statuses such as carrier synchronization, frame synchronization, and signal-to-noise ratio (Eb / No) in real time. The system log is complete and supports remote fault alarms and log retrieval, making fault location more convenient and efficient.

[0025] Sixth, convenient remote interaction and adaptability to multiple scenarios. This invention supports remote configuration, data distribution and status monitoring via gigabit Ethernet, has a self-closed-loop detection function, and can be widely adapted to various application scenarios such as on-orbit satellite telemetry and control, ground equipment commissioning, and portable ground stations, demonstrating strong versatility and practicality. Attached Figure Description

[0026] The accompanying drawings, which form part of this invention, are used to provide a further understanding of the invention. The illustrative embodiments of the invention and their descriptions are used to explain the invention and do not constitute an undue limitation of the invention. In the drawings: Figure 1 This is a hardware architecture block diagram of an embedded satellite telemetry, tracking, and command (TT&C) integrated baseband provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of the parameter configuration and data interaction process of an embedded satellite telemetry, tracking, and command integrated baseband provided in an embodiment of the present invention; Figure 3 This is a circuit topology diagram of a power module for an embedded satellite telemetry, tracking, and command (TT&C) integrated baseband, provided in an embodiment of the present invention. Figure 4 This is a system internal data interaction and software logic architecture diagram of an embedded satellite telemetry, tracking, and command integrated baseband provided in an embodiment of the present invention.

[0027] Explanation of reference numerals in the attached figures: 101. ZYNQ SoC core module; 102. PS terminal; 103. PL terminal; 104. On-chip AXI bus; 105. Storage module; 106. Network interface module; 107. Baseband processing module; 108. Digital-to-analog / analog-to-digital converter module; 109. Intermediate frequency interface module; 110. Power supply module; 201. Remote host computer; 202. Gigabit Ethernet; 203. X-band inverter; 204. Satellite. Detailed Implementation

[0028] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other.

[0029] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicating orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature. In the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0030] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art will understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0031] The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0032] like Figures 1 to 4As shown, an embedded satellite telemetry, telemetry and data transmission integrated baseband includes: a ZYNQ SoC core module 101, an intermediate frequency interface module 109, a storage module 105, a network interface module 106, a digital-to-analog / analog-to-digital conversion module 108, a baseband processing module 107, and a power supply module 110. The ZYNQ SoC core module 101 integrates a PS terminal 102 and a PL terminal 103. The PS terminal 102 and the PL terminal 103 communicate with each other via an on-chip AXI bus 104. The PS terminal 102 is used to run the embedded operating system for parameter configuration management, network protocol stack processing and data cache scheduling, while the PL terminal 103 is used to build a high-speed data path. The baseband processing module 107 is implemented using independent FPGA logic and is used to perform multi-mode baseband signal processing. The baseband processing module 107 and the PL terminal 103 interact with each other via the LVDS bus for data and parameters. The intermediate frequency interface module 109 is connected to the digital-to-analog / analog-to-digital converter module 108, and the digital-to-analog / analog-to-digital converter module 108 is connected to the baseband processing module 107, which is used to convert the intermediate frequency signal into a digital signal and send it to the baseband processing module 107. Both storage module 105 and network interface module 106 are connected to PS terminal 102; Power module 110 is used to supply power to each module; During downlink data processing, the demodulated data from the baseband processing module 107 is transmitted to the PL terminal 103 via the LVDS bus. The PL terminal 103 then moves the data to the PS terminal 102 via the on-chip AXI bus 104. The PS terminal 102 caches the data in the storage module 105 and outputs it through the network interface module 106.

[0033] The specific embodiments of the present invention are as follows: Example 1: Hardware Architecture of an Embedded Satellite Telemetry, Control and Data Transmission Integrated Baseband like Figure 1 As shown, this embodiment provides an embedded satellite telemetry, tracking, and command (TT&C) integrated baseband. This baseband aims to solve the problems of low integration, large size and power consumption, and low data interaction efficiency of traditional discrete architectures, and is particularly suitable for miniaturized applications such as small satellites, portable ground stations, and on-orbit commissioning. The baseband mainly includes a ZYNQ SoC core module 101, an intermediate frequency interface module 109, a storage module 105, a network interface module 106, a digital-to-analog / analog-to-digital converter module 108, a baseband processing module 107, and a power supply module 110. It should be noted that the ZYNQ SoC core module 101 of this invention generally refers to a system-on-a-chip (SoC) using a heterogeneous architecture, i.e., a chip that integrates a processor core and a programmable logic array internally; ZYNQ is only one preferred specific implementation model.

[0034] The ZYNQ SoC core module 101 is the control and data processing hub of the entire system. This module adopts a system-on-a-chip (SoC) architecture, specifically the XC7Z045 or a similar heterogeneous SoC chip. It integrates a PS (Power Switch) terminal 102 and a PL (Power Logic Terminal) terminal 103. The PS terminal 102 is an embedded processor core, specifically an ARM Cortex-A9 dual-core processor or other high-performance embedded processor, responsible for system control, network protocol processing, data buffer scheduling, and status monitoring. The PL terminal 103 is an FPGA logic array, responsible for high-speed data paths and hardware acceleration logic. High-speed data exchange between the PS terminal 102 and the PL terminal 103 is achieved through an on-chip AXI bus 104. The AXI bus 104 includes, but is not limited to, standard bus protocols such as AXI4, AXI4-Lite, or AXI-Stream. This on-chip interconnect architecture eliminates the traditional external bus relay design, greatly improving the bandwidth and reliability of data transmission, with bandwidth reaching [missing information]. The above solutions address the issues of limited bandwidth and high error rate inherent in traditional external buses.

[0035] The baseband processing module 107 is implemented using independent FPGA logic and is responsible for processing all communication baseband signals. The baseband processing module 107 interacts with the PL terminal 103 of the ZYNQ SoC core module 101 via an LVDS bus for data and parameter exchange. This design allows the PL terminal 103 and PS terminal 102 of the ZYNQ SoC core module 101 to handle only data exchange and parameter configuration, while the complex signal processing tasks are handled by the independent baseband processing module 107. This achieves specialized task division and avoids the problem of poor functional compatibility caused by limited single FPGA resources.

[0036] The intermediate frequency (IF) interface module 109 is responsible for transmitting and receiving radio frequency (RF) and intermediate frequency (IF) signals. This module includes a 70MHz IF interface for spread spectrum measurement and control and low-to-medium speed data transmission; a 1.2GHz IF interface for high-speed data transmission; and an X-band inverter interface using an SMA-K connector. The IF interface module 109 supports AGC control, with a control range greater than or equal to... In terms of circuit implementation, the intermediate frequency interface module 109 includes a two-stage AGC processing circuit, an attenuation processing circuit, a single-ended to differential processing circuit, and an intermediate frequency filtering processing circuit to ensure signal quality over a wide dynamic range.

[0037] The digital-to-analog / analog-to-digital converter module 108 is connected between the intermediate frequency (IF) interface module 109 and the baseband processing module 107, and is responsible for converting analog signals to digital signals. Specifically, the baseband processing module 107 is connected to an IF AD / DA chip, such as an ADC08D502 and a DAC5687 or equivalent conversion chip, as well as an AGC circuit and an RF interface module, via an I / O interface. The baseband processing module 107 and the PL terminal 103 of the ZYNQ SoC core module 101 exchange data and parameters via an LVDS bus.

[0038] Storage module 105 is connected to PS terminal 102 and is used for data storage and program execution. Storage module 105 includes SPI FLASH with a capacity of [missing information]. It is used to store firmware and configuration parameters; it includes DDR3 SDRAM with a capacity of Used for data caching; and EEPROM, with a capacity of It is used to save parameters when power is off. The PS terminal 102 is connected to the DDR3 SDRAM via the on-chip AXI HP bus, and the specific model can be MT41J64M16JT-125.

[0039] The network interface module 106 is connected to the PS terminal 102, employing a dual-channel gigabit Ethernet interface with a physical interface of RJ45. One channel is used for remote configuration and control, while the other is used for telemetry and data transmission output, supporting real-time data distribution and remote monitoring. The PS terminal 102 connects to the dual-channel gigabit Ethernet, SPI FLASH, EEPROM, and UART debug interface via the MIO interface.

[0040] Power module 110 provides a stable power supply to the system. For example... Figure 3 As shown, power module 110 supports AC220V or DC12V power supply. Power module 110 uses power chips such as SCT2460 and LMZ14203. The specific circuit topology is as follows: Input voltage The initial conversion is performed using the SCT2460 chip.

[0041] First power supply branch: Input voltage Converted by SCT2460 Then converted by PTH08T250WAD It supplies the core logic of the measurement and control data transmission circuit system, such as the FPGA core voltage.

[0042] Second power supply branch: Input voltage Converted by SCT2460 It is then split into four paths, which are converted by the LMZ10505TZ-ADJ chip respectively. , , and It supplies the various peripheral interfaces and memory chips of the supply system.

[0043] Third power supply branch: Input voltage Directly converted by the LMZ14203TZ-ADJ chip and It supplies analog circuits and other modules.

[0044] Power module 110 output , , , The voltage is equal to that of the ZYNQ SoC core module 101 and other modules, and the overall power consumption is less than or equal to the required voltage. .

[0045] The overall size is designed to be less than or equal to Weight less than or equal to This achieves miniaturization and lightweight design.

[0046] Example 2: System Software and Logical Architecture and High-Speed ​​Data Processing Mechanism like Figure 4 As shown, this embodiment describes in detail the internal data interaction and software logic architecture of the system. The system is divided into a baseband processing unit, a PL terminal 103, a PS terminal 102, and a network interface module 106.

[0047] A1. Functional Implementation of the Baseband Processing Unit The baseband processing unit includes data transceiver interface programs, modulation and demodulation programs, encoding and decoding programs, framing and deframing programs, and a high-speed data buffer interface. This unit is responsible for multi-mode baseband signal processing, data preprocessing, and hardware acceleration.

[0048] In terms of spread spectrum telemetry and control processing, it supports PCM-CDMA-BPSK modulation and demodulation, completes pseudocode acquisition and tracking, carrier synchronization, convolution / RS encoding and decoding, scrambling / descrambling, and is compatible with the CCSDS standard.

[0049] In terms of low- and medium-speed data transmission processing, it supports BPSK / QPSK modulation and demodulation, with a code rate range of [missing information]. to It enables frame synchronization, Viterbi decoding, and data framing.

[0050] In terms of high-speed data transmission processing, it supports BPSK / QPSK / SQPSK (Shaped Quadrature Phase Shift Keying) / 8PSK modulation and demodulation, with a code rate range of [missing information]. to A parallel carrier synchronization algorithm is used to achieve high-speed data demodulation, adaptive equalization, and deinterleaving.

[0051] A2. Serial-to-parallel conversion and transmission mechanism of high-speed data streams This is one of the core technical points of this invention. The baseband processing module 107 acquires the satellite wireless data transmission signal from the intermediate frequency interface through a high-speed ADC. When the data rate is particularly high, for example reaching... When, the corresponding clock frequency is Such a high-frequency clock cannot be directly processed in a carrier loop within the FPGA.

[0052] Therefore, the system performed serial-to-parallel conversion. Specifically, the data stream at the PL end... Through serial-to-parallel conversion, the data enters the FIFO at a ratio of 1:N, where N is an integer greater than 1, preferably 8 or 16. This reduces the parallel data flow rate to [a lower frequency]. or .

[0053] The PL terminal 103 operates using multiple phase-locked loops (e.g., 8 phase-locked loops) corresponding to the conversion ratio, which is significantly different from the traditional low-speed single-carrier loop synchronization. To address the multi-channel clock skew and phase alignment issues during high-speed serial-to-parallel conversion, the ADC device selected in this system supports outputting data to the FPGA with the clock phase aligned, thus ensuring data synchronization.

[0054] The PL terminal 103 verifies and recovers the data, and re-frames the network. Subsequently, the AXI bus uses a DMA mechanism to move parallel data from the PL terminal 103 FIFO to the PS terminal 102. This mechanism effectively solves the problem of clock asynchrony between different sources. For 2-byte width... The PS102 can efficiently process the frequency data stream and forward it via Gigabit Ethernet.

[0055] A3. Software Function Implementation of PS End 102 The PS102 is equipped with an embedded Linux system. The Linux system on the PS102 first runs network protocol stack processing functions, integrating TCP / UDP protocol stacks or other standard network transmission protocols. Through network protocols, the PS102 system establishes a communication connection with the remote computer to achieve data exchange.

[0056] PS version 102 implements the following five major functions: First, parameter configuration management. It provides a host computer interface, supporting one-click macro configuration, configuration file import / export, and online parameter modification for parameters such as spreading code rate, modulation scheme, encoding type, and frame length. Configuration commands are directly sent to the PL terminal 103 via the on-chip AXI bus 104, with a latency of less than [time value missing]. .

[0057] Second, network protocol stack processing. Remote parameter configuration, telemetry / data transmission distribution, and remote control command reception are achieved through a gigabit Ethernet interface. It supports UDP multicast and PDXP protocol data encapsulation, where PDXP stands for Packet Data Exchange Protocol.

[0058] Third, data caching and scheduling. An external DDR3 storage module 105 is used to achieve real-time caching and storage of telemetry data and high-speed data transmission data, in *.dat format, with playback functionality. The cache capacity is greater than or equal to... It supports data retrieval by timestamp.

[0059] Fourth, status monitoring and logging. Real-time acquisition of operating parameters such as carrier synchronization status, frame synchronization status, signal strength, Eb / No, and bit error rate from the PL terminal 103, generating log files that support local storage and remote log push.

[0060] Fifth, remote interactive control. It receives control commands from a remote host computer to enable equipment start / stop and mode switching, including spread spectrum measurement and control, medium-low speed data transmission, high-speed data transmission modes, and self-closed-loop detection and control.

[0061] Example 3: System Workflow and Interaction Methods like Figure 2 As shown, this embodiment describes the system's workflow in a real-world satellite communication scenario. In the figure, 201 is the remote host computer, 202 is Gigabit Ethernet, 102 is the PS terminal, 104 is the on-chip AXI bus, 103 is the PL terminal, 109 is the intermediate frequency interface module, 203 is the X-band frequency converter, and 204 is the satellite.

[0062] B1. Parameter Configuration Process The remote host computer 201 sends configuration commands via Gigabit Ethernet 202. The PS terminal 102 receives the commands and performs parameter parsing and verification. Subsequently, the PS terminal 102 sends the commands to the PL terminal 103 via the on-chip AXI bus 104. The PL terminal 103 completes parameter loading and mode configuration, such as configuring it to spread spectrum telemetry mode. The total latency is less than [spread spectrum telemetry mode value missing]. It supports online modification and one-click configuration.

[0063] B2. Data Uplink Process This process is used for remote control or high-speed uploading. The PS terminal 102 frames the remote control commands or uploading data. The framed data is sent to the PL terminal 103 via the on-chip AXI bus 104. The PL terminal 103 sends the data to the baseband processing module 107 via the LVDS bus. The baseband processing module 107 performs physical layer processing such as encoding, scrambling, and modulation. The processed digital signal is converted into an analog signal by the digital-to-analog / analog-to-digital converter module 108 and sent to the intermediate frequency interface module 109. The signal is then sent to the X-band inverter 203 via the intermediate frequency interface module 109, and finally converted into a radio frequency signal for transmission to the satellite 204.

[0064] B3. Data Downlink Process This process is used for telemetry or data transmission. Satellite 204 transmits downlink signals. The signal is down-converted to a 70MHz intermediate frequency (IF) signal by X-band converter 203 and sent to IF interface module 109. The IF signal is converted into a digital signal by digital-to-analog / analog-to-digital converter 108 and then sent to baseband processing module 107, where physical layer processing such as demodulation, decoding, and descrambling is performed. The processed digital baseband data is transmitted to PL terminal 103 via LVDS bus. PL terminal 103 performs serial-to-parallel conversion and AXI bus encapsulation, and then sends it to PS terminal 102 via on-chip AXI bus 104. PS terminal 102 receives the telemetry data and performs buffering, storage, and unpacking processing. One channel of data is sent to remote host computer 201 for display via Gigabit Ethernet 202, and the other channel generates a log file.

[0065] B4. Status Monitoring Process During equipment operation, the baseband processing module 107 collects operating parameters in real time. The operating parameters are sent to the PS terminal 102 via the LVDS bus and the on-chip AXI bus 104. The PS terminal 102 summarizes the parameters and generates logs, which are then sent to the remote host computer 201 via Gigabit Ethernet 202 to realize status display and fault alarm.

[0066] B5. Self-closed-loop detection and control The system supports self-closed-loop detection, which is used to detect whether the remote control, telemetry, and data transmission functions of the baseband system are complete and whether the hardware system is working stably. The detection is based on the hardware loop composed of intermediate frequency output and intermediate frequency input. The specific detection process includes: (1) Remote control loop detection: The remote control signal (after modulation) output by the measurement and control baseband is looped back to the detection channel of the remote control loop through the internal loop to verify the connectivity of the remote control link. (2) Telemetry simulation detection: The system has a telemetry simulation channel, which loops the simulated telemetry signal back to the telemetry receiving channel to perform loopback detection of the telemetry channel and verify the integrity of the demodulation and decoding functions.

[0067] Example 4: Software Configuration and Hardware Connection Details In terms of hardware connectivity, the ZYNQ SoC core module 101 uses the XC7Z045 chip. The PS terminal 102 connects to dual-channel Gigabit Ethernet, SPI FLASH, EEPROM, and UART debug interface via the MIO interface. The PS terminal 102 also connects to DDR3 SDRAM via the on-chip AXI HP bus. The baseband processing module 107 connects to the intermediate frequency AD / DA chip, AGC circuit, and RF interface module via the I / O interface.

[0068] In terms of software configuration, the embedded Linux system kernel of the PS terminal 102 was ported, the ZYNQ device tree was loaded, and the AXI bus interface and network driver were configured. Host computer configuration software was developed, providing parameter configuration interface, status display interface, and data playback interface.

[0069] The PL terminal 103 completes the logic design through the Vivado development tool, integrates spread spectrum measurement and control, medium and low speed data transmission, and high speed data transmission IP cores, and is configured with an on-chip AXI bus interface to realize high-speed data interaction with the PS terminal 102.

[0070] After the device is powered on, PS terminal 102 boots the Linux system, loads configuration parameters, and initializes the network interface and AXI bus. PL terminal 103 loads the firmware, completes hardware initialization, and enters standby mode.

[0071] Compared with the prior art, the present invention has the following significant advantages: First, it is highly integrated, miniaturized, and low-power, making it perfectly suited for miniaturized applications. This invention breaks away from the limitations of traditional measurement and control data transmission baseband architectures that rely on discrete FPGAs, DSPs, and dedicated bus chassis. It innovatively adopts a ZYNQ SoC integrated architecture, highly integrating the ARM processor and FPGA logic within a single chip, with a dedicated baseband processing module for specialized division of labor. This design completely eliminates cumbersome external control boards and complex chassis connections, significantly reducing the number of components and board area. Combined with the meticulously designed power module topology of this invention, it uses a high-efficiency DC-DC converter chip for multi-channel voltage regulation, strictly controlling the overall power consumption to within 15W, reducing the overall size to within 200mm × 150mm × 50mm, and the weight to below 5kg. Compared with conventional industrial control chassis-type basebands, it has significant advantages in miniaturization and low power consumption. Specifically, conventional industrial control chassis-type basebands using the PCI / VME bus architecture typically have dimensions of approximately 400mm × 250mm × 150mm, a weight usually between 12kg and 15kg, and a power consumption generally exceeding 30W. However, using the baseband provided in this embodiment of the invention, the overall size is reduced to 200mm × 150mm × 50mm, the longest side length is reduced to 200mm, the linear size is reduced by approximately 60%, and the weight is reduced to below 5kg, approximately 67% lighter than the conventional 15kg. The power consumption is strictly controlled to below 15W, a 50% reduction compared to the conventional 30W. These improvements fully meet the extremely demanding requirements of small satellite onboard systems, portable ground stations, and field testing applications with stringent size, weight, and power consumption constraints.

[0072] Secondly, the data interaction is high-speed, reliable, and has sufficient bandwidth, completely solving the bottleneck of high-speed data transmission. This invention achieves data interaction between the PS and PL ends through an on-chip AXI bus, with a bus bandwidth exceeding 10Gbps, completely solving the problems of limited bandwidth and high bit error rate of traditional external buses. For high-speed data transmission signals up to 900Mbps, this invention innovatively adopts a 1:8 or 1:16 serial-to-parallel conversion processing mechanism at the PL end, combined with multiple phase-locked loops working in parallel, reducing the parallel data stream rate to [a lower value]. or The system utilizes a DMA mechanism to directly move parallel data to the PS end. This mechanism not only cleverly solves the technical challenge of FPGAs being unable to directly perform carrier loop processing under high-frequency clocks, but also effectively overcomes signal distortion caused by clock sources and asynchrony. The system can support packet-free transmission of high-speed data transmission at 600Mbps and above, with a bit error rate reduced to 10%. -5 The following features significantly improve the reliability and real-time performance of data interaction.

[0073] Third, the parameter configuration is highly efficient, flexible, and real-time, significantly improving operational efficiency. This invention manages parameter configuration directly through an embedded Linux system on the PS terminal. Configuration commands do not require external links; instead, they are directly sent to the PL terminal via the on-chip AXI bus, with latency strictly controlled within 50ms throughout the process. The system supports one-click macro configuration of parameters such as spreading code rate, modulation scheme, and encoding type, as well as configuration file import / export and remote online modification. This flattened configuration chain eliminates the latency accumulation caused by traditional multi-level links, significantly improving configuration efficiency. Specifically, in a comparative test of system operating mode switching (such as switching from spread spectrum measurement and control mode to high-speed data transmission mode), the traditional architecture using an external PCI / VME bus chassis and independent control board relay requires multiple levels of external bus handshakes and manual parameter sending, resulting in an average time of about 50 seconds to complete a full configuration. However, using the baseband provided in this embodiment of the invention, one-click macro configuration is supported through the PS terminal, and the configuration command is directly sent to the PL terminal through the on-chip AXI bus, resulting in an average time of about 10 seconds to complete a full configuration, improving configuration efficiency by about 80%. This allows the equipment to quickly respond to control commands from the remote host computer, achieving seamless mode switching and greatly improving the operation and maintenance efficiency of field joint testing and on-orbit joint commissioning.

[0074] Fourth, it is compatible with multiple systems, flexible in function, and scalable, effectively reducing maintenance costs. The baseband processing module of this invention is implemented using independent FPGA logic and integrates multi-system baseband processing IP cores, enabling simultaneous compatibility with various signal systems such as PCM-CDMA-BPSK spread spectrum measurement and control, BPSK / QPSK low-speed data transmission, and BPSK / QPSK / SQPSK / 8PSK high-speed data transmission. The specialized division of labor between the PS and PL ends makes resource scheduling more flexible, avoiding compatibility issues caused by the limited resources of a single chip. When upgrading algorithms or adapting to new systems, only the PL end firmware needs to be updated without modifying any hardware structure, achieving flexible functional expansion and effectively reducing the later maintenance and upgrade costs of the equipment.

[0075] Fifth, comprehensive status monitoring and convenient fault location make the system more stable and reliable. This invention collects operating parameters from multiple modules uniformly via the PS terminal, enabling real-time display of key statuses such as carrier synchronization, frame synchronization, signal strength, signal-to-noise ratio (Eb / No), and bit error rate. Complete log records are maintained, and remote fault alarms and log retrieval are supported, significantly improving fault location efficiency. Specifically, in a comparative test of locating typical link faults (such as frame synchronization anomalies in high-speed data transmission mode), traditional systems, due to the scattered log records of each independent module, required engineers to log into multiple nodes separately to export logs and perform manual comparison and analysis, resulting in an average fault location time of approximately 120 minutes per test. However, using the baseband provided in this invention, the PS terminal uniformly collects operating parameters from multiple modules and generates structured log files with unified timestamps, supporting remote keyword one-click retrieval and automatic alarms. This reduces the average fault location time to approximately 35 minutes, improving fault location efficiency by approximately 70%. Furthermore, the system incorporates a self-closed-loop detection and control function, directly looping the transmitted signal back to the receiving end through an internal loop for closed-loop detection of remote control loops, telemetry simulations, and data transmission simulations. This design enables rapid verification of link connectivity and data integrity before or during equipment deployment, ensuring stable operation of the hardware system and significantly improving the overall reliability and maintainability of the system.

[0076] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. An embedded satellite telemetry, tracking, and command (TT&C) integrated baseband, characterized in that, include: The ZYNQ SoC core module (101), intermediate frequency interface module (109), storage module (105), network interface module (106), digital-to-analog / analog-to-digital converter module (108), baseband processing module (107), and power module (110); The ZYNQ SoC core module (101) integrates a PS terminal (102) and a PL terminal (103). The PS terminal (102) and the PL terminal (103) communicate with each other via an on-chip AXI bus (104). The PS terminal (102) is used to run an embedded operating system for parameter configuration management, network protocol stack processing and data cache scheduling. The PL terminal (103) is used to build a high-speed data path. The baseband processing module (107) is implemented using independent FPGA logic and is used to perform multi-mode baseband signal processing. The baseband processing module (107) and the PL terminal (103) interact with each other via the LVDS bus for data and parameters. The intermediate frequency interface module (109) is connected to the digital-to-analog / analog-to-digital converter module (108), and the digital-to-analog / analog-to-digital converter module (108) is connected to the baseband processing module (107) to convert the intermediate frequency signal into a digital signal and send it to the baseband processing module (107). Both the storage module (105) and the network interface module (106) are connected to the PS terminal (102); The power supply module (110) is used to supply power to each module; During downlink data processing, the demodulated data from the baseband processing module (107) is transmitted to the PL terminal (103) via the LVDS bus. The PL terminal (103) then moves the data to the PS terminal (102) via the on-chip AXI bus (104). The PS terminal (102) caches the data in the storage module (105) and outputs it through the network interface module (106).

2. The embedded satellite telemetry, tracking, and command (TT&C) integrated baseband according to claim 1, characterized in that, The PS end (102) is an ARM Cortex-A9 dual-core processor, and the PL end (103) is an FPGA logic array; the on-chip AXI bus (104) includes the AXI HP bus, and the PS end (102) is connected to the DDR3 SDRAM in the storage module (105) through the AXI HP bus.

3. The embedded satellite telemetry, tracking, and command integrated baseband according to claim 1, characterized in that, The baseband processing module (107) supports high-speed data transmission processing, with a code rate range of [missing information]. to ; The PL terminal (103) is configured to process data transmitted from the baseband processing module (107). The data stream undergoes a 1:8 or 1:16 serial-to-parallel conversion process, reducing the parallel data stream rate to [a lower frequency]. or It operates using multiple phase-locked loops corresponding to the serial-to-parallel conversion ratio; the PL terminal (103) uses a DMA mechanism to transfer parallel data to the PS terminal (102) via the on-chip AXI bus (104).

4. The embedded satellite telemetry, tracking, and command integrated baseband according to claim 1, characterized in that, The embedded operating system on the PS terminal (102) is Linux, which is used to implement status monitoring, log recording and remote interactive control; Parameter configuration management directly sends instructions to the PL terminal (103) via the on-chip AXI bus (104), with a latency of less than [missing information]. .

5. The embedded satellite telemetry, tracking, and command integrated baseband according to claim 1, characterized in that, The intermediate frequency interface module (109) includes a 70MHz intermediate frequency interface, a 1.2GHz intermediate frequency interface, and an X-band inverter interface. It supports AGC control with a control range greater than or equal to... ; The digital-to-analog / analog-to-digital conversion module (108) includes an intermediate frequency AD / DA chip, and the baseband processing module (107) is connected to the intermediate frequency AD / DA chip through an IO interface.

6. The embedded satellite telemetry, tracking, and command integrated baseband according to claim 1, characterized in that, The storage module (105) includes SPI FLASH, DDR3 SDRAM and EEPROM; SPI FLASH is used to store firmware and configuration parameters, and EEPROM is used to save parameters when power is off; The network interface module (106) adopts a dual-channel gigabit Ethernet interface, one channel for remote configuration and control, and the other channel for telemetry and data transmission output.

7. The embedded satellite telemetry, tracking, and command integrated baseband according to claim 1, characterized in that, The power module (110) supports AC220V or DC12V power supply, and uses SCT2460 and LMZ14203 power chips for output. , , , Voltage, total power consumption less than or equal to .

8. A data interaction method for an embedded satellite telemetry, tracking, and command (TT&C) integrated baseband, using an embedded satellite TT&C integrated baseband as described in any one of claims 1-7, characterized in that, Includes the following steps: Parameter configuration steps: The PS terminal (102) receives the configuration command sent by the remote host computer (201) through the network interface module (106), and after parsing, sends the command to the PL terminal (103) through the on-chip AXI bus (104). The PL terminal (103) completes parameter loading and mode configuration. Data uplink steps: The PS terminal (102) frames the data and sends it to the PL terminal (103) via the on-chip AXI bus (104). The PL terminal (103) sends the data to the baseband processing module (107). The baseband processing module (107) performs encoding, scrambling, and modulation processing, and then outputs the data to the X-band inverter (203) via the digital-to-analog / analog-to-digital converter module (108) and the intermediate frequency interface module (109) to transmit the radio frequency signal. Downlink data steps: The intermediate frequency signal is sent to the baseband processing module (107) via the digital-to-analog / analog-to-digital converter module (108) to complete demodulation, decoding and descrambling. Then, it is transmitted to the PL terminal (103) via the LVDS bus. The PL terminal (103) sends the signal to the PS terminal (102) via the on-chip AXI bus (104). The PS terminal (102) performs buffering and unpacking processing and outputs the signal through the network interface module (106). Status monitoring steps: The baseband processing module (107) collects operating parameters in real time and sends them to the PS terminal (102) through the PL terminal (103) and the on-chip AXI bus (104). The PS terminal (102) summarizes the data and outputs it through the network interface module (106).

9. The data interaction method according to claim 8, characterized in that, In the data uplink step, the PS terminal (102) frames the remote control command or the uploaded data; In the data downlink step, after receiving telemetry data, the PS terminal (102) sends one path to the remote host computer (201) for display through the network interface module (106), and the other path generates a log file.

10. The data interaction method according to claim 8, characterized in that, It also includes a self-closed-loop detection step: the transmitted signal is directly looped back to the receiver through an internal loop composed of intermediate frequency output and intermediate frequency input to perform remote control loop detection and telemetry simulation detection to verify link connectivity and data integrity; Remote control loop detection includes: looping the modulated remote control signal back to the detection channel; telemetry simulation detection includes: looping back to the telemetry receiving channel through the telemetry simulation channel.

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