Silicon photonic chip operating point control system, electronic device, and method

Abstract

The application relates to the technical field of photoelectric control, and discloses a silicon optical chip operating point control system, an electronic device and a method, wherein the system comprises: a bias voltage driving module adapted to output a bias voltage, wherein the bias voltage comprises a direct current reference component and a frequency interference component; a photoelectric detection module adapted to receive a modulated light signal of a silicon optical chip in response to the bias voltage, and convert the modulated light signal into a feedback electric signal; and a hardware logic module configured to: perform step-by-step updating on the direct current reference component, and perform spectrum analysis during the step-by-step updating process, so as to determine an optimal operating point of the silicon optical chip according to the spectrum analysis result; wherein the hardware logic module performs real-time Fourier transform on the feedback electric signal to perform the spectrum analysis, and the time interval of the step-by-step updating is synchronous with the hardware operation time length of the hardware logic module. The application improves the response speed of the operating point of the silicon optical chip through the closed-loop control of the spectrum analysis and the step-by-step updating performed by the hardware logic module.

Description

Technical Field

[0001] This application relates to the field of optoelectronic control technology, and in particular to a silicon photonics chip operating point control system, electronic device and method. Background Technology

[0002] Silicon photonics chips utilize photons instead of electrons as information carriers, offering advantages such as high bandwidth, low power consumption, and low latency. However, the operating points of key components in silicon photonics chips, such as Mach-Zehnder modulators and micro-ring modulators, are susceptible to drift due to factors like temperature, wavelength, and process variations.

[0003] In related technologies, to ensure that these devices operate at their optimal linearity point or specific bias point, a central processing unit (CPU) typically uses a software-based closed-loop control system to adjust the bias voltage applied to the modulator in real time to achieve the modulator's optimal operating point. However, the response speed of the entire control loop is limited by the CPU's serial task execution capability. Furthermore, uncertainties such as software interrupts and operating system scheduling further limit the response speed of the entire control loop, making it impossible to effectively suppress high-speed, large-amplitude bias drift and severely affecting the modulation signal quality of silicon photonics chips. Summary of the Invention

[0004] This application provides a silicon photonics chip operating point control system, electronic device, and method, which solves the technical problem in related technologies where feedback control executed by software results in limited loop response speed, and achieves the technical effect of improving the operating point locking response speed.

[0005] To achieve the above objectives, the main technical solutions adopted in this application include: In a first aspect, this application provides a silicon photonics chip operating point control system, the system comprising: A bias drive module, the bias drive module being adapted to output a bias voltage, wherein the bias voltage includes a DC reference component and a scrambling component; A photoelectric detection module, wherein the photoelectric detection module is adapted to receive a modulated optical signal from a silicon photonic chip in response to the bias voltage, and convert the modulated optical signal into a feedback electrical signal; Hardware logic module, the hardware logic module being configured as follows: The DC reference component is updated in steps, and the feedback electrical signal is subjected to spectrum analysis under the disturbance of the scrambling component during the update process, so as to determine the optimal operating point of the silicon photonic chip based on the spectrum analysis results. The hardware logic module performs real-time Fourier transform on the feedback electrical signal based on a preset window to perform the spectrum analysis, and the time interval of the step update is synchronized with the hardware operation time of the hardware logic module to complete one spectrum analysis within the preset window.

[0006] The operating point control system proposed in this application updates the DC reference component in steps through a hardware logic module. During the step update process, the feedback signal is subjected to spectral analysis under scrambling component disturbances to determine the optimal operating point of the silicon photonics chip. Compared to related technologies where the feedback control algorithm is executed by the processor in software, this application utilizes a hardware logic module to perform spectral analysis, completing the feedback signal processing and bias voltage update decisions at the hardware level. This eliminates the need for software interrupt responses and task scheduling, avoiding processing delays caused by serial instruction execution. Furthermore, the hardware logic module performs real-time Fourier transforms on the feedback signal based on a preset window using hardware processing logic. The step update time interval is synchronized with the hardware computation time, ensuring that each bias voltage step update is synchronized with the completion of the spectral analysis. The iteration cycle of the control loop is directly determined by the hardware computation speed. Thus, from the output of the feedback signal from the photoelectric detection module to the triggering of the step update by the hardware logic module, a hardware-dominated closed-loop control link is formed, effectively improving the response speed of the operating point control and enabling the system to respond to bias drift more promptly. Meanwhile, real-time spectrum analysis based on a fixed preset window ensures consistency and stability for each analysis, which helps improve the accuracy of determining the optimal operating point.

[0007] Optionally, the hardware logic module is further configured as follows: The DC reference component is globally scanned with a first preset step size to obtain the global spectral characteristics of the feedback electrical signal associated with the scrambling component; The current operating point is determined based on the maximum amplitude of the global spectral characteristics, and a candidate bias range is determined based on the current operating point and a preset offset.

[0008] This application performs a coarse scan of the DC reference component using a first preset step size, which can quickly locate the current operating point corresponding to the maximum amplitude of the global spectral characteristics within a wide voltage range. Furthermore, by determining the candidate bias voltage range based on the current operating point and a preset offset, the subsequent fine scan range can be pre-limited to this candidate range. This effectively compresses the search space of subsequent scans while ensuring that the region where the optimal operating point is located is not lost, thereby further improving the overall operating point locking efficiency.

[0009] Optionally, the hardware logic module is further configured as follows: The first and second neighborhood voltage values ​​corresponding to the two interval boundaries of the candidate bias interval are determined, and the DC reference component is locally scanned based on the current operating point, the first neighborhood voltage value, and the second neighborhood voltage value to obtain the local spectral features of the feedback electrical signal associated with the scrambling component. The optimal operating point of the silicon photonic chip is determined based on the local spectral characteristics.

[0010] This application determines the first and second neighboring voltage values ​​corresponding to the two interval boundaries of a candidate bias voltage interval, and performs a local scan based on the current operating point and these two neighboring voltage values. This enables a more refined search of the DC reference component within the candidate interval, thereby obtaining more accurate local spectral characteristics. Compared to determining the candidate interval solely through a global scan, this local scanning process effectively improves the positioning accuracy of the optimal operating point.

[0011] Optionally, the hardware logic module is further configured as follows: If the maximum amplitude value in the local spectral features corresponds to the first neighborhood voltage value or the second neighborhood voltage value, then the current operating point is translated in the direction of the corresponding neighborhood voltage value according to the second preset step size, and the local scanning process is repeated until the maximum amplitude value in the local spectral features corresponds to the current operating point, so as to determine the optimal operating point based on the current operating point; Wherein, the second preset step size is smaller than the first preset step size.

[0012] This application determines whether the maximum amplitude of a local spectral feature corresponds to a neighboring voltage value at the interval boundary. When this condition is met, the current operating point is shifted in the corresponding direction by a second preset step size. This drives the current operating point to continuously move along the direction of increasing spectral feature, forming an iterative mechanism for directional optimization. This iterative process approaches the optimal operating point with finer voltage increments, thus improving positioning accuracy while ensuring the correct convergence direction. Repeated local scanning until the maximum amplitude corresponds to the current operating point ensures that the system eventually converges stably to the true optimal operating point, improving the accuracy and reliability of operating point locking.

[0013] Optionally, the hardware logic module includes a hardware Fast Fourier Transform core integrated on an FPGA chip, and the hardware Fast Fourier Transform core is configured to extract the amplitude of the first harmonic corresponding to the scrambling component in the feedback electrical signal as the global spectral feature or the local spectral feature.

[0014] Optionally, the silicon photonics chip includes a laser, and the system further includes a temperature control module integrated on the FPGA chip. The temperature control module is configured to acquire the operating temperature of the laser, generate a temperature compensation signal based on the operating temperature, and adjust the power of the laser using the temperature compensation signal to stabilize the light source temperature of the silicon photonics chip at a set value.

[0015] This application uses a temperature control module to acquire the laser's operating temperature and generate a temperature compensation signal. This compensation signal is then used to adjust the laser power, stabilizing the light source temperature at a set value. Since the laser's output wavelength drifts with changes in operating temperature, and the transmission characteristics of silicon photonics chips are closely related to wavelength, temperature instability can lead to power fluctuations caused by non-bias voltage mixing into the feedback signal. By locking the light source temperature at the set value through the temperature control module, interference from temperature drift on the modulated optical signal power can be effectively suppressed. This ensures that changes in the feedback signal only reflect adjustments to the bias voltage, thereby improving the accuracy of the mapping relationship between spectral characteristics and the bias operating point. This enhances the reliability of optimal operating point determination and strengthens the system's stability under different ambient temperature conditions.

[0016] Optionally, the bias drive module includes: The signal generating unit is configured to generate the scrambling component having a preset frequency; The signal superposition unit is configured to superimpose the scrambling component onto the DC reference component to output the bias voltage.

[0017] This application constructs a bias drive module by setting up a signal generation unit and a signal superposition unit. The signal generation unit generates a scrambling component with a preset frequency, and the signal superposition unit superimposes this scrambling component onto a DC reference component to output a bias voltage. This modular structure allows the frequency and amplitude of the scrambling component to be independently configured, enabling flexible adjustment of scrambling parameters according to different types of silicon photonics chips, thus enhancing the system's adaptability. Furthermore, the generation and superposition of the sinusoidal signal are directly completed by the hardware unit, eliminating the need for software synthesis of the scrambling signal and digital-to-analog conversion for output. This helps ensure the real-time performance and purity of the bias voltage output, providing a stable and reliable signal excitation source for subsequent spectrum analysis.

[0018] Secondly, this application provides an electronic device, the electronic device comprising: Silicon photonics chip; And the aforementioned silicon photonics chip operating point control system.

[0019] Thirdly, this application provides a method for controlling the operating point of a silicon photonic chip, the method being applied to the aforementioned silicon photonic chip operating point control system, the method comprising: Obtain a bias voltage, wherein the bias voltage includes a DC reference component and a scrambling component; The system receives a modulated optical signal from a silicon photonics chip in response to the bias voltage and converts the modulated optical signal into a feedback electrical signal. The DC reference component is updated in steps, and the feedback electrical signal is subjected to spectrum analysis under the disturbance of the scrambling component during the update process, so as to determine the optimal operating point of the silicon photonic chip based on the spectrum analysis results. Specifically, the feedback electrical signal is subjected to real-time Fourier transform based on a preset window to perform the spectrum analysis, and the time interval of the step update is synchronized with the hardware operation time for completing one spectrum analysis within the preset window.

[0020] Optionally, the silicon photonic chip includes a laser; Before acquiring the bias voltage, the method further includes: The operating temperature of the laser is collected, and a temperature compensation signal is generated based on the operating temperature. The power of the laser is adjusted using the temperature compensation signal so that the light source temperature of the silicon photonic chip is stabilized at a set value.

[0021] The operating point control method proposed in this application utilizes a hardware logic module to perform spectrum analysis, completing the feedback signal processing and bias voltage update decisions at the hardware level. This eliminates the need for software interrupt responses and task scheduling, avoiding processing delays caused by serial instruction execution. Furthermore, it can perform real-time Fourier transforms on the feedback signal based on a preset window, with the step update time interval synchronized with the hardware computation time. This ensures that each bias voltage update is synchronized with the completion of the spectrum analysis, and the iteration cycle of the control loop is directly determined by the hardware computation speed. Thus, from the output feedback signal from the photoelectric detection module to the triggering of step updates by the hardware logic module, a hardware-dominated closed-loop control link is formed, effectively improving the response speed of operating point control and enabling the system to respond to bias voltage drift more promptly. Simultaneously, real-time spectrum analysis based on a fixed preset window ensures the consistency and stability of each analysis, contributing to improved accuracy in determining the optimal operating point. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0023] Figure 1This is one of the structural schematic diagrams of a silicon photonics chip operating point control system provided in the embodiments of this application; Figure 2 A second schematic diagram of a silicon photonics chip operating point control system provided in this application embodiment; Figure 3 This is a flowchart illustrating a silicon photonics chip operating point control method provided in an embodiment of this application. Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0025] In silicon photonics chips, the operating points of key components such as Mach-Zehnder modulators (MZMs) and micro-ring modulators (MRMs) are susceptible to drift due to factors such as temperature, wavelength, and process variations. To ensure that these components operate at their optimal linearity point or specific bias point, a closed-loop control system is required to adjust the bias voltage applied to them in real time.

[0026] Currently, related technologies typically employ bias control schemes based on microcontroller units (MCUs) or digital signal processors (DSPs). However, this approach has the following drawbacks: First, the CPU of the MCU or DSP must execute all tasks sequentially, including sampling, algorithm calculation, and voltage output. When faced with computationally intensive control algorithms, the processor's computing power becomes a system bottleneck. Furthermore, the uncertainty and delay introduced by software interrupts and operating system scheduling limit the response speed of the control loop, making it difficult to effectively suppress high-speed, large-amplitude bias drift. Second, the interrupt- and software polling-based processing method results in jitter and unpredictability in the entire processing delay from photoelectric detection signal input to bias voltage output. This introduces additional noise and errors for applications requiring precise phase control (such as coherent optical communication). Third, high-performance MCUs or DSPs are inherently expensive, increasing system cost and printed circuit board area. Additionally, the high-frequency operation of the CPU core leads to higher power consumption.

[0027] In order to solve the problems of low control bandwidth, slow response speed, poor real-time performance and uncertain timing in the above-mentioned silicon photonics chip bias control scheme based on MCU / DSP, this application provides a silicon photonics chip 20 bias control scheme based on FPGA that is high-speed, low-latency, high real-time performance and timing deterministic.

[0028] Figure 1 This is a schematic diagram of the structure of a silicon photonics chip operating point control system 10 according to an embodiment of this application, as shown below. Figure 1 As shown, the system includes a bias driving module 11, a photoelectric detection module 12, and a hardware logic module 13. The bias driving module 11 is adapted to output a bias voltage, wherein the bias voltage includes a DC reference component and a scrambling component. The photoelectric detection module 12 is adapted to receive the modulated optical signal of the silicon photonic chip 20 in response to the bias voltage and convert the modulated optical signal into a feedback electrical signal. The hardware logic module 13 is configured to: perform step updates on the DC reference component, and perform spectrum analysis on the feedback electrical signal under the perturbation of the scrambling component during the step update process, so as to determine the optimal operating point of the silicon photonic chip 20 based on the spectrum analysis results; wherein, the hardware logic module 13 performs real-time Fourier transform on the feedback electrical signal based on a preset window to perform spectrum analysis, and the time interval of the step update is synchronized with the hardware operation time of the hardware logic module 13 to complete one spectrum analysis within the preset window.

[0029] Specifically, such as Figure 1 The silicon photonics chip 20 includes a laser 21, a modulator 22 (including but not limited to MZM, MRM, Sagnac ring, etc.), and a beam splitter 23. The laser 21 generates continuous laser light as a light source. The modulator 22 modulates the continuous laser light in response to a bias voltage and generates a modulated optical signal. The beam splitter 23 divides the modulated optical signal into two paths: one branch serves as the main optical path output, and the other branch is fed back to the photoelectric detection module 12. For example, one branch outputs 99% of the modulated optical signal through the fiber array, while the other branch sends 1% of the modulated optical signal to the photoelectric detection module 12 in the aforementioned operating point control system.

[0030] In this embodiment, the hardware logic module 13 described above is implemented using an FPGA chip. For example, the FPGA chip model is XC7VX690T. The FPGA chip also includes an analog-to-digital interface controller (ADC) and a digital-to-analog interface controller (DAC). The ADC controller is used to connect to an external analog-to-digital converter (ADC), and the DAC controller is used to connect to an external digital-to-analog converter (DAC). The FPGA chip also includes a timing control and state machine module to generate the precise timing control signals required for both the internal FPGA and the external ADC / DAC.

[0031] like Figure 1 As shown, the input terminal of the photoelectric detection module 12 is connected to another branch of the beam splitter 23 to receive the modulated optical signal. The output terminal of the photoelectric detection module 12 is connected to the input terminal of the hardware logic module 13 through an analog-to-digital converter. The input terminal of the hardware logic module 13 is connected to the input terminal of the bias drive module 11 through a digital-to-analog converter. The output terminal of the bias drive module 11 is connected to the bias electrode of the modulator 22.

[0032] Furthermore, the photoelectric detection module 12 includes a photodetector (PD) and an analog-to-digital converter. The photodetector is used to receive one modulated optical signal split by the beam splitter 23 and convert it into an analog electrical signal. The analog-to-digital converter is used to convert the analog electrical signal into a digital feedback electrical signal and output it to the hardware logic module 13.

[0033] Hardware logic module 13 consists of pure hardware logic circuits, including a lookup table, multipliers, adders, registers, and hardware fast Fourier transform cores. Unlike software solutions that rely on sequential CPU instruction execution, the arithmetic units of hardware logic module 13 can execute in parallel and synchronously, and the total delay from signal sampling to control output is fixed and completely predictable.

[0034] Furthermore, the timing control and state machine module generates a precise clock to control the analog-to-digital interface controller to read the feedback electrical signal S at a fixed, jitter-free, high-speed sampling rate (100 MSPS). f'b .

[0035] Hardware logic module 13 receives feedback electrical signals from photoelectric detection module 12, samples the feedback electrical signals based on a preset window, and performs real-time Fourier transform to extract spectral features associated with the scrambling components in the feedback electrical signals. Then, hardware logic module 13 determines the degree and direction of the deviation of the current operating point from the optimal operating point based on the extracted spectral features, and generates a DC reference component V with corresponding amplitude based on the determination result. dcThe digital signal is then converted into the DC reference component V by a digital-to-analog converter. dc The digital signal is converted into an analog signal and output to the bias drive module 11.

[0036] The bias drive module 11 receives the DC reference component V from the hardware logic module 13. dc The analog signal simultaneously generates a sinusoidal signal of a preset frequency as the aforementioned scrambling component V0. Then, the bias drive module 11 further generates the DC reference component V0. dc The bias voltage V is formed by superimposing the scrambling component V0. out The signal is then fed into the bias electrode of the silicon photonics chip 20. It is understood that the operating point of the modulator 22 is set by the bias voltage. Under the drive of the bias voltage, the transmission characteristic curve of the modulator 22 exhibits a cosine function shape. Specifically, the output optical power of the modulator 22 changes periodically with the change of the bias voltage. Different operating points correspond to different modulation characteristics. For example, the quadrature operating point is located at the midpoint of the linear region of the transmission characteristic curve, where the linearity of the modulated signal is optimal and the nonlinear distortion is minimal. Zero points or peak points are suitable for specific types of modulation formats. The DC reference component in the bias voltage is used to set the static operating point of the modulator 22 at the target position, while the scrambling component, by making a small-amplitude perturbation to the operating point near the static point, couples the deviation information of the operating point into the output optical signal in the form of a perturbation frequency component, so that it can be detected and corrected subsequently through spectrum analysis.

[0037] It should be noted that each time the hardware logic module 13 completes a spectrum analysis, it triggers a step update of the DC reference component. The time interval of this step update is synchronized with the hardware operation time of the hardware logic module 13 to complete a spectrum analysis within a preset window, so that the adjustment cycle of the bias voltage matches the operation rate of the spectrum analysis, thereby realizing real-time closed-loop control dominated by hardware.

[0038] In this way, through continuous iteration, the hardware logic module 13 gradually brings the DC reference component closer to the bias voltage position corresponding to the maximum amplitude of the spectral characteristics. This position is the optimal operating point of the modulator 22. When the hardware logic module 13 determines that the current spectral analysis result meets the optimal conditions, it stops the step update and locks the DC reference component at the current value, thereby ensuring that the operating point of the modulator 22 is stably maintained at the optimal operating point.

[0039] The operating point control system provided in this application embodiment updates the DC reference component in steps through the hardware logic module 13, and performs spectrum analysis on the feedback electrical signal under the disturbance of the scrambling component during the step update process to determine the optimal operating point of the silicon photonics chip 20. Compared with the feedback control algorithm executed by the processor in software in related technologies, this application uses the hardware logic module 13 to implement spectrum analysis, completing the decision-making of feedback electrical signal processing and bias voltage update at the hardware level, without the need for software interrupt response and task scheduling, thus avoiding the processing delay caused by serial instruction execution. Furthermore, the hardware logic module 13 uses hardware processing logic to perform real-time Fourier transform on the feedback electrical signal based on a preset window, and the time interval of the step update is synchronized with the hardware operation time, so that each step update of the bias voltage is synchronized with the completion time of the spectrum analysis, and the iteration rhythm of the control loop is directly determined by the hardware operation speed. Thus, from the output of the feedback electrical signal by the photoelectric detection module 12 to the triggering of the step update by the hardware logic module 13, a hardware-dominated closed-loop control link is formed, which effectively improves the response speed of the operating point control and enables the system to respond to bias drift more promptly. Meanwhile, real-time spectrum analysis based on a fixed preset window ensures consistency and stability for each analysis, which helps improve the accuracy of determining the optimal operating point.

[0040] Furthermore, such as Figure 2 As shown, in some embodiments of this application, the bias drive module 11 includes a signal generation unit 111 and a signal superposition unit 112. The signal generation unit 111 is configured to generate a scrambling component with a preset frequency, and the signal superposition unit 112 is configured to superimpose the scrambling component onto the DC reference component to output a bias voltage.

[0041] Specifically, the signal generation unit 111 is used to generate a sinusoidal signal as a scrambling component. For example, the frequency of the scrambling component is 600Hz. The signal superposition unit 112 is an adder circuit used to receive the DC reference component analog signal output by the hardware logic module 13 after digital-to-analog conversion, and electrically superimpose the scrambling component with the DC reference component to generate a bias voltage.

[0042] This embodiment of the application constructs a bias driving module 11 by setting a signal generation unit 111 and a signal superposition unit 112. The signal generation unit 111 is used to generate a scrambling component with a preset frequency, and the signal superposition unit 112 is used to superimpose the scrambling component onto the DC reference component to output a bias voltage. This modular structure allows the frequency and amplitude of the scrambling component to be configured independently, enabling flexible adjustment of scrambling parameters according to different types of silicon photonic chips 20, thus enhancing the system's adaptability. Furthermore, the generation and superposition of the sinusoidal signal are directly completed by the hardware unit, eliminating the need for software synthesis of the scrambling signal and digital-to-analog conversion for output. This helps ensure the real-time performance and purity of the bias voltage output, providing a stable and reliable signal excitation source for subsequent spectrum analysis.

[0043] like Figure 1 As shown, in some embodiments of this application, the laser 21 in the silicon photonic chip 20 can be a distributed feedback laser (DFB). A DFB is a semiconductor laser that achieves distributed feedback and wavelength selection by integrating a Bragg grating in the active waveguide layer. Its core feature is that it outputs a stable single-mode laser.

[0044] Furthermore, the system also includes a temperature control module 14 integrated on the FPGA chip. The temperature control module 14 is configured to acquire the operating temperature of the laser 21 and generate a temperature compensation signal based on the operating temperature. The power of the laser 21 is adjusted using the temperature compensation signal so that the light source temperature of the silicon photonic chip 20 is stabilized at the set value.

[0045] Specifically, the temperature control module 14 is implemented in hardware logic within the FPGA and includes a thermoelectric cooler (TEC) chip. It adjusts the drive current of the TEC chip using a PID control algorithm to perform heating or cooling operations on the laser 21, causing the actual operating temperature of the laser 21 to converge to the set value. The parameters of the PID control algorithm (such as the Kp, Ki, and Kd coefficients of the PID) can be dynamically reconfigured by an external CPU via the configuration bus within the FPGA (such as AXI-Lite), while the algorithm itself still runs on the hardware pipeline.

[0046] After the temperature of laser 21 stabilizes at the set value, the temperature control module 14 then controls laser 21 to turn on light output, ensuring that laser 21 outputs continuous laser light at a stable wavelength. By locking the temperature of laser 21 before optical power feedback detection, the temperature control module 14 eliminates the interference of output optical power fluctuations caused by wavelength drift on the subsequent bias control loop.

[0047] Furthermore, in this embodiment, temperature control and bias control are divided into two independent and coordinated control loops. The temperature control loop, as a slow loop, has a response time constant determined by the thermal time constant of the laser 21, and is used to maintain the long-term stability of the light source wavelength. The bias control loop, as a fast loop, has a response speed determined by the hardware logic module 13's spectrum analysis calculation time, and is used to track and suppress high-speed drift of the bias operating point in real time. The two control loops ensure the stable operation of the silicon photonics chip 20 from the two dimensions of the light source's physical characteristics and modulation electrical characteristics, respectively, avoiding control conflicts and cross-interferences that may occur when a single control loop simultaneously deals with disturbances at different time scales.

[0048] In this embodiment, the temperature control module 14 acquires the operating temperature of the laser 21 and generates a temperature compensation signal. This compensation signal is used to adjust the power of the laser 21, stabilizing the light source temperature at a set value. Since the output wavelength of the laser 21 drifts with changes in operating temperature, and the transmission characteristics of the silicon photonics chip 20 are closely related to wavelength, temperature instability can lead to power fluctuations caused by non-bias voltage mixing into the feedback electrical signal. By locking the light source temperature at the set value through the temperature control module 14, the interference of temperature drift on the modulated optical signal power can be effectively suppressed, ensuring that changes in the feedback electrical signal only reflect adjustments to the bias voltage. This improves the accuracy of the mapping relationship between spectral characteristics and the bias operating point, enhances the reliability of optimal operating point determination, and strengthens the stability of the system under different ambient temperature conditions.

[0049] In some embodiments of this application, the hardware logic module 13 is further configured to: perform a global scan of the DC reference component with a first preset step size to obtain global spectral characteristics associated with the scrambling component in the feedback electrical signal; determine the current operating point based on the maximum amplitude of the global spectral characteristics; and determine a candidate bias voltage range based on the current operating point and a preset offset.

[0050] Specifically, in the initial stage, the hardware logic module 13 performs a full-range scan of the DC reference component from the starting voltage to the ending voltage at a first preset step size. For example, the starting voltage is 0V, the ending voltage is 3V, and the first preset step size is 100mV. During the global scan, after each step update, the hardware logic module 13 updates the continuously input feedback electrical signal S. f'b Perform real-time Fourier transform to extract the feedback electrical signal S f'b The amplitude A1 of the first harmonic corresponding to the 600Hz scramble frequency is used as the global spectral feature mentioned above, and this amplitude is stored in relation to the voltage step.

[0051] It should be noted that, in some embodiments of this application, the optical power of the PD feedback is used as the feedback electrical signal S. f'b In some other embodiments of this application, as an alternative, the feedback electrical signal S...f'b It can also be an I / Q component signal from a coherent receiver, an eye diagram quality indicator (such as eye opening) from an optical sampling oscilloscope, or any other analog or digital signal that can characterize the bias state of the silicon photonics chip 20. Regardless of the specific type of feedback signal, as long as its subsequent processing and control are implemented based on an FPGA hardware pipeline, it can be considered an alternative implementation of the solution in this application.

[0052] Understandably, the specific process of the above-mentioned spectrum analysis is as follows: the hardware logic module 13 continuously samples the feedback electrical signal at a preset fixed sampling rate to obtain time-domain sampled data of a preset window length; the hardware logic module 13 performs a real-time Fourier transform on the time-domain sampled data to convert the time-domain signal to the frequency domain; the hardware logic module 13 extracts the first harmonic amplitude at the frequency point corresponding to the frequency of the scrambling component from the frequency domain result. The magnitude of this amplitude reflects the degree to which the current operating point deviates from the optimal operating point. Since the scrambling component is preset to a fixed frequency, the hardware logic module 13 only needs to extract the amplitude information corresponding to the fixed frequency point in the frequency domain, without scanning the entire frequency band, thereby significantly reducing the computational load and hardware resource overhead of the spectrum analysis. The entire spectrum analysis process is executed in a pipelined manner by the hardware fast Fourier transform kernel, without involving the fetching, decoding, and execution of software instructions, ensuring the real-time nature and determinism of the analysis results.

[0053] After the full-range scan is completed, the hardware logic module 13 compares the first harmonic amplitude corresponding to each voltage step, records the voltage value corresponding to the maximum amplitude as the current operating point, and determines the candidate bias voltage range with the current operating point as the center and a preset offset as the radius. For example, let the voltage value corresponding to the maximum amplitude be V. x With a preset offset of 20mV, the candidate bias range is (V x -20mV, V x V x +20mV).

[0054] This application embodiment performs a coarse scan of the DC reference component using a first preset step size through a global scan. This enables the rapid location of the current operating point corresponding to the maximum amplitude of the global spectral characteristics within a wide voltage range. Furthermore, by determining a candidate bias voltage range based on the current operating point and a preset offset, the subsequent fine scan range can be pre-limited within this candidate range. This effectively compresses the search space of subsequent scans while ensuring that the region where the optimal operating point is located is not lost, thereby further improving the overall operating point locking efficiency.

[0055] In some embodiments of this application, the hardware logic module 13 is further configured to: determine the first neighborhood voltage value and the second neighborhood voltage value corresponding to the two interval boundaries of the candidate bias interval, and perform a local scan of the DC reference component based on the current operating point, the first neighborhood voltage value and the second neighborhood voltage value to obtain the local spectral features associated with the scrambling component in the feedback electrical signal; and determine the optimal operating point of the silicon photonics chip 20 based on the local spectral features.

[0056] Furthermore, during the local fine scanning process, the hardware logic module 13 is also configured to: if the maximum amplitude value in the local spectral features corresponds to a first neighboring voltage value or a second neighboring voltage value, then shift the current operating point towards the corresponding neighboring voltage value direction by a second preset step size, and repeat the local scanning process until the maximum amplitude value in the local spectral features corresponds to the current operating point, so as to determine the optimal operating point based on the current operating point. The second preset step size is smaller than the first preset step size.

[0057] Specifically, the candidate bias range is (V x -20mV, V x V x As an example, during the local scan process, the DC reference component is set to V (+20mV). x -20mV, V x and V x +20mV, meaning the current operating point is V. x The voltage value of the first neighborhood is V x -20mV, second neighborhood voltage value V x +20mV, the second preset step size is 5mV. The hardware logic module 13 extracts the first harmonic amplitude A1 corresponding to the scrambling component in the feedback electrical signal from the above three voltage points as local spectral features, and compares the magnitudes of the three. It can be understood that the spectral analysis process here is the same as the global scanning process, which can be referred to in the previous description and will not be repeated here.

[0058] If the current working point V x If the amplitude is the largest at a given point, the current operating point is determined to be the optimal operating point, and the iteration stops. If the voltage value V in the first neighborhood is the largest... x The amplitude is largest at -20mV, so the current operating point is shifted to the side with the larger amplitude by a second preset step, and the shifted voltage value V is used as the reference. x -5mV is taken as the new current operating point. If the second neighboring voltage value V... x If the amplitude is maximum at +20mV, then shift the current operating point to the side with the larger amplitude by a second preset step size, and use the shifted voltage value V. x+5mV is used as the new current operating point. The above three-point spectrum analysis and comparison process is repeated until the local spectrum characteristic amplitude at the current operating point is the maximum value among the three points. The iteration stops when the current operating point is determined as the optimal operating point.

[0059] This embodiment of the application determines the first and second neighboring voltage values ​​corresponding to the two interval boundaries of the candidate bias interval, and performs a local scan based on the current operating point and these two neighboring voltage values. This enables a more refined search of the DC reference component within the candidate interval, thereby obtaining more accurate local spectral features. Compared to determining the candidate interval only through a global scan, this local scanning process can effectively improve the positioning accuracy of the optimal operating point.

[0060] Furthermore, this embodiment of the application determines whether the maximum amplitude of the local spectral features corresponds to the neighboring voltage value at the interval boundary, and when this condition is met, translates the current operating point in the corresponding direction by a second preset step size. This drives the current operating point to continuously move along the direction of increasing spectral features, forming an iterative mechanism for directional optimization. This iterative process can gradually approach the optimal operating point with finer voltage increments, thereby improving positioning accuracy while ensuring the correct convergence direction. Repeatedly performing local scans until the maximum amplitude corresponds to the current operating point ensures that the system eventually converges stably to the true optimal operating point, which helps improve the accuracy and reliability of operating point locking.

[0061] It is understood that the embodiments of this application implement global coarse scanning and local fine scanning through hardware logic module 13, combining the wide-range and rapid positioning capability of global scanning with the high-precision three-point comparison and iteration mechanism of local scanning. While ensuring a wide-range search capability, it achieves fine-grained optimal working point locking. This non-linear search method is faster and more noise-resistant than simple linear scanning. Furthermore, both global coarse scanning and local fine scanning are executed continuously in a pipeline manner by the same hardware logic module 13, without the need for software intervention, further shortening the total time from scanning start to locking completion.

[0062] In some embodiments of this application, the hardware logic module 13 includes a hardware Fast Fourier Transform core integrated on an FPGA chip, and the hardware Fast Fourier Transform core is configured to extract the amplitude of the first harmonic of the corresponding scrambling component in the feedback electrical signal as a global spectral feature or a local spectral feature.

[0063] Specifically, the hardware Fast Fourier Transform (FFT) core performs a real-time Fourier Transform on the feedback signal based on a preset window, extracting the first harmonic amplitude corresponding to the scrambling component in the feedback signal. The preset window length is a fixed value; for example, the data window length for a single frame FFT is 4096 sampling points. The window length determines the hardware computation time for the hardware FFT core to complete a single real-time Fourier Transform. In this embodiment, the step interval is strictly equal to the FFT calculation time for 4096 sampling points. That is, after completing the real-time Fourier Transform of each frame of data, the hardware FFT core outputs the calculation result of the first harmonic amplitude and triggers the step update of the DC reference component. The step update time interval is strictly synchronized with the hardware computation time to ensure that a stable spectrum analysis result can be obtained at each voltage step.

[0064] It should be noted that in some embodiments of this application, the analog-to-digital converter (ADC) and digital-to-analog converter (DAC) are implemented using independent external chips. Alternatively, for FPGA chips that integrate hard-core ADCs and DACs, the above functions can also be implemented directly using their internal ADC and DAC modules. In this case, the analog-to-digital interface controller and the DAC interface controller can be connected to the corresponding hard-core modules inside the FPGA chip, which can further reduce system costs and the printed circuit board area.

[0065] Therefore, compared with MCU / DSP-based software solutions, this application, through its parallel pipelined hardware architecture, reduces the computational latency of the control algorithm from microseconds or even milliseconds in MCU / DSP to nanoseconds, significantly improving control bandwidth and response speed. This effectively suppresses high-speed bias drift on the silicon photonics chip 20 caused by rapid thermal or electro-optic effects. Furthermore, the entire control process (sampling, calculation, and output) is completed by hardware logic within a fixed clock cycle, eliminating uncertainties such as software interrupts and task scheduling. The control loop latency is completely fixed and predictable. This deterministic ultra-low latency characteristic is particularly important for applications with stringent phase noise requirements, such as coherent optical communication and microwave photonics, significantly improving the system signal-to-noise ratio and bit error rate. Furthermore, in scenarios requiring high-speed, multi-channel control, FPGAs can utilize their abundant logic resources to implement multiple control modules in parallel. Low-end FPGAs can meet the requirements of this solution, and the cost per channel is far lower than that of using multiple high-performance MCUs or DSPs with high-speed ADCs / DACs. At the same time, this application completely offloads the heavy real-time control tasks to the FPGA hardware. If a CPU is present in the system, it can focus on non-real-time tasks such as upper-layer communication, data reporting, and system monitoring, further improving the overall system operating efficiency.

[0066] At the algorithm level, this application employs a variable step-size search strategy combining large-step coarse scanning with three-point neighborhood fine scanning. This nonlinear search method offers faster convergence and stronger noise resistance compared to simple linear scanning. Furthermore, this application establishes a hardware synchronization mechanism, ensuring that the step interval is strictly equal to the preset window's FFT operation time. This guarantees stable spectral analysis results at each voltage level, resolving the scanning omission problem caused by software delay uncertainties in traditional MCU / DSP solutions.

[0067] At the system architecture level, this embodiment divides temperature control and bias control into two independent and coordinated control loops. The temperature control loop, as a slow loop, has a response time constant determined by the thermal time constant of the laser 21, and is used to maintain the long-term stability of the light source wavelength. The bias control loop, as a fast loop, has a response speed determined by the spectrum analysis calculation time of the hardware logic module 13, and is used to track and suppress high-speed drift of the bias operating point in real time. The two control loops ensure the stable operation of the silicon photonics chip 20 from the two dimensions of the physical characteristics of the light source and the modulation electrical characteristics, respectively, avoiding the control conflicts and performance degradation that may occur when a single control loop simultaneously deals with disturbances at different time scales.

[0068] Accordingly, such as Figure 1 As shown, this application provides an electronic device, which includes a silicon photonics chip 20 and a silicon photonics chip operating point control system 10 as described in the above embodiment.

[0069] Further functional descriptions of the above modules and units are the same as those in the corresponding embodiments described above, and will not be repeated here.

[0070] The electronic device provided in this application, with its silicon photonics chip operating point control system 10, differs from related technologies where the feedback control algorithm is executed by a processor in software. Instead, it utilizes a hardware logic module 13 to perform spectrum analysis, completing the feedback signal processing and bias voltage update decisions at the hardware level. This eliminates the need for software interrupt responses and task scheduling, avoiding processing delays caused by serial instruction execution. Furthermore, the hardware logic module 13 includes a hardware Fast Fourier Transform (FFT) core, capable of performing real-time FFT on the feedback signal based on a preset window. The time interval for step updates is synchronized with the hardware computation time, ensuring that each bias voltage update is synchronized with the completion of the spectrum analysis. The iteration cycle of the control loop is directly determined by the hardware computation speed. Thus, from the output feedback signal from the photoelectric detection module 12 to the triggering of step updates by the hardware logic module 13, a hardware-dominated closed-loop control link is formed, effectively improving the response speed of operating point control and enabling the system to respond to bias voltage drift more promptly. Simultaneously, real-time spectrum analysis based on a fixed preset window ensures consistency and stability in each analysis, contributing to improved accuracy in determining the optimal operating point.

[0071] Accordingly, such as Figure 3 As shown, this application provides a method for controlling the operating point of a silicon photonics chip. The method is applied to the operating point control system described in the above embodiment and includes the following steps: Step S1: Obtain the bias voltage, wherein the bias voltage includes a DC reference component and a scrambling component; Step S3: Receive the modulated optical signal from the silicon photonics chip in response to the bias voltage, and convert the modulated optical signal into a feedback electrical signal; Step S5 involves performing a step update on the DC reference component and conducting a spectrum analysis on the feedback signal under the disturbance of the scrambling component during the step update process to determine the optimal operating point of the silicon photonics chip based on the spectrum analysis results. Specifically, a real-time Fourier transform is performed on the feedback signal based on a preset window to perform spectrum analysis, and the time interval of the step update is synchronized with the hardware computation time for completing one spectrum analysis within the preset window.

[0072] Furthermore, before obtaining the bias voltage, the method also includes: The operating temperature of the laser 21 is collected, and a temperature compensation signal is generated based on the operating temperature. The power of the laser 21 is adjusted using the temperature compensation signal so that the light source temperature of the silicon photonic chip 20 is stabilized at the set value.

[0073] Further descriptions of the above steps are the same as those in the corresponding embodiments described above, and will not be repeated here.

[0074] For ease of description, the above devices are described separately by function as various units. Of course, in implementing this application, the functions of each unit can be implemented in one or more software and / or hardware.

[0075] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0076] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to interchangeably. Each embodiment focuses on describing the differences from other embodiments. In particular, the method embodiments are basically similar to the system embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0077] The above description is merely an embodiment of this application and is not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

[0078] Although embodiments of this application have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of this application, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A silicon photonics chip operating point control system, characterized in that, The system includes: A bias drive module, the bias drive module being adapted to output a bias voltage, wherein the bias voltage includes a DC reference component and a scrambling component; A photoelectric detection module, wherein the photoelectric detection module is adapted to receive a modulated optical signal from a silicon photonic chip in response to the bias voltage, and convert the modulated optical signal into a feedback electrical signal; Hardware logic module, the hardware logic module being configured as follows: The DC reference component is updated in steps, and the feedback electrical signal is subjected to spectrum analysis under the disturbance of the scrambling component during the update process, so as to determine the optimal operating point of the silicon photonic chip based on the spectrum analysis results. The hardware logic module performs real-time Fourier transform on the feedback electrical signal based on a preset window to perform the spectrum analysis, and the time interval of the step update is synchronized with the hardware operation time of the hardware logic module to complete one spectrum analysis within the preset window.

2. The system according to claim 1, characterized in that, The hardware logic module is also configured to: The DC reference component is globally scanned with a first preset step size to obtain the global spectral characteristics of the feedback electrical signal associated with the scrambling component; The current operating point is determined based on the maximum amplitude of the global spectral characteristics, and a candidate bias range is determined based on the current operating point and a preset offset.

3. The system according to claim 2, characterized in that, The hardware logic module is also configured to: The first and second neighborhood voltage values ​​corresponding to the two interval boundaries of the candidate bias interval are determined, and the DC reference component is locally scanned based on the current operating point, the first neighborhood voltage value, and the second neighborhood voltage value to obtain the local spectral features of the feedback electrical signal associated with the scrambling component. The optimal operating point of the silicon photonic chip is determined based on the local spectral characteristics.

4. The system according to claim 3, characterized in that, The hardware logic module is also configured to: If the maximum amplitude value in the local spectral features corresponds to the first neighborhood voltage value or the second neighborhood voltage value, then the current operating point is translated in the direction of the corresponding neighborhood voltage value according to the second preset step size, and the local scanning process is repeated until the maximum amplitude value in the local spectral features corresponds to the current operating point, so as to determine the optimal operating point based on the current operating point; Wherein, the second preset step size is smaller than the first preset step size.

5. The system according to claim 3 or 4, characterized in that, The hardware logic module includes a hardware Fast Fourier Transform core integrated on an FPGA chip, and the hardware Fast Fourier Transform core is configured to extract the amplitude of the first harmonic corresponding to the scrambling component in the feedback electrical signal as the global spectral feature or the local spectral feature.

6. The system according to claim 5, characterized in that, The silicon photonics chip includes a laser, and the system also includes a temperature control module integrated on the FPGA chip. The temperature control module is configured to acquire the operating temperature of the laser, generate a temperature compensation signal based on the operating temperature, and adjust the power of the laser using the temperature compensation signal to stabilize the light source temperature of the silicon photonics chip at a set value.

7. The system according to claim 1, characterized in that, The bias drive module includes: The signal generating unit is configured to generate the scrambling component having a preset frequency; The signal superposition unit is configured to superimpose the scrambling component onto the DC reference component to output the bias voltage.

8. An electronic device, characterized in that, The electronic device includes: Silicon photonics chip; And the silicon photonics chip operating point control system as described in any one of claims 1 to 7.

9. A method for controlling the operating point of a silicon photonic chip, characterized in that, The method is applied to the silicon photonics chip operating point control system as described in any one of claims 1 to 7, and the method includes: Obtain a bias voltage, wherein the bias voltage includes a DC reference component and a scrambling component; The system receives a modulated optical signal from a silicon photonics chip in response to the bias voltage and converts the modulated optical signal into a feedback electrical signal. The DC reference component is updated in steps, and the feedback electrical signal is subjected to spectrum analysis under the disturbance of the scrambling component during the update process, so as to determine the optimal operating point of the silicon photonic chip based on the spectrum analysis results. Specifically, the feedback electrical signal is subjected to real-time Fourier transform based on a preset window to perform the spectrum analysis, and the time interval of the step update is synchronized with the hardware operation time for completing one spectrum analysis within the preset window.

10. The method according to claim 9, characterized in that, The silicon photonic chip includes a laser; Before acquiring the bias voltage, the method further includes: The operating temperature of the laser is collected, and a temperature compensation signal is generated based on the operating temperature. The power of the laser is adjusted using the temperature compensation signal so that the light source temperature of the silicon photonic chip is stabilized at a set value.

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