A multi-mode adaptive jamming signal generator

Abstract

The application discloses a kind of multi-mode adaptive interference signal generators, belong to communication technical field, including control link module, local oscillator signal generation unit, digital interference generation module, combiner CB1, coupler DC1, power amplitude control unit and feedback control unit, solve the technical problem that radio frequency test signal source can carry out multiple signal collaborative configuration, output power is stable, and can be switched under different test working conditions fast, the application can generate three independent radio frequency signals, amplitude, phase, frequency and modulation mode can be independently adjusted, can realize wide frequency band, high-precision radio frequency test, satisfy different product performance test demand, guarantee measurement result reliability, multistage filter, equalizer and radio frequency shaping processing, realize high signal-to-noise ratio test signal, improve debugging precision, improve long-term operation and test stability under multiple environments, can be system-level multi-signal interference simulation test, provide reliable data support for product research and development.

Description

Technical Field

[0001] This invention belongs to the field of communication technology, and in particular relates to a multi-mode adaptive interference signal generator. Background Technology

[0002] In the research and development and production of communication equipment, radio frequency modules, and electronic systems, it is often necessary to debug and test the performance of the product under test under different operating conditions, such as receiver sensitivity, anti-interference capability, dynamic range, and linearity. Therefore, a radio frequency test signal source capable of outputting multiple frequencies, amplitudes, and modulation methods is often needed to simulate different operating environments and excitation conditions.

[0003] Currently, most existing RF test signal sources employ a single signal channel structure or combine multiple independent devices to output multiple test signals. However, these technologies are not only large and costly, but also lack a unified control and synchronization mechanism between multiple signals, making it difficult to meet the needs of coordinated configuration and rapid switching of multiple RF signals in complex testing scenarios.

[0004] In addition, existing RF test equipment mostly adopts open-loop regulation in output power control, which is easily affected by device aging, temperature changes and load conditions, resulting in unstable output amplitude and thus reducing the accuracy and repeatability of test results.

[0005] Therefore, there is an urgent need for a compact, highly configurable RF signal generator capable of coordinating the output of multiple RF test signals and having adaptive power adjustment capabilities, in order to improve the efficiency and reliability of performance debugging and testing of products under test. Summary of the Invention

[0006] The purpose of this invention is to provide a multi-mode adaptive interference signal generator, which solves the technical problems of radio frequency test signal sources being able to perform multi-channel signal collaborative configuration, stable output power, and rapid switching under different test conditions.

[0007] To achieve the above objectives, the present invention adopts the following technical solution:

[0008] A multi-mode adaptive interference signal generator includes a control link module, a local oscillator signal generation unit, a digital interference generation module, a combiner CB1, a coupler DC1, a power amplitude control unit, and a feedback control unit. The local oscillator signal generation unit, the digital interference generation module, the power amplitude control unit, and the feedback control unit are all connected to the control link module. The digital interference generation module is connected to the combiner CB1, the combiner CB1 is connected to the coupler DC1, and the coupler DC1 is connected to both the power amplitude control unit and the feedback control unit. The local oscillator signal generation unit is also connected to the digital interference generation module. The control link module is connected to a host computer.

[0009] The control link module is used to control and configure the three interference signal sources; the local oscillator signal generation unit is used to generate the local oscillator signal.

[0010] The digital interference generation module includes three signal channels, which are used to amplify and filter the three interference signal sources and mix them with the local oscillator signal, respectively; the three signal channels are controlled by three radio frequency switches; the combiner CB1 is used to combine the three signals output by the digital interference generation module and output the combined signal RFSELout.

[0011] The direct path of coupler DC1 is used to output the combined signal RFSELout to the power amplitude control unit; the coupling path of coupler DC1 is used to output the coupled signal to the feedback control unit.

[0012] The power amplitude control unit is used to attenuate, amplify, filter and equalize the combined signal RFSELout, and output the final interference output signal RF_OUT; the feedback control unit is used to detect the power of the coupled signal and feed the detection result back to the control link module.

[0013] Preferably, the control link module includes a communication module, an FPGA chip IC10, a DAC module IC12, a DAC module IC13, and a DDS module IC14;

[0014] The communication module, DAC module IC12, DAC module IC13 and DDS module IC14 are all connected to the FPGA chip IC10;

[0015] The communication module connects to the host computer and establishes communication.

[0016] DAC module IC12, DAC module IC13 and DDS module IC14 output interference source DAC_A, interference source DAC_B and interference source DAC_C respectively;

[0017] Interference source DAC_A, interference source DAC_B, and interference source DAC_C constitute the three interference signal sources;

[0018] The three signal channels of the digital interference generation module are the first signal channel, the second signal channel, and the third signal channel, respectively.

[0019] The first signal channel, the second signal channel, and the third signal channel respectively receive interference source DAC_A, interference source DAC_B, and interference source DAC_C;

[0020] The signal output terminals of the first signal channel, the second signal channel, and the third signal channel are each independently controlled by three radio frequency switches;

[0021] The local oscillator signal generation unit includes a local oscillator signal module IC15, a buffer amplifier IC16, a buffer amplifier IC17, a buffer amplifier IC18, a filter LPF6, a filter LPF7, and a filter LPF8. The local oscillator signal module IC15 is connected to the FPGA chip IC10, and the local oscillator signal module IC15 is also connected to the input terminals of the buffer amplifier IC16, the buffer amplifier IC17, and the buffer amplifier IC18, respectively.

[0022] The output of buffer amplifier IC16 is connected to filter LPF6, and filter LPF6 outputs the local oscillator LOA.

[0023] The output of buffer amplifier IC17 is connected to filter LPF7, and filter LPF7 outputs the local oscillator LOB.

[0024] The output of buffer amplifier IC18 is connected to filter LPF8, and filter LPF8 outputs the local oscillator LOC.

[0025] Local oscillator source LOA, local oscillator source LOB, and local oscillator source LOC constitute the local oscillator signal, which is respectively input to the first signal channel, the second signal channel, and the third signal channel;

[0026] The first signal channel mixes the local oscillator LOA with the interference source DAC_A; the second signal channel mixes the local oscillator LOB with the interference source DAC_B; and the third signal channel mixes the local oscillator LOC with the interference source DAC_C.

[0027] Preferably, the first signal channel includes a filter LPF1, a vector modulator IC19, a mixer MIX1, an attenuator IC1, a filter LPF2, and an RF switch SPDT1;

[0028] The input of filter LPF1 is connected to the interference source DAC_A, and the output is connected to vector modulator IC19. Vector modulator IC19 is connected to mixer MIX1. Mixer MIX1 is connected to attenuator IC1. Attenuator IC1 is connected to filter LPF2. Filter LPF2 is connected to RF switch SPDT1. RF switch SPDT1 outputs signal SPDT_A. Mixer MIX1 is also connected to the local oscillator LOA. Attenuator IC1 is also connected to FPGA chip IC10.

[0029] The second signal channel includes filter BPF1, vector modulator IC20, mixer MIX2, attenuator IC2, filter LPF3, and RF switch SPDT2;

[0030] The input of filter BPF1 is connected to the interference source DAC_B, and the output is connected to vector modulator IC20. Vector modulator IC20 is connected to mixer MIX2. Mixer MIX2 is connected to attenuator IC2. Attenuator IC2 is connected to filter LPF3. Filter LPF3 is connected to RF switch SPDT2. RF switch SPDT2 outputs signal SPDT_B. Mixer MIX2 is also connected to the local oscillator LOB. Attenuator IC2 is also connected to FPGA chip IC10.

[0031] The third signal channel includes a filter LPF10, a vector modulator IC21, a mixer MIX3, an attenuator IC3, a filter LPF4, and an RF switch SPDT3;

[0032] The input of filter LPF10 is connected to the interference source DAC_C, and the output is connected to vector modulator IC21. Vector modulator IC21 is connected to mixer MIX3. Mixer MIX3 is connected to attenuator IC3. Attenuator IC3 is connected to filter LPF4. Filter LPF4 is connected to RF switch SPDT3. RF switch SPDT3 outputs signal SPDT_C. Mixer MIX3 is also connected to the local oscillator LOC. Attenuator IC3 is also connected to FPGA chip IC10.

[0033] RF switches SPDT1, SPDT2, and SPDT3 are all connected to the FPGA chip IC10.

[0034] Signals SPDT_A, SPDT_B, and SPDT_C constitute the three signals output by the digital interference generation module, all of which enter the combiner CB1.

[0035] Preferably, the communication module is model W5500; the FPGA chip IC10 is model XC7A100T-2FTG256C; the DAC module IC12 and the DAC module IC13 are both model AD9744; and the DDS module IC14 is model AD9910.

[0036] The filters LPF1, LPF2, LPF3, LPF4, LPF6, LPF7 and LPF8 are all of model LFHP-6000;

[0037] The vector modulator IC19, the vector modulator IC20, and the vector modulator IC21 are all of model AD8340;

[0038] The mixers MIX1, MIX2, and MIX3 are all of model HMC219B;

[0039] The attenuator IC1, attenuator IC2 and attenuator IC3 are all model PE43711;

[0040] The radio frequency switch SPDT1, the radio frequency switch SPDT2 and the radio frequency switch SPDT3 are all of model HMC547;

[0041] The filter BPF1 is model SBP-1000+;

[0042] The filter LPF10 is model LFHP-6000;

[0043] The model of the local oscillator signal module IC15 is AD9910;

[0044] The buffer amplifier IC16, the buffer amplifier IC17, and the buffer amplifier IC18 are all of model ADL5610.

[0045] Preferably, the power amplitude control unit includes a driver amplifier IC5, an attenuator IC8, a medium power amplifier IC6, a final stage amplifier IC7, a filter BPF2, an equalizer EQ1, and a filter LPF5;

[0046] The feedback control unit includes a power detection module IC30 and an ADC module IC9;

[0047] The combined signal RFSELout is connected to Port1 of coupler DC1, Port2 of coupler DC1 is connected to the input of driver amplifier IC5, Port4 is connected to matching load R1, and Port3 is connected to power detection module IC30.

[0048] The output of the driver amplifier IC5 is connected to the attenuator IC8, the attenuator IC8 is connected to the input of the medium power amplifier IC6, the output of the medium power amplifier IC6 is connected to the input of the final stage amplifier IC7, the output of the final stage amplifier IC7 is connected to the filter BPF2, the filter BPF2 is connected to the equalizer EQ1, the equalizer EQ1 is connected to the filter LPF5, and the filter LPF5 outputs the final interference output signal RF_OUT.

[0049] The power detection module IC30 is connected to the ADC module IC9;

[0050] Both the ADC module IC9 and the attenuator IC8 are connected to the FPGA chip IC10.

[0051] Preferably, the driver amplifier IC5 is model ADL5610; the attenuator IC8 is model PE43711; the medium power amplifier IC6 is model QPA1043; the final stage amplifier IC7 is model CGH40010F; the filter BPF2 is model SBP-3000+; the equalizer EQ1 is model TR-EQ-6000; the filter LPF5 is model LFHP-6000; the power detection module IC30 is model ADL5513; the ADC module IC9 is model AD7980; the combiner CB1 is model ZFRSC-2050+; and the coupler DC1 is model QPD-30-6-20.

[0052] This invention discloses a multi-mode adaptive interference signal generator, which solves the technical problems of RF test signal sources enabling multi-channel signal collaborative configuration, stable output power, and rapid switching under different test conditions. This invention can generate three independent RF signals, with independently adjustable amplitude, phase, frequency, and modulation method, allowing for more comprehensive performance tuning of the product under test under multi-signal and multi-frequency conditions. The front end can be configured with a local oscillator frequency of 0.5–3 GHz. Combined with the baseband signal, it can achieve wide-band, high-precision RF testing, meeting the performance testing needs of different products. Through multi-stage amplification, programmable attenuators, and closed-loop power feedback adjustment, the output power is stable and repeatable, ensuring the reliability of measurement results. Multi-stage filters, equalizers, and RF shaping processing are also included. Effectively suppresses spurious and out-of-band signals, achieving high signal-to-noise ratio test signals and improving debugging accuracy. Real-time power detection and feedback control can automatically compensate for temperature drift, device discreteness, and load changes, improving long-term operation and testing stability under various environments. The FPGA-controlled DAC / DDS module can flexibly output various signal types, including sine, amplitude modulation, frequency modulation, or arbitrary waveforms, enabling rapid adaptation for new products or multi-scenario testing. Front-end signal synthesis, power conditioning, and feedback control are integrated into a single platform, reducing the number of external test equipment and improving debugging efficiency in laboratories or production lines. It can be used for performance debugging of various products under test, such as RF communication modules, antennas, power amplifiers, and receivers, and can also perform system-level multi-signal interference simulation testing, providing reliable data support for product development. Attached Figure Description

[0053] Figure 1 This is a block diagram illustrating the principle of the present invention;

[0054] Figure 2 This is a schematic block diagram of the control link module of the present invention;

[0055] Figure 3 This is a block diagram of the digital interference generation module of the present invention;

[0056] Figure 4 This is a schematic block diagram of the combiner CB1, coupler DC1, and power amplitude control unit of the present invention;

[0057] Figure 5 This is a block diagram of the local oscillator signal generation unit of the present invention. Detailed Implementation

[0058] Depend on Figures 1-5The multi-mode adaptive interference signal generator shown includes a control link module, a local oscillator signal generation unit, a digital interference generation module, a combiner CB1, a coupler DC1, a power amplitude control unit, and a feedback control unit. The local oscillator signal generation unit, the digital interference generation module, the power amplitude control unit, and the feedback control unit are all connected to the control link module. The digital interference generation module is connected to the combiner CB1. The combiner CB1 is connected to the coupler DC1. The coupler DC1 is connected to both the power amplitude control unit and the feedback control unit.

[0059] The local oscillator signal generation unit is also connected to the digital interference generation module; the control link module is connected to the host computer.

[0060] The control link module is used to control and configure the three interference signal sources; the local oscillator signal generation unit is used to generate the local oscillator signal.

[0061] The digital interference generation module includes three signal channels, which are used to amplify and filter the three interference signal sources and mix them with the local oscillator signal, respectively; the three signal channels are controlled by three radio frequency switches; the combiner CB1 is used to combine the three signals output by the digital interference generation module and output the combined signal RFSELout.

[0062] The control link module includes a communication module, an FPGA chip IC10, a DAC module IC12, a DAC module IC13, and a DDS module IC14;

[0063] The communication module, DAC module IC12, DAC module IC13 and DDS module IC14 are all connected to the FPGA chip IC10;

[0064] The communication module connects to the host computer and establishes communication.

[0065] DAC module IC12, DAC module IC13 and DDS module IC14 output interference source DAC_A, interference source DAC_B and interference source DAC_C respectively;

[0066] Interference source DAC_A, interference source DAC_B, and interference source DAC_C constitute the three interference signal sources;

[0067] The three signal channels of the digital interference generation module are the first signal channel, the second signal channel, and the third signal channel, respectively.

[0068] The first signal channel, the second signal channel, and the third signal channel respectively receive interference source DAC_A, interference source DAC_B, and interference source DAC_C;

[0069] The signal output terminals of the first signal channel, the second signal channel, and the third signal channel are each independently controlled by three radio frequency switches;

[0070] The local oscillator signal generation unit includes a local oscillator signal module IC15, a buffer amplifier IC16, a buffer amplifier IC17, a buffer amplifier IC18, a filter LPF6, a filter LPF7, and a filter LPF8. The local oscillator signal module IC15 is connected to the FPGA chip IC10, and the local oscillator signal module IC15 is also connected to the input terminals of the buffer amplifier IC16, the buffer amplifier IC17, and the buffer amplifier IC18, respectively.

[0071] The output of buffer amplifier IC16 is connected to filter LPF6, and filter LPF6 outputs the local oscillator LOA.

[0072] The output of buffer amplifier IC17 is connected to filter LPF7, and filter LPF7 outputs the local oscillator LOB.

[0073] The output of buffer amplifier IC18 is connected to filter LPF8, and filter LPF8 outputs the local oscillator LOC.

[0074] Local oscillator source LOA, local oscillator source LOB, and local oscillator source LOC constitute the local oscillator signal, which is respectively input to the first signal channel, the second signal channel, and the third signal channel;

[0075] The first signal channel mixes the local oscillator LOA with the interference source DAC_A; the second signal channel mixes the local oscillator LOB with the interference source DAC_B; and the third signal channel mixes the local oscillator LOC with the interference source DAC_C.

[0076] The first signal channel includes a filter LPF1, a vector modulator IC19, a mixer MIX1, an attenuator IC1, a filter LPF2, and an RF switch SPDT1;

[0077] The input of filter LPF1 is connected to the interference source DAC_A, and the output is connected to vector modulator IC19. Vector modulator IC19 is connected to mixer MIX1. Mixer MIX1 is connected to attenuator IC1. Attenuator IC1 is connected to filter LPF2. Filter LPF2 is connected to RF switch SPDT1. RF switch SPDT1 outputs signal SPDT_A. Mixer MIX1 is also connected to the local oscillator LOA. Attenuator IC1 is also connected to FPGA chip IC10.

[0078] The second signal channel includes filter BPF1, vector modulator IC20, mixer MIX2, attenuator IC2, filter LPF3, and RF switch SPDT2;

[0079] The input of filter BPF1 is connected to the interference source DAC_B, and the output is connected to vector modulator IC20. Vector modulator IC20 is connected to mixer MIX2. Mixer MIX2 is connected to attenuator IC2. Attenuator IC2 is connected to filter LPF3. Filter LPF3 is connected to RF switch SPDT2. RF switch SPDT2 outputs signal SPDT_B. Mixer MIX2 is also connected to the local oscillator LOB. Attenuator IC2 is also connected to FPGA chip IC10.

[0080] The third signal channel includes a filter LPF10, a vector modulator IC21, a mixer MIX3, an attenuator IC3, a filter LPF4, and an RF switch SPDT3;

[0081] The input of filter LPF10 is connected to the interference source DAC_C, and the output is connected to vector modulator IC21. Vector modulator IC21 is connected to mixer MIX3. Mixer MIX3 is connected to attenuator IC3. Attenuator IC3 is connected to filter LPF4. Filter LPF4 is connected to RF switch SPDT3. RF switch SPDT3 outputs signal SPDT_C. Mixer MIX3 is also connected to the local oscillator LOC. Attenuator IC3 is also connected to FPGA chip IC10.

[0082] RF switches SPDT1, SPDT2, and SPDT3 are all connected to the FPGA chip IC10.

[0083] Signals SPDT_A, SPDT_B, and SPDT_C constitute the three signals output by the digital interference generation module, all of which enter the combiner CB1.

[0084] The communication module is model W5500; the FPGA chip IC10 is model XC7A100T-2FTG256C; the DAC module IC12 and the DAC module IC13 are both model AD9744; the DDS module IC14 is model AD9910, 0.5–3GHz, 14-bit frequency control word, PN<-90dBc / Hz@20kHz;

[0085] The filters LPF1, LPF2, LPF3, LPF4, LPF6, LPF7, and LPF8 are all of model LFHP-6000, with f_c=6GHz, IL<1dB, and RL>20dB.

[0086] The vector modulator IC19, the vector modulator IC20 and the vector modulator IC21 are all AD8340, 0–1V input, 360° continuous control, DC–3GHz;

[0087] Mixer MIX1, mixer MIX2 and mixer MIX3 are all HMC219B, RF / LO: 0.5–3GHz, IF=DC–500MHz, ConversionLoss=8dB, LO-RFIsolation>30dB;

[0088] The attenuator IC1, attenuator IC2 and attenuator IC3 are all model PE43711, 0–31.5dB, 0.5dB step, 0.1–3GHz.

[0089] The radio frequency switch SPDT1, the radio frequency switch SPDT2 and the radio frequency switch SPDT3 are all of model HMC547;

[0090] The filter BPF1 is model SBP-1000+, with the following parameters: f0=1GHz, BW=200MHz, IL<1dB, RL>20dB.

[0091] The filter LPF10 is model LFHP-6000;

[0092] The model of the local oscillator signal module IC15 is AD9910;

[0093] The buffer amplifier IC16, the buffer amplifier IC17, and the buffer amplifier IC18 are all of model ADL5610.

[0094] In this embodiment, the front-end signal synthesis and frequency conversion consists of a control link module, a local oscillator signal generation unit, and a digital interference generation module. The control link module establishes a communication connection with the host computer through the communication module and configures and controls the FPGA chip according to the configuration parameters issued by the host computer. The FPGA chip controls the output parameters of the DAC module IC12, DAC module IC13, and DDS module IC14 respectively, thereby generating three digital baseband signals, which constitute interference source DAC_A, interference source DAC_B, and interference source DAC_C respectively.

[0095] Under the control of the FPGA chip, the local oscillator signal generation unit generates a programmable local oscillator signal from the local oscillator signal module IC15. After passing through three buffer amplifiers and low-pass filters, it forms local oscillator sources LOA, LOB and LOC respectively, which are used for frequency conversion of the three signal channels.

[0096] The digital interference generation module includes a first signal channel, a second signal channel, and a third signal channel. The three signal channels respectively perform filtering, vector modulation, and mixing processing on the corresponding digital baseband signals to realize the frequency conversion from baseband signals to radio frequency signals.

[0097] First signal channel: After the interference source DAC_A is filtered by low-pass filter LPF1 to suppress image and spurious signals, it enters vector modulator IC19 to achieve amplitude and phase modulation. Then, it is up-converted in mixer MIX1 with local oscillator LOA. The mixed output signal is amplitude controlled and out-of-band suppressed by programmable attenuator IC1 and low-pass filter LPF2. Finally, the radio frequency signal SPDT_A is output by radio frequency switch SPDT1.

[0098] Second signal channel: The interference source DAC_B is first limited in frequency band by the bandpass filter BPF1, and then modulated by the vector modulator IC20. It is then frequency-converted with the local oscillator LOB in the mixer MIX2. The mixed output signal is then amplitude-adjusted and spectrum-cleaned by the attenuator IC2 and the low-pass filter LPF3, and finally output as the radio frequency signal SPDT_B by the radio frequency switch SPDT2.

[0099] The third signal channel: The interference source DAC_C is filtered by the low-pass filter LPF10 and then enters the vector modulator IC21 for modulation processing. It is then frequency-converted with the local oscillator LOC in the mixer MIX3. The mixed output signal is processed by the attenuator IC3 and the low-pass filter LPF4, and then the radio frequency signal SPDT_C is output by the radio frequency switch SPDT3.

[0100] Finally, the three RF signals SPDT_A, SPDT_B and SPDT_C can be independently turned on or off under the control of the FPGA chip, and together they constitute the multi-channel RF output of the front-end signal synthesis and frequency conversion unit.

[0101] The three RF signals SPDT_A, SPDT_B, and SPDT_C are completely independent and controllable in terms of frequency, amplitude, phase, and modulation method. They can flexibly simulate RF test signals of different frequency bands and modulation forms, significantly improving the debugging and performance evaluation capabilities of the product under test under multiple operating conditions and multiple frequency points.

[0102] The direct path of coupler DC1 is used to output the combined signal RFSELout to the power amplitude control unit; the coupling path of coupler DC1 is used to output the coupled signal to the feedback control unit.

[0103] The power amplitude control unit is used to attenuate, amplify, filter and equalize the combined signal RFSELout, and output the final interference output signal RF_OUT; the feedback control unit is used to detect the power of the coupled signal and feed the detection result back to the control link module.

[0104] The power amplitude control unit includes a driver amplifier IC5, an attenuator IC8, a medium power amplifier IC6, a final stage amplifier IC7, a filter BPF2, an equalizer EQ1, and a filter LPF5.

[0105] The feedback control unit includes a power detection module IC30 and an ADC module IC9;

[0106] The combined signal RFSELout is connected to Port1 of coupler DC1, Port2 of coupler DC1 is connected to the input of driver amplifier IC5, Port4 is connected to matching load R1, and Port3 is connected to power detection module IC30.

[0107] The output of the driver amplifier IC5 is connected to the attenuator IC8, the attenuator IC8 is connected to the input of the medium power amplifier IC6, the output of the medium power amplifier IC6 is connected to the input of the final stage amplifier IC7, the output of the final stage amplifier IC7 is connected to the filter BPF2, the filter BPF2 is connected to the equalizer EQ1, the equalizer EQ1 is connected to the filter LPF5, and the filter LPF5 outputs the final interference output signal RF_OUT.

[0108] The power detection module IC30 is connected to the ADC module IC9;

[0109] Both the ADC module IC9 and the attenuator IC8 are connected to the FPGA chip IC10.

[0110] The driver amplifier IC5 is model ADL5610, with gain = 20dB, P1dB = +16dBm, 0.5–3GHz, and NF < 3dB; the attenuator IC8 is model PE43711; the medium power amplifier IC6 is model QPA1043, with gain = 38dB, P1dB = +43dBm, 0.5–3GHz; the final stage amplifier IC7 is model CGH40010F, with gain = 10dB, P3dB = +50dBm, 0.5–3GHz; and the filter BPF2 is model SBP-3000+, with BPF2: f0 = 3GHz, BW = 500MHz. IL < 1.2dB, RL > 18dB; the equalizer EQ1 is model TR-EQ-6000; the filter LPF5 is model LFHP-6000; the power detection module IC30 is model ADL5513, -30 to +13dBm, 0.5–3GHz; the ADC module IC9 is model AD7980, 16-bit, 1MSPS; the combiner CB1 is model ZFRSC-2050+; the coupler DC1 is model QPD-30-6-20, 0.5–3GHz, Coupling 6dB±0.5, IL < 1dB, Isolation > 20dB.

[0111] In this embodiment, the radio frequency power conditioning and output are accomplished by the combiner CB1, the coupler DC1, and the power amplitude control unit. The three radio frequency signals SPDT_A, SPDT_B, and SPDT_C from the front-end signal synthesis and frequency conversion unit first enter the combiner CB1 for radio frequency combining to form the combined signal RFSELout.

[0112] The combined signal RFSELout is power-distributed through coupler DC1. The signal input of the direct channel is sent to the power amplitude control unit, while the signal of the coupled channel is output to the closed-loop power monitoring unit for subsequent power detection.

[0113] The power amplitude control unit sequentially includes a driver amplifier IC5, a programmable attenuator IC8, a medium-power amplifier IC6, and a final-stage power amplifier IC7. Through multi-stage amplification and attenuation, it achieves a wide dynamic range adjustment of the RF output power. The amplified signal is then spectrally shaped and amplitude-frequency characteristic compensated by a bandpass filter BPF2, an equalizer EQ1, and a low-pass filter LPF5 before outputting the final RF test signal RF_OUT.

[0114] This embodiment employs a multi-stage conditioning structure of "attenuation-amplification-filtering-equalization" to effectively suppress out-of-band spurious signals and power fluctuations while ensuring a wide adjustable range of output power. This ensures that the output RF signal has good amplitude consistency and spectral purity throughout the entire operating frequency band, making it suitable for high-precision RF performance testing of the product under test.

[0115] In this embodiment, closed-loop power monitoring and adaptive control are performed by the feedback control unit. The coupling signal output by the coupler DC1 is input to the power detection module IC30. The power detection module converts the radio frequency signal into a voltage signal proportional to the power, and the ADC module IC9 performs analog-to-digital conversion before feeding it back to the FPGA chip IC10.

[0116] Based on the feedback power detection results, the FPGA chip dynamically adjusts the DAC output parameters in the front-end signal synthesis and frequency conversion unit and the programmable attenuator IC8 in the power amplitude control unit to achieve closed-loop control of the RF output power.

[0117] By introducing a closed-loop power feedback mechanism, the feedback control unit can effectively compensate for the impact of temperature drift, device variability, and load changes on output power, enabling the system to maintain stable and repeatable RF output power during long-term operation and under different working conditions, thereby improving the consistency and reliability of test results.

[0118] For example, in a scenario covering an RF test band from 0.5 GHz to 3 GHz, the frequency planning method is as follows:

[0119] The baseband frequency range of the three signals DAC_A, DAC_B and DAC_C is preferably DC to hundreds of megahertz.

[0120] The local oscillator frequency output by the local oscillator signal module IC15 can be programmably configured in the range of 0.5GHz to 3GHz.

[0121] The first signal channel generates a first RF test signal in the range of 0.5–3 GHz by mixing the baseband signal with the local oscillator LOA. The second signal channel generates a second RF test signal with a different center frequency than the first signal channel by mixing the local oscillator LOB with the corresponding baseband signal. The third signal channel generates a third RF test signal with a different frequency point or different modulation form than the first two by mixing the local oscillator LOC with the corresponding baseband signal. The three RF signals can form a multi-carrier test signal in the same frequency band, or they can be configured as a combination signal of different frequency bands. After being combined, they are output in a unified manner for performance debugging and verification of the product under test under wide frequency band and multi-signal conditions.

[0122] This invention discloses a multi-mode adaptive interference signal generator, which solves the technical problems of RF test signal sources enabling multi-channel signal collaborative configuration, stable output power, and rapid switching under different test conditions. This invention can generate three independent RF signals, with independently adjustable amplitude, phase, frequency, and modulation method, allowing for more comprehensive performance tuning of the product under test under multi-signal and multi-frequency conditions. The front end can be configured with a local oscillator frequency of 0.5–3 GHz. Combined with the baseband signal, it can achieve wide-band, high-precision RF testing, meeting the performance testing needs of different products. Through multi-stage amplification, programmable attenuators, and closed-loop power feedback adjustment, the output power is stable and repeatable, ensuring the reliability of measurement results. Multi-stage filters, equalizers, and RF shaping processing are also included. Effectively suppresses spurious and out-of-band signals, achieving high signal-to-noise ratio test signals and improving debugging accuracy. Real-time power detection and feedback control can automatically compensate for temperature drift, device discreteness, and load changes, improving long-term operation and testing stability under various environments. The FPGA-controlled DAC / DDS module can flexibly output various signal types, including sine, amplitude modulation, frequency modulation, or arbitrary waveforms, enabling rapid adaptation for new products or multi-scenario testing. Front-end signal synthesis, power conditioning, and feedback control are integrated into a single platform, reducing the number of external test equipment and improving debugging efficiency in laboratories or production lines. It can be used for performance debugging of various products under test, such as RF communication modules, antennas, power amplifiers, and receivers, and can also perform system-level multi-signal interference simulation testing, providing reliable data support for product development.

Claims

1. A multi-mode adaptive interference signal generator, characterized in that: The system includes a control link module, a local oscillator signal generation unit, a digital interference generation module, a combiner CB1, a coupler DC1, a power amplitude control unit, and a feedback control unit. The local oscillator signal generation unit, digital interference generation module, power amplitude control unit, and feedback control unit are all connected to the control link module. The digital interference generation module is connected to the combiner CB1, which is connected to the coupler DC1. The coupler DC1 is connected to both the power amplitude control unit and the feedback control unit. The local oscillator signal generation unit is also connected to the digital interference generation module. The control link module is connected to a host computer. The control link module is used to control and configure the three interference signal sources; the local oscillator signal generation unit is used to generate the local oscillator signal. The digital interference generation module includes three signal channels, which are used to amplify and filter the three interference signal sources and mix them with the local oscillator signal, respectively; the three signal channels are controlled by three radio frequency switches; the combiner CB1 is used to combine the three signals output by the digital interference generation module and output the combined signal RFSELout. The direct path of coupler DC1 is used to output the combined signal RFSELout to the power amplitude control unit; the coupling path of coupler DC1 is used to output the coupled signal to the feedback control unit. The power amplitude control unit is used to attenuate, amplify, filter and equalize the combined signal RFSELout, and output the final interference output signal RF_OUT; the feedback control unit is used to detect the power of the coupled signal and feed the detection result back to the control link module.

2. The multi-mode adaptive interference signal generator as described in claim 1, characterized in that: The control link module includes a communication module, an FPGA chip IC10, a DAC module IC12, a DAC module IC13, and a DDS module IC14; The communication module, DAC module IC12, DAC module IC13 and DDS module IC14 are all connected to the FPGA chip IC10; The communication module connects to the host computer and establishes communication. DAC module IC12, DAC module IC13 and DDS module IC14 output interference source DAC_A, interference source DAC_B and interference source DAC_C respectively; Interference source DAC_A, interference source DAC_B, and interference source DAC_C constitute the three interference signal sources; The three signal channels of the digital interference generation module are the first signal channel, the second signal channel, and the third signal channel, respectively. The first signal channel, the second signal channel, and the third signal channel respectively receive interference source DAC_A, interference source DAC_B, and interference source DAC_C; The signal output terminals of the first signal channel, the second signal channel, and the third signal channel are each independently controlled by three radio frequency switches; The local oscillator signal generation unit includes a local oscillator signal module IC15, a buffer amplifier IC16, a buffer amplifier IC17, a buffer amplifier IC18, a filter LPF6, a filter LPF7, and a filter LPF8. The local oscillator signal module IC15 is connected to the FPGA chip IC10, and the local oscillator signal module IC15 is also connected to the input terminals of the buffer amplifier IC16, the buffer amplifier IC17, and the buffer amplifier IC18, respectively. The output of buffer amplifier IC16 is connected to filter LPF6, and filter LPF6 outputs the local oscillator LOA. The output of buffer amplifier IC17 is connected to filter LPF7, and filter LPF7 outputs the local oscillator LOB. The output of buffer amplifier IC18 is connected to filter LPF8, and filter LPF8 outputs the local oscillator LOC. Local oscillator source LOA, local oscillator source LOB, and local oscillator source LOC constitute the local oscillator signal, which is respectively input to the first signal channel, the second signal channel, and the third signal channel; The first signal channel mixes the local oscillator LOA with the interference source DAC_A; The second signal channel mixes the local oscillator LOB with the interference source DAC_B; The third signal channel mixes the local oscillator (LOC) with the interference source (DAC_C).

3. The multi-mode adaptive interference signal generator as described in claim 2, characterized in that: The first signal channel includes a filter LPF1, a vector modulator IC19, a mixer MIX1, an attenuator IC1, a filter LPF2, and an RF switch SPDT1; The input of filter LPF1 is connected to the interference source DAC_A, and the output is connected to vector modulator IC19. Vector modulator IC19 is connected to mixer MIX1. Mixer MIX1 is connected to attenuator IC1. Attenuator IC1 is connected to filter LPF2. Filter LPF2 is connected to RF switch SPDT1. RF switch SPDT1 outputs signal SPDT_A. Mixer MIX1 is also connected to the local oscillator LOA. Attenuator IC1 is also connected to FPGA chip IC10. The second signal channel includes filter BPF1, vector modulator IC20, mixer MIX2, attenuator IC2, filter LPF3, and RF switch SPDT2; The input of filter BPF1 is connected to the interference source DAC_B, and the output is connected to vector modulator IC20. Vector modulator IC20 is connected to mixer MIX2. Mixer MIX2 is connected to attenuator IC2. Attenuator IC2 is connected to filter LPF3. Filter LPF3 is connected to RF switch SPDT2. RF switch SPDT2 outputs signal SPDT_B. Mixer MIX2 is also connected to the local oscillator LOB. Attenuator IC2 is also connected to FPGA chip IC10. The third signal channel includes a filter LPF10, a vector modulator IC21, a mixer MIX3, an attenuator IC3, a filter LPF4, and an RF switch SPDT3; The input of filter LPF10 is connected to the interference source DAC_C, and the output is connected to vector modulator IC21. Vector modulator IC21 is connected to mixer MIX3. Mixer MIX3 is connected to attenuator IC3. Attenuator IC3 is connected to filter LPF4. Filter LPF4 is connected to RF switch SPDT3. RF switch SPDT3 outputs signal SPDT_C. Mixer MIX3 is also connected to the local oscillator LOC. Attenuator IC3 is also connected to FPGA chip IC10. RF switches SPDT1, SPDT2, and SPDT3 are all connected to the FPGA chip IC10. Signals SPDT_A, SPDT_B, and SPDT_C constitute the three signals output by the digital interference generation module, all of which enter the combiner CB1.

4. The multi-mode adaptive interference signal generator as described in claim 3, characterized in that: The communication module is model W5500; the FPGA chip IC10 is model XC7A100T-2FTG256C; the DAC module IC12 and the DAC module IC13 are both model AD9744; the DDS module IC14 is model AD9910. The filters LPF1, LPF2, LPF3, LPF4, LPF6, LPF7 and LPF8 are all of model LFHP-6000; The vector modulator IC19, the vector modulator IC20, and the vector modulator IC21 are all of model AD8340; The mixers MIX1, MIX2, and MIX3 are all of model HMC219B; The attenuator IC1, attenuator IC2 and attenuator IC3 are all model PE43711; The radio frequency switch SPDT1, the radio frequency switch SPDT2 and the radio frequency switch SPDT3 are all of model HMC547; The filter BPF1 is model SBP-1000+; The filter LPF10 is model LFHP-6000; The model of the local oscillator signal module IC15 is AD9910; The buffer amplifier IC16, the buffer amplifier IC17, and the buffer amplifier IC18 are all of model ADL5610.

5. A multi-mode adaptive interference signal generator as described in claim 1, characterized in that: The power amplitude control unit includes a driver amplifier IC5, an attenuator IC8, a medium power amplifier IC6, a final stage amplifier IC7, a filter BPF2, an equalizer EQ1, and a filter LPF5. The feedback control unit includes a power detection module IC30 and an ADC module IC9; The combined signal RFSELout is connected to Port1 of coupler DC1, Port2 of coupler DC1 is connected to the input of driver amplifier IC5, Port4 is connected to matching load R1, and Port3 is connected to power detection module IC30. The output of the driver amplifier IC5 is connected to the attenuator IC8, the attenuator IC8 is connected to the input of the medium power amplifier IC6, the output of the medium power amplifier IC6 is connected to the input of the final stage amplifier IC7, the output of the final stage amplifier IC7 is connected to the filter BPF2, the filter BPF2 is connected to the equalizer EQ1, the equalizer EQ1 is connected to the filter LPF5, and the filter LPF5 outputs the final interference output signal RF_OUT. The power detection module IC30 is connected to the ADC module IC9; Both the ADC module IC9 and the attenuator IC8 are connected to the FPGA chip IC10.

6. The multi-mode adaptive interference signal generator as described in claim 5, characterized in that: The driver amplifier IC5 is model ADL5610; the attenuator IC8 is model PE43711; the medium power amplifier IC6 is model QPA1043; the final stage amplifier IC7 is model CGH40010F; the filter BPF2 is model SBP-3000+; the equalizer EQ1 is model TR-EQ-6000; the filter LPF5 is model LFHP-6000; the power detection module IC30 is model ADL5513; the ADC module IC9 is model AD7980; the combiner CB1 is model ZFRSC-2050+; and the coupler DC1 is model QPD-30-6-20.

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