Timestamp synchronization method and apparatus, terminal device, and storage medium
Patent Information
- Application Number
- CN202510339389.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-21
- Publication Date
- 2026-09-22
AI Technical Summary
[0004]本发明提供一种时间戳同步方法、装置、终端设备及存储介质，以解决现有的时间戳同步方法通常手动周期性插入虚拟对齐码，以实现时间戳同步，但是虚拟对齐码的插入周期与时钟偏差会导致时间戳误差累积，导致时间戳精度较低的技术问题
[0032]本发明通过采用SFD标志采样时钟的双沿采样所述SFD标志的第一SFD信号，能够将SFD信号上升沿的采样最大误差缩减到采样时钟周期的一半，能够有效提高时间戳采样的精确度，进而能够有效提高时间戳同步的精确度。
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Figure CN122802092A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of time synchronization technology, and in particular to a timestamp synchronization method, apparatus, terminal device, and storage medium. Background Technology
[0002] With the development of network technology, passive positioning, power transmission, and other fields, the requirements for time synchronization performance between devices are becoming increasingly stringent. The high precision of the 1588v2 1-STEP timestamp is the most basic requirement for ensuring the performance of the 1588v2 protocol system. Most Ethernet PCS layers have cross-clock domain FIFOs, and the FIFO delay becomes uncertain after multiple resets / power-on / off cycles. In 1-STEP mode, because the MAC layer needs to estimate the time when PTP packets are sent to the PMA exit in advance, the aforementioned FIFO delay uncertainty reduces the accuracy of the 1-STEP timestamp, affecting the application scenarios and system performance of 1588v2.
[0003] Existing timestamp synchronization methods typically involve manually inserting virtual alignment codes periodically to achieve timestamp synchronization. However, the insertion period of the virtual alignment codes and the clock deviation can lead to the accumulation of timestamp errors, resulting in low timestamp accuracy. Summary of the Invention
[0004] This invention provides a timestamp synchronization method, apparatus, terminal device, and storage medium to solve the technical problem that existing timestamp synchronization methods typically involve manually and periodically inserting virtual alignment codes to achieve timestamp synchronization, but the insertion period of the virtual alignment codes and clock deviations can lead to the accumulation of timestamp errors, resulting in low timestamp accuracy.
[0005] This invention provides a timestamp synchronization method, comprising:
[0006] The system receives MAC frames sent by the user through the MAC layer, extracts the first SFD flag from the MAC frame, samples the first TOD time based on the first SFD flag, and outputs the first timestamp based on the first TOD time.
[0007] The PCS layer receives MAC frames sent by the user, extracts the second SFD flag from the MAC frame, samples the second TOD time based on the second SFD flag, and outputs a second timestamp based on the second TOD time; wherein, the first timestamp and the second timestamp are a first set of timestamps;
[0008] Upon receiving the first set of timestamps, the first timestamp difference between the second timestamp and the first timestamp is determined, and upon receiving the next set of timestamps, the timestamp of the current message frame is determined based on the first timestamp difference;
[0009] Insert the timestamp of the current message frame into the current message frame to complete the timestamp synchronization of the current message frame.
[0010] Furthermore, before receiving the MAC frame sent by the user through the MAC layer, extracting the first SFD flag from the MAC frame, sampling the first TOD time based on the first SFD flag, and outputting the first timestamp according to the first TOD time, the method further includes:
[0011] The MAC layer and the PCS layer are reset and released to ensure that the channel delay of the MAC layer and the PCS layer is fixed, and to ensure that there are no near-end errors or far-end errors in the continuous bytes received by the MAC layer.
[0012] Furthermore, the step of sampling the first TOD time based on the first SFD flag includes:
[0013] The first SFD signal with the first SFD flag is sampled using either a single or double edge of the SFD flag sampling clock.
[0014] The first TOD time is obtained based on the sampling of the first SD signal.
[0015] Furthermore, extracting the second SFD flag from the MAC frame includes:
[0016] The corresponding PCS data frame is obtained by physically encoding the MAC frame.
[0017] Extract the second SFD flag from the PCS data frame.
[0018] Furthermore, the sampling of the second TOD time based on the second SFD flag includes:
[0019] After the second SFD flag is bit-width converted, the second SFD signal of the second SFD flag is obtained by sampling the single or double edge of the SFD flag sampling clock.
[0020] Furthermore, upon receiving the first set of timestamps, the following is also included:
[0021] First, update the first timestamp in the first set of timestamps. After the first timestamp has been updated and the channel delay of the MAC layer and the PCS layer is fixed, update the second timestamp in the first set of timestamps.
[0022] Furthermore, the timestamp of the current message frame is inserted into the current message frame to complete the timestamp synchronization of the current message frame, including:
[0023] Generate corresponding control instructions based on the timestamp of the current message frame;
[0024] According to the control command, the timestamp of the current message frame is inserted into the current message frame, and the checksum and cyclic redundancy check of the current message frame are updated.
[0025] The present invention also provides a timestamp synchronization device, comprising:
[0026] The first timestamp output module is used to receive MAC frames sent by the user through the MAC layer, extract the first SFD flag in the MAC frame, sample the first TOD time based on the first SFD flag, and output the first timestamp according to the first TOD time.
[0027] The second timestamp output module receives MAC frames sent by the user through the PCS layer, extracts the second SFD flag from the MAC frame, samples the second TOD time based on the second SFD flag, and outputs the second timestamp based on the second TOD time; wherein, the first timestamp and the second timestamp are the first set of timestamps;
[0028] The module for determining the timestamp to be inserted is used to determine the first timestamp difference between the second timestamp and the first timestamp when the first set of timestamps is received, and to determine the timestamp of the current message frame based on the first timestamp difference when the next set of timestamps is received;
[0029] The timestamp synchronization module is used to insert the timestamp of the current message frame into the current message frame to complete the timestamp synchronization of the current message frame.
[0030] The present invention also provides a terminal device, including: a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor, wherein the processor executes the computer program to implement the timestamp synchronization method as described above.
[0031] The present invention also provides a computer-readable storage medium comprising a stored computer program; wherein, when the computer program is executed, it controls the device where the computer-readable storage medium is located to perform the timestamp synchronization method described above.
[0032] This invention employs dual-edge sampling of the first SFD signal of the SFD flag using the SFD flag sampling clock, which reduces the maximum sampling error of the rising edge of the SFD signal to half of the sampling clock period, effectively improving the accuracy of timestamp sampling and thus improving the accuracy of timestamp synchronization.
[0033] Furthermore, after the first timestamp is updated and the channel delay is fixed, the present invention updates the second timestamp in the first set of timestamps. This avoids the clock tree phase drift causing fluctuations in the difference between the two timestamps when the channel delay is not fixed, thereby effectively reducing the clock phase difference and accumulated error, and thus effectively improving the accuracy of timestamp synchronization. Attached Figure Description
[0034] Figure 1 This is a flowchart illustrating the timestamp synchronization method provided in an embodiment of the present invention;
[0035] Figure 2 This is a schematic diagram of the timestamp synchronization system provided in an embodiment of the present invention;
[0036] Figure 3 This is a schematic diagram of the timestamp synchronization device provided in an embodiment of the present invention. Detailed Implementation
[0037] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0038] In the description of this application, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "multiple" means two or more.
[0039] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.
[0040] Please see Figure 1 This invention provides a timestamp synchronization method, comprising:
[0041] S1. Receive the MAC frame sent by the user through the MAC layer, extract the first SFD flag in the MAC frame, sample the first TOD time based on the first SFD flag, and output the first timestamp according to the first TOD time.
[0042] In one embodiment, the present invention can be executed in a timestamp synchronization system, wherein the timestamp synchronization system includes a MAC layer and a PCS layer (physical coding layer).
[0043] In this embodiment of the invention, the MAC layer and PCS layer need to be initialized before timestamp synchronization. The initialization process includes resetting and releasing the MAC and PCS layers, ensuring clock stability, and fixing the channel delay between the MAC and PCS layers. Initialization is considered complete when the PCS layer completes linkup (the physical coding sublayer completes hardware initialization, protocol negotiation, and signal synchronization with the peer device, entering a state where stable data transmission is possible), the MAC layer receives 512 consecutive bytes without near-end or far-end errors, and the MAC layer can receive, process, and send user Ethernet frame data.
[0044] In this embodiment of the invention, after initialization, the MAC layer parses the MAC message input by the user to obtain a MAC frame. The MAC layer monitors the bit stream transmitted by the physical layer in real time through hardware circuits (such as shift registers). When a specific pattern of SFD (Start of Frame Delimiter) (such as binary 10101011) is detected, the frame parsing process is triggered to mark the start of a valid frame, thereby extracting the SFD flag in the MAC frame.
[0045] In this embodiment of the invention, the first TOD (Time-of-Day, typically 96 bits of time information as defined by 1588v2) time is obtained by sampling the first SFD flag, and the current timestamp is output as the first timestamp when the first TOD time is collected.
[0046] S2. Receive the MAC frame sent by the user through the PCS layer, extract the second SFD flag from the MAC frame, sample the second TOD time based on the second SFD flag, and output the second timestamp based on the second TOD time; wherein, the first timestamp and the second timestamp are the first set of timestamps;
[0047] In this embodiment of the invention, the PCS layer physically encodes the MAC frame to obtain a PCS data frame, then parses the PCS data frame to obtain the second SFD flag, samples the second TOD time using the second SFD flag, and outputs the current timestamp as the second timestamp when the second TOD time is obtained.
[0048] S3. When the first set of timestamps is received, determine the difference between the second timestamp and the first timestamp, and when the next set of timestamps is received, determine the timestamp of the current message frame based on the difference between the first timestamps.
[0049] In this embodiment of the invention, a first timestamp and a second timestamp generated based on the same frame message sent by the user are used as a set of timestamps. Upon receiving the first set of timestamps, the difference between the second timestamp and the first timestamp is determined to be:
[0050] Δt=T1b-T1a
[0051] Where Δt is the timestamp difference, T1b is the second timestamp, T1a is the first timestamp, and the initial power-on value of Δt is 0.
[0052] In this embodiment of the invention, when the timestamp difference is calculated, the difference is kept unchanged until the next set of timestamps is reached. Then, a new timestamp difference is recalculated. When the MAC layer receives the next set of timestamps, the timestamp of the current message frame is determined based on the first timestamp difference: TS = T1a + Δt, where the timestamp of the current message frame is 1-STEP timestamp.
[0053] S4. Insert the timestamp of the current message frame into the current message frame to complete the timestamp synchronization of the current message frame.
[0054] In this embodiment of the invention, when the MAC layer receives the next set of timestamps, it can generate a 1588 control command to control the corresponding modification of the PTP (Precision Time Protocol) frame, i.e., the message frame, so that the timestamp of the current message frame is inserted into the current message frame, thereby completing the timestamp synchronization of the current message frame.
[0055] By employing a dual-edge sampling clock to sample the first SFD signal of the SFD flag, this embodiment of the invention can reduce the maximum sampling error of the rising edge of the SFD signal to half of the sampling clock period, thereby effectively improving the accuracy of timestamp sampling and thus effectively improving the accuracy of timestamp synchronization.
[0056] Furthermore, in this embodiment of the invention, after the first timestamp is updated and the channel delay is fixed, the second timestamp in the first set of timestamps is updated. This can avoid the second timestamp being updated when the channel delay is not fixed, and the clock tree phase drift causing fluctuations in the difference between the two timestamps. This can effectively reduce the clock phase difference and accumulated error, thereby effectively improving the accuracy of timestamp synchronization.
[0057] In one embodiment, before step S1, which involves receiving a MAC frame sent by the user through the MAC layer, extracting the first SFD flag from the MAC frame, sampling the first TOD time based on the first SFD flag, and outputting the first timestamp based on the first TOD time, the method further includes:
[0058] The MAC layer and PCS layer are reset and released to ensure that the channel delay of the MAC layer and PCS layer is fixed, and to ensure that there are no near-end errors or far-end errors in the continuous bytes received by the MAC layer.
[0059] In this embodiment of the invention, near-end errors or far-end errors may include error codewords defined in the Ethernet protocol. For example, Local Fault: a failure of the local PHY; Remote Fault: a failure of the PHY connecting to the target network at the remote end. The RS sublayer in the MAC layer will determine this type of error to confirm whether the MAC can process normal data packets.
[0060] In this embodiment of the invention, the reset and release operation ensures that the MAC layer and PCS layer enter a stable working mode from the initial state, avoiding the influence of residual state on timing, thereby enabling the clock signal (such as tod_clk) to achieve phase locking, reducing the timestamp sampling error caused by clock jitter or non-synchronization; and ensuring the integrity of the data received by the MAC layer.
[0061] In one embodiment, step S1, sampling the first TOD time based on the first SFD flag, includes:
[0062] S11. The first SFD signal of the first SFD flag is sampled using a single or double edge of the SFD flag sampling clock.
[0063] In this embodiment of the invention, the first SFD signal SFD_1a of the first SFD flag can be sampled using the DDR sampling method (clock double-edge sampling method). The SFD flag sampling clock is tod_clk*N, and the TOD time sampling clock is tod_clk. Specifically, sampling is performed using the rising and falling edges of the sampling clock. The SFD signal is sampled twice in one clock cycle. The relationship between the rising edge of the sampled signal SFD and the rising edge of the sampling clock is uncertain. Therefore, the maximum error between the new rising edge of the SFD signal after clock sampling and the rising edge of the original SFD signal is half of the SFD flag sampling clock cycle, i.e., T1_error = 1 / (2*T(tod_clk*N). clk *N)), where T1_error is the maximum error.
[0064] S12. Obtain the first TOD time based on the sampling of the first SD signal.
[0065] In this embodiment of the invention, when the TOD time sampling clock is tod_clk, the first TOD time is obtained by sampling based on the rising edge of SFD_1a. Since the SFD flag sampling clock and the TOD time sampling clock are from the same source, the maximum error of the first timestamp is T1_error.
[0066] The embodiments of the present invention employ dual-edge sampling of the first SFD signal of the first SFD flag using the SFD flag sampling clock, which can reduce the maximum sampling error of the rising edge of the SFD signal to half of the sampling clock period, effectively improving the accuracy of timestamp sampling, and thus effectively improving the accuracy of timestamp synchronization.
[0067] In one embodiment, step S2, extracting the second SFD flag from the MAC frame, includes:
[0068] S21. After physically encoding the MAC frame, the corresponding PCS data frame is obtained.
[0069] In this embodiment of the invention, the original MAC frame output by the MAC layer is passed to the PCS layer, and the PCS layer can perform 64B / 66B encoding processing on the original MAC frame to obtain the corresponding PCS data frame.
[0070] S22. Extract the second SFD flag from the PCS data frame.
[0071] In this embodiment of the invention, the corresponding PCS data frame is obtained by physically encoding the MAC frame, which can effectively reduce the impact of transmission errors on the SFD flag. Furthermore, by accurately extracting the synchronization header or explicit SFD field, the timestamp error can be effectively limited to the physical layer clock cycle level, thereby effectively improving the accuracy of timestamp synchronization.
[0072] In one embodiment, step S2, sampling the second TOD time based on the second SFD flag, includes:
[0073] After the second SFD flag is bit-width converted, the second SFD signal of the second SFD flag is obtained by sampling the single or double edge of the SFD flag sampling clock.
[0074] In this embodiment of the invention, since 10G and above Ethernet protocols all use 64B / 66B encoding and decoding, the data bit width inside the PCS layer is usually an integer multiple of 66 bits, requiring an asynchronous data bit width conversion submodule to convert the data bit width to an integer multiple of 8 bits.
[0075] In this embodiment of the invention, the method of sampling the second SFD signal is the same as the method of sampling the first SFD signal, both of which are obtained by sampling using a single-edge or double-edge sampling method.
[0076] The embodiments of the present invention employ dual-edge sampling of the second SFD signal of the second SFD flag using the SFD flag sampling clock, which can reduce the maximum sampling error of the rising edge of the SFD signal to half of the sampling clock period, effectively improving the accuracy of timestamp sampling, and thus effectively improving the accuracy of timestamp synchronization.
[0077] In one embodiment, step S3, upon receiving the first set of timestamps, further includes:
[0078] First, update the first timestamp in the first set of timestamps. After the first timestamp is updated and the channel delays of the MAC layer and PCS layer are fixed, update the second timestamp in the first set of timestamps.
[0079] In this embodiment of the invention, when the MAC layer receives two timestamps from the first set of timestamps, the first time in the first set of timestamps is updated first. After the data stream flows from the MAC layer to the PCS layer, and the channel delay between the MAC layer and the PCS layer is fixed, the second timestamp in the first set of timestamps is updated.
[0080] In this embodiment of the invention, after the first timestamp is updated and the channel delay is fixed, the second timestamp in the first set of timestamps is updated. This can avoid updating the second timestamp when the channel delay is not fixed, and the clock tree phase drift will cause fluctuations in the difference between the two timestamps. This can effectively reduce the clock phase difference and accumulated error.
[0081] In one embodiment, step S4, inserting the timestamp of the current message frame into the current message frame to complete the timestamp synchronization of the current message frame, includes:
[0082] S41. Generate the corresponding control command based on the timestamp of the current message frame;
[0083] In this embodiment of the invention, instruction generation can be implemented using a state machine in an FGGA or ASIC. For example, different correction algorithms can be selected based on the PTP message type (Sync / Delay_Req), and mapped to specific opcodes using a lookup table (LUT). In this embodiment of the invention, the control instructions include timestamp information and corresponding timestamp control information.
[0084] S42. Insert the timestamp of the current message frame into the current message frame according to the control command, and update the checksum and cyclic redundancy check of the current message frame.
[0085] In this embodiment of the invention, according to the protocol standard (such as IEEE 1588V2), the timestamp is inserted into a specific position in the message to complete the timestamp synchronization. For example, in the Sync message, the timestamp is usually located in the originTimestamp field, which occupies 8 bytes.
[0086] In this embodiment of the invention, when a timestamp is inserted into a message frame, the original data content changes and the original checksum is no longer accurate. This embodiment of the invention can avoid the situation where the message frame is not judged to be damaged due to mismatch when the checksum is received, thus causing the data to be discarded, by correspondingly updating the checksum and cyclic redundancy check. This ensures the reliability of timestamp synchronization.
[0087] Please see Figure 2 An embodiment of the present invention also provides a timestamp synchronization system, wherein the timestamp synchronization method of the above embodiment can be executed in the timestamp synchronization system. The timestamp synchronization system includes a MAC layer, a PCS layer, a first TOD sampling module and a second TOD sampling module. The MAC layer includes an MSC transmission processing module, a MAC message parsing module, a PTP message modification module and a 1-STEP timestamp generation module. The PCS layer includes a PCS transmission module and an asynchronous data bit width conversion module.
[0088] In this embodiment of the invention, the MAC layer receives MAC packets, and the MAC transmission processing module receives and processes the MAC packets, including statistical information generation, inter-frame interval adjustment, and padding addition. The MAC packet parsing module receives the MAC frame sent by the MAC transmission processing module, obtains the corresponding SFD field position, outputs the SFD flag signal to the first TOD sampling module, and simultaneously transmits the data packet to the lower-level PTP packet modification module. The packet modification module, according to the 1588 control command, controls whether to perform 1-STEP stamping on the packet. According to the origin Timestamp position indication in the 1588 control command, the timestamp output by the 1-STEP timestamp generation module is inserted into the PTP packet. For the stamped PTP packet, according to the checksum position indication in the 1588 control command, the checksum is updated or zeroed. Finally, the CRC calculation and insertion are completed, and the XGMII packet is output to the lower-level PCS layer for processing.
[0089] The PCS layer receives MAC frames transmitted from the MAC layer and completes the corresponding PCS processing and FEC encoding (optional) operations as specified by the Ethernet protocol, including obtaining the SFD field position of the PCS packet and outputting the PCS data packet and SFD flag signal to the asynchronous data bit width conversion module.
[0090] The asynchronous data bit width conversion module completes the conversion of PCS data bit width to PMA parallel data bit width, and at the same time completes the cross-clock domain processing of data from the PCS clock domain to the PMA parallel clock domain.
[0091] The first TOD sampling module uses a high-frequency clock tod_clk*N (N is a positive integer not equal to 0) to sample the SFD flag signal output by the MAC layer, obtaining SFD_1a. The rising edge of SFD_1a is detected in the tod_clk clock domain, and the input TOD time is sampled at the rising edge of SFD_1a, outputting the timestamp T1a.
[0092] The second TOD sampling module uses a high-frequency clock tod_clk*N to sample the SFD flag signal output by the PCS, obtaining SFD_1b. The rising edge of SFD_1b is detected in the tod_clk clock domain, and the input TOD time is sampled at the rising edge of SFD_1b. This time is then compensated for the fixed delay in the PMA, and a timestamp T1b is output. T1b is equivalent to the timestamp of the PTP message arriving at the PMA serial output.
[0093] After the 1-STEP timestamp generation module completes MAC and PCS reset and the operating clock stabilizes, the transmission channel delay is fixed. During initialization, Δt = T1b - T1a is calculated. During operation, based on the values of Δt and T1a, the accurate 1-STEP timestamp TS is calculated and transmitted to the PTP message modification module.
[0094] Implementing the embodiments of the present invention has the following beneficial effects:
[0095] By employing a dual-edge sampling clock to sample the first SFD signal of the SFD flag, this embodiment of the invention can reduce the maximum sampling error of the rising edge of the SFD signal to half of the sampling clock period, thereby effectively improving the accuracy of timestamp sampling and thus effectively improving the accuracy of timestamp synchronization.
[0096] Furthermore, in this embodiment of the invention, after the first timestamp is updated and the channel delay is fixed, the second timestamp in the first set of timestamps is updated. This can avoid the second timestamp being updated when the channel delay is not fixed, and the clock tree phase drift causing fluctuations in the difference between the two timestamps. This can effectively reduce the clock phase difference and accumulated error, thereby effectively improving the accuracy of timestamp synchronization.
[0097] Please see Figure 3 Based on the same inventive concept as the above embodiments, the present invention also provides a timestamp synchronization device, comprising:
[0098] The first timestamp output module 10 is used to receive MAC frames sent by the user through the MAC layer, extract the first SFD flag in the MAC frame, sample the first TOD time based on the first SFD flag, and output the first timestamp according to the first TOD time.
[0099] The second timestamp output module 20 receives MAC frames sent by the user through the PCS layer, extracts the second SFD flag from the MAC frame, samples the second TOD time based on the second SFD flag, and outputs the second timestamp based on the second TOD time; wherein, the first timestamp and the second timestamp are the first set of timestamps;
[0100] The timestamp to be inserted determination module 30 is used to determine the first timestamp difference between the second timestamp and the first timestamp when the first set of timestamps is received, and to determine the timestamp of the current message frame based on the first timestamp difference when the next set of timestamps is received;
[0101] The timestamp synchronization module 40 is used to insert the timestamp of the current message frame into the current message frame to complete the timestamp synchronization of the current message frame.
[0102] In one embodiment, the timestamp synchronization device further includes an initialization module, used for:
[0103] The MAC layer and PCS layer are reset and released to ensure that the channel delay of the MAC layer and PCS layer is fixed, and to ensure that there are no near-end errors or far-end errors in the continuous bytes received by the MAC layer.
[0104] In one embodiment, the first timestamp output module 10 is further configured to:
[0105] The first SFD signal of the first SFD flag is sampled using a single or double edge of the SFD flag sampling clock.
[0106] The first TOD time is obtained based on the sampling of the first SD signal.
[0107] In one embodiment, the second timestamp output module 20 is further configured to:
[0108] After physical encoding of the MAC frame, the corresponding PCS data frame is obtained;
[0109] Extract the second SFD flag from the PCS data frame.
[0110] In one embodiment, the second timestamp output module 20 is further configured to:
[0111] After the second SFD flag is bit-width converted, the second SFD signal of the second SFD flag is obtained by sampling the single or double edge of the SFD flag sampling clock.
[0112] In one embodiment, the timestamp to be inserted determination module 30 is further configured to:
[0113] First, update the first timestamp in the first set of timestamps. After the first timestamp is updated and the channel delays of the MAC layer and PCS layer are fixed, update the second timestamp in the first set of timestamps.
[0114] In one embodiment, the timestamp synchronization module 40 is further configured to:
[0115] Generate the corresponding control command based on the timestamp of the current message frame;
[0116] According to the control command, insert the timestamp of the current message frame into the current message frame, and update the checksum and cyclic redundancy check of the current message frame.
[0117] Accordingly, one embodiment of the present invention also provides a terminal device, including: a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor, wherein the processor executes the computer program to implement the timestamp synchronization method of any of the above embodiments.
[0118] The terminal device in this embodiment includes a processor, a memory, and a computer program and computer instructions stored in the memory and executable on the processor. When the processor executes the computer program, it implements the various steps described in Embodiment 1 above, for example... Figure 1 Steps S1 to S4 are shown. Alternatively, when the processor executes a computer program, it implements the functions of each module / unit in the above-described device embodiment, such as the timestamp determination module 30.
[0119] For example, a computer program can be divided into one or more modules / units, one or more of which are stored in memory and executed by a processor to complete the present invention. One or more modules / units can be a series of computer program instruction segments capable of performing a specific function, which describe the execution process of the computer program in a terminal device. For example, the timestamp to be inserted determination module 30 is used to determine the first timestamp difference between the second timestamp and the first timestamp when a first set of timestamps is received, and to determine the timestamp of the current message frame based on the first timestamp difference when the next set of timestamps is received.
[0120] Terminal devices can be computing devices such as desktop computers, laptops, handheld computers, and cloud servers. Terminal devices may include, but are not limited to, processors and memory. Those skilled in the art will understand that the schematic diagrams are merely examples of terminal devices and do not constitute a limitation on the terminal devices. They may include more or fewer components than illustrated, or combine certain components, or different components. For example, terminal devices may also include input / output devices, network access devices, buses, etc.
[0121] The processor can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor can be a microprocessor or any conventional processor. The processor is the control center of the terminal device, connecting all parts of the terminal device through various interfaces and lines.
[0122] Memory can be used to store computer programs and / or modules. The processor implements various functions of the terminal device by running or executing the computer programs and / or modules stored in the memory, and by accessing data stored in the memory. Memory may mainly include a program storage area and a data storage area. The program storage area may store the operating system, applications required for at least one function, etc.; the data storage area may store data created based on the use of the mobile terminal, etc. In addition, memory may include high-speed random access memory, and may also include non-volatile memory, such as hard disks, RAM, plug-in hard disks, smart media cards (SMC), secure digital cards (SD cards), flash cards, at least one disk storage device, flash memory device, or other volatile solid-state storage devices.
[0123] If the modules / units integrated into the terminal device are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments of the present invention can also be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable medium can include: any entity or device capable of carrying computer program code, recording media, USB flash drives, portable hard drives, magnetic disks, optical disks, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signals, telecommunication signals, and software distribution media, etc. It should be noted that the content included in the computer-readable medium can be appropriately added or removed according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, the computer-readable medium does not include electrical carrier signals and telecommunication signals.
[0124] Accordingly, one embodiment of the present invention also provides a computer-readable storage medium, which includes a stored computer program, wherein, when the computer program is running, it controls the device where the computer-readable storage medium is located to execute the timestamp synchronization method of any of the above embodiments.
[0125] The above specific embodiments further illustrate the purpose, technical solution, and beneficial effects of the present invention in detail. It should be understood that the above are merely specific embodiments of the present invention and are not intended to limit the scope of protection of the present invention. In particular, it should be noted that any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention for those skilled in the art.
Claims
1. A timestamp synchronization method, characterized in that, include: The system receives MAC frames sent by the user through the MAC layer, extracts the first SFD flag from the MAC frame, samples the first TOD time based on the first SFD flag, and outputs the first timestamp based on the first TOD time. The PCS layer receives MAC frames sent by the user, extracts the second SFD flag from the MAC frame, samples the second TOD time based on the second SFD flag, and outputs a second timestamp based on the second TOD time; wherein, the first timestamp and the second timestamp are a first set of timestamps; Upon receiving the first set of timestamps, the first timestamp difference between the second timestamp and the first timestamp is determined, and upon receiving the next set of timestamps, the timestamp of the current message frame is determined based on the first timestamp difference; Insert the timestamp of the current message frame into the current message frame to complete the timestamp synchronization of the current message frame.
2. The timestamp synchronization method as described in claim 1, characterized in that, Before receiving a MAC frame sent by the user through the MAC layer, extracting the first SFD flag from the MAC frame, sampling the first TOD time based on the first SFD flag, and outputting the first timestamp based on the first TOD time, the method further includes: The MAC layer and the PCS layer are reset and released to ensure that the channel delay of the MAC layer and the PCS layer is fixed, and to ensure that there are no near-end errors or far-end errors in the consecutive bytes received by the MAC layer.
3. The timestamp synchronization method as described in claim 1, characterized in that, The sampling of the first TOD time based on the first SFD flag includes: The first SFD signal with the first SFD flag is sampled using either a single or double edge of the SFD flag sampling clock. The first TOD time is obtained based on the sampling of the first SD signal.
4. The timestamp synchronization method as described in claim 1, characterized in that, Extracting the second SFD flag from the MAC frame includes: The corresponding PCS data frame is obtained by physically encoding the MAC frame. Extract the second SFD flag from the PCS data frame.
5. The timestamp synchronization method as described in claim 1, characterized in that, The sampling of the second TOD time based on the second SFD flag includes: After the second SFD flag is bit-width converted, the second SFD signal of the second SFD flag is obtained by sampling the single or double edge of the SFD flag sampling clock.
6. The timestamp synchronization method as described in claim 1, characterized in that, Upon receiving the first set of timestamps, the following is also included: First, update the first timestamp in the first set of timestamps. After the first timestamp has been updated and the channel delay of the MAC layer and the PCS layer is fixed, update the second timestamp in the first set of timestamps.
7. The timestamp synchronization method as described in claim 1, characterized in that, Inserting the timestamp of the current message frame into the current message frame to complete the timestamp synchronization of the current message frame includes: Generate corresponding control instructions based on the timestamp of the current message frame; According to the control command, the timestamp of the current message frame is inserted into the current message frame, and the checksum and cyclic redundancy check of the current message frame are updated.
8. A timestamp synchronization device, characterized in that, include: The first timestamp output module is used to receive MAC frames sent by the user through the MAC layer, extract the first SFD flag in the MAC frame, sample the first TOD time based on the first SFD flag, and output the first timestamp according to the first TOD time. The second timestamp output module receives MAC frames sent by the user through the PCS layer, extracts the second SFD flag from the MAC frame, samples the second TOD time based on the second SFD flag, and outputs the second timestamp based on the second TOD time; wherein, the first timestamp and the second timestamp are the first set of timestamps; The module for determining the timestamp to be inserted is used to determine the first timestamp difference between the second timestamp and the first timestamp when the first set of timestamps is received, and to determine the timestamp of the current message frame based on the first timestamp difference when the next set of timestamps is received; The timestamp synchronization module is used to insert the timestamp of the current message frame into the current message frame to complete the timestamp synchronization of the current message frame.
9. A terminal device, characterized in that, include: A processor, a memory, and a computer program stored in the memory and configured to be executed by the processor, wherein the processor, when executing the computer program, implements the timestamp synchronization method as described in any one of claims 1-7.
10. A computer-readable storage medium, characterized in that, The computer-readable storage medium includes a stored computer program; wherein, when the computer program is executed, it controls the device where the computer-readable storage medium is located to perform the timestamp synchronization method as described in any one of claims 1-7.