A method and system for transmitting a synchronization time based on a shared clock

Abstract

The application discloses a method and system for transmitting a synchronous time based on a shared clock, and belongs to the technical field of shared synchronization signals. The method comprises the following steps: a plurality of interconnected FPGAs each maintain a high-frequency counter as a shared clock, and exchange counter value information in a master-slave timing mode; a slave device uses the master device counter value and compensates for communication delay to obtain a counter value of a local timer; and the counter values of the FPGAs are basically consistent. After a local three-phase synchronization signal is received, the FPGA uses the shared clock time as an interrupt time, and the interrupt time is transmitted to other FPGAs in a timing communication. The application breaks away from the mode of transmitting a synchronization signal triggered by the edge change of a synchronization signal in the prior art.

Description

Technical Field

[0001] This application belongs to the field of shared synchronization signal technology, and in particular relates to a method and system for transmitting synchronization time based on a shared clock. Background Technology

[0002] In multi-controller collaborative control systems, GPS time synchronization signals are introduced to ensure the comparability of event records. However, the accuracy is limited to milliseconds at most, which is insufficient for real-time control requirements. Taking the excitation system as an example, a synchronization signal deviation of no more than 10 microseconds is necessary to guarantee control accuracy.

[0003] The intelligent power cabinet in the excitation system is equipped with a controller that can automatically generate trigger pulses according to the trigger angle sent by the excitation regulating cabinet. The anode voltage of the power cabinet is shaped into a synchronous square wave, and the rising edge of the synchronous square wave serves as the start of the current cycle. The implementation scheme for the intelligent power cabinet to output trigger pulses is as follows: Figure 1 As shown, the rising edge of the A-phase synchronization signal is generally used as the starting point of the current cycle. The control angle interrupt delay of Timer 1 is set. In the control angle interrupt, in addition to outputting the first pair of trigger pulses, a 60° interrupt delay of Timer 2 is also set. Subsequent pulses are output sequentially in the 60° interrupt of Timer 2. If the A-phase synchronization signal fails and switching to another phase is required, the pulses output in each interrupt need to be adjusted according to the synchronization phase to adapt to the phase change. For example, when using B-phase synchronization, a third pair of pulses needs to be output in the control angle interrupt.

[0004] The time difference between the rising edges of two in-phase synchronization signals is the current period, corresponding to 360°. Therefore, the formula for converting the control angle into a delay is as follows:

[0005] Where t is the delay corresponding to the control angle, T is the current period, and α is the control angle.

[0006] Existing technologies have proposed the concept of shared synchronization signals. The invention patent "High Redundancy Synchronization Technology for Intelligent Rectifier Bridges Based on FPGA and Communication Network" (201910223958.X) proposes transmitting synchronization signals to other power cabinets via fiber optic communication. This allows the FPGA of each power cabinet controller to obtain the three-phase synchronization signals from all power cabinets. The MCU of the power cabinet controller then selects one of these synchronization signals according to preset rules as the shared synchronization driver to trigger pulses for each power cabinet. This solution eliminates phase deviations caused by differences in the hardware parameters of different shaping circuits and significantly enhances the redundancy of the synchronization signals, ensuring normal output even if the three-phase synchronization signal locally connected to a power cabinet completely disappears due to a fault.

[0007] The invention patent "Method, System and Medium for Simultaneous Transmission of Data Information and Sharing Synchronization Signal" (202210663166.6) proposes a method for FPGA to transmit synchronization signal and communication data simultaneously on the same optical fiber: the rising edge of the synchronization signal is forwarded in the form of a narrow pulse, and the communication data is transmitted after a 2-millisecond delay after the arrival of the synchronization signal to avoid conflict between the two.

[0008] Current technology transmits synchronization signals and communication data simultaneously in communication lines, which may interfere with each other. In practice, the real-time requirements for transmitting synchronization signals are not high; there is a control angle delay between the rising edge of the synchronization signal and the first pair of trigger pulses. Based on field engineering experience, the minimum control angle is no less than 10°, and even when the anode voltage frequency reaches 100Hz, this delay is still 277 microseconds. By transmitting the synchronization moment to the MCU within 100 microseconds after the synchronization signal appears, the MCU has sufficient time to set the delay and ensure pulse accuracy.

[0009] If the synchronization signal comes from the power cabinet itself, it's perfectly fine for the FPGA to use its own timer count as the synchronization moment. However, if the synchronization signal comes from FPGAs in other power cabinets, their timer counts are meaningless. Only when each power cabinet FPGA has a high-precision reference clock, similar to GPS timing, does the synchronization interrupt moment defined by this reference clock become meaningful.

[0010] Therefore, it is necessary to provide a new method and system for transmitting synchronization moments based on a shared clock to solve the above-mentioned technical problems. Summary of the Invention

[0011] The purpose of this disclosure is to provide a method and system for transmitting synchronization moments based on a shared clock in order to solve the above-mentioned problems.

[0012] This disclosure achieves the above objectives through the following technical solutions: A method for transmitting synchronization moments based on a shared clock includes the following steps: The interconnected FPGAs are organized into a master-slave configuration for timed communication. Each FPGA is assigned a unique serial number and is initially a slave device upon power-up. Based on the preset priority of each FPGA and the real-time communication network status, a unique master device in the network is dynamically determined and maintained through distributed negotiation. Each FPGA maintains a counter that cycles at the same frequency as a shared clock, continuously increasing at the same counting frequency. The communication frame carries the counter count value at the time of transmission, the master / slave status, and the communication status. After receiving the count value from the master device, the slave device adds a communication delay compensation value and calibrates its own counter to ensure that the shared clock count value of all FPGAs in the network remains consistent. Each FPGA performs high-frequency timing communication. Based on the shared clock, each FPGA converts the arrival event of the local synchronization signal into synchronization time information with a unified time base and transmits it through the high-frequency timing communication. When the FPGA receives the specified synchronization time information, it generates an interrupt signal to trigger the microcontroller MCU to process it.

[0013] As a further optimization of this disclosure, the communication information between multiple FPGAs includes whether this FPGA is the master device and whether it can receive information from other FPGAs normally.

[0014] As a further optimization of this disclosure, based on the preset priority of each FPGA and the real-time communication network status, a unique master device in the network is dynamically determined and maintained through distributed negotiation, including: If an FPGA acting as a slave device discovers that there is no master device currently present by obtaining data from other FPGAs, it sets a master device delay according to its own sequence number, with a shorter delay for lower sequence numbers; if there is still no master device when the master device delay ends, this FPGA becomes the master device; other FPGAs cancel their delays and maintain slave device status after detecting the presence of a master device. If the FPGA acting as the master device discovers that another FPGA is also a master device, it sets a delay to exit the master device state according to its own serial number. The lower the serial number, the longer the delay. If there is still another FPGA as the master device when the delay ends, this FPGA becomes a slave device. If a communication failure occurs between a slave device and the master device, the slave device with the best communication status and the smallest sequence number will be reselected as the master device.

[0015] As a further optimization of this disclosure, the counter is a 32-bit counter that increments cyclically at a frequency of 100MHz.

[0016] As a further optimization of this disclosure, the frequency of the high-frequency timing communication is not less than 10kHz.

[0017] As a further optimization of this disclosure, each FPGA, based on the shared clock, converts the arrival event of the local synchronization signal into synchronization time information with a unified time base, and transmits it through the high-frequency timing communication; when the FPGA receives the specified synchronization time information, it generates an interrupt signal to trigger the microcontroller MCU to process it, including: When the local synchronization signal of any FPGA arrives, the FPGA records the current count value of its own shared clock corresponding to the arrival time of the synchronization signal as the synchronization time, and sends the synchronization time and its corresponding phase sequence information to other FPGAs in the high-frequency timing communication. If multiple synchronization signals arrive within a communication cycle, the FPGA records the synchronization time of each synchronization signal in the order of arrival time and sends them sequentially in subsequent communication cycles. When the FPGA receives a synchronization signal from another FPGA that is designated as a shared synchronization signal, it outputs an interrupt pulse signal to trigger the microcontroller MCU to perform interrupt processing.

[0018] As a further optimization of this disclosure, the communication delay compensation value is calculated based on the communication baud rate, frame length and counting frequency. The slave device updates its own counter by adding the compensation value to the received master device count value.

[0019] A system for transmitting synchronization times based on a shared clock includes: The master-slave device confirmation module is used to organize timed communication between multiple interconnected FPGAs in a one-master-multiple-slave configuration. Each FPGA is pre-set with a unique serial number and is initially a slave device upon power-up. Based on the preset priority of each FPGA and the real-time communication network status, the module dynamically determines and maintains a unique master device in the network through distributed negotiation. The shared clock synchronization module maintains a counter that cycles at the same frequency as the shared clock within each FPGA. The counter continuously increments at the same counting frequency. The communication frame carries the counter count value at the time of transmission, the master / slave status, and the communication status. After receiving the count value from the master device, the slave device adds a communication delay compensation value and calibrates its own counter to ensure that the shared clock count value of all FPGAs in the network remains consistent. The synchronization signal transmission module enables high-frequency timing communication between each FPGA. Based on the shared clock, each FPGA converts the arrival event of the local synchronization signal into synchronization time information with a unified time base, and transmits it through the high-frequency timing communication. When an FPGA receives the specified synchronization time information, it generates an interrupt signal to trigger the microcontroller MCU to process it.

[0020] An electronic device includes a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other through the communication bus; Memory, used to store computer programs; A processor is used to execute a program stored in memory to implement the method of transmitting synchronization time based on a shared clock.

[0021] A computer-readable storage medium storing a computer program that, when executed by a processor, implements the method for transmitting synchronization times based on a shared clock.

[0022] The beneficial effects of this disclosure are as follows: The counter count values ​​are exchanged in a master-slave configuration. The slave devices use the master device's count value and compensate for communication delays as their own timer count values. This ensures that the count values ​​of each FPGA counter are basically consistent. After the local three-phase synchronization signal arrives, the FPGA uses this shared clock moment as the interrupt moment and transmits it to other FPGAs in the timing communication. This departs from the mode of transmitting synchronization signals triggered by the change of the synchronization signal edge in the existing technology. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This is a schematic diagram of a conventional trigger pulse generation scheme; Figure 2 This is a flowchart of a method in an embodiment of this disclosure; Figure 3 This is a schematic diagram of four FPGAs interconnected in an embodiment of this disclosure; Figure 4 This is a schematic diagram illustrating a communication failure between FPGAs in an embodiment of this disclosure; Figure 5 This is a schematic diagram of the controller for accessing the synchronization signal in an embodiment of this disclosure; Figure 6 This is a schematic diagram of the FPGA periodic communication transmission process in an embodiment of this disclosure; Figure 7 This is a schematic diagram of the FPGA receiving process in an embodiment of this disclosure; Figure 8 This is a schematic diagram of the FPGA's transmission response when multiple rising edges of synchronization signals arrive consecutively during a communication cycle in an embodiment of this disclosure; Figure 9 This is a schematic diagram illustrating the response of the FPGA when it receives a specified synchronization signal from the MCU in an embodiment of this disclosure. Figure 10 This is a system structure block diagram of an embodiment of this disclosure; Figure 11 This is a block diagram of the device structure in an embodiment of this disclosure. Detailed Implementation

[0025] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0026] like Figure 2 As shown, a method for transmitting synchronization moments based on a shared clock includes the following steps: S1. Organize the interconnected multiple FPGAs (Field Programmable Gate Arrays) into a master-slave configuration for timed communication. Each FPGA is pre-assigned a unique serial number and initially functions as a slave device upon power-up. Based on the preset priorities of each FPGA and the real-time communication network status, dynamically determine and maintain a unique master device in the network through distributed negotiation, including: The interconnected FPGAs are organized into a master-slave configuration for timed communication. The communication data includes whether the FPGA is the master device and whether it can receive information from other FPGAs.

[0027] Each FPGA is pre-assigned a different serial number and is configured as a slave device after power-on.

[0028] If an FPGA acting as a slave device detects that no master device exists based on data from other FPGAs, it sets a master device delay according to its own sequence number, with lower sequence numbers resulting in shorter delays. If no master device exists by the end of the master device delay, this FPGA becomes the master device. Other FPGAs cancel their delays upon detecting the presence of a master device and maintain their slave device status.

[0029] If the FPGA acting as the master device detects another FPGA also acting as the master device, it sets a delay to exit the master device state based on its own serial number; the lower the serial number, the longer the delay. If another FPGA is still acting as the master device when the delay ends, this FPGA becomes a slave device.

[0030] If a communication failure occurs between a slave device and the master device, the slave device with the best communication status and the smallest sequence number will be reselected as the master device.

[0031] S2. Each FPGA maintains an internal counter that cycles at the same frequency as a shared clock, continuously increasing at the same counting frequency. The communication frame carries the counter value at the time of transmission, the master / slave status, and the communication status. After receiving the master device's counter value, the slave device adds a communication delay compensation value and calibrates its own counter to ensure that the shared clock count value of all FPGAs in the network remains consistent, including: Each FPGA maintains a 32-bit high-frequency counter as a shared clock, which increments cyclically at the same frequency, and the count value of this clock is used as the time stamp of an event. FPGA communication data includes the count value of this counter at the time of communication. After receiving data from the master device, the slave device compensates for the communication delay by adding the master device's count value to its own counter value.

[0032] S3. High-frequency timing communication is performed between the FPGAs. Based on the shared clock, each FPGA converts the arrival event of its local synchronization signal into synchronization time information with a unified time base, and transmits it through the high-frequency timing communication. When an FPGA receives the specified synchronization time information, it generates an interrupt signal to trigger the microcontroller (MCU) to process the information, including: FPGAs perform high-frequency timing communication with a communication frequency of at least 10kHz. Upon the arrival of the synchronization signal, the synchronization time is determined by the current common clock count. In the next communication, the synchronization time and corresponding phase sequence are transmitted to other FPGAs.

[0033] If multiple rising edges of the synchronization signal arrive before the start of the next communication cycle, the FPGA will record the times of all rising edges of the synchronization signal and transmit them to other FPGAs in chronological order in subsequent communication cycles.

[0034] If the synchronization time received by the FPGA comes from the MCU (Micro Controller Unit) specifying the phase of the FPGA, the FPGA will output a narrow pulse to trigger an MCU interrupt. The MCU will then receive the interrupt time and perform subsequent processing.

[0035] In this embodiment, the purpose of this disclosure is to propose a synchronization signal transmission method that is different from the invention patent "Method, System and Medium for Simultaneous Transmission of Data Information and Shared Synchronization Signal". The interconnected FPGA maintains a shared clock through high-frequency communication, records the rising edge time of the local three-phase synchronization signal in the form of clock count value, and shares it with other FPGAs in timed communication. The communication time is completely different from the rising edge time of the synchronization signal, which is different from the mode of transmitting the synchronization signal triggered by the event of the change of the synchronization signal edge in the prior art.

[0036] This solution is applicable to FPGAs with interconnected communication, such as... Figure 3 The four interconnected FPGA modules are shown.

[0037] Each FPGA maintains a 32-bit counter as a shared clock. After power-on, it starts from 0 and increments at a frequency of 100MHz to the maximum value 0xffffffff, then returns to 0 from the maximum value and continues to increment, thus counting in a loop.

[0038] The FPGA is pre-set with a sequence number parameter starting from 1. It organizes time synchronization communication in a master-slave mode. In addition to the timer count value, the time synchronization information processing also includes information on whether it is a master device. Generally, only one FPGA is allowed to act as a master device.

[0039] Upon power-up, all FPGAs initially function as slave devices. When an FPGA detects from the received timing information that there is no master device, it immediately sets an online delay of 200 + 200 × sequence number microseconds. The FPGA with sequence number 1 (hereinafter referred to as FPGA1, and so on for other FPGAs) will become the master device 400 microseconds after power-up initialization. In the next communication cycle, other FPGAs that are currently slave devices will detect the existence of a master device, stop, and clear their own online delay counts. In other words, when all FPGAs power on simultaneously, the FPGA with the smallest sequence number will become the master device.

[0040] If multiple master devices exist simultaneously, the current master device is set to have an online exit delay of 2000 - 200 × sequence number in microseconds. Master devices with smaller sequence numbers will be converted to slave devices in descending order of sequence number until only one master device remains. For example, Figure 3 The four interconnected FPGA modules shown have the following behavior: Upon power-up, FPGA1 becomes the master device, and its external communication stops. The remaining FPGAs will detect the absence of a master device in the next communication cycle, and FPGA2 will become the master device after a delay. If FPGA1 resumes external communication, both FPGA1 and FPGA2 will simultaneously become master devices, and both will set an exit online delay of 2000 - 200 × sequence number microseconds. FPGA2 will become a slave device after 1600 microseconds. In the next communication cycle, FPGA1 will detect that it is now the only master device remaining, stop its exit master device delay count, and clear its own exit master device delay count.

[0041] If a communication failure occurs between the master and slave devices, the slave device with the best status and smallest sequence number needs to be selected as the master device based on the current communication status. The criterion for evaluating the FPGA communication status is the number of FPGAs with which it is communicating normally: such as... Figure 4 As shown, when FPGA1 acts as the master device, communication with FPGA2 is interrupted. At this time, including itself, the number of FPGAs communicating normally with FPGA1 and FPGA2 is 3, while the number of FPGAs communicating normally with FPGA3 and FPGA4 is 4, exceeding the number of master devices FPGA1. After FPGA3 and FPGA4 meet the conditions to become master devices, an online delay of 200 + 200 × sequence number microseconds is initiated. FPGA3 will become the master device after 800 microseconds, and then FPGA4 will exit and clear the online delay count.

[0042] The time synchronization communication frequency between FPGAs is 10kHz, i.e., the communication cycle is 100 microseconds. Every 10 communication cycles constitute a time synchronization cycle, during which the FPGA sends its own 32-bit counter value. This time synchronization data includes not only the current count value of its own 32-bit counter, but also its own master / slave status and whether it has received data from other FPGAs. See Table 1 below: Table 1 contains 8 bytes of timing information.

[0043] The master device and the slave device are distinguished by data ID. For example, the data ID for the master device to synchronize time is 1, while the data ID for the slave device to send its own counter status is 2.

[0044] The communication status byte is defined as shown in Table 2. Each bit represents the communication status between this FPGA and the corresponding FPGA. This allows the receiver to reselect the master device in case of communication failure.

[0045] Table 2 Communication Status Bytes

[0046] Because the communication wiring sequence is fixed, the receiving FPGA can identify the sending FPGA by which communication channel the received data comes from.

[0047] After receiving the count value sent by the master device, the FPGA immediately adds the communication delay to it as its own counter value. For example, if FPGAs follow a serial transmission protocol, each byte contains 1 start bit, 1 stop bit, 8 data bits, and no parity bit, i.e., each byte is 10 bits. 8 bytes of data require 80 bits to be transmitted, taking 80 microseconds at a communication baud rate of 1 Mbps (bits per second). At a counting frequency of 100 MHz, this equates to a value of 8000. The received count value is then increased by 8000 to become the shared clock count value. In this way, the shared clock count values ​​of all FPGAs are essentially consistent, and the time scale of an event recorded by one FPGA using the shared clock count value is also meaningful for reference on other FPGAs.

[0048] The synchronization signal is a crucial signal in the phase-controlled rectifier bridge, serving as the reference start point for the current cycle to align the trigger pulses for the MCU. Current technology still transmits the locally connected three-phase synchronization signal to other devices via signal triggering, which requires high real-time performance and may interfere with data communication. Introducing a shared clock allows the rising edge of the synchronization signal to be sent to other devices during timing communication, reducing real-time requirements while maintaining sufficient accuracy, and without interfering with normal communication.

[0049] like Figure 5As shown, the controller of the intelligent power cabinet is usually composed of an FPGA and an MCU. It has a local three-phase synchronization signal. The FPGA and MCU communicate and interconnect inside the controller. In order to enable the MCU to receive the required synchronization interrupt time in time, one pin of the FPGA is configured as an output and connected to the external interrupt trigger signal input pin of the MCU. When the FPGA receives the shared synchronization signal specified by the MCU, it can start the corresponding real-time processing flow of the MCU through this pin.

[0050] When the rising edge of the local synchronization signal arrives, the FPGA simply records the rising edge time and increments the synchronization signal counter, completing the group transmission of the synchronization signal time in the next communication cycle. See Table 3 for the data frame content of the transmitted synchronization signal time. Phase sequence byte 1 represents phase A, 2 represents phase B, and 4 represents phase C.

[0051] Table 3. Synchronization signal time data frames

[0052] See FPGA cycle transmission process Figure 6 Prioritize sending synchronization signals when there are no synchronization signals, wait to send when the synchronization task for the current cycle is completed, and finally complete the transmission of other status data.

[0053] See the receiving process. Figure 7 When the MCU receives the shared synchronization time specified by the MCU, it immediately outputs a narrow pulse on the interrupt pin connected to the MCU to trigger the corresponding processing flow of the MCU. When other data is received, it is stored in the data area for the MCU to process in the periodic task.

[0054] When the synchronization signal is abnormal, multiple synchronization signal moments may arrive within a single communication cycle: for example, when the C-phase primary side of the synchronization PT is disconnected, the rising edges of phases B and C in the connected three-phase synchronization signal are almost identical; another situation is that the synchronization signal is disturbed. The FPGA does not handle these anomalies but transmits them sequentially to other FPGAs according to the first-in-first-out principle, as follows: Figure 8 As shown.

[0055] If both synchronization signals within the communication cycle are at the shared synchronization signal time, the receiver will trigger the MCU external interrupt twice, which will be handled by the MCU, as follows: Figure 9 As shown.

[0056] like Figure 10 As shown, embodiments of this disclosure provide a system for transmitting synchronization moments based on a shared clock, including: The master-slave device confirmation module is used to organize timed communication between multiple interconnected FPGAs in a one-master-multiple-slave configuration. Each FPGA is pre-set with a unique serial number and is initially a slave device upon power-up. Based on the preset priority of each FPGA and the real-time communication network status, the module dynamically determines and maintains a unique master device in the network through distributed negotiation. The shared clock synchronization module maintains a counter that cycles at the same frequency as the shared clock within each FPGA. The counter continuously increments at the same counting frequency. The communication frame carries the counter count value at the time of transmission, the master / slave status, and the communication status. After receiving the count value from the master device, the slave device adds a communication delay compensation value and calibrates its own counter to ensure that the shared clock count value of all FPGAs in the network remains consistent. The synchronization signal transmission module enables high-frequency timing communication between each FPGA. Based on the shared clock, each FPGA converts the arrival event of the local synchronization signal into synchronization time information with a unified time base, and transmits it through the high-frequency timing communication. When an FPGA receives the specified synchronization time information, it generates an interrupt signal to trigger the microcontroller MCU to process it.

[0057] The implementation process of the functions and roles of each module in the above system is detailed in the implementation process of the corresponding steps in the above method, and will not be repeated here.

[0058] For the system embodiments, since they basically correspond to the method embodiments, the relevant parts can be referred to in the description of the method embodiments. The system embodiments described above are merely illustrative. The modules described as separate components may or may not be physically separate, and the components shown as modules may or may not be physical modules, that is, they may be located in one place or distributed across multiple network modules. Some or all of the modules can be selected to achieve the purpose of this disclosure according to actual needs. Those skilled in the art can understand and implement this without creative effort.

[0059] See Figure 11 The electronic device provided in the embodiments of this disclosure includes a processor 1110, a communication interface 1120, a memory 1130 and a communication bus 1140, wherein the processor 1110, the communication interface 1120 and the memory 1130 communicate with each other through the communication bus 1140. Memory 1130 is used to store computer programs; When the processor 1110 executes the program stored in the memory 1130, it implements the above-described method for transmitting synchronization time based on a shared clock.

[0060] The aforementioned communication bus 1140 can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. This communication bus 1140 can be divided into an address bus, a data bus, a control bus, etc. For ease of illustration, it is represented by only one thick line in the figure, but this does not indicate that there is only one bus or one type of bus.

[0061] The communication interface 1120 is used for communication between the above-mentioned electronic device and other devices.

[0062] The memory 1130 may include random access memory (RAM) or non-volatile memory, such as at least one disk storage device. Optionally, the memory 1130 may also be at least one storage device located remotely from the aforementioned processor 1110.

[0063] Embodiments of this disclosure also provide a computer-readable storage medium. The computer-readable storage medium stores a computer program that, when executed by a processor, implements the method for transmitting synchronization times based on a shared clock as described above.

[0064] The embodiments described above are merely examples of several implementations of this disclosure, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent disclosure. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this disclosure, and these modifications and improvements all fall within the protection scope of this disclosure.

Claims

1. A method for transmitting synchronization time based on a shared clock, characterized in that, Includes the following steps: The multiple interconnected FPGAs are organized into a master-slave configuration for timed communication. Each FPGA is pre-set with a unique serial number and is initially a slave device upon power-up. Based on the preset priority of each FPGA and the real-time communication network status, a unique master device in the network is dynamically determined and maintained through distributed negotiation. Each FPGA maintains a counter that cycles at the same frequency as a shared clock, continuously increasing at the same counting frequency. The communication frame carries the counter count value at the time of transmission, the master-slave status, and the communication status. After receiving the count value from the master device, the device adds the communication delay compensation value and calibrates its own counter to ensure that the shared clock count value of the entire FPGA network remains consistent. Each FPGA performs high-frequency timing communication. Based on the shared clock, each FPGA converts the arrival event of the local synchronization signal into synchronization time information with a unified time base and transmits it through the high-frequency timing communication. When the FPGA receives the specified synchronization time information, it generates an interrupt signal to trigger the microcontroller MCU to process it.

2. The method for transmitting synchronization time based on a shared clock according to claim 1, characterized in that, Communication information between multiple FPGAs includes whether this FPGA is the master device and whether it can receive information from other FPGAs normally.

3. The method for transmitting synchronization time based on a shared clock according to claim 1, characterized in that, Based on the preset priorities of each FPGA and the real-time communication network status, a unique master device in the network is dynamically determined and maintained through distributed negotiation, including: If an FPGA acting as a slave device discovers that there is no master device currently present by obtaining data from other FPGAs, it sets a master device delay according to its own sequence number, with a shorter delay for lower sequence numbers; if there is still no master device when the master device delay ends, this FPGA becomes the master device; other FPGAs cancel their delays and maintain slave device status after detecting the presence of a master device. If the FPGA acting as the master device discovers that another FPGA is also a master device, it sets a delay to exit the master device state according to its own serial number. The lower the serial number, the longer the delay. If there is still another FPGA as the master device when the delay ends, this FPGA becomes a slave device. If a communication failure occurs between a slave device and the master device, the slave device with the best communication status and the smallest sequence number will be reselected as the master device.

4. The method for transmitting synchronization time based on a shared clock according to claim 1, characterized in that, The counter is a 32-bit counter that increments cyclically at a frequency of 100MHz.

5. The method for transmitting synchronization time based on a shared clock according to claim 1, characterized in that, The frequency of the high-frequency timing communication is not less than 10kHz.

6. The method for transmitting synchronization time based on a shared clock according to claim 1, characterized in that, Each FPGA, based on the shared clock, converts the arrival event of the local synchronization signal into synchronization time information with a unified time base, and transmits it through the high-frequency timing communication. When the FPGA receives the specified synchronization time information, it generates an interrupt signal to trigger the microcontroller (MCU) to process the information, including: When the local synchronization signal of any FPGA arrives, the FPGA records the current count value of its own shared clock corresponding to the arrival time of the synchronization signal as the synchronization time, and sends the synchronization time and its corresponding phase sequence information to other FPGAs in the high-frequency timing communication. If multiple synchronization signals arrive within a communication cycle, the FPGA records the synchronization time of each synchronization signal in the order of arrival time and sends them sequentially in subsequent communication cycles. When the FPGA receives a synchronization signal from another FPGA that is designated as a shared synchronization signal, it outputs an interrupt pulse signal to trigger the microcontroller MCU to perform interrupt processing.

7. The method for transmitting synchronization time based on a shared clock according to claim 1, characterized in that, The communication delay compensation value is calculated based on the communication baud rate, frame length, and counting frequency. The slave device updates its own counter by adding the compensation value to the count value received from the master device.

8. A system for transmitting synchronization time based on a shared clock, characterized in that, include: The master-slave device confirmation module is used to organize timed communication between multiple interconnected FPGAs in a master-slave configuration. Each FPGA is pre-set with a unique serial number and is initially a slave device upon power-up. Based on the preset priority of each FPGA and the real-time communication network status, a unique master device in the network is dynamically determined and maintained through distributed negotiation. The shared clock synchronization module maintains a counter that cycles at the same frequency as the shared clock within each FPGA. The counter continuously increments at the same counting frequency. The communication frame carries the counter count value at the time of transmission, the master-slave status, and the communication status. After receiving the count value from the master device, the device adds the communication delay compensation value and calibrates its own counter to ensure that the shared clock count value of the entire FPGA network remains consistent. The synchronization signal transmission module enables high-frequency timing communication between each FPGA. Based on the shared clock, each FPGA converts the arrival event of the local synchronization signal into synchronization time information with a unified time base, and transmits it through the high-frequency timing communication. When an FPGA receives the specified synchronization time information, it generates an interrupt signal to trigger the microcontroller MCU to process it.

9. An electronic device, characterized in that, It includes a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other through the communication bus; Memory, used to store computer programs; A processor for executing a program stored in memory to implement the method for transmitting synchronization times based on a shared clock, as described in any one of claims 1-7.

10. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, it implements the method for transmitting synchronization time based on a shared clock as described in any one of claims 1-7.

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