Optical time-frequency fusion delivery system and clock acquisition method

Abstract

The application provides an optical time frequency fusion transmission system and a clock acquisition method. The system comprises a master station, a slave station and a single-fiber bidirectional optical fiber link connecting the master station and the slave station. The master station utilizes an electrical frequency comb to generate a harmonic wave, which is directly modulated and transmitted to the slave station through the optical fiber. The slave station performs frequency division modulation on the detected signal and transmits it back. The master station receives the back transmission signal and generates a phase error signal to realize closed-loop compensation of the link phase noise. Meanwhile, the slave station uses a high-stability frequency signal to optimize the WR time synchronization link. Through the phase-shifting architecture of "coarse adjustment segmented phase selection + hardware picosecond fine adjustment", the stability of time synchronization is significantly improved. The application solves the technical problems of large link reflection interference, weak phase noise suppression capability and limited time synchronization accuracy in the traditional optical fiber time frequency transmission, and realizes high-precision time frequency integrated transmission on a long-distance optical fiber at a picosecond level.

Description

Technical Field

[0001] This invention relates to the field of distributed high-precision synchronization technology, specifically to the field of precision time and frequency transmission based on optical fiber transmission, and more specifically, to an optical time and frequency fusion transmission system and a clock acquisition method. Background Technology

[0002] High-precision time and frequency transmission is a core support for modern precision equipment, communication networks, and major scientific infrastructure. With the iteration of collaborative detection and high-speed wireless communication technologies, the industry has raised picosecond-level requirements for phase noise suppression, long-distance transmission anti-interference, and synchronization stability in fiber optic time and frequency synchronization. The current mainstream technical approach involves deploying a frequency transmission link and a time synchronization protocol (such as White Rabbit, WR) on a single-fiber bidirectional optical fiber link. The former is responsible for the long-distance reproduction of a high-stability frequency reference, while the latter is responsible for the distribution and synchronization of the absolute clock. However, this "dual-track parallel" architecture has inherent defects at three levels, making it difficult for the overall system performance to meet the picosecond-level target requirements.

[0003] The first issue is the insufficient phase noise compensation and anti-reflection capabilities of the frequency transmission link itself. On the one hand, to achieve low-noise frequency transmission, existing solutions mostly employ optical interferometry or narrow-linewidth laser optical phase-locked loop structures. While these achieve good noise suppression, the system's optical path is complex, highly sensitive to environmental vibrations and temperature drift, and the hardware costs are high, making large-scale network deployment difficult. While pure electrical domain bidirectional compensation schemes are cost-effective, they lack harmonic reference constraints, resulting in insufficient depth of phase noise tracking compensation. On the other hand, in bidirectional transmission scenarios, traditional four-way frequency division loopback schemes rely solely on simple frequency division to separate the round-trip signal frequencies, lacking an independent and stable harmonic reference. Forward and return signals are susceptible to interference from Rayleigh backscattering in the fiber and parasitic reflections from connectors, leading to the inability of the phase detection stage to distinguish between valid and reflected signals. This significantly degrades phase measurement accuracy, particularly noticeable in long-distance fiber optic scenarios.

[0004] The second issue is the limited stability of the clock source upon which the time synchronization protocol itself relies. While the WR protocol can achieve sub-nanosecond time synchronization through Ethernet message exchange, its slave operating clock relies entirely on the clock recovery circuit (CDR) within the FPGA to extract it from the data stream. This recovery process itself introduces significant phase jitter, thus limiting the short-term stability of synchronization to the noise level of the slave's local crystal oscillator. A deeper problem lies in the fact that the frequency transmission link and the WR time message link are physically independent. The highly stable signal output from the frequency link cannot be directly "injected" into the WR synchronization link as its clock reference, making it difficult to break through the nanosecond level in time synchronization accuracy.

[0005] The third aspect: There is an inherent contradiction between the adjustment range and accuracy of slave clock phase adjustment methods. Traditional WR slave phase correction only uses a single delay chip, DLL, or single-stage PLL phase shifting. Among these, a single delay chip cannot cover the entire clock cycle; frequent relocking of the DLL introduces additional phase disturbances; and the single-stage PLL phase shift step is too large, failing to achieve picosecond-level fine phase alignment, making it difficult to match the hundreds of picosecond phase detection resolution of DDMTD. In other words, existing methods cannot simultaneously meet the requirements of "full cycle coverage" and "picosecond-level stepping".

[0006] To address the aforementioned multiple shortcomings, existing time-frequency synchronization schemes attempt to improve upon them by using frequency transfer-assisted WR synchronization. For example, the invention application with application number CN202510059977.9 uses a common frequency multiplier to generate a reference signal, employs a four-way frequency divider structure to achieve frequency domain isolation of the round-trip optical signal, and then constructs a bidirectional frequency transfer link to optimize the WR synchronization clock. However, this scheme still has significant limitations: First, its frequency transfer link does not have an independent electrical frequency comb harmonic reference, nor does it construct a closed-loop phase compensation constraint relationship for multi-mixer cascades. Therefore, its suppression capability is limited when facing Rayleigh backscattering and connector reflection interference in single-fiber bidirectional optical fiber links, and its phase noise compensation effect is insufficient in long-distance transmission scenarios. Second, its phase adjustment stage only uses a general-purpose delay chip, which cannot cover the entire clock cycle for phase shifting, and cannot achieve picosecond-level fine compensation, thus limiting the potential for improving the short-term stability of the WR clock.

[0007] In summary, existing time-frequency fusion transmission schemes suffer from problems such as large link reflection interference, weak phase noise suppression capability, and limited time synchronization accuracy, making it impossible to achieve high-precision integrated time-frequency transmission at the picosecond level over long-distance optical fibers. Summary of the Invention

[0008] Therefore, the purpose of this invention is to overcome the shortcomings of the prior art and provide an optical time-frequency fusion transmission system and clock acquisition method based on an electrical frequency comb.

[0009] The objective of this invention is achieved through the following technical solution:

[0010] According to a first aspect of the present invention, an optical time-frequency fusion transfer system based on an electrical frequency comb is provided, the system comprising a master station, a slave station, and a single-fiber bidirectional optical fiber link connecting the master station and the slave station, wherein:

[0011] The master station includes a reference clock, a frequency transmission motherboard, a WR motherboard, a first optical circulator, and a first wavelength division multiplexer. The reference clock is connected to the frequency transmission motherboard, the frequency transmission motherboard is connected to the first optical circulator, and the first optical circulator is connected to the first wavelength division multiplexer to form a master station-side frequency unit. The reference clock is connected to the WR motherboard, and the WR motherboard is connected to the first wavelength division multiplexer to form a master station-side clock unit. The master station-side frequency unit is used to generate a radio frequency carrier signal, compensate it, and then transmit the compensated radio frequency carrier signal to the slave station through a single-fiber bidirectional optical fiber link. The master station-side clock unit is used to generate a 125MHz Ethernet reference clock and transmit it to the slave station through a single-fiber bidirectional optical fiber link.

[0012] The slave station includes a frequency transmission slave board, a WR slave board, a second optical circulator, and a second wavelength division multiplexer. The frequency transmission slave board is connected to the second optical circulator, and the second optical circulator is connected to the second wavelength division multiplexer to form a slave-side frequency unit. The WR slave board is connected to the second wavelength division multiplexer to form a slave-side clock unit, and the frequency transmission slave board is connected to the WR slave board. The slave-side frequency unit is used to receive the radio frequency carrier signal from the master station-side frequency unit, and transmit the radio frequency carrier signal as a high-stability frequency signal to the WR slave board and then transmit it back to the frequency transmission main board after frequency division. The slave-side clock unit is used to receive the 125MHz Ethernet reference clock from the master station-side clock unit and the high-stability frequency signal from the slave-side frequency unit, and calibrate the 125MHz Ethernet reference clock according to the high-stability frequency signal to output the calibrated clock.

[0013] The frequency transmission motherboard integrates an electrical frequency comb module, wherein the reference clock outputs a 10MHz reference clock signal, the electrical frequency comb module generates a 4GHz harmonic reference signal based on the 10MHz reference clock signal, the frequency transmission motherboard generates a phase error signal based on the 4GHz harmonic reference signal, the radio frequency carrier signal generated by the master station side frequency unit and the frequency-divided radio frequency carrier signal returned by the slave station side frequency unit, and then sends the generated radio frequency carrier signal to the slave station after compensating for the phase error signal.

[0014] The WR slave board integrates an optimization logic module, which includes a phase detection module, a filtering module, and a phase shifting module. The phase detection module acquires the phase difference between the 125MHz Ethernet reference clock and the high-stability frequency signal received by the slave station. The filtering module receives the phase difference and filters it to generate a closed-loop control signal for adjusting the phase shifting module. The phase shifting module is configured with a logic controller, a phase-locked loop coarse adjuster, and a programmable delay unit. The logic controller receives the closed-loop control signal and generates coarse and fine adjustment control strategies accordingly. The phase-locked loop coarse adjuster includes a phase-locked loop and a 4-to-1 multiplexer, receiving the coarse adjustment control strategy and the 125MHz Ethernet reference clock, dividing one clock cycle of the 125MHz Ethernet reference clock into four equal-phase intervals, and selecting one of the four equal-phase intervals as the phase channel according to the coarse adjustment control strategy. The programmable delay unit is a programmable delay chain built into the FPGA, used to perform picosecond-level phase compensation on the selected phase channel according to the fine adjustment control strategy to obtain a calibrated clock.

[0015] Preferably, the frequency transmission motherboard further includes a voltage-controlled oscillator, a first mixer, a master station frequency divider, a first photodetector, a second mixer, a third mixer, a proportional-integral controller, and a first laser diode, wherein: the voltage-controlled oscillator is used to generate a radio frequency carrier signal and send it to the first mixer and the first laser diode; the first mixer is used to receive the radio frequency carrier signal and a 4GHz harmonic reference signal generated by an electrical frequency comb, and after mixing the two, send them to the master station frequency divider; the master station frequency divider is used to receive the signal sent from the first mixer and divide it to obtain a first difference frequency signal; the first photodetector is used to transmit the frequency-divided radio frequency carrier signal returned from the master station through a single-fiber bidirectional optical fiber. The optical signal in the link is restored to an electrical signal and sent to the second mixer; the second mixer is used to receive the electrical signal from the first photodetector and the 4GHz harmonic reference signal generated by the electrical frequency comb, and mix the two to obtain a second difference frequency signal, which is then sent to the third mixer; the third mixer is used to receive the first difference frequency signal and the second difference frequency signal, and mix the two to obtain a phase error signal, which is then sent to the proportional-integral controller; the proportional-integral controller is used to generate a control voltage based on the phase error signal, which is used to drive the voltage-controlled oscillator to adjust the frequency of the radio frequency carrier signal; the first laser diode is used to generate a corresponding optical carrier for the radio frequency carrier signal.

[0016] Preferably, the proportional-integral controller continuously adjusts the frequency of the radio frequency carrier signal by generating a control voltage to regulate the voltage-controlled oscillator until the system enters a locked state, wherein the locked state satisfies the following frequency constraint relationship:

[0017]

[0018]

[0019] in, This represents the frequency of the radio frequency carrier signal generated by the voltage-controlled oscillator. The frequency representing the 4GHz harmonic reference signal, This represents the frequency of the frequency-divided radio frequency carrier signal transmitted back from the slave station.

[0020] Preferably, the master station frequency divider divides the signal from the first mixer by four to obtain the first difference frequency signal, and the slave station frequency unit divides the RF carrier signal from the master station frequency unit by four and then sends it back to the frequency transmission main board.

[0021] Preferably, the WR motherboard includes a phase-locked loop (PLL) and a White Rabbit Precision Time Protocol (BRT) core. The PLL is used to acquire a 10MHz reference clock signal and multiply it to a 125MHz Ethernet reference clock. The BRT core is used to acquire the 125MHz Ethernet reference clock and transmit it to the slave station via a single-fiber bidirectional optical fiber link, and to use the 125MHz Ethernet reference clock as a timestamp and servo synchronization reference.

[0022] Preferably, the single-fiber bidirectional optical fiber link transmits optical carriers with three wavelengths: 1550nm, 1470nm, and 1490nm. The 1550nm optical carrier carries the radio frequency carrier signal sent from the master station to the slave station; the 1470nm optical carrier carries the 125MHz Ethernet reference clock sent from the master station to the slave station; and the 1490nm optical carrier carries the frequency-divided radio frequency carrier signal sent from the slave station to the master station.

[0023] Preferably, the phase detection module uses a DDMTD digital dual-mixer time difference measurement unit, and its phase measurement resolution is ≤100ps.

[0024] Preferably, the programmable delay unit is IDELAYE2, which is an IOB hardware primitive built into the Xilinx 7 series FPGA.

[0025] According to a second aspect of the present invention, a clock acquisition method for a White Rabbit application terminal is provided, wherein the White Rabbit application terminal refers to a terminal that supports the White Rabbit Precision Time Protocol and updates its own clock through the protocol. The method includes: S1, connecting the White Rabbit application terminal to a slave-side frequency unit of the system as described in the first aspect of the present invention, enabling the White Rabbit application terminal to acquire the calibrated clock output by the slave-side frequency unit. S2, the master-side frequency unit of the system generates a radio frequency carrier signal, compensates it, and transmits the compensated radio frequency carrier signal to the slave station via a single-fiber bidirectional optical fiber link; the master-side clock unit generates a 125MHz Ethernet reference clock and transmits it to the slave station via the same single-fiber bidirectional optical fiber link. S3, the slave-side frequency unit receives the radio frequency carrier signal from the master-side frequency unit and transmits it as a high-stability frequency signal to the WR slave board; the slave-side clock unit receives the 125MHz Ethernet reference clock from the master-side clock unit and the high-stability frequency signal from the slave-side frequency unit, and calibrates the 125MHz Ethernet reference clock according to the high-stability frequency signal to output the calibrated clock to the White Rabbit application terminal.

[0026] Compared with existing technologies, the advantages of this invention are as follows: By using a compensation mechanism to form an RF carrier signal between the forward optical carrier driven by the master station's electrical frequency comb and the frequency return signal from the slave station, efficient electrical domain compensation for phase noise in the fiber optic link is achieved, effectively suppressing co-channel interference introduced by Rayleigh backscattering and connector reflection. Simultaneously, the slave station uses the highly stable signal recovered from frequency transmission as a reference, and through a closed-loop feedback consisting of a phase detection module, a filtering module, and a two-stage phase-shifting architecture of "coarse adjustment + fine adjustment," performs picosecond-level phase correction on the clock signal received by the slave station. This significantly reduces short-term jitter in the time synchronization link, combining strong anti-fiber reflection interference capability, deep link phase noise suppression capability, low-cost pure electrical domain closed-loop architecture, and picosecond-level high-precision phase-shifting capability, allowing clock synchronization accuracy to break through the nanosecond level and enter the picosecond level. Therefore, this invention has broad application prospects in scenarios with stringent requirements for short-term synchronization stability and link anti-reflection interference capability, such as atomic metrology, distributed radar collaborative detection, 5G / 6G base station synchronization, deep space telemetry and control, and synchronization of large scientific devices. Attached Figure Description

[0027] Figure 1 This is a schematic diagram of the overall architecture of an optical time-frequency fusion transfer system based on an electrical frequency comb according to an embodiment of the present invention.

[0028] Figure 2 This is a schematic diagram of the connection architecture between the frequency transmission motherboard and the frequency transmission slave board of an optical time-frequency fusion transmission system based on an electrical frequency comb according to an embodiment of the present invention.

[0029] Figure 3This is a schematic diagram of the optimized logic module architecture of the WR slave board of an optical time-frequency fusion transfer system based on an electrical frequency comb according to an embodiment of the present invention.

[0030] Figure 4 This is a schematic diagram of the phase-shifting module architecture of the optimized logic module of the WR slave board of the optical time-frequency fusion transfer system based on an electrical frequency comb, according to an embodiment of the present invention. Detailed Implementation

[0031] The technical solution of the present invention will be clearly and completely described below with reference to the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0032] As mentioned in the background section, existing time-frequency fusion transmission schemes suffer from problems such as large link reflection interference, weak phase noise suppression capability, and limited time synchronization accuracy, making it impossible to achieve high-precision integrated time-frequency transmission at the picosecond level over long-distance optical fibers.

[0033] To address the aforementioned issues, this invention provides an optical time-frequency fusion transmission system based on an electrical frequency comb, enabling high-precision integrated time-frequency transmission over long-distance optical fibers at the picosecond level.

[0034] Before providing a detailed description of the present invention, the following explanations are provided for some of the technologies and terms involved in the present invention:

[0035] CIR: An optical circulator is a multi-port optical device with non-reciprocal characteristics. Its non-reciprocity is primarily based on the Faraday magneto-optical effect, achieving unidirectional sequential transmission of optical signals through internal components such as birefringent crystals and Faraday rotators. When an optical signal is input from any port, it can be output from the next port in the numerical order shown in the diagram with very little loss, while the loss to all other ports from that port is very high, making them disconnected ports.

[0036] WDM (Wavelength Division Multiplexing) is a technology that combines two or more optical carrier signals of different wavelengths (carrying various information) at the transmitting end using a multiplexer (also called a multiplexer) and couples them into the same optical fiber for transmission. At the receiving end, the optical carriers of various wavelengths are separated by a demultiplexer (also called a demultiplexer), and then further processed by an optical receiver to recover the original signal.

[0037] PLL: Phase Locked Loop is a circuit technology that compares the phase difference of two electrical signals with similar frequencies (carrying phase / frequency information) inside the loop, and outputs an error voltage to drive a controlled oscillator, so that the phase and frequency of the controlled signal are synchronously locked with the reference signal.

[0038] WR PTP Core (White Rabbit Precision Time Protocol Core, or WRPC for short) is a high-precision synchronization IP core integrated in the FPGA. It is the core hardware logic unit of the WR (White Rabbit) synchronization system. It combines the unified reference frequency, timestamp, and phase information of the entire network at the master end through protocol frames and high-speed optical Ethernet multiplexing and coupling it to a single optical fiber for bidirectional transmission.

[0039] PD: A photodetector is a core device that converts light signals into electrical signals. Its principle is based on the change in conductivity of the irradiated material caused by radiation.

[0040] MIX: A mixer is a circuit whose output signal frequency is equal to the sum, difference, or other combination of the frequencies of the two input signals.

[0041] Divide-by-N (1 / N): This is a fundamental radio frequency / digital signal processing technology in the fields of frequency synthesis, phase-locked loop (PLL), and time-frequency synchronization. It sends a high-frequency input carrier signal into a frequency divider circuit, divides it into N cycles, and merges every N complete oscillation cycles of the input signal into one output cycle. The final output frequency is a synchronous signal with the same source frequency of 1 / N of the input frequency, realizing the downconversion of a high-frequency reference to a low-frequency standard clock.

[0042] PI: Proportional-integral (PI) circuit is a widely used control circuit in the field of engineering control. It adjusts system errors through proportional and integral control methods, thereby achieving precise control.

[0043] VCO: Voltage Controlled Oscillator converts the input control voltage signal (carrying phase error information) into a continuous carrier electrical signal. The amplitude of the input voltage directly determines the frequency of the output oscillation signal.

[0044] LD: Laser Diode is the core electro-optical conversion device in optical communication and fiber optic time and frequency transmission systems; it converts the input drive current (carrying power and modulation information) into a directional coherent monochromatic laser signal, which is then injected into the optical fiber path to complete optical carrier transmission.

[0045] 4-1 MUX: The 4-to-1 Multiplexer is a fundamental combinational logic routing unit in digital time and frequency circuits and FPGA timing cores. It takes four independent digital / RF carrier signals (carrying different clock, phase, and control timing information) as parallel inputs, and uses a 2-bit selection control signal to select one of the signals at a time to connect to a single common output path. This enables multiple signals to share a single transmission channel in a time-division manner. The output signal completely retains the frequency, phase, and level information of the selected inputs and supplies them to back-end units such as frequency dividers, DDMTD phase detectors, WR PTP servos, and RF drivers for timing processing.

[0046] DDMTD: Digital Dual Mixer Time Difference uses digital logic such as FPGA triggers, numerically controlled oscillators, digital filters, and digital counters to complete all mixing and time difference calculations. It has higher hardware integration, smaller size, and lower temperature drift and additional noise.

[0047] IDELAYE2: The IDELAYE2 input programmable delay unit is a hardware primitive built into the IOB (Input / Output Block) of Xilinx 7 series FPGAs (Artix-7 / Kintex-7 / Virtex-7). It is dedicated to performing high-precision, calibrable, and programmable analog delay adjustment on input signals. It is a real delay chain hardware that exists on the silicon chip and is not a delay circuit generated by logic synthesis.

[0048] The present invention will now be described in detail.

[0049] In summary, refer to Figure 1 The optical time-frequency fusion transmission system based on an electrical frequency comb provided by this invention includes a master station, a slave station, and a single-fiber bidirectional optical fiber link connecting the master station and the slave station, wherein:

[0050] The master station includes a reference clock, a frequency transmission motherboard, a WR motherboard, a first optical circulator, and a first wavelength division multiplexer. The reference clock is connected to the frequency transmission motherboard, the frequency transmission motherboard is connected to the first optical circulator, and the first optical circulator is connected to the first wavelength division multiplexer to form a master station-side frequency unit. The reference clock is connected to the WR motherboard, and the WR motherboard is connected to the first wavelength division multiplexer to form a master station-side clock unit. The master station-side frequency unit is used to generate a radio frequency carrier signal, compensate it, and then transmit the compensated radio frequency carrier signal to the slave station through a single-fiber bidirectional optical fiber link. The master station-side clock unit is used to generate a 125MHz Ethernet reference clock and transmit it to the slave station through a single-fiber bidirectional optical fiber link.

[0051] The slave station includes a frequency transmission slave board, a WR slave board, a second optical circulator, and a second wavelength division multiplexer. The frequency transmission slave board is connected to the second optical circulator, and the second optical circulator is connected to the second wavelength division multiplexer to form a slave-side frequency unit. The WR slave board is connected to the second wavelength division multiplexer to form a slave-side clock unit, and the frequency transmission slave board is connected to the WR slave board. The slave-side frequency unit is used to receive the radio frequency carrier signal from the master station-side frequency unit, and transmit the radio frequency carrier signal as a high-stability frequency signal to the WR slave board and then transmit it back to the frequency transmission main board after frequency division. The slave-side clock unit is used to receive the 125MHz Ethernet reference clock from the master station-side clock unit and the high-stability frequency signal from the slave-side frequency unit, and calibrate the 125MHz Ethernet reference clock according to the high-stability frequency signal to output the calibrated clock.

[0052] like Figure 2 As shown, the frequency transmission motherboard integrates an electrical frequency comb module (i.e. Figure 2 The frequency comb in the circuit consists of a 10MHz reference clock output and an electrical frequency comb module that generates a 4GHz harmonic reference signal based on the 10MHz reference clock signal. The frequency transmission motherboard generates a phase error signal based on the 4GHz harmonic reference signal, the RF carrier signal generated by the master station's frequency unit, and the frequency-divided RF carrier signal returned by the slave station's frequency unit. The generated RF carrier signal is then compensated based on the phase error signal before being sent to the slave station.

[0053] The WR integrates an optimization logic module within the board, such as... Figure 3 As shown, the optimization logic module includes a phase detection module, a filtering module, and a phase shifting module. The phase detection module is used to acquire the phase difference between the 125MHz Ethernet reference clock and the high-stability frequency signal received from the slave station. The filtering module receives the phase difference and filters it to generate a closed-loop control signal for adjusting the phase shifting module. Figure 4 As shown, the phase-shifting module is equipped with a logic controller, a phase-locked loop coarse tuner, and a programmable delay unit (i.e., Figure 4 In the IDELAYE2 section (a preferred embodiment of the programmable delay unit), the logic controller receives the closed-loop control signal and generates coarse and fine adjustment control strategies accordingly. The phase-locked loop coarse adjuster includes a phase-locked loop and a 4-to-1 multiplexer, which receives the coarse adjustment control strategy and a 125MHz Ethernet reference clock, divides one clock cycle of the 125MHz Ethernet reference clock into four equal-phase intervals, and selects one of the four equal-phase intervals as a phase channel according to the coarse adjustment control strategy. The programmable delay unit is a programmable delay chain built into the FPGA, which performs picosecond-level phase compensation on the selected phase channel according to the fine adjustment control strategy to obtain the calibrated clock.

[0054] This invention uses electrical frequency comb harmonics to fix the frequency difference, fundamentally isolating co-frequency reflection interference. This avoids problems found in traditional schemes that share ordinary frequency-doubled low-frequency signals, such as poor signal spectrum purity, inability to cancel VCO frequency conversion noise, noise introduced by the frequency multiplier circuit, and the presence of a large amount of non-fiber noise in the mixing output error signal. Furthermore, the phase-shifting module of this invention employs a closed-loop de-jitter architecture of "coarse adjustment segmented phase selection + hardware picosecond fine adjustment" to optimize the WR fiber optic frequency transmission synchronization clock, balancing adjustment range and phase-shifting accuracy through two-stage linkage. Specifically, in the coarse adjustment segmented phase selection stage, using the 125MHz high-stability clock to be corrected as input, the phase-locked loop coarse adjuster generates four 125MHz clocks with uniformly spaced phases, dividing the 8ns complete clock cycle into four 2ns phase intervals. The 4-1 MUX receives the coarse adjustment control strategy and automatically selects the 2ns interval clock closest to the target phase as the coarse adjustment output, achieving full-cycle blind-zone-free coarse phase alignment. In the hardware picosecond fine-tuning stage, the coarse-tuned output clock is fed into the programmable delay unit, with a fixed hardware single-tap delay step of 78ps and a fine compensation range covering 2.5ns. Picosecond-level phase fine-tuning is achieved by dynamically adjusting the number of taps, and the overall phase shift resolution after two-stage linkage is ≤100ps. After correction, the edge of the high-stability frequency signal is perfectly aligned with the edge of the clock recovered by the WR slave board. This low-jitter, high-stability signal directly replaces the native CDR clock recovered by the WR slave board, supplying the White Rabbit Precision Time Protocol kernel of the WR slave board to complete timestamp marking and link delay servo synchronization, significantly reducing the short-term jitter of the WR synchronization clock, and improving the synchronization stability to the tens of picosecond level. Therefore, the system of this invention improves the time and frequency synchronization stability by an order of magnitude compared with traditional solutions, and can achieve ultra-high precision clock synchronization at the picosecond level.

[0055] To better understand the present invention, each step will be described in detail below with reference to specific embodiments.

[0056] According to one embodiment of the present invention, still referring to Figure 2The frequency transmission motherboard also includes a voltage-controlled oscillator, a first mixer, a master station frequency divider, a first photodetector, a second mixer, a third mixer, a proportional-integral controller, and a first laser diode. Specifically: the voltage-controlled oscillator generates a radio frequency carrier signal and sends it to the first mixer and the first laser diode; the first mixer receives the radio frequency carrier signal and a 4GHz harmonic reference signal generated by an electrical frequency comb, mixes them, and sends the mixture to the master station frequency divider; the master station frequency divider receives the signal from the first mixer and divides it to obtain a first difference frequency signal; the first photodetector transmits the frequency-divided radio frequency carrier signal returned from the master station via a single-fiber bidirectional optical fiber link. The optical signal is recovered into an electrical signal and sent to a second mixer; the second mixer is used to receive the electrical signal from the first photodetector and the 4GHz harmonic reference signal generated by the electrical frequency comb, and mix the two to obtain a second difference frequency signal, which is then sent to a third mixer; the third mixer is used to receive the first difference frequency signal and the second difference frequency signal, and mix the two to obtain a phase error signal, which is then sent to a proportional-integral controller; the proportional-integral controller is used to generate a control voltage based on the phase error signal, which is used to drive a voltage-controlled oscillator to adjust the frequency of the radio frequency carrier signal; the first laser diode is used to generate a corresponding optical carrier for the radio frequency carrier signal.

[0057] This invention constructs a triple mixing closed loop and defines a dedicated frequency constraint relationship. It relies on an electrical frequency comb to generate an independent 4GHz harmonic reference to fix the round-trip signal frequency difference, naturally suppressing co-channel interference caused by fiber Rayleigh backscattering and connector parasitic reflections. In contrast, traditional solutions only employ a "common frequency multiplier + simple 4-way divider" mechanism, lacking harmonic reference constraints, resulting in weak reflection interference suppression and significantly higher phase errors over long distances. Furthermore, this invention performs phase noise compensation entirely in the electrical domain, eliminating the need for expensive narrow-linewidth lasers and complex optical interference loops. The hardware of this invention utilizes only mature electrical frequency combs, mixers, and FPGA devices, resulting in high system integration, strong robustness to vibration and temperature drift, and suitability for large-scale network deployment. Existing optical compensation and electrical frequency transmission solutions cannot simultaneously achieve low cost and low phase noise.

[0058] According to one embodiment of the present invention, the proportional-integral controller continuously adjusts the frequency of the radio frequency carrier signal by generating a control voltage to regulate the voltage-controlled oscillator until the system enters a locked state, wherein the locked state satisfies the following frequency constraint relationship:

[0059]

[0060]

[0061] in, This represents the frequency of the radio frequency carrier signal generated by the voltage-controlled oscillator. The frequency representing the 4GHz harmonic reference signal, This represents the frequency of the frequency-divided radio frequency carrier signal transmitted back from the station. In this embodiment, all phase disturbances caused by fiber temperature and mechanical stress are canceled out in real time; the independent harmonic reference signal provided by the electrical frequency comb fixes the round-trip signal frequency difference, and the clutter signals generated by fiber Rayleigh backscattering and connector reflections cannot meet the effective mixing frequency conditions, significantly reducing the impact of reflection interference on phase measurements. However, if only a common frequency multiplier is used instead of the electrical frequency comb, without an independent 4GHz harmonic reference, and lacking a triple mixing link and dedicated frequency constraint equations, it is impossible to rely on harmonic isolation of reflected clutter, resulting in a 3-5 times deterioration in the synchronous TDEV stability index for the same fiber length.

[0062] According to one embodiment of the present invention, the master station frequency divider divides the signal from the first mixer by four to obtain the first difference frequency signal, and the slave station frequency unit divides the radio frequency carrier signal from the master station frequency unit by four and then transmits it back to the frequency transmission main board.

[0063] According to one embodiment of the present invention, the WR motherboard includes a phase-locked loop and a White Rabbit Precision Time Protocol core. The phase-locked loop is used to acquire a 10MHz reference clock signal and multiply it to a 125MHz Ethernet reference clock. The White Rabbit Precision Time Protocol core is used to acquire the 125MHz Ethernet reference clock and transmit it to the slave station through a single-fiber bidirectional optical fiber link, and to use the 125MHz Ethernet reference clock as a timestamp and servo synchronization reference.

[0064] According to one embodiment of the present invention, a single-fiber bidirectional optical fiber link transmits optical carriers with three wavelengths: 1550nm, 1470nm, and 1490nm. The 1550nm optical carrier carries the radio frequency carrier signal sent from the master station to the slave station; the 1470nm optical carrier carries the 125MHz Ethernet reference clock sent from the master station to the slave station; and the 1490nm optical carrier carries the frequency-divided radio frequency carrier signal sent from the slave station to the master station. In this embodiment, the S-band (1470 / 1490nm) and C-band (1550nm) spectral ranges are completely isolated, with no optical crosstalk. The frequency carriers and WR time messages do not interfere with each other, achieving integrated time-frequency co-fiber transmission, saving fiber optic cabling resources, and reducing network hardware costs.

[0065] According to one embodiment of the present invention, the phase detection module adopts a DDMTD digital dual-mixer time difference measurement unit, and its phase measurement resolution is ≤100ps.

[0066] According to one embodiment of the present invention, the programmable delay unit is IDELAYE2, which is an IOB hardware primitive built into the Xilinx 7 series FPGA. Besides IDELAYE2, MMCM or a custom-designed dedicated programmable delay line (PDE) can also be used as alternatives. This embodiment employs a PLL segmented coarse adjustment + FPGA hardware IDELAYE2 fine-tuning linkage architecture, achieving full coverage of the 8ns clock cycle, 78ps picosecond-level compensation in steps, no frequent relocking phase disturbances, and a phase shift resolution ≤100ps. It perfectly matches the DDMTD high-precision phase detector unit, fundamentally reducing WR clock jitter and significantly improving short-term time synchronization stability.

[0067] To better understand the optical time-frequency fusion transfer system based on an electrical frequency comb of the present invention, it will be further described below from the perspective of the system's workflow. The workflow of this system includes:

[0068] T1. Main station reference signal generation and forward optical carrier transmission:

[0069] The reference clock outputs a 10MHz reference clock signal, one of which is fed into the electrical frequency comb module to generate a 4GHz harmonic reference signal through frequency multiplication. The other path is fed into the PLL of the WR motherboard with a 125MHz Ethernet reference clock multiplied by a certain factor; the voltage-controlled oscillator (VCO) outputs an angular frequency. The radio frequency signal drives the first laser diode LD1 to generate a 1550nm forward optical carrier, which is then sent to the slave station via the first wavelength division multiplexer WDM1 through a single-fiber bidirectional optical fiber.

[0070] T2, Slave station opto-demodulation, frequency division return and high-stability frequency output:

[0071] The 1550nm forward optical carrier is separated by the second wavelength division multiplexer (WDM2) at the slave station, and then sent to the second photodetector (PD2) via the second optical circulator (CIR2) for demodulation to obtain a high-stability electrical signal. This high-stability electrical signal is split into two paths: one serves as the slave station's high-stability frequency reference signal, and the other is divided by four by the slave station's N-divider to generate a signal that satisfies… The return radio frequency signal is modulated by the second laser diode LD2 to generate a return optical signal, which is then sent back into the optical fiber to the main station.

[0072] T3, Phase noise compensation for the triple-mixer closed-loop link of the main station:

[0073] T31, the main station's first photodetector PD1 receives the returned optical signal and converts it into a returned electrical signal. .

[0074] T32, VCO output signals With harmonic reference signal The signal is fed into the first mixer MIX1 for mixing, and the output signal is divided by four by the N divider at the main station to obtain the difference frequency signal. .

[0075] T33, Return Electrical Signal Directly with harmonic reference signal The signal is fed into the second mixer MIX2 to obtain the difference frequency signal. .

[0076] T34, difference frequency signal , The signal is fed into the third mixer (MIX3) to extract the phase error signal. The phase error signal is then used by a proportional-integral (PI) controller to generate the output signal for regulating the control voltage of the VCO. The system satisfies the constraints after locking. It can cancel phase noise in fiber optic links in real time.

[0077] T4. Two-level phase shift jitter optimization and WR high-precision synchronization:

[0078] The T41, DDMTD digital dual-mixer time difference measurement unit acquires the phase difference between the clock recovered from the slave station WR slave board and the high-stability frequency reference signal.

[0079] The T42 and PLL divide the 125MHz, 8ns period clock into four 2ns phase intervals and complete coarse phase alignment through a 4-1 MUX. The coarse adjustment clock is sent to the FPGA's built-in IDELAYE2 to complete picosecond-level fine phase compensation in 78ps steps. The overall phase shift resolution of the two-stage linkage is ≤100ps.

[0080] T43, the filtering module smooths the phase error and feeds it back to the phase shifting module to dynamically correct the phase offset, so that the edge of the high-stability frequency signal is aligned with the clock recovered by WR from the board. The corrected high-stability frequency signal replaces the original clock recovered by WR from the board to complete the picosecond-level stable clock synchronization.

[0081] In summary, the system of this invention has an independent electrical frequency comb module at the main station, which generates a stable 4GHz harmonic reference signal by frequency multiplication of a 10MHz atomic reference signal. As a dedicated benchmark for closed-loop error extraction; constructing a system including VCO output signal Harmonic reference signal ,Send signals back from station This invention utilizes a three-way signal triple mixing error extraction link. By relying on a fixed harmonic reference output from an electrical frequency comb to stabilize the round-trip signal frequency difference, it can simultaneously complete closed-loop compensation for phase noise across the entire link, addressing co-frequency interference introduced by Rayleigh backscattering and connector parasitic reflections in electrically isolated optical fibers. This eliminates the need for high-cost, narrow-linewidth lasers, resulting in a simple overall architecture and strong robustness to temperature drift disturbances caused by temperature and vibration. Furthermore, this invention employs a PLL to equally divide the 125MHz clock signal of the WR system with an 8ns period into four phase intervals of 2ns. This, combined with a 4-1MUX (four-to-one multiplexer), achieves coarse phase alignment without blind spots throughout the entire clock cycle. Then, it utilizes the FPGA's native hardware primitive IDELAYE2 to achieve picosecond-level fine phase compensation, with a single tap delay step of 78ps. After the two-stage architecture works together, the overall phase shift resolution is no greater than 100ps. The system is equipped with a DDMTD (Digital Dual Mixer Phase Detector) to acquire the phase difference between the WR recovery clock and the high-stability fiber frequency signal in real time, forming a closed-loop dynamic correction path. This avoids the additional phase disturbances introduced by the frequent relocking of traditional single-stage phase shifting circuits, reduces the phase jitter of the WR synchronization clock, and improves the short-term stability of time synchronization. Furthermore, the system of this invention achieves single-fiber co-transmission of high-stability frequency carrier and WR time message through WDM wavelength division multiplexing. It utilizes the low-phase-noise, high-stability frequency output from the electrical frequency comb link to directly drive the WR synchronization clock, breaking the accuracy limitation of traditional WR relying solely on Ethernet to recover the clock, and ultimately realizing picosecond-level integrated time and frequency transmission over long-distance optical fibers.

[0082] The WR master-slave nodes and PTP synchronization logic of the system of this invention are fully compatible with existing White Rabbit application terminal equipment, and can directly upgrade existing WR synchronization networks, exhibiting excellent backward compatibility. According to one embodiment of the invention, the invention also provides a clock acquisition method for a White Rabbit application terminal, the method comprising: S1, connecting the White Rabbit application terminal to the slave-side frequency unit of the system of the invention, enabling the White Rabbit application terminal to acquire the calibrated clock output by the slave-side frequency unit; S2, the master-side frequency unit of the system generates a radio frequency carrier signal, compensates it, and transmits the compensated radio frequency carrier signal to the slave station through a single-fiber bidirectional optical fiber link; the master-side clock unit generates a 125MHz Ethernet reference clock and transmits it to the slave station through a single-fiber bidirectional optical fiber link. S3. The slave station-side frequency unit receives the radio frequency carrier signal from the master station-side frequency unit and transmits the radio frequency carrier signal as a high-stability frequency signal to the WR slave board. The slave station-side clock unit receives the 125MHz Ethernet reference clock from the master station-side clock unit and the high-stability frequency signal from the slave station-side frequency unit, and calibrates the 125MHz Ethernet reference clock according to the high-stability frequency signal to output the calibrated clock to the White Rabbit application terminal.

[0083] In summary, the present invention achieves efficient electrical domain compensation for phase noise in fiber optic links by using a compensation mechanism that combines the forward optical carrier driven by the master station's electrical frequency comb with the frequency return signal from the slave station to form an RF carrier signal. This effectively suppresses co-channel interference introduced by Rayleigh backscattering and connector reflection. Simultaneously, the slave station uses the highly stable signal recovered from frequency transmission as a reference, and through a closed-loop feedback mechanism consisting of a phase detection module, a filtering module, and a two-stage phase-shifting architecture of "coarse adjustment + fine adjustment," performs picosecond-level phase correction on the received clock signal, significantly reducing short-term jitter in the time synchronization link. Therefore, this invention solves the problems of large link reflection interference, weak phase noise suppression, and limited time synchronization accuracy in existing time-frequency fusion transmission schemes, achieving picosecond-level high-precision integrated time-frequency transmission over long-distance optical fibers, breaking through the nanosecond level and entering the picosecond level for clock synchronization accuracy. Therefore, the present invention has broad application prospects in scenarios with stringent requirements for short-term synchronization stability and link anti-reflection interference capabilities, such as atomic metrology, distributed radar collaborative detection, 5G / 6G base station synchronization, deep space telemetry and control, and synchronization of large scientific instruments.

[0084] It should be noted that although the steps are described in a specific order above, it does not mean that the steps must be executed in the above specific order. In fact, some of these steps can be executed concurrently, or even in a different order, as long as the required function can be achieved.

[0085] This invention can be a computer device, a computer program product, or a computer-readable storage medium. A computer program product primarily refers to a software product that implements this invention through a computer program. A computer-readable storage medium can be a tangible device that holds and stores instructions used by an instruction execution device. Computer-readable storage media can include, but are not limited to, electrical storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination thereof. More specific examples (a non-exhaustive list) of computer-readable storage media include: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital multifunction disc (DVD), memory sticks, floppy disks, mechanical encoding devices, such as punch cards or recessed protrusions storing instructions thereon, and any suitable combination thereof.

[0086] The above description is merely a preferred embodiment of the present invention. It should be understood that the present invention is not limited to the forms disclosed herein and should not be construed as excluding other embodiments. It can be used in various other combinations, modifications, and environments, and can be altered within the scope of the concept described herein through the above teachings or related technologies or knowledge. Modifications and variations made by those skilled in the art that do not depart from the spirit and scope of the present invention should be within the protection scope of the appended claims.

Claims

1. An optical time-frequency fusion transfer system based on an electrical frequency comb, characterized in that, The system includes a master station, a slave station, and a single-fiber bidirectional optical fiber link connecting the master station and the slave station, wherein: The master station includes a reference clock, a frequency transmission motherboard, a WR motherboard, a first optical circulator, and a first wavelength division multiplexer. The reference clock is connected to the frequency transmission motherboard, the frequency transmission motherboard is connected to the first optical circulator, and the first optical circulator is connected to the first wavelength division multiplexer to form a master station-side frequency unit. The reference clock is connected to the WR motherboard, and the WR motherboard is connected to the first wavelength division multiplexer to form a master station-side clock unit. The master station-side frequency unit is used to generate a radio frequency carrier signal, compensate it, and then transmit the compensated radio frequency carrier signal to the slave station through a single-fiber bidirectional optical fiber link. The master station-side clock unit is used to generate a 125MHz Ethernet reference clock and transmit it to the slave station through a single-fiber bidirectional optical fiber link. The slave station includes a frequency transmission slave board, a WR slave board, a second optical circulator, and a second wavelength division multiplexer. The frequency transmission slave board is connected to the second optical circulator, and the second optical circulator is connected to the second wavelength division multiplexer to form a slave-side frequency unit. The WR slave board is connected to the second wavelength division multiplexer to form a slave-side clock unit, and the frequency transmission slave board is connected to the WR slave board. The slave-side frequency unit is used to receive the radio frequency carrier signal from the master station-side frequency unit, and transmit the radio frequency carrier signal as a high-stability frequency signal to the WR slave board and then transmit it back to the frequency transmission main board after frequency division. The slave-side clock unit is used to receive the 125MHz Ethernet reference clock from the master station-side clock unit and the high-stability frequency signal from the slave-side frequency unit, and calibrate the 125MHz Ethernet reference clock according to the high-stability frequency signal to output the calibrated clock. The frequency transmission motherboard integrates an electrical frequency comb module, wherein the reference clock outputs a 10MHz reference clock signal, the electrical frequency comb module generates a 4GHz harmonic reference signal based on the 10MHz reference clock signal, the frequency transmission motherboard generates a phase error signal based on the 4GHz harmonic reference signal, the radio frequency carrier signal generated by the master station side frequency unit and the frequency-divided radio frequency carrier signal returned by the slave station side frequency unit, and the generated radio frequency carrier signal is compensated according to the phase error signal before being sent to the slave station; The WR slave board integrates an optimization logic module, which includes a phase detection module, a filtering module, and a phase shifting module. The phase detection module acquires the phase difference between the 125MHz Ethernet reference clock and the high-stability frequency signal received by the slave station. The filtering module receives the phase difference and filters it to generate a closed-loop control signal for adjusting the phase shifting module. The phase shifting module is configured with a logic controller, a phase-locked loop coarse adjuster, and a programmable delay unit. The logic controller receives the closed-loop control signal and generates coarse and fine adjustment control strategies accordingly. The phase-locked loop coarse adjuster includes a phase-locked loop and a 4-to-1 multiplexer, receiving the coarse adjustment control strategy and the 125MHz Ethernet reference clock, dividing one clock cycle of the 125MHz Ethernet reference clock into four equal-phase intervals, and selecting one of the four equal-phase intervals as the phase channel according to the coarse adjustment control strategy. The programmable delay unit is a programmable delay chain built into the FPGA, used to perform picosecond-level phase compensation on the selected phase channel according to the fine adjustment control strategy to obtain a calibrated clock.

2. The optical time-frequency fusion transfer system based on an electrical frequency comb according to claim 1, characterized in that, The frequency transmission motherboard also includes a voltage-controlled oscillator, a first mixer, a master station frequency divider, a first photodetector, a second mixer, a third mixer, a proportional-integral controller, and a first laser diode, wherein: The voltage-controlled oscillator is used to generate a radio frequency carrier signal and send it to the first mixer and the first laser diode; The first mixer is used to receive the radio frequency carrier signal and the 4GHz harmonic reference signal generated by the electrical frequency comb, and after mixing the two, it is sent to the main station frequency divider. The master station frequency divider is used to receive the signal sent by the first mixer and divide it to obtain the first difference frequency signal. The first photodetector is used to recover the frequency-divided radio frequency carrier signal returned from the station from the optical signal in the single-fiber bidirectional optical fiber link into an electrical signal, and send it into the second mixer. The second mixer is used to receive the electrical signal from the first photodetector and the 4GHz harmonic reference signal generated by the electrical frequency comb, and to mix the two to obtain the second difference frequency signal, which is then sent to the third mixer. The third mixer is used to receive the first difference frequency signal and the second difference frequency signal, and to perform mixing processing on the two to obtain a phase error signal, which is then sent to the proportional-integral controller. The proportional-integral controller is used to generate a control voltage based on the phase error signal, and the control voltage is used to drive the voltage-controlled oscillator to adjust the frequency of the radio frequency carrier signal. The first laser diode is used to generate a corresponding optical carrier for the radio frequency carrier signal.

3. The optical time-frequency fusion transfer system based on an electrical frequency comb according to claim 2, characterized in that, The proportional-integral controller continuously adjusts the frequency of the radio frequency carrier signal by generating a control voltage to regulate the voltage-controlled oscillator until the system enters a locked state, which satisfies the following frequency constraint relationship: ； ； in, This represents the frequency of the radio frequency carrier signal generated by the voltage-controlled oscillator. The frequency representing the 4GHz harmonic reference signal, This represents the frequency of the frequency-divided radio frequency carrier signal transmitted back from the slave station.

4. The optical time-frequency fusion transfer system based on an electrical frequency comb according to claim 2, characterized in that, The master station frequency divider divides the signal from the first mixer by four to obtain the first difference frequency signal. The slave station frequency unit divides the RF carrier signal from the master station frequency unit by four and then sends it back to the frequency transmission main board.

5. The optical time-frequency fusion transfer system based on an electrical frequency comb according to claim 1, characterized in that, The WR motherboard includes a phase-locked loop (PLL) and a White Rabbit Precision Time Protocol (BRT) core. The PLL is used to acquire a 10MHz reference clock signal and multiply it to a 125MHz Ethernet reference clock. The BRT core is used to acquire a 125MHz Ethernet reference clock and transmit it to the slave station via a single-fiber bidirectional optical fiber link. It also uses the 125MHz Ethernet reference clock as a timestamp and a servo synchronization reference.

6. The optical time-frequency fusion transfer system based on an electrical frequency comb according to claim 1, characterized in that, The single-fiber bidirectional optical fiber link transmits optical carriers with three wavelengths: 1550nm, 1470nm, and 1490nm. The 1550nm optical carrier carries the radio frequency carrier signal sent from the master station to the slave station; the 1470nm optical carrier carries the 125MHz Ethernet reference clock sent from the master station to the slave station; and the 1490nm optical carrier carries the frequency-divided radio frequency carrier signal sent from the slave station to the master station.

7. The optical time-frequency fusion transfer system based on an electrical frequency comb according to claim 1, characterized in that, The phase detection module uses a DDMTD digital dual-mixer time difference measurement unit, and its phase measurement resolution is ≤100ps.

8. The optical time-frequency fusion transfer system based on an electrical frequency comb according to claim 1, characterized in that, The programmable delay unit is IDELAYE2, which is an IOB hardware primitive built into the Xilinx 7 series FPGA.

9. A method for obtaining a clock for a White Rabbit application terminal, characterized in that, The method includes: S1. Connect the White Rabbit application terminal to the slave-side frequency unit of the system as described in any one of claims 1-8, so that the White Rabbit application terminal can obtain the calibrated clock output by the slave-side frequency unit. S2. The master station-side frequency unit of the system generates a radio frequency carrier signal and compensates it, then transmits the compensated radio frequency carrier signal to the slave station through a single-fiber bidirectional optical fiber link. The master station-side clock unit generates a 125MHz Ethernet reference clock and transmits it to the slave station through a single-fiber bidirectional optical fiber link. S3. The slave station-side frequency unit receives the radio frequency carrier signal from the master station-side frequency unit and transmits the radio frequency carrier signal as a high-stability frequency signal to the WR slave board. The slave station-side clock unit receives the 125MHz Ethernet reference clock from the master station-side clock unit and the high-stability frequency signal from the slave station-side frequency unit, and calibrates the 125MHz Ethernet reference clock according to the high-stability frequency signal to output the calibrated clock to the White Rabbit application terminal.

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