Photovoltaic power station time correction system, photovoltaic power station time correction method and inverter

Abstract

The application discloses a photovoltaic power station time correction system, a photovoltaic power station time correction method and an inverter, and belongs to the technical field of photovoltaic power stations. The system comprises a time-providing device, a data collector, a PLC master node, a PLC slave node and an inverter with a first processing core and a second processing core. The time-providing device provides an original reference time; the data collector, the PLC master node and the first processing core respectively determine first, second and third delay compensation amounts; the PLC slave node determines a frequency offset compensation amount according to the receiving time of a plurality of PLC beacon frames and a theoretical beacon period; and the second processing core determines a correction time according to the original reference time and each compensation amount added step by step and updates a local system clock. The application can improve the time correction accuracy of the inverter by compensating for multi-stage delays and crystal oscillator frequency offsets in the time correction information transmission process.

Description

Technical Field

[0001] This application belongs to the field of photovoltaic power station technology, and in particular relates to a photovoltaic power station time synchronization system, a photovoltaic power station time synchronization method and an inverter. Background Technology

[0002] As photovoltaic power plants continue to expand in scale, a large number of inverters are typically installed within them. To meet the needs of operational data acquisition, fault event recording, power dispatch, and equipment coordinated control, it is necessary for all inverters to operate according to a unified time base.

[0003] Existing photovoltaic power plants typically use network time synchronization to send a reference time to each inverter to update the inverter's local system clock. Due to factors such as the power plant's communication network hierarchy, communication environment, and equipment processing capabilities, communication and processing delays may occur during the transmission and forwarding of time synchronization information. Simultaneously, the local crystal oscillators on the inverter side may have frequency offsets, causing cumulative deviations in the local system clock between adjacent time synchronization cycles.

[0004] Existing time synchronization methods are unable to effectively compensate for the multi-level delays and local crystal oscillator frequency offsets generated during the transmission of time synchronization information, resulting in a deviation between the inverter's local system clock and the reference time, which makes it difficult to meet the high-precision time synchronization requirements of photovoltaic power plants. Summary of the Invention

[0005] This application aims to address at least one of the technical problems existing in the prior art. To this end, this application proposes a photovoltaic power station time synchronization system, a photovoltaic power station time synchronization method, and an inverter to compensate for the multi-level delays and local crystal oscillator frequency offsets generated during the time synchronization information transmission process, thereby improving the time synchronization accuracy of the inverter's local system clock.

[0006] In a first aspect, this application provides a photovoltaic power station time synchronization system, which includes a time synchronization device, a data acquisition unit, a PLC master node, a PLC slave node, and an inverter, wherein the inverter includes a first processing core and a second processing core; The timing device is used to provide the original reference time to the data acquisition unit; The data acquisition device is used to determine the first delay compensation amount corresponding to the processing and transmission of the time synchronization information, and to send the first time synchronization information carrying the original reference time and the first delay compensation amount to the PLC master node; The PLC master node is used to determine the second delay compensation amount at the time of sending the PLC beacon frame after receiving the first time synchronization information, and encapsulate the original reference time, the first delay compensation amount and the second delay compensation amount in the reserved field of the PLC beacon frame and broadcast it. The PLC slave node is used to determine the frequency offset compensation amount based on the reception time of multiple PLC beacon frames and the theoretical beacon period, and append the frequency offset compensation amount to the time synchronization information extracted from the PLC beacon frames to obtain the second time synchronization information and send it to the first processing core; The first processing core is used to determine the third delay compensation amount, append the third delay compensation amount to the second time synchronization information, obtain the third time synchronization information, and send it to the second processing core; The second processing core is used to determine the correction time based on the original reference time in the third time synchronization information and the gradually added compensation amount, and to update the local system clock based on the correction time; The original reference time remains unchanged during transmission, and the first delay compensation amount, the second delay compensation amount, the frequency offset compensation amount, and the third delay compensation amount are added step by step.

[0007] Secondly, this application provides a method for synchronizing the time of a photovoltaic power station, the method comprising: The first delay compensation amount is determined by the data acquisition device, and the first time synchronization information carrying the original reference time and the first delay compensation amount provided by the time synchronization device is sent to the PLC master node. After receiving the first time synchronization information, the PLC master node determines the second delay compensation amount at the time of sending the PLC beacon frame, encapsulates the original reference time, the first delay compensation amount and the second delay compensation amount in the reserved field of the PLC beacon frame and broadcasts them. The frequency offset compensation amount is determined by the PLC slave node based on the reception time of multiple PLC beacon frames and the theoretical beacon period. The frequency offset compensation amount is added to the time synchronization information extracted from the PLC beacon frames to obtain the second time synchronization information and send it to the first processing core of the inverter. The third delay compensation amount is determined by the first processing core, and the third delay compensation amount is added to the second time synchronization information to obtain the third time synchronization information and send it to the second processing core of the inverter. The second processing core determines the correction time based on the original reference time, first delay compensation amount, second delay compensation amount, third delay compensation amount and frequency offset compensation amount in the third time synchronization information, and updates the local system clock based on the correction time; The original reference time remains unchanged during transmission, and the first delay compensation amount, the second delay compensation amount, the frequency offset compensation amount, and the third delay compensation amount are added step by step.

[0008] Thirdly, this application provides an inverter, which includes a PLC slave node, a first processing core, and a second processing core. The PLC slave node is used to extract the original reference time, a first delay compensation amount, and a second delay compensation amount from received PLC beacon frames, determine the frequency offset compensation amount based on the reception time of multiple PLC beacon frames and the theoretical beacon period, and add the frequency offset compensation amount to obtain second time synchronization information and send it to the first processing core. The first processing core is used to determine a third delay compensation amount corresponding to the processing and transmission process of the second time synchronization information, add the third delay compensation amount to obtain third time synchronization information, and send it to the second processing core. The second processing core is used to determine the correction time based on the original reference time in the third time synchronization information and each compensation amount added step by step, and update the local system clock based on the correction time.

[0009] Fourthly, this application provides an electronic device, which includes a processor, a memory, and a computer program stored in the memory and capable of running on the processor. When the computer program is executed by the processor, it implements the processing procedure corresponding to the electronic device in the photovoltaic power station time synchronization method.

[0010] The above-described one or more technical solutions in the embodiments of this application have at least one of the following technical effects: The original reference time is provided to the data acquisition unit via a time synchronization device, providing a unified time calibration reference for all inverters in the photovoltaic power station. The data acquisition unit determines a first delay compensation amount during the processing and transmission of time calibration information, and sends this first delay compensation amount along with the original reference time to the PLC master node, thereby compensating for the time overhead incurred by the time synchronization information on the data acquisition unit side. The PLC master node determines a second delay compensation amount when the PLC beacon frame is transmitted, and broadcasts the original reference time, the first delay compensation amount, and the second delay compensation amount using a reserved field in the PLC beacon frame. This allows the time calibration information to be sent to the PLC slave nodes along with the PLC beacon frame, and... The time overhead incurred by the PLC master node during processing, waiting, and transmission is compensated. Based on this, the PLC slave node determines the frequency offset compensation amount according to the reception time of multiple PLC beacon frames and the theoretical beacon period, which can compensate for the cumulative time deviation caused by the local crystal oscillator frequency offset. The first processing core further determines the third delay compensation amount and adds it to the second time synchronization information, which can compensate for the time overhead incurred during the processing and transmission of the time synchronization information within the inverter. The second processing core comprehensively determines the correction time and updates the local system clock by integrating the original reference time and the progressively added compensation amounts, so that the correction time can reflect the time deviation of the time synchronization information in each level of nodes and communication links. Simultaneously, the original reference time remains unchanged during transmission, and each compensation amount is added progressively, maintaining a unified time reference and retaining compensation information at each level. This reduces the impact of multi-level transmission delays and local crystal oscillator frequency offset on the time synchronization results, improving the time synchronization accuracy of the inverter in the photovoltaic power plant.

[0011] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0012] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which: Figure 1 This is a schematic diagram of the structure of the photovoltaic power station time synchronization system provided in the embodiments of this application; Figure 2 This is a schematic diagram of the time synchronization process of the PLC master node provided in the embodiment of this application; Figure 3 This is a schematic diagram of the time synchronization process of the PLC slave node provided in the embodiment of this application; Figure 4 This is a schematic flowchart of the photovoltaic power station time synchronization method provided in the embodiments of this application; Figure 5 This is a schematic diagram of the structure of the electronic device provided in the embodiments of this application. Detailed Implementation

[0013] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. The described embodiments are some, but not all, embodiments of this application. Other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are all within the protection scope of this application.

[0014] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects, not to describe a specific order or sequence. It should be understood that such terms can be used interchangeably where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein; the objects distinguished by "first," "second," etc., are generally of the same class and do not limit the number of objects; for example, a first object can be one or more. Furthermore, "and / or" in the specification and claims indicates at least one of the connected objects, and the character " / " generally indicates an "or" relationship between the preceding and following related objects.

[0015] The operation of a photovoltaic (PV) power plant relies on a unified time base for all equipment to ensure the accuracy and reliability of data acquisition, fault recording, sequence of events (SOE), and power dispatching. PV power plants can use various time synchronization methods, including Ethernet Network Time Protocol (NTP), Global Positioning System (GPS) or BeiDou independent time synchronization, LoRa wireless time synchronization, RS485 wired time synchronization, and Power Line Communication (PLC). Among these, PLC communication can reuse existing power cables, eliminating the need for additional communication lines, and is adaptable to the electromagnetic interference environment of PV power plants, making it suitable for communication between string inverters and intelligent subarray controllers.

[0016] In one PLC carrier time synchronization process, the station-level NTP time server provides a reference time. The data acquisition unit (SAU) in the intelligent subarray controller acquires this reference time and sends it to the PLC master node (Central Coordinator, CCO). The PLC master node broadcasts time messages to each PLC slave node (Station, STA) through the PLC service channel. The PLC slave nodes forward the received time messages to the corresponding inverters, which then update their local system clocks based on the received time messages. This process transmits independent synchronization messages through the PLC service channel, failing to utilize the periodic broadcasting and network synchronization characteristics of PLC beacon frames, and also failing to compensate for the delays caused by the time synchronization information passing through various nodes and communication links.

[0017] Specifically, the process of transmitting time synchronization information from the data acquisition unit to the inverter's local system clock involves message processing and serial transmission by the data acquisition unit, message processing and PLC carrier transmission by the PLC master node, and data processing and transmission between the first and second processing cores within the inverter. The time overhead generated at each of these stages accumulates progressively, potentially leading to time synchronization errors on the order of milliseconds or even seconds. This causes the actual time when the inverter updates its local system clock to deviate from the station-level reference time, making it difficult to meet the microsecond-level time accuracy requirements of services such as SOE and fault recording.

[0018] Furthermore, transmitting independent synchronization messages via the PLC service channel requires occupying service data time slots, which may increase the probability of transmission conflicts between synchronization messages and service data, thereby affecting the reliability of service data transmission. The local crystal oscillator of the PLC slave node may also have a physical frequency offset. If this frequency offset is not compensated for based on the periodic reception of PLC beacon frames, a continuously accumulating time error may occur between adjacent synchronization periods.

[0019] Meanwhile, the lack of a unified time synchronization information format and register mapping relationship between different nodes may lead to inconsistent parsing methods for time and compensation fields by different devices, increasing the difficulty of device integration and maintenance. If the receiving end of the time synchronization information lacks a unified mechanism for cyclic redundancy check, function code check, register address check, and standard error code handling, abnormal message transmission or parsing may also cause time synchronization failure and increase the difficulty of anomaly localization.

[0020] Based on this, this application provides a photovoltaic power station time synchronization system that transmits the original reference time through PLC beacon frames and adds delay compensation at each level for the processing and transmission processes corresponding to the data acquisition unit, PLC master node, and inverter internal processing core. At the same time, the frequency offset compensation is determined based on the reception time of multiple PLC beacon frames and the theoretical beacon period, so as to reduce the impact of multi-level transmission delay and local crystal oscillator frequency offset on the time synchronization result and improve the time synchronization accuracy of the inverter's local system clock.

[0021] like Figure 1 As shown in the embodiment of this application, the photovoltaic power station time synchronization system includes a station-level NTP time synchronization server, an intelligent subarray controller, and one or more inverters. The station-level NTP time synchronization server serves as a time synchronization device, providing the original UTC reference time. The intelligent subarray controller includes a data acquisition unit (SAU) and a PLC master node (CCO). Each inverter includes a PLC slave node (STA), an Advanced RISC Machines (ARM) core, and a Digital Signal Processor (DSP) core, wherein the ARM core serves as the first processing core and the DSP core serves as the second processing core.

[0022] The station-level NTP time synchronization server and the data acquisition unit (SAU) are connected via Ethernet, enabling the SAU to receive time synchronization messages sent by the station-level NTP time synchronization server. The SAU is connected to the PLC master node (CCO) via a Universal Asynchronous Receiver / Transmitter (UART) serial communication link. The PLC master node (CCO) is connected to each PLC slave node (STA) via a power line carrier communication link. The PLC slave nodes (STA) are connected to the ARM core via a UART serial communication link, and the ARM core is connected to the DSP core via an internal communication bus. The UART serial communication links between the SAU and the PLC master node (CCO), and between the PLC slave nodes (STA) and the ARM core, use an industrial-grade RS485 physical interface. The existing power cables of the photovoltaic power station are reused as the PLC carrier transmission medium between the PLC master node (CCO) and the PLC slave nodes (STA).

[0023] Figure 1 The example uses the Serial Peripheral Interface (SPI) bus as an internal communication bus between the ARM core and the DSP core. In other embodiments, the External Memory Interface (EMIF) or other internal communication buses capable of handling data transfer between cores may also be used.

[0024] In this embodiment, the data flow is transmitted hierarchically from top to bottom. The station-level NTP time synchronization server serves as the unified time source for the entire station, sending standard NTP reference time messages to the data acquisition unit (SAU) via the Ethernet TCP / IP network to provide UTC standard time; the accuracy of this raw UTC reference time can reach the millisecond level, for example, ±1 millisecond. After the data acquisition unit (SAU) parses and extracts the original reference time, it adds a first delay compensation amount T1. After the PLC master node (CCO) verifies and caches the corresponding time synchronization information, it adds a second delay compensation amount T2 and broadcasts it to all PLC slave nodes (STA) via a beacon frame when the PLC beacon cycle of no more than 10 seconds arrives. The PLC slave nodes (STA) parse the beacon frame, determine the frequency offset compensation amount Δt, and send it to the ARM core in a single transmission via the UART serial port without waiting for a response. After the ARM core parses the time synchronization information and adds a third delay compensation amount T3, it sends the complete time synchronization information, including T0, T1, T2, Δt, and T3, to the DSP core via SPI, EMIF, or other internal high-speed buses. The DSP core updates its local system clock accordingly, completing the unified time synchronization of all devices in the station.

[0025] Specifically, the station-level NTP time synchronization server provides the raw reference time to the data acquisition unit (SAU). After receiving the time authorization message, the data acquisition unit (SAU) determines the first delay compensation amount corresponding to the time authorization message parsing, delay calculation, time synchronization information encapsulation, and UART transmission process, and sends the first time synchronization information to the PLC master node (CCO) via the UART serial communication link. The first time synchronization information carries the raw reference time and the first delay compensation amount.

[0026] After receiving the first time synchronization information, the PLC master node CCO verifies, parses, and caches the information, and waits for the PLC beacon frame to be sent. When the PLC beacon frame transmission opportunity arrives, the PLC master node CCO determines the second delay compensation amount corresponding to the verification, parsing, caching, and waiting for the PLC beacon frame transmission, as well as the PLC beacon frame encapsulation and transmission process. It then encapsulates the original reference time, the first delay compensation amount, and the second delay compensation amount into the reserved fields of the PLC beacon frame and broadcasts the PLC beacon frame to each PLC slave node STA via the power line carrier communication link.

[0027] After receiving a PLC beacon frame from the STA (Slave Node), the PLC extracts the original reference time, the first delay compensation amount, and the second delay compensation amount from the reserved fields of the PLC beacon frame. Simultaneously, the STA records the reception time of the PLC beacon frame and determines the local crystal oscillator frequency offset based on the reception times of multiple PLC beacon frames and the theoretical beacon period, thereby determining the frequency offset compensation amount. The STA appends the frequency offset compensation amount to the extracted time synchronization information to obtain the second time synchronization information, and then sends the second time synchronization information to the ARM core via the UART serial communication link.

[0028] After receiving the second time synchronization information, the ARM core determines the third delay compensation amount corresponding to the parsing, delay calculation, encapsulation, and internal communication bus transmission processes of the second time synchronization information. It then appends the third delay compensation amount to the second time synchronization information to obtain the third time synchronization information, and sends the third time synchronization information to the DSP core through internal communication buses such as the SPI bus.

[0029] After receiving the third time synchronization information, the DSP core determines the correction time based on the original reference time, the first delay compensation amount, the second delay compensation amount, the frequency offset compensation amount, and the third delay compensation amount in the third time synchronization information, and updates the inverter's local system clock according to the correction time. During the above time synchronization information transmission process, the original reference time remains unchanged, and each node adds the corresponding compensation amount to the time synchronization information step by step, so that the DSP core can comprehensively compensate for the time deviation generated when the time synchronization information passes through the data acquisition unit SAU, the PLC master node CCO, the PLC slave node STA, and the ARM core.

[0030] For ease of explanation, the original UTC reference time provided by the station-level NTP time synchronization server is denoted as T0, the first delay compensation amount determined by the data acquisition unit is denoted as T1, the second delay compensation amount determined by the PLC master node is denoted as T2, and the third delay compensation amount determined by the ARM core is denoted as T3. T0 remains unchanged during transmission, while T1, T2, the frequency offset compensation amount Δt, and T3 are added step by step according to the time synchronization link.

[0031] The first delay compensation amount T1, the second delay compensation amount T2, and the third delay compensation amount T3 are used to compensate for the positive time overhead generated by each link. The frequency offset compensation amount Δt takes a positive or negative value according to the offset direction of the local crystal oscillator to indicate increased compensation or reverse deduction. The DSP core obtains the correction time based on T0, T1, T2, T3, and Δt.

[0032] For example, the correction time ultimately determined by the DSP core is Then the end-point uniform correction relationship can be expressed as:

[0033] Where T0 is the original UTC reference time provided by the station-level NTP time synchronization server, and in one configuration, the absolute value of its reference error is no greater than 1ms; T1 is the first delay compensation amount; T2 is the second delay compensation amount; T3 is the third delay compensation amount; Δt is the frequency offset compensation amount of the STA local crystal oscillator.

[0034] Therefore, each intermediate node does not rewrite T0 using local time, but only adds the corresponding delay data or frequency offset compensation value, and the DSP core completes a unified correction at the end of the time synchronization link. This can avoid the accumulation of errors caused by multiple corrections by intermediate nodes, reduce the computational complexity of intermediate nodes, and improve system reliability.

[0035] The photovoltaic power station time synchronization system provided in this application embodiment provides the original reference time to the data acquisition unit through the time synchronization device, providing a unified time synchronization reference for each inverter in the photovoltaic power station. The data acquisition unit determines a first delay compensation amount during the processing and transmission of time synchronization information, and sends the first delay compensation amount and the original reference time together to the PLC master node, thereby compensating for the time overhead incurred by the time synchronization information on the data acquisition unit side. The PLC master node determines a second delay compensation amount when the PLC beacon frame is transmitted, and uses the reserved field of the PLC beacon frame to carry the original reference time, the first delay compensation amount and the second delay compensation amount for broadcasting, so that the time synchronization information can be sent down with the PLC beacon frame. The PLC slave node compensates for the time overhead incurred by the PLC master node in processing, waiting, and transmitting data. Based on this, the PLC slave node determines the frequency offset compensation amount according to the reception time of multiple PLC beacon frames and the theoretical beacon period, which can compensate for the cumulative time deviation caused by the local crystal oscillator frequency offset. The first processing core further determines the third delay compensation amount and adds it to the second time synchronization information, which can compensate for the time overhead incurred by the time synchronization information in the inverter's internal processing and transmission. The second processing core integrates the original reference time and the progressively added compensation amounts to determine the correction time and update the local system clock, so that the correction time can reflect the time deviation of the time synchronization information in each level of nodes and communication links. Simultaneously, the original reference time remains unchanged during transmission, and each compensation amount is added progressively, maintaining a unified time reference and retaining the compensation information at each level. This reduces the impact of multi-level transmission delays and local crystal oscillator frequency offset on the time synchronization results, improving the time synchronization accuracy of the inverter in the photovoltaic power plant.

[0036] In some embodiments, the data collector is used to record the moment when it receives the timing message sent by the timing device and triggers the reception completion interrupt through a local hardware timer; the first delay compensation amount is used to compensate for the time overhead incurred by the data collector from receiving the timing message to sending the first time synchronization information. The time overhead includes the time consumed by parsing the timing message, the time consumed by delay calculation, the time consumed by encapsulating the first time synchronization information, and the transmission time consumed by sending the first time synchronization information through the serial communication link.

[0037] The data acquisition unit receives the time signal sent by the station-level NTP time synchronization server via Ethernet. The time signal carries the original reference time. When the data acquisition unit fully receives the time signal and triggers a reception completion interrupt, it records the time corresponding to the reception completion interrupt through a local hardware timer, and uses this time as the starting point for delay compensation on the data acquisition unit side.

[0038] In some embodiments, the data acquisition unit, PLC master node and ARM core are each equipped with a hardware high-precision timer with a resolution of 1 microsecond. The delay measurement at each level is triggered by the message reception completion interrupt and the transmission completion interrupt. The corresponding time difference is determined by the hardware timestamp to reduce the impact of software task scheduling and instruction execution jitter on the delay measurement and realize the microsecond-level quantization of the delay at each level.

[0039] After receiving the time signal, the data acquisition unit parses the signal, extracts the original reference time, and performs the determination of the first delay compensation amount, the encapsulation of the first time synchronization information, and the transmission of the first time synchronization information. The first time synchronization information can be a Modbus-RTU frame and is transmitted to the PLC master node via the UART serial communication link. The time overhead corresponding to the first delay compensation amount includes the time spent parsing the signal signal, the delay calculation time spent determining the first delay compensation amount, the encapsulation time spent encapsulating the original reference time and the first delay compensation amount into the first time synchronization information, and the transmission time spent sending the first time synchronization information via the UART serial communication link.

[0040] From the perspective of the complete quantification of the first link delay, the data acquisition unit takes the moment when the timing message reception completion interruption occurs as the first start moment and the moment when the Modbus-RTU frame transmission is completed and triggers the transmission completion interruption as the first end moment. The difference between the two is the measured value of the complete link delay on the data acquisition unit side. This complete measured value includes the total time overhead of timing message parsing, delay calculation, frame encapsulation, and UART serial transmission, and is used to calibrate the first delay compensation amount T1 for subsequent timing cycles.

[0041] It should be noted that the first time synchronization information, PLC beacon frame, and third time synchronization information must all carry the corresponding delay compensation amount before the transmission at this level is completed, while the complete transmission time can only be obtained after transmission is completed. To solve this timing problem, each node can add the currently occurring processing time to the estimated transmission time determined based on the frame length, communication parameters, and historical complete measured values, as the delay compensation amount carried in the current cycle; after transmission is completed, the estimated transmission time or compensation parameters used in subsequent cycles are calibrated using the current complete measured value. Thus, the delay compensation amount carried in the current cycle is distinguishable from the complete measured value obtained after transmission is completed.

[0042] By using a local hardware timer to record the timing start point when the timer message reception is interrupted, the impact of factors such as software task scheduling on the timing start point can be reduced. By compensating for the time overhead caused by timer message parsing, delay calculation, time synchronization information encapsulation and serial transmission through the first delay compensation amount, the impact of data acquisition side processing and transmission delay on the accuracy of the original reference time transmission can be reduced, providing a more accurate time basis for subsequent level-by-level delay compensation.

[0043] In some embodiments, the PLC master node is used to record the moment when the first time synchronization information is received and the reception completion interrupt is triggered by a local hardware timer; the second delay compensation amount is used to compensate for the time overhead incurred by the PLC master node from receiving the first time synchronization information to sending the PLC beacon frame. The time overhead includes the time consumed by verifying and parsing the first time synchronization information, the buffering time, the waiting time for the PLC beacon frame to be sent, the encapsulation time of the PLC beacon frame, and the transmission time of sending the PLC beacon frame through the power line carrier communication link.

[0044] The PLC master node receives the first time synchronization information sent by the data acquisition unit via the UART serial communication link. The first time synchronization information can be a Modbus-RTU frame, carrying the original reference time and the first delay compensation amount. When the PLC master node fully receives the first time synchronization information and triggers a reception completion interrupt, it records the time corresponding to the reception completion interrupt through a local hardware timer, and uses this time as the timing start point for delay compensation on the PLC master node side.

[0045] After receiving the first time synchronization information, the PLC master node verifies and parses it to extract the original reference time and the first delay compensation amount. The verified first time synchronization information is then cached in its local storage area. Since PLC beacon frames are sent according to a preset beacon cycle, after completing the verification, parsing, and caching of the first time synchronization information, the PLC master node waits for the next PLC beacon frame to be sent. When this transmission opportunity arrives, the PLC master node determines the second delay compensation amount, encapsulates the original reference time, the first delay compensation amount, and the second delay compensation amount into a reserved field in the PLC beacon frame, and broadcasts the PLC beacon frame to all PLC slave nodes via the power line carrier communication link.

[0046] The time overhead corresponding to the second delay compensation includes the time consumed by the PLC master node in verifying and parsing the first time synchronization information, the time consumed in caching the first time synchronization information, the waiting time consumed from the receipt of the completion information to the arrival of the PLC beacon frame transmission opportunity, the time consumed in encapsulating the time synchronization information into the PLC beacon frame, and the transmission time consumed in sending the PLC beacon frame through the power line carrier communication link. The waiting time for the PLC beacon frame transmission opportunity may vary depending on the reception time of the first time synchronization information; therefore, including this waiting time in the second delay compensation can compensate for the dynamic time deviation introduced by the PLC beacon cycle.

[0047] From the perspective of the complete quantification of the second link delay, the PLC master node takes the moment when the first time synchronization information reception completion interruption occurs as the second start time, and the moment when the PLC beacon frame broadcast transmission completion and trigger transmission completion interruption occurs as the second end time. The difference between the two is the measured value of the complete link delay on the PLC master node side. This complete measured value includes the total time overhead of the first time synchronization information verification and parsing, information buffering, beacon waiting period, beacon frame encapsulation, and power line carrier transmission.

[0048] According to the above determination method, before the beacon frame is sent, the PLC master node determines the second delay compensation amount T2 carried in the current beacon frame based on the verification, parsing, buffering and waiting time that has occurred from the second start time to the current encapsulation time, as well as the expected encapsulation and carrier transmission time calibrated by the historical complete measured value; after the transmission is completed, the second delay compensation amount of the subsequent beacon cycle is calibrated based on the current complete measured value.

[0049] By using a local hardware timer to record the timing start point when the first time synchronization information reception is interrupted, the impact of software scheduling and task switching on delay measurement can be reduced. The second delay compensation amount compensates for the time overhead caused by information verification and parsing, buffering, beacon waiting, beacon frame encapsulation and carrier transmission, especially reducing the impact of beacon waiting time changes on time synchronization accuracy, thereby improving the time accuracy of time synchronization information transmitted through the PLC master node and power line carrier communication link.

[0050] In some embodiments, the first processing core is used to record the moment when the second time synchronization information is received and the reception completion interrupt is triggered by a local hardware timer; the third delay compensation amount is used to compensate for the time overhead incurred from the time the first processing core receives the second time synchronization information to the time it sends the third time synchronization information to the second processing core. The time overhead includes the parsing time of the second time synchronization information, the delay calculation time, the encapsulation time of the third time synchronization information, and the transmission time of sending the third time synchronization information through the internal communication bus.

[0051] The PLC slave node sends the second time synchronization information to the ARM core via the UART serial communication link. The second time synchronization information can be a Modbus-RTU frame, carrying the original reference time, the first delay compensation amount, the second delay compensation amount, and the frequency offset compensation amount. When the ARM core fully receives the second time synchronization information and triggers a receive completion interrupt, it records the time corresponding to the receive completion interrupt through a local hardware timer, and uses this time as the starting point for the inverter's internal processing of inter-core delay compensation.

[0052] After receiving the second time synchronization information, the ARM core parses it, extracts the original reference time and various compensation values, and determines the third delay compensation value. Subsequently, the ARM core appends the third delay compensation value to the second time synchronization information, encapsulates the original reference time, the first delay compensation value, the second delay compensation value, the frequency offset compensation value, and the third delay compensation value to obtain the third time synchronization information, which is then sent to the DSP core via the internal communication bus. The internal communication bus can be a Serial Peripheral Interface (SPI) bus, or other communication buses within the inverter that enable data transmission between the ARM core and the DSP core.

[0053] The time overhead corresponding to the third delay compensation amount includes the time consumed by the ARM core in parsing the second time synchronization information, the delay calculation time consumed in determining the third delay compensation amount, the time consumed in encapsulating the third time synchronization information, and the transmission time consumed in sending the third time synchronization information to the DSP core through the internal communication bus. After receiving the third time synchronization information, the DSP core determines the correction time based on the original reference time and the compensation amounts added step by step in the third time synchronization information, and updates the inverter's local system clock based on the correction time.

[0054] From the perspective of a complete quantification of the third link delay, the ARM core takes the moment when the second time synchronization information reception interrupt is completed as the third start moment, and the moment when the third time synchronization information is completed and transmitted through the internal communication bus as the third end moment. The difference between the two is the complete inter-core delay measurement value between the ARM core and the DSP core. This complete measurement value includes the total time overhead of second time synchronization information parsing, delay calculation, third time synchronization information encapsulation, and internal communication bus transmission.

[0055] According to the above determination method, before the third time synchronization information is sent, the ARM core determines the third delay compensation amount T3 carried by the current third time synchronization information based on the processing time that has occurred from the third start time to the current packaging time and the expected internal communication bus transmission time calibrated by the historical complete measured value; after the transmission is completed, the third delay compensation amount of the subsequent cycle is calibrated based on the current complete measured value.

[0056] By using a local hardware timer to record the timing start point when the second time synchronization information reception is interrupted, the impact of ARM core software scheduling and task switching on delay measurement can be reduced. By compensating for the time overhead generated by parsing the second time synchronization information, calculating the delay, encapsulating the third time synchronization information, and transmitting the internal communication bus through the third delay compensation amount, the impact of data processing and transmission delays between the inverter's internal processing cores on the time synchronization result can be reduced, enabling the DSP core to obtain a more accurate correction time.

[0057] In some embodiments, the PLC slave node is configured to: record the first beacon reception time and the second beacon reception time corresponding to the first PLC beacon frame and the second PLC beacon frame received consecutively; determine the actual beacon interval based on the first beacon reception time and the second beacon reception time; determine the local crystal oscillator frequency offset based on the deviation between the actual beacon interval and the theoretical beacon period and the theoretical beacon period; and determine the frequency offset compensation amount based on the local crystal oscillator frequency offset and the running time elapsed since the previous PLC beacon frame was received.

[0058] The PLC master node broadcasts PLC beacon frames according to a preset theoretical beacon cycle, and the PLC slave node continuously receives PLC beacon frames via a power line carrier communication link. When a PLC slave node receives the first PLC beacon frame, it records the first beacon reception time corresponding to that first PLC beacon frame; when it receives the second PLC beacon frame adjacent to the first PLC beacon frame, it records the second beacon reception time corresponding to that second PLC beacon frame. The first and second beacon reception times can be recorded by the local hardware timer of the PLC slave node.

[0059] The PLC calculates the time difference between the second beacon reception time and the first beacon reception time from the slave node to obtain the actual beacon interval. Let the first beacon reception time be... The second beacon reception time is The theoretical beacon period is The actual beacon interval ΔT can then be expressed as:

[0060] The PLC compares the actual beacon interval ΔT with the theoretical beacon period from the node and determines the local crystal oscillator frequency offset based on the deviation between the two. In one example, the local crystal oscillator frequency offset δ can be expressed as:

[0061] Among them, the theoretical beacon cycle The default value is 10,000,000 microseconds, or 10 seconds; let the running time elapsed since the previous PLC beacon frame was received be... The frequency offset compensation amount is:

[0062] Δt is added as a signed compensation value to the time synchronization information, and its compensation direction is determined according to the speed of the local crystal oscillator.

[0063] When the actual beacon interval is greater than the theoretical beacon period, it indicates that the time interval recorded by the PLC slave node based on the local crystal oscillator is too large; when the actual beacon interval is less than the theoretical beacon period, it indicates that the time interval recorded by the PLC slave node based on the local crystal oscillator is too small. Therefore, the sign of the local crystal oscillator frequency offset can reflect the offset direction of the local system clock relative to the PLC beacon period, and its absolute value can reflect the corresponding degree of offset.

[0064] After determining the local crystal oscillator frequency offset, the PLC slave node records the elapsed running time since receiving the previous PLC beacon frame, and determines the frequency offset compensation amount based on the local crystal oscillator frequency offset and this running time. The absolute value of the frequency offset compensation amount Δt is determined by multiplying the absolute value of the local crystal oscillator frequency offset by the running time, and its sign is opposite to that of the local crystal oscillator frequency offset: when the local system clock runs faster than the theoretical beacon period, Δt takes a negative value to deduct the accumulated time deviation in reverse; when the local system clock runs slower, Δt takes a positive value to increase the corresponding compensation.

[0065] The PLC adds the determined frequency offset compensation amount to the original reference time, the first delay compensation amount, and the second delay compensation amount extracted from the PLC beacon frame to obtain the second time synchronization information. The second time synchronization information is then sent to the first processing core so that the second processing core can compensate for the time accumulation deviation caused by the local crystal oscillator frequency offset when determining the correction time.

[0066] By utilizing the periodic broadcasting characteristics of PLC beacon frames, the frequency offset of the local crystal oscillator of the PLC slave node is estimated by the deviation between the actual reception interval of consecutive PLC beacon frames and the theoretical beacon period. This allows for dynamic reflection of the local crystal oscillator's operating deviation without the need for a separate frequency offset measurement link. Furthermore, by determining the frequency offset compensation amount based on the local crystal oscillator's frequency offset and operating time, the cumulative error caused by the local crystal oscillator's frequency offset over time can be suppressed, thereby improving the time maintenance accuracy between adjacent time synchronization periods.

[0067] Under certain test conditions, the typical inherent frequency offset of the local crystal oscillator of a PLC slave node is ±20ppm. Using the frequency offset compensation method described above, and after two beacon cycles (20 seconds), the local crystal oscillator frequency offset error can be suppressed to within ±2ppm. This process reuses the inherent synchronization characteristics of the PLC beacon frame, eliminating the need for additional frequency offset measurement hardware.

[0068] In some embodiments, the PLC slave node is further configured to: record the reception time of the PLC beacon frame and skip the determination of the frequency offset compensation amount when the PLC beacon frame is received for the first time; and determine the frequency offset compensation amount based on the current reception time and the previous reception time when the PLC beacon frame is received for a non-first time, and update the previous reception time to the current reception time after sending the second time synchronization information.

[0069] The PLC slave node is configured with a time record variable to store the time of the previous PLC beacon frame reception. Each time the PLC slave node receives a PLC beacon frame, it records the reception time corresponding to this PLC beacon frame through a local hardware timer and checks whether the previous reception time has already been stored in the time record variable.

[0070] When the PLC slave node receives a PLC beacon frame for the first time, since there is no previous reception time to compare with this reception time, the actual beacon interval cannot be determined based on the reception times of two consecutive PLC beacon frames. Therefore, the PLC slave node records the first reception time and skips the determination of the current frequency offset compensation amount. This time synchronization can be performed based on the original reference time extracted from the PLC beacon frame, the first delay compensation amount, and the second delay compensation amount, without performing frequency offset compensation based on the beacon interval.

[0071] When a PLC slave node receives a PLC beacon frame (not for the first time), it reads the previously saved reception time and calculates the difference between the current reception time and the previous reception time to obtain the actual beacon interval. Subsequently, the PLC slave node determines the local crystal oscillator frequency offset based on the deviation between the actual beacon interval and the theoretical beacon period, and determines the frequency offset compensation amount based on the local crystal oscillator frequency offset and the running time elapsed since the previous PLC beacon frame was received.

[0072] The PLC slave node appends the frequency offset compensation amount to the time synchronization information extracted from the current PLC beacon frame to obtain the second time synchronization information, which is then sent to the first processing core. After sending the second time synchronization information, the PLC slave node updates the previous reception time stored in the time recording variable to the current reception time, making the current reception time the comparison reference for the arrival of the next PLC beacon frame. Thus, the frequency offset compensation amount is determined based on the reception times of two adjacent PLC beacon frames.

[0073] By skipping the determination of frequency offset compensation when receiving a PLC beacon frame for the first time, invalid or erroneous frequency offset calculation results due to the lack of the previous reception time can be avoided. By updating the previous reception time to the current reception time after the second time synchronization information is sent, the current reception time can be prevented from being overwritten in advance, ensuring the correspondence between the reception times of adjacent PLC beacon frames, thereby improving the continuity and accuracy of the calculation of local crystal oscillator frequency offset rate and frequency offset compensation.

[0074] In some embodiments, the reserved field is a field in the PLC beacon frame that is not occupied by service data; the PLC master node is used to encapsulate the original reference time, the first delay compensation amount and the second delay compensation amount in the reserved field without changing the frame length of the PLC beacon frame, so that the transmission of time synchronization information does not occupy the PLC service data time slot.

[0075] The PLC master node generates and broadcasts PLC beacon frames according to a preset beacon cycle. The PLC beacon frame has a predetermined frame structure, including fields for transmitting beacon control information and reserved fields not currently occupied by PLC service data. These reserved fields can be pre-reserved extended fields in the PLC beacon frame or currently unused data areas, and their space can accommodate the original reference time, the first delay compensation amount, and the second delay compensation amount.

[0076] When the PLC beacon frame transmission time arrives, the PLC master node retrieves the original reference time and the first delay compensation amount from the buffered first time synchronization information, and then retrieves the corresponding second delay compensation amount. Subsequently, the PLC master node writes the original reference time, the first delay compensation amount, and the second delay compensation amount into the reserved fields of the PLC beacon frame according to the preset field order and data format. The original control fields and other beacon information of the PLC beacon frame remain unchanged, and the PLC beacon frame after encapsulating the time synchronization information retains its original frame length.

[0077] In one specific example, the reserved field of the PLC beacon frame has a field length of at least 20 bytes. The original reference time, the first delay compensation amount, and the second delay compensation amount together occupy 16 bytes, with the remaining bytes still used as reserved space. The above byte number is only used to illustrate a specific frame structure and does not constitute a limitation on the capacity of the reserved field or the length of each field.

[0078] Because the time synchronization information is broadcast using reserved fields in the PLC beacon frame, it does not increase the total length of the PLC beacon frame, nor does it occupy the PLC service data time slot. Therefore, it reduces the probability of data collisions between synchronization messages and service messages, and is suitable for the strong electromagnetic interference and long-distance transmission communication environment of photovoltaic power plants. Compared to laying separate time synchronization lines or configuring independent time synchronization modules for each inverter, this multiplexing method does not require additional time synchronization hardware, which helps reduce engineering deployment costs.

[0079] The PLC master node broadcasts a PLC beacon frame carrying time synchronization information via a power line carrier communication link. After receiving the PLC beacon frame, each PLC slave node extracts the original reference time, the first delay compensation amount, and the second delay compensation amount from the reserved fields according to the field positions and data formats agreed upon with the PLC master node, and uses the extracted time synchronization information for subsequent frequency offset compensation and inverter local system clock correction.

[0080] Since the time synchronization information is transmitted along with the PLC beacon frames periodically sent by the PLC master node, there is no need to generate and send separate PLC synchronization messages, nor is it necessary to allocate PLC service data time slots for the time synchronization information. Therefore, by reusing the reserved fields of the PLC beacon frames, broadcast transmission of the time synchronization information can be achieved without changing the PLC beacon frame length or the existing beacon transmission mechanism. This reduces the occupation of PLC service bandwidth, lowers the probability of transmission conflicts between synchronization messages and service data, and improves the utilization efficiency of PLC communication resources.

[0081] In some embodiments, the data acquisition unit and the PLC master node, as well as the PLC slave node and the first processing core, are connected via UART serial communication links, and time synchronization information is transmitted using the Modbus Remote Terminal Unit (RTU) protocol. Specifically, the data acquisition unit acts as the sending node for the first time synchronization information, and the PLC master node acts as the receiving node for the first time synchronization information; the PLC slave node acts as the sending node for the second time synchronization information, and the first processing core acts as the receiving node for the second time synchronization information.

[0082] The system pre-configures register mappings corresponding to time synchronization information and allocates corresponding holding registers for the original reference time, first delay compensation amount, second delay compensation amount, frequency offset compensation amount, and third delay compensation amount. These holding registers are arranged consecutively according to the transmission order of the fields in the time synchronization information, enabling nodes at each level to identify the meaning of the corresponding fields based on their identical register locations. When the data acquisition unit sends the first time synchronization information to the PLC master node, it writes the original reference time and the first delay compensation amount into the corresponding consecutive holding registers. When the PLC slave node sends the second time synchronization information to the first processing core, it writes the original reference time, the first delay compensation amount, the second delay compensation amount, and the frequency offset compensation amount into the corresponding consecutive holding registers.

[0083] In one specific implementation, the data acquisition unit and PLC slave nodes can use the write multiple holding register function code in the Modbus-RTU protocol to send time synchronization information. Each time field in the original reference time can be represented by a separate holding register, and each compensation amount can be represented by multiple holding registers. For example, each time field in the original reference time can be represented by a 16-bit unsigned integer, and the first delay compensation amount, second delay compensation amount, frequency offset compensation amount, and third delay compensation amount can be represented by 32-bit integers, and split into two consecutive 16-bit holding registers respectively. The sending and receiving nodes of the time synchronization information use the same byte order, field order, and data length, thereby enabling the writing and reading of time synchronization information according to a unified data format.

[0084] This embodiment is designed with low latency, high reliability, and standardization as the principles for its communication protocol. The serial links between the data acquisition unit and the PLC master node, and between the PLC slave node and the ARM core, follow the Modbus-RTU V1.0 protocol and employ unified physical layer parameters, data link layer parameters, and frame structure. The PLC master node and PLC slave node use PLC beacon frames, while the ARM core and DSP core use an internally defined protocol. However, both use a unified time synchronization field meaning, data format, and bit allocation. Therefore, while adapting to the strong electromagnetic interference and long-distance transmission scenarios of photovoltaic power plants, it can support parsing and interfacing between devices from different manufacturers and models.

[0085] In a specific communication parameter configuration, the UART serial communication link uses 8 data bits, 1 stop bit, and no parity bit, with a default baud rate of 115200bps, which can also be configured to 9600bps, 19200bps, 38400bps, or 57600bps. Based on each byte including 1 start bit, 8 data bits, and 1 stop bit, at the default baud rate, the theoretical serial transmission time for a 21-byte time synchronization frame is 1.823 milliseconds, and the theoretical serial transmission time for a 29-byte time synchronization frame is 2.517 milliseconds; the actual transmission time is measured by a hardware timer and includes corresponding delay compensation.

[0086] In a specific register mapping, starting at address 810, consecutive holding registers are allocated in the order of original reference time, T1, T2, frequency offset compensation Δt, and T3, and the corresponding ending address is extended according to the number of fields accumulated for each level of time synchronization information. Taking the original reference time occupying four 16-bit registers and each compensation value occupying two 16-bit registers as an example, the third time synchronization information uses 12 consecutive holding registers from addresses 810 to 821. The time field uses a 16-bit unsigned integer; T1, T2, and T3 use 32-bit unsigned integers with a range of 0 to 4294 seconds; Δt uses a 32-bit signed integer; each 32-bit field is split into two 16-bit registers. The millisecond and microsecond fields are set separately to provide sub-millisecond time resolution. For the next-level reading node, the already written time synchronization fields are read-only data; the original reference time is written by the data acquisition unit and transmitted transparently throughout the process, while each compensation field is written level by level by the corresponding node. The register update cycle is synchronized with the PLC beacon cycle, with a default update cycle of 10 seconds.

[0087] Each node determines the amount of data to be transmitted based on the number of fields required. In one example, the first time synchronization information sent by the data acquisition unit to the PLC master node CCO includes 6 registers, with a Modbus-RTU frame length of 21 bytes; the time synchronization data transmitted by the PLC master node CCO to the PLC slave node STA corresponds to 8 registers, occupying 16 bytes in the PLC beacon frame; the second time synchronization information sent by the PLC slave node STA to the ARM core includes 10 registers, with a Modbus-RTU frame length of 29 bytes; the third time synchronization information sent by the ARM core to the DSP core corresponds to 12 register fields, with the actual frame length determined according to the internal communication protocol. The ARM core and DSP core do not use the standard Modbus-RTU protocol, but rather an internally defined protocol, mapping the aforementioned time fields, compensation fields, and register mapping relationships to the internal communication frames to maintain consistency in field meaning, data format, and bit allocation.

[0088] After receiving the second time synchronization information, the first processing core parses the original reference time, the first delay compensation amount, the second delay compensation amount, and the frequency offset compensation amount according to the preset register mapping relationship, and appends the determined third delay compensation amount to the corresponding field to obtain the third time synchronization information. The first and second processing cores transmit the third time synchronization information using an internal communication protocol suitable for the internal communication bus. Although the third time synchronization information is no longer transmitted using the Modbus-RTU protocol, its fields still retain the field meanings, arrangement order, and data formats specified by the aforementioned register mapping relationship, so that the second processing core can parse the third time synchronization information according to the same field definitions.

[0089] By adopting a unified register mapping relationship among different nodes, it is possible to avoid the ambiguity caused by different field definitions for the original reference time and various compensation quantities by different nodes. This facilitates the writing, reading and forwarding of time synchronization information level by level among the data acquisition unit, PLC master node, PLC slave node, first processing core and second processing core. At the same time, the transmission of the first and second time synchronization information based on the existing Modbus-RTU communication mechanism, and the use of the same field meaning and data format in the internal communication protocol, can reduce the data conversion complexity between different communication links, improve equipment compatibility and system maintenance efficiency.

[0090] In some embodiments, the PLC master node is used to perform cyclic redundancy check, function code check and register address check on the first time synchronization information in sequence, and cache the first time synchronization information after the check passes; the PLC master node is also used to, when receiving multiple first time synchronization information within a PLC beacon cycle, use the later received first time synchronization information to overwrite the earlier received first time synchronization information, and encapsulate the last received and verified first time synchronization information into a PLC beacon frame.

[0091] The data acquisition unit sends the first time synchronization information to the PLC master node using the Modbus-RTU protocol. This first time synchronization information includes the original reference time, the first delay compensation amount, and the function code, register address, and cyclic redundancy check (CRC) code used for frame identification and verification. Upon receiving the first time synchronization information, the PLC master node sequentially performs CRC verification, function code verification, and register address verification.

[0092] Specifically, the PLC master node first recalculates the cyclic redundancy check (CRC) code based on the message data in the first time synchronization information, excluding the CRC code, and then compares the recalculated CRC code with the CRC code carried in the first time synchronization information. If the two are inconsistent, it indicates that the first time synchronization information may have had a data error during transmission. The PLC master node then terminates further processing of the first time synchronization information and does not write it into the cache.

[0093] After the cyclic redundancy check passes, the PLC master node verifies the function code in the first time synchronization information to determine if it is a pre-defined time synchronization information writing function code. For example, this function code could be the write multiple holding registers function code in the Modbus-RTU protocol. If the function code does not meet the preset requirements, the PLC master node will not parse or cache the register data in the message.

[0094] After the function code verification passes, the PLC master node further verifies the register addresses in the first time synchronization information to determine whether the starting register address and its corresponding register range match the preset time synchronization information register mapping relationship. Once the register address verification passes, the PLC master node parses the original base time and the first delay compensation amount according to the preset register mapping relationship and writes the verified first time synchronization information into the local buffer area. Therefore, only the first time synchronization information that has passed cyclic redundancy check, function code verification, and register address verification in sequence is used for encapsulation of subsequent PLC beacon frames.

[0095] In one specific implementation, the Cyclic Redundancy Check (CRC) uses the CRC-16 / MODBUS algorithm, whose generator polynomial is G(x) = x^16 + x^15 + x^2 + 1, where x is a polynomial variable. During the check, the initial value of the 16-bit register is preset to 0xFFFF. Each data byte is XORed sequentially with the lower 8 bits of the register, and then the register is shifted right by 1 bit. If the shifted-out bit is 1, the shifted register is XORed with the reflection polynomial 0xA001. After processing all data bytes in the above manner, the resulting register value is not additionally inverted and is appended to the end of the frame in the order of low byte first, high byte last, to detect transmission errors. For time synchronization frames that fail the CRC check, the PLC master node discards them directly. For time synchronization frames with invalid function codes or whose starting register address or number of registers does not conform to the preset register mapping relationship, the PLC master node can return a standard exception response according to the Modbus-RTU protocol to locate message type errors or register access errors.

[0096] All Modbus-RTU time synchronization frames mentioned above employ the CRC-16 / MODBUS algorithm for data integrity verification and use the 0x10 function code, i.e., writing multiple holding registers, to avoid conflicts with other service function codes of the inverter or controller; the frame length is dynamically adjusted according to the number of registers currently being transmitted. Through unified function codes, CRC verification, register mapping, and anomaly response mechanisms, data integrity, interoperability, and fault location efficiency can be improved in environments with strong electromagnetic interference.

[0097] Within a PLC beacon cycle, the data acquisition unit may send multiple first time synchronization messages to the PLC master node. Upon receiving the first successfully verified first time synchronization message, the PLC master node writes it to its local cache. When it receives another successfully verified first time synchronization message within the same PLC beacon cycle, it uses the later received first time synchronization message to overwrite the previously received first time synchronization message in the cache. If the later received first time synchronization message fails any of the above verifications, it is not used to overwrite the already cached valid information.

[0098] When the PLC beacon frame transmission time arrives, the PLC master node reads the last received and verified first time synchronization information from its local buffer, obtains the original reference time and the first delay compensation amount, and encapsulates them together with the second delay compensation amount into the reserved field of the PLC beacon frame. Therefore, the PLC beacon frame carries the most valid time synchronization information within the current PLC beacon cycle that is closest to the beacon transmission time.

[0099] By sequentially performing cyclic redundancy check, function code check, and register address check, errors in transmitted data, message type, and register mapping can be identified, preventing abnormal time synchronization information from entering subsequent time synchronization links. By using the later received valid time synchronization information to overwrite the earlier received valid time synchronization information within the same PLC beacon cycle, multiple time synchronization messages can be avoided from being cached, and the original reference time with higher timeliness is given priority for beacon encapsulation, thereby improving the reliability and real-time performance of time synchronization information.

[0100] In some embodiments, when the data acquisition device sends the first time synchronization information to the PLC master node, the PLC master node broadcasts a PLC beacon frame to the PLC slave node, and the PLC slave node sends the second time synchronization information to the first processing core, a one-way, non-acknowledgment transmission method is adopted; the time synchronization device is used to provide the original reference time to the data acquisition device according to a preset time synchronization period, so that nodes that have not received the time synchronization information corresponding to the current time synchronization period can synchronize their time based on the time synchronization information corresponding to the next time synchronization period.

[0101] The time synchronization device is a station-level NTP time synchronization server, which sends time synchronization messages carrying the original reference time to the data acquisition unit according to the preset time synchronization cycle. Each time synchronization cycle corresponds to one time synchronization information transmission process. The data acquisition unit generates the first time synchronization information based on the original reference time of the current time synchronization cycle, and transmits it to the first processing core of the inverter in sequence through the PLC master node and PLC slave node.

[0102] When the data acquisition unit sends the first time synchronization information to the PLC master node, it adopts a one-way, non-acknowledgment transmission method. After sending the first time synchronization information, the data acquisition unit does not wait for the PLC master node to return an acknowledgment response, nor does it resend the first time synchronization information within the current time synchronization cycle due to the lack of an acknowledgment response. After the PLC master node receives the first time synchronization information and verifies it, it buffers it; if it does not receive the first time synchronization information or the received first time synchronization information fails verification, it does not use the first time synchronization information for time synchronization processing in the current time synchronization cycle.

[0103] When the PLC master node sends PLC beacon frames to the PLC slave nodes, it also adopts a one-way, non-acknowledgment transmission method. When the transmission time for the PLC beacon frame arrives, the PLC master node broadcasts a PLC beacon frame carrying time synchronization information via the power line carrier communication link. Each PLC slave node receives the PLC beacon frame but does not send an acknowledgment response to the PLC master node for that PLC beacon frame. This avoids multiple PLC slave nodes simultaneously returning responses, thus preventing the occupation of power line carrier communication resources.

[0104] When the PLC slave node sends the second time synchronization information to the first processing core, it also adopts a one-way, no-acknowledgment transmission method. After the PLC slave node completes the transmission of the second time synchronization information, it does not wait for the first processing core to return an acknowledgment, nor does it perform retransmission based on the acknowledgment within the current time synchronization period. After receiving the second time synchronization information, the first processing core continues to determine the third delay compensation amount and transmit the third time synchronization information.

[0105] If any node in the PLC master node, PLC slave node, or first processing core fails to receive the time synchronization information corresponding to the current time synchronization cycle, that node can skip the corresponding time synchronization process for the current time synchronization cycle. The station-level NTP time synchronization server re-provides the original reference time to the data acquisition unit in the next time synchronization cycle, and each node re-executes the time synchronization process based on the time synchronization information corresponding to the next time synchronization cycle. Therefore, without needing to set up response waiting and message retransmission mechanisms within the current time synchronization cycle, the re-distribution of time synchronization information can be achieved using periodic time synchronization.

[0106] In one specific configuration, the default synchronization period for the station-level NTP time synchronization server is 30 minutes. The aforementioned one-way no-acknowledgment means that a normal time synchronization frame that passes verification does not return an acknowledgment frame, nor does it perform retransmission within the current time synchronization period based on the acknowledgment frame; standard abnormal responses returned for illegal function codes or illegal register accesses are not considered acknowledgment responses for normal time synchronization frames.

[0107] By adopting a one-way, non-acknowledgment transmission method, the occupation of serial communication links and power line carrier communication links by acknowledgment and retransmission messages can be reduced, and additional and uncertain transmission delays introduced by acknowledgment waiting and message retransmission can be avoided. At the same time, by utilizing the periodic time synchronization mechanism of the time synchronization device, nodes that have not received the current time synchronization information can obtain the time synchronization information again in the next time synchronization cycle, thereby simplifying the communication process while ensuring that the time synchronization process has continuous recovery capability.

[0108] The core node in this embodiment employs a layered decoupling, event-driven, interrupt-triggered, beacon synchronization, coverage update, and unidirectional forwarding processing mechanism. It completes message verification, information updates, beacon encapsulation, and forwarding according to a unified protocol. Each node quantifies its own latency and appends it level by level, ultimately achieving centralized correction by the DSP core. This mechanism enables the CCO to periodically and deterministically issue time synchronization information based on the beacon cycle, adapting unidirectional transmission to weak PLC carrier network environments and prioritizing the issuance of the latest valid time synchronization data.

[0109] like Figure 2 As shown, Figure 2 This paper illustrates a time synchronization process for the PLC master node (CCO). Figure 2In this context, "Logger" refers to the aforementioned data acquisition unit (SAU). The CCO, as the time synchronization data aggregation and beacon bearer node, is responsible for message reception, validity verification, delay measurement, beacon encapsulation, and broadcast transmission. Its processing is driven by dual events: UART receive interrupt and beacon timer interrupt. After power-on, the PLC master node completes hardware initialization, configuring the UART to the default 115200bps, 8 data bits, 1 stop bit, and no parity bit. It starts the PLC carrier protocol stack and the default 10-second beacon period timer, initializes the time synchronization information buffer to an invalid state, and enters event listening mode.

[0110] After a UART receive interrupt is triggered, the PLC master node receives the Modbus-RTU time synchronization frame sent by the data acquisition unit. It then sequentially checks whether the CRC-16 / MODBUS check passes, whether the function code is 0x10, and whether the register address is within the time synchronization register range of 810 to 815. Function code 0x10 indicates writing to multiple holding registers. Registers 810 to 815 are used to carry the original reference time and the first delay compensation amount T1 in the current data acquisition unit's time synchronization frame. If the CRC check fails, the message is discarded directly; if the function code or register address is invalid, a standard exception response can be returned; if all checks are satisfied, the PLC master node parses the original reference time and T1, synchronously records the received time t_recv, and writes the time synchronization information to the buffer.

[0111] Within the current PLC beacon cycle, if the PLC master node receives a new, verified data acquisition time synchronization frame again, it will overwrite the previously cached content with the time synchronization information and reception time in the new frame, retaining only the latest valid record. After the beacon timer interrupt is triggered and the beacon transmission time is reached, the PLC master node determines the second delay compensation amount T2 carried in the current PLC beacon frame based on the processing and waiting time that has already occurred and the estimated transmission time calibrated with historical complete measured values. Figure 2 In the PLC beacon frame, `t_send` represents the expected transmission completion time, determined by the actual transmission trigger time and the calibrated expected transmission duration. The PLC master node encapsulates the original reference time, T1, and T2 into the reserved fields of the PLC beacon frame and broadcasts them to all online PLC slave nodes (STAs) via existing power cables. When a PLC beacon frame transmission completion interruption is triggered, the transmission completion time is recorded, and the complete measured PLC link delay from the reception time to the transmission completion time is obtained. Based on this, the second delay compensation parameter used in subsequent beacon cycles is calibrated. After transmission is completed, the PLC master node clears the current time synchronization buffer and resumes listening state, waiting for the next UART receive interrupt or beacon timer interrupt.

[0112] like Figure 3 As shown, Figure 3This paper illustrates a time synchronization process for a PLC slave node (STA). The STA, acting as a beacon parsing, frequency offset compensation, and time synchronization information forwarding node, is responsible for real-time monitoring of the CCO beacon, parsing time synchronization information, calculating the local crystal oscillator frequency offset, and encapsulating and forwarding the time synchronization frame. This process is driven by the PLC beacon reception interrupt. After power-on, the PLC slave node completes hardware initialization, configures the PLC carrier parameters, joins the PLC network where the PLC master node (CCO) resides, configures the UART parameters for communication with the ARM core to the default 115200bps, 8 data bits, 1 stop bit, and no parity bit, initializes the previous beacon reception time variable t_beacon1 to zero, starts the local high-precision timer, and enters beacon monitoring mode.

[0113] After the PLC beacon reception interruption is triggered, the PLC slave node receives the CCO beacon frame, verifies the validity of the beacon frame header and determines whether it contains time synchronization information; if the frame header is invalid or does not contain time synchronization information, the current processing ends and the PLC continues to listen for the next PLC beacon frame; if it is valid and contains time synchronization information, the reserved field is parsed, the original reference time, the first delay compensation amount T1 and the second delay compensation amount T2 are extracted, and the reception time of this PLC beacon frame is recorded as t_beacon2.

[0114] When t_beacon1 is zero, it indicates that the current PLC beacon frame is the first received PLC beacon frame, and the PLC slave node skips this frequency offset calculation. When t_beacon1 is not zero, the PLC slave node determines the actual beacon interval based on t_beacon2 and t_beacon1, and calculates the local crystal oscillator frequency offset rate and frequency offset compensation amount Δt in combination with the theoretical beacon period. The PLC slave node encapsulates the original reference time, T1, T2, and Δt into a Modbus-RTU time synchronization frame, and sends it to the inverter's ARM core in a single transmission via the UART serial communication link without waiting for acknowledgment. After transmission, the local buffer is cleared, t_beacon1 is updated to t_beacon2, and the beacon listening state is restored.

[0115] In some embodiments, the root mean square method can be used to evaluate the theoretical total time synchronization error of the system. Let the NTP reference time error, data acquisition unit delay compensation error, PLC master node delay compensation error, ARM core inter-core delay compensation error, and crystal oscillator frequency offset compensation error be ΔT0, ΔT1, ΔT2, ΔT3, and Δt, respectively. Then the theoretical total time synchronization error ΔT can be expressed as:

[0116] For example, when the absolute values ​​of ΔT0, ΔT1, ΔT2, ΔT3, and Δt are no greater than 1 millisecond, 10 microseconds, 50 microseconds, 20 microseconds, and 10 microseconds respectively, the absolute value of the theoretical total time synchronization error obtained according to the above root mean square relationship is no greater than 1.002 milliseconds. If GPS or BeiDou direct time synchronization is used to replace NTP reference time, and the absolute value of ΔT0 is no greater than 1 microsecond, the absolute value of the theoretical total time synchronization error can be further reduced to within 55 microseconds.

[0117] In a field test, the aforementioned time synchronization system was applied to a 10MW centralized photovoltaic power station. Using the station-level time source output as a reference, the absolute value of the time synchronization link deviation was measured to be no greater than 23 microseconds, and it operated continuously for 30 days without experiencing synchronization loss. These test results demonstrate that the combination of multi-level delay compensation, PLC beacon frequency offset compensation, and unified calibration at the DSP end can maintain high link time synchronization accuracy and operational stability in the context of strong electromagnetic interference and multi-level communication links in photovoltaic power stations.

[0118] The above embodiments describe the photovoltaic power station time synchronization system from the perspective of system structure and the functions of each component node. Based on the same technical concept, this application also provides a photovoltaic power station time synchronization method, which can be executed by the photovoltaic power station time synchronization system of any of the foregoing embodiments. The descriptions of the time synchronization device, data acquisition unit, PLC master node, PLC slave node, first processing core and second processing core in the system embodiments are all applicable to this method embodiment.

[0119] like Figure 4 As shown, the method includes the following steps: Step 410: Determine the first delay compensation amount through the data acquisition device, and send the first time synchronization information carrying the original reference time and the first delay compensation amount provided by the time synchronization device to the PLC master node; Step 420: After receiving the first time synchronization information, the PLC master node determines the second delay compensation amount at the time of sending the PLC beacon frame, encapsulates the original reference time, the first delay compensation amount and the second delay compensation amount in the reserved field of the PLC beacon frame and broadcasts them. Step 430: The frequency offset compensation amount is determined by the PLC slave node based on the reception time of multiple PLC beacon frames and the theoretical beacon period. The frequency offset compensation amount is added to the time synchronization information extracted from the PLC beacon frames to obtain the second time synchronization information and send it to the first processing core of the inverter. Step 440: Determine the third delay compensation amount through the first processing core, add the third delay compensation amount to the second time synchronization information, obtain the third time synchronization information, and send it to the second processing core of the inverter; Step 450: The second processing core determines the correction time based on the original reference time, the first delay compensation amount, the second delay compensation amount, the third delay compensation amount, and the frequency offset compensation amount in the third time synchronization information, and updates the local system clock based on the correction time; wherein, the original reference time remains unchanged during the transmission process, and the first delay compensation amount, the second delay compensation amount, the frequency offset compensation amount, and the third delay compensation amount are added step by step.

[0120] The data acquisition unit obtains the original reference time provided by the time synchronization device, determines the first delay compensation amount corresponding to the processing and transmission of time synchronization information, and generates first time synchronization information carrying the original reference time and the first delay compensation amount. The data acquisition unit sends the first time synchronization information to the PLC master node through a serial communication link, so that the original reference time and the first delay compensation amount generated on the data acquisition side are transmitted to the PLC master node.

[0121] After receiving the first time synchronization information, the PLC master node processes and buffers the information, and waits for the PLC beacon frame to be sent. When the PLC beacon frame is ready to be sent, the PLC master node determines the second delay compensation amount corresponding to the process from receiving the first time synchronization information to sending the PLC beacon frame. It then encapsulates the original reference time, the first delay compensation amount, and the second delay compensation amount into the reserved field of the PLC beacon frame and broadcasts the PLC beacon frame via the power line carrier communication link.

[0122] After receiving a PLC beacon frame, the PLC slave node extracts the original reference time, the first delay compensation amount, and the second delay compensation amount from the reserved fields of the PLC beacon frame. The PLC slave node records the reception times of multiple PLC beacon frames, determines the local crystal oscillator frequency offset based on the reception times of multiple PLC beacon frames and the theoretical beacon period, and determines the frequency offset compensation amount based on the local crystal oscillator frequency offset. The PLC slave node appends the frequency offset compensation amount to the time synchronization information extracted from the PLC beacon frame to obtain the second time synchronization information, and sends the second time synchronization information to the first processing core of the inverter.

[0123] After receiving the second time synchronization information, the first processing core determines the third delay compensation amount corresponding to the processing and transmission process of the second time synchronization information, adds the third delay compensation amount to the second time synchronization information to obtain the third time synchronization information, and sends the third time synchronization information to the second processing core of the inverter through the internal communication bus.

[0124] After receiving the third time synchronization information, the second processing core extracts the original reference time, the first delay compensation amount, the second delay compensation amount, the frequency offset compensation amount, and the third delay compensation amount from the third time synchronization information, and determines the correction time based on the original reference time and the above compensation amounts. Subsequently, the second processing core updates the inverter's local system clock according to the correction time to keep the inverter's local system clock synchronized with the station-level time reference.

[0125] During the aforementioned time synchronization process, the original reference time remains unchanged as it is transmitted between the data acquisition unit, PLC master node, PLC slave node, first processing core, and second processing core. The first delay compensation, second delay compensation, frequency offset compensation, and third delay compensation are added sequentially according to the transmission order of the time synchronization information. Each node does not use its local time to replace the original reference time, thereby enabling the second processing core to comprehensively process time deviations at all levels based on a unified original reference time.

[0126] According to the photovoltaic power station time synchronization method provided in this application, the original reference time is provided to the data acquisition unit through the time synchronization device, providing a unified time synchronization reference for each inverter in the photovoltaic power station; the data acquisition unit determines the first delay compensation amount and sends the first delay compensation amount and the original reference time together to the PLC master node, which can compensate for the time overhead incurred by the data acquisition unit in processing and sending time synchronization information; the PLC master node determines the second delay compensation amount through the timing of the PLC beacon frame transmission, and broadcasts the original reference time, the first delay compensation amount and the second delay compensation amount using the reserved field of the PLC beacon frame, which can... The system compensates for the processing, waiting, and transmission time overhead of the PLC master node. By determining the frequency offset compensation amount based on the reception times of multiple PLC beacon frames and the theoretical beacon period through the PLC slave node, it can compensate for the accumulated time deviation caused by the local crystal oscillator frequency offset. The first processing core determines and adds a third delay compensation amount, which can compensate for the time overhead generated by the inverter's internal processing and transmission. The second processing core integrates the original reference time and the progressively added compensation amounts to determine the correction time and update the local system clock, reducing the impact of multi-level processing delays, communication link transmission delays, and local crystal oscillator frequency offsets on the time synchronization results. Simultaneously, the original reference time remains unchanged during transmission, and the progressively added compensation amounts maintain a unified time reference and retain compensation information at each level, thereby improving the inverter's time synchronization accuracy.

[0127] The above embodiments illustrate the photovoltaic power plant time synchronization scheme from the perspectives of system composition and method flow. Considering that the time synchronization information is ultimately used to correct the local system clock of the inverter, this application embodiment also provides an inverter capable of performing inverter-side time synchronization processing. The descriptions of the PLC slave node, the first processing core, the second processing core, and various compensation quantities in the foregoing system and method embodiments are all applicable to the following inverter embodiments.

[0128] In some embodiments, the inverter includes a PLC slave node, a first processing core, and a second processing core. The first processing core can be an ARM core, and the second processing core can be a DSP core. The PLC slave node is connected to an external PLC master node via a power line carrier communication link, the PLC slave node is connected to the ARM core via a UART serial communication link, and the ARM core is connected to the DSP core via an internal communication bus such as an SPI bus.

[0129] The PLC slave node receives the PLC beacon frame broadcast by the PLC master node and extracts the original reference time, the first delay compensation amount, and the second delay compensation amount from the reserved fields of the PLC beacon frame. The first delay compensation amount is used to compensate for the time overhead generated on the data acquisition side, and the second delay compensation amount is used to compensate for the time overhead generated on the PLC master node side.

[0130] The PLC slave node records the reception times of multiple PLC beacon frames. Based on the reception times of these frames and the theoretical beacon period, it determines the local crystal oscillator frequency offset and then determines the frequency offset compensation amount. Subsequently, the PLC slave node appends the frequency offset compensation amount to the time synchronization information extracted from the PLC beacon frames, obtaining second time synchronization information including the original reference time, a first delay compensation amount, a second delay compensation amount, and a frequency offset compensation amount. This second time synchronization information is then sent to the ARM core.

[0131] After receiving the second time synchronization information, the ARM core determines the third delay compensation amount corresponding to the parsing, delay calculation, information encapsulation, and internal communication bus transmission processes of the second time synchronization information. The ARM core appends the third delay compensation amount to the second time synchronization information to obtain the third time synchronization information, and then sends the third time synchronization information to the DSP core through the internal communication bus.

[0132] After receiving the third time synchronization information, the DSP core determines the correction time based on the original reference time, the first delay compensation amount, the second delay compensation amount, the frequency offset compensation amount, and the third delay compensation amount in the third time synchronization information, and updates the inverter's local system clock based on this correction time. During this process, the original reference time remains unchanged, and each compensation amount is added sequentially according to the time synchronization information transmission process.

[0133] The inverter provided in this application embodiment obtains the original reference time and upstream delay compensation amounts from the PLC beacon frames through the PLC slave node, and determines the frequency offset compensation amount based on the reception time of multiple PLC beacon frames, which can simultaneously compensate for the cumulative error caused by upstream transmission delay and local crystal oscillator frequency offset; the first processing core further determines and adds a third delay compensation amount, which can compensate for the time overhead generated by the inverter's internal processing and transmission; the second processing core combines the original reference time and the gradually added compensation amounts to determine the correction time, which can reduce the impact of multi-level communication delay, local crystal oscillator frequency offset and inter-processing core delay on the local system clock, and improve the inverter's time calibration accuracy.

[0134] The aforementioned photovoltaic power station time synchronization method can be executed collaboratively by multiple electronic devices within the photovoltaic power station. These electronic devices may include intelligent subarray controllers, inverters, and corresponding control devices. Specifically, the intelligent subarray controller executes the processing procedures corresponding to the data acquisition unit and the PLC master node, while the inverter executes the processing procedures corresponding to the PLC slave node, the first processing core, and the second processing core.

[0135] In some embodiments, such as Figure 5 As shown in the illustration, this application also provides an electronic device 500. The electronic device 500 can be an intelligent subarray controller, an inverter, or a corresponding control device. The electronic device 500 includes a processor 501, a memory 502, and a computer program stored in the memory 502 and capable of running on the processor 501. The processor 501 is communicatively connected to the memory 502 to read and execute the computer program. When the computer program is executed by the processor 501, it implements the processing procedures corresponding to the electronic device 500 in the aforementioned photovoltaic power station time synchronization method and achieves the corresponding technical effects. To avoid repetition, these will not be elaborated further here. The processor 501 may include one or more processing units; when the electronic device 500 is an inverter, the one or more processing units may include a first processing core and a second processing core.

[0136] This application also provides a non-transitory computer-readable storage medium. The non-transitory computer-readable storage medium stores a computer program. When the computer program is executed by the processor of an electronic device, it implements the processing procedures corresponding to the electronic device in the aforementioned photovoltaic power station time synchronization method. When the processors of multiple electronic devices execute their respective computer programs, they can collaboratively implement the aforementioned photovoltaic power station time synchronization method and achieve the corresponding technical effects. To avoid repetition, further details are omitted here.

[0137] The processor can be the processor in the intelligent subarray controller, inverter, or corresponding control device in the above embodiments. Non-transitory computer-readable storage media include read-only memory (ROM), random access memory (RAM), magnetic disk, optical disk, or other media capable of storing computer programs.

[0138] This application also provides a computer program product, which includes a computer program. When the computer program is executed by the processor of an electronic device, it implements the processing procedures corresponding to the electronic device in the above-described photovoltaic power station time synchronization method; when the computer program is executed by the processors of multiple electronic devices, the multiple electronic devices cooperate to implement the above-described photovoltaic power station time synchronization method.

[0139] This application also provides a chip, which is applied to an electronic device in a photovoltaic power plant time synchronization system. The chip includes a processor and a communication interface, with the processor coupled to the communication interface. The processor runs programs or instructions to implement the processing procedures corresponding to the electronic device in the photovoltaic power plant time synchronization method described above. The chip can be located in an intelligent subarray controller, inverter, or corresponding control device, and communicates with other nodes in the photovoltaic power plant time synchronization system through the communication interface.

[0140] In some embodiments, the chip may also be referred to as a system-on-a-chip (SoC). The chip may include one or more processors, and may also include memory for storing programs or instructions.

[0141] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, it should be noted that the scope of the methods and apparatuses in the embodiments of this application is not limited to performing functions in the order shown or discussed, but may also include performing functions substantially simultaneously or in the reverse order, depending on the functions involved. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

[0142] As described above, the corresponding processing steps in the above method embodiments can be implemented using a combination of software and hardware, or solely through hardware. The computer software product can be stored in a non-transitory computer-readable storage medium and includes programs or instructions for causing electronic devices to execute the corresponding processing steps. When the programs or instructions are executed by processors of multiple electronic devices within the photovoltaic power station, the multiple electronic devices can collaboratively implement the above-described photovoltaic power station time synchronization method.

[0143] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the above-described embodiments. The above-described embodiments are merely illustrative and not restrictive. Under the guidance of this application, many other forms can be made without departing from the spirit and scope of the claims, and all of them are within the protection scope of this application.

[0144] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0145] Although embodiments of this application have been shown and described, it is understood that various changes, modifications, substitutions and variations can be made to these embodiments without departing from the principles and spirit of this application, the scope of which is defined by the claims and their equivalents.

Claims

1. A photovoltaic power station time synchronization system, characterized in that, It includes a time synchronization device, a data acquisition unit, a PLC master node, a PLC slave node, and an inverter, wherein the inverter includes a first processing core and a second processing core; The timing device is used to provide the original reference time to the data acquisition unit; The data acquisition device is used to determine the first delay compensation amount corresponding to the processing and transmission of the time synchronization information, and to send the first time synchronization information carrying the original reference time and the first delay compensation amount to the PLC master node; The PLC master node is used to determine the second delay compensation amount at the time of sending the PLC beacon frame after receiving the first time synchronization information, and encapsulate the original reference time, the first delay compensation amount and the second delay compensation amount in the reserved field of the PLC beacon frame and broadcast it. The PLC slave node is used to determine the frequency offset compensation amount based on the reception time of multiple PLC beacon frames and the theoretical beacon period, and append the frequency offset compensation amount to the time synchronization information extracted from the PLC beacon frames to obtain the second time synchronization information and send it to the first processing core; The first processing core is used to determine the third delay compensation amount, append the third delay compensation amount to the second time synchronization information, obtain the third time synchronization information, and send it to the second processing core; The second processing core is used to determine the correction time based on the original reference time in the third time synchronization information and the gradually added compensation amount, and to update the local system clock based on the correction time; The original reference time remains unchanged during transmission, and the first delay compensation amount, the second delay compensation amount, the frequency offset compensation amount, and the third delay compensation amount are added step by step.

2. The photovoltaic power station time synchronization system according to claim 1, characterized in that, The time synchronization device is a station-level NTP time synchronization server, the data acquisition unit and the PLC master node are set in the intelligent subarray controller, and the PLC slave node, the first processing core and the second processing core are set in the inverter; The first processing core is an ARM core, and the second processing core is a DSP core; The station-level NTP time synchronization server is connected to the data acquisition unit via Ethernet. The data acquisition unit is connected to the PLC master node and the PLC slave node is connected to the ARM core via serial communication links. The PLC master node and the PLC slave node are connected via power line carrier communication links. The ARM core and the DSP core are connected via an internal communication bus.

3. The photovoltaic power station time synchronization system according to claim 1, characterized in that, The data acquisition unit is used to record the moment when it receives the timing message sent by the timing device and triggers the interruption upon completion of reception through a local hardware timer; The first delay compensation amount is used to compensate for the time overhead incurred by the data collector from receiving the authorization message to sending the first time synchronization information. The time overhead includes the time spent parsing the authorization message, the time spent calculating the delay, the time spent encapsulating the first time synchronization information, and the transmission time spent sending the first time synchronization information through the serial communication link.

4. The photovoltaic power station time synchronization system according to claim 1, characterized in that, The PLC master node is used to record the moment when the first time synchronization information is received and the reception completion interrupt is triggered by a local hardware timer. The second delay compensation amount is used to compensate for the time overhead incurred between the PLC master node receiving the first time synchronization information and sending the PLC beacon frame. The time overhead includes the time spent on verifying and parsing the first time synchronization information, the buffering time, the waiting time for the PLC beacon frame to be sent, the encapsulation time of the PLC beacon frame, and the transmission time of sending the PLC beacon frame through the power line carrier communication link.

5. The photovoltaic power station time synchronization system according to claim 1, characterized in that, The first processing core is used to record the moment when the second time synchronization information is received and the reception completion interrupt is triggered by a local hardware timer; The third delay compensation amount is used to compensate for the time overhead incurred from the time the first processing core receives the second time synchronization information to the time it sends the third time synchronization information to the second processing core. The time overhead includes the parsing time of the second time synchronization information, the delay calculation time, the encapsulation time of the third time synchronization information, and the transmission time of sending the third time synchronization information through the internal communication bus.

6. The photovoltaic power station time synchronization system according to claim 1, characterized in that, The PLC slave node is used for: Record the first beacon reception time and the second beacon reception time corresponding to the first PLC beacon frame and the second PLC beacon frame received consecutively; The actual beacon interval is determined based on the first beacon reception time and the second beacon reception time; The local crystal oscillator frequency offset is determined based on the deviation between the actual beacon interval and the theoretical beacon period, as well as the theoretical beacon period. The frequency offset compensation amount is determined based on the local crystal oscillator frequency offset rate and the running time elapsed since the previous PLC beacon frame was received.

7. The photovoltaic power station time synchronization system according to claim 6, characterized in that, The PLC slave node is also used for: Upon first receiving a PLC beacon frame, record the reception time of the PLC beacon frame and skip the determination of the frequency offset compensation amount; When a PLC beacon frame is received for the first time, the frequency offset compensation amount is determined based on the current reception time and the previous reception time, and after sending the second time synchronization information, the previous reception time is updated to the current reception time.

8. The photovoltaic power station time synchronization system according to claim 1, characterized in that, The reserved fields are the fields in the PLC beacon frame that are not occupied by business data; The PLC master node is used to encapsulate the original reference time, the first delay compensation amount, and the second delay compensation amount in the reserved field without changing the frame length of the PLC beacon frame, so that the transmission of time synchronization information does not occupy the PLC service data time slot.

9. The photovoltaic power station time synchronization system according to claim 1, characterized in that, The data acquisition device transmits time synchronization information with the PLC master node and with the PLC slave node and the first processing core based on the Modbus-RTU protocol. The original reference time and compensation amount contained in the first and second time synchronization information are mapped to a continuous holding register group according to a preset register mapping relationship, so that the sending node and receiving node of the time synchronization information can write, read and forward the time synchronization information according to a unified field meaning and data format; The first processing core and the second processing core transmit the third time synchronization information based on an internal communication protocol. The third time synchronization information follows the field meaning and data format corresponding to the preset register mapping relationship.

10. The photovoltaic power station time synchronization system according to claim 1, characterized in that, The PLC master node is used to perform cyclic redundancy check, function code check and register address check on the first time synchronization information in sequence, and cache the first time synchronization information after the check passes; The PLC master node is also used to, when receiving multiple first time synchronization messages within a PLC beacon cycle, use the later received first time synchronization message to overwrite the earlier received first time synchronization message, and encapsulate the last received and verified first time synchronization message into the PLC beacon frame.

11. The photovoltaic power station time synchronization system according to claim 1, characterized in that, When the data acquisition device sends the first time synchronization information to the PLC master node, the PLC master node broadcasts the PLC beacon frame to the PLC slave node, and the PLC slave node sends the second time synchronization information to the first processing core, a one-way transmission method without returning an acknowledgment frame is used. The timing device is used to provide the original reference time to the data collector according to a preset timing cycle, so that nodes that have not received the timing information corresponding to the current timing cycle can perform timing synchronization based on the timing information corresponding to the next timing cycle.

12. A method for synchronizing the time of a photovoltaic power station, characterized in that, include: The first delay compensation amount is determined by the data acquisition device, and the first time synchronization information carrying the original reference time and the first delay compensation amount provided by the time synchronization device is sent to the PLC master node. After receiving the first time synchronization information, the PLC master node determines the second delay compensation amount at the time of sending the PLC beacon frame, encapsulates the original reference time, the first delay compensation amount and the second delay compensation amount in the reserved field of the PLC beacon frame and broadcasts them. The frequency offset compensation amount is determined by the PLC slave node based on the reception time of multiple PLC beacon frames and the theoretical beacon period. The frequency offset compensation amount is added to the time synchronization information extracted from the PLC beacon frames to obtain the second time synchronization information and send it to the first processing core of the inverter. The third delay compensation amount is determined by the first processing core, and the third delay compensation amount is added to the second time synchronization information to obtain the third time synchronization information and send it to the second processing core of the inverter. The second processing core determines the correction time based on the original reference time, first delay compensation amount, second delay compensation amount, third delay compensation amount and frequency offset compensation amount in the third time synchronization information, and updates the local system clock based on the correction time; The original reference time remains unchanged during transmission, and the first delay compensation amount, the second delay compensation amount, the frequency offset compensation amount, and the third delay compensation amount are added step by step.

13. An inverter, characterized in that, Includes PLC slave nodes, a first processing core, and a second processing core; The PLC slave node is used to extract the original reference time, the first delay compensation amount and the second delay compensation amount from the received PLC beacon frames, determine the frequency offset compensation amount according to the reception time of multiple PLC beacon frames and the theoretical beacon period, and add the frequency offset compensation amount to obtain the second time synchronization information and send it to the first processing core. The first processing core is used to determine the third delay compensation amount corresponding to the processing and transmission process of the second time synchronization information, and to add the third delay compensation amount to obtain the third time synchronization information and send it to the second processing core; The second processing core is used to determine the correction time based on the original reference time, the first delay compensation amount, the second delay compensation amount, the frequency offset compensation amount and the third delay compensation amount in the third time synchronization information, and to update the local system clock based on the correction time.

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