A communication method and apparatus

Abstract

The application provides a communication method and device for improving transmission performance through information bit allocation in polar code encoding. The method comprises: determining a first bit set according to a rate matching set and a first sequence, and determining the number of information bits of I sub-blocks according to the first bit set and a first reliability sequence; determining I encoding matrices according to the number of information bits in the I sub-blocks, and performing encoding according to the I encoding matrices. The rate matching set comprises the serial numbers of at least one bit, the first bit set comprises the serial numbers of at least one bit, the first sequence comprises the serial numbers of at least one bit, and I is an integer greater than 1. In the application, the information bit allocation of each sub-block is obtained based on the reliability sequence and the first sequence, which can improve the flexibility of code length and code rate, and help improve the transmission performance.

Description

Technical Field

[0001] This application relates to the field of communication technology, and in particular to a communication method and apparatus. Background Technology

[0002] Polar codes were selected as the control channel coding scheme in the 5th generation (5G) communication standard. Polar codes are a coding scheme that can be rigorously proven to "achieve" the Shannon channel capacity and have the advantages of good decoding performance and low complexity.

[0003] Currently, polar code channel coding can be performed by coupling short codes to long codes. For example, a 64-bit polar core can be constructed using four 16-bit sub-blocks, and a 64-bit codeword can be obtained from the 64-bit polar core. The number of information bits in each sub-block affects transmission performance. Therefore, when coupling short codes to long codes, how to allocate the number of information bits in each sub-block to improve transmission performance is an urgent problem to be solved. Summary of the Invention

[0004] This application provides a communication method and apparatus for improving transmission performance by allocating information bits in polar code encoding.

[0005] In a first aspect, embodiments of this application provide an encoding method, which can be executed by a first device. Unless otherwise specified, the "first device" in this application can refer to the first device itself (e.g., a terminal, terminal device, or network device), a component used in the first device (e.g., a functional module, communication module, processor, circuit, chip, or chip system), or a logic module or software capable of implementing all or part of the functions of the first device. The component used in the first device can be within the first device or independent of it. The first device can be a transmitting device, and correspondingly, the receiving device is a second device.

[0006] Taking the first device as the executing entity as an example, the method includes:

[0007] A first bit set is determined based on the rate matching set and the first sequence, and the number of information bits in I sub-blocks is determined based on the first bit set and the first reliability sequence; I coding matrices are determined based on the number of information bits in the I sub-blocks, and encoding is performed based on the I coding matrices. Here, the rate matching set includes the index of at least one bit, the first bit set includes the index of at least one bit, the first sequence includes the index of at least one bit, and I is an integer greater than 1.

[0008] In this application, the information bit allocation for each sub-block is obtained based on the reliability sequence and the first sequence. This allows for flexible allocation of the number of information bits according to the code length of the sub-block. Since the number of information bits and the code length determine the code rate, this application can flexibly allocate the code rate, which helps improve transmission performance. For example, allocating more information bits to sub-blocks with shorter code lengths increases the code rate of the corresponding sub-blocks, resulting in better transmission performance.

[0009] Secondly, embodiments of this application provide a decoding method, which can be executed by a second device. Unless otherwise specified, the "second device" in this application can refer to the second device itself (e.g., a terminal, terminal equipment, or network device), a component within the second device (e.g., a functional module, communication module, processor, circuit, chip, or chip system), or a logic module or software capable of implementing all or part of the functions of the second device. The components used in the second device can be within the second device or independent of it. The second device can be a receiving device.

[0010] Taking the second device as the executing entity as an example, the method includes:

[0011] A first bit set is determined based on the rate matching set and the first sequence, and the number of information bits in I sub-blocks is determined based on the first bit set and the first reliability sequence; I coding matrices are determined based on the number of information bits in the I sub-blocks, and decoding is performed based on the I coding matrices. Here, the rate matching set includes the index of at least one bit, the first bit set includes the index of at least one bit, the first sequence includes the index of at least one bit, and I is an integer greater than 1.

[0012] In this application, the information bit allocation for each sub-block is obtained based on the reliability sequence and the first sequence. This allows for flexible allocation of the number of information bits according to the code length of the sub-block. Since the number of information bits and the code length determine the code rate, this application can flexibly allocate the code rate, which helps improve transmission performance. For example, allocating more information bits to sub-blocks with shorter code lengths increases the code rate of the corresponding sub-blocks, resulting in better transmission performance.

[0013] Based on the first and second aspects mentioned above, the following design is proposed:

[0014] In one possible design, the reliability of at least one index in the first bit set is less than the reliability of any index in the rate matching set.

[0015] Typically, shortening or puncturing bits in the rate matching set are mostly located towards the end (i.e., with larger sequence numbers). Therefore, sub-blocks with larger sequence numbers have a greater number of shortening or puncturing bits, resulting in a shorter code length after rate matching. However, the reliability sequence shows that bits with higher reliability are mostly located towards the end (i.e., with larger sequence numbers). In the design described above, the reliability of at least one sequence number in the first bit set is less than the reliability of any sequence number in the rate matching set. Therefore, sub-blocks with smaller sequence numbers have at least one less information bit than sub-blocks with larger sequence numbers. As described earlier, sub-blocks with larger sequence numbers have a shorter code length after rate matching. Thus, the above design can increase the number of information bits in sub-blocks with shorter code lengths, thereby increasing the code rate and information bit reliability of the corresponding sub-blocks, contributing to improved transmission performance.

[0016] For example, taking a mother code length N of 128 and a sub-block encoding matrix of 64, the rate matching set is [79,47,111,31,95,63,127]. It can be seen that the number of shortened or punctured bits in the sub-blocks with sequence numbers ranging from 0 to 63 is 3, and the number of shortened or punctured bits in the sub-blocks with sequence numbers ranging from 64 to 127 is 4. The code length of the sub-blocks with sequence numbers ranging from 0 to 63 after rate matching is greater than that of the sub-blocks with sequence numbers ranging from 64 to 127 after rate matching. Assume the first reliability sequence is [0, 1, 2, 4, 8, 16, 32, 3, 5, 64, 9, 6, 17, 10, 18, 12, 33, 65, 20, 34, 24, 36, 7, 66, 11, 40, 68, 19, 13, 48, 14, 72, 21, 35, 26, 80, 37, 25, 22, 38, 96, 67, 41, 28, 69, 42, 49, 74, 70, 44, 81, 50, 73, 15, 52, 23, 76, 82, 56, 27, 97, 39, 84, 29, 43, 98, 88, 30, 71, 45, 100, 51, 4 6, 75, 104, 53, 77, 54, 83, 57, 112, 78, 85, 58, 99, 86, 60, 89, 101, 31, 90, 102, 105, 92, 47, 106, 55, 113, 79, 108, 59, 114, 87, 116, 61, 91, 120, 62, 103, 93, 107, 94, 109, 115, 110, 117, 118, 121, 122, 63, 124, 95, 111, 119, 123, 125, 126, 127], wherein the first reliability sequence includes bit numbers sorted from low to high. It can be seen that most of the bits with higher reliability in the first reliability ranking have larger sequence numbers. Therefore, by ensuring that the reliability of at least one sequence number in the first bit set is less than the reliability of any sequence number in the rate matching set, the sub-block with sequence number range 0-63 can have at least one less information bit than the sub-block with sequence number range 64-127. As described above, the code length of the sub-block with sequence number range 64-127 after rate matching is relatively small. It can be seen that the number of information bits in the sub-block with smaller code length can be increased.

[0017] In one possible design, at least one index in the rate matching set is not included in the first bit set. Unlike methods that exclude information bits corresponding to the rate matching set when allocating information bits, this method excludes bits corresponding to the first bit set when allocating information bits. Since the reliability of bits corresponding to the first bit set is relatively low, this can improve the reliability of the information bits and thus help improve transmission performance.

[0018] In one possible design, the number of indices in the first bit set that fall within the index range of the i-th sub-block out of I sub-blocks is greater than or equal to the number of indices in the rate-matching set that fall within the index range of the i-th sub-block, where i = {0, 1, ..., I-1}. This method ensures that the number of information bits in each sub-block does not exceed the code length of the rate-matched sub-block, thus improving transmission performance.

[0019] In one possible design, the encoding length of each of the I encoding matrices is M. The sequence number of the i-th sub-block is greater than or equal to i*M and less than (i+1)*M. The number of sequences in the first bit set that are greater than or equal to i*M and less than (i+1)*M is greater than or equal to the number of sequences in the rate-matching set that are greater than or equal to i*M and less than (i+1)*M, where M is an integer greater than 1. This method, when the encoding length of the I sub-blocks is the same, ensures that the number of information bits in each sub-block does not exceed the code length of the rate-matched sub-block, thus improving transmission performance.

[0020] In one possible design, the information bits included in the I sub-blocks consist of: the K most reliable bits (excluding the bits indicated by the first bit set) sorted according to the first reliability from the N bits, where N is the mother code length and K is the total number of information bits in the I sub-blocks; the information bits of the i-th sub-block of the I sub-blocks consist of: the number of bits among the K bits whose index falls within the index range of the i-th sub-block, i = {0, 1, ..., I-1}. This design, by allocating information bits based on the reliability sequence and the first bit set, allows for flexible code length and code rate, and stable performance.

[0021] In one possible design, the first bit set comprises I subsets, where the i-th subset of the I subsets includes A. i A serial number i The value of A is determined based on the rate matching set. i The sequence number is determined based on the rate matching set and the first sequence, i = {0, 1, ..., I-1}. The above design ensures that the number of information bits in each sub-block does not exceed the code length of the rate-matched sub-block, and that the reliability of the pre-frozen bits is relatively low, thereby increasing the reliability of the information bits and improving transmission performance.

[0022] In one possible design, A i The sequence number is A, from back to front of the first sequence. i The value of each sequence number plus B i Definitely, B i It is the index of the first bit of the i-th sub-block in I sub-blocks.

[0023] In one possible design, I encoding matrices correspond to J encoding lengths, and the first sequence comprises J sequences, each corresponding one-to-one with one of the J encoding lengths, where J is an integer greater than 0 and less than or equal to I; wherein the length of the j-th sequence in the first sequence is greater than or equal to M. j / 2,M j Let J be the j-th encoding length among J encoding lengths, where j = {0, 1, ..., J-1}. The above design reduces the configuration overhead of the first bit set by storing a shorter first sequence.

[0024] In one possible design, M j =64, the j-th sequence is [30, 37, 24, 39, 55, 34, 45, 28, 46, 60, 33, 25, 9, 13, 23, 58, 29, 19, 57, 63, 27, 53, 35, 43, 62, 51, 3, 49, 59, 11, 15, 47].

[0025] In one possible design, M j =32, the j-th sequence is [2, 13, 14, 28, 1, 26, 25, 31, 21, 3, 11, 30, 19, 17, 27, 15].

[0026] In one possible design, M j =16, the j-th sequence is [2, 13, 14, 1, 3, 11, 15, 12].

[0027] The above design allows the pre-frozen bit to be placed in a bit with relatively low reliability, thereby helping to improve transmission performance.

[0028] Thirdly, a communication device is provided. The device can implement the method described in any possible implementation of any of the first or second aspects described above. The device possesses the functions of the first or second device described above. The device is, for example, a terminal device, a component or functional module for a terminal device, a network device, or a component or functional module for a network device, etc.

[0029] In one optional implementation, the device may include modules corresponding one-to-one with the methods / operations / steps / actions performed in any possible implementation of any of the first to second aspects. These modules may be hardware circuits, software, or a combination of hardware circuits and software. In another optional implementation, the device includes a processing unit (sometimes also called a processing module) and a communication unit (sometimes also called a transceiver module, communication module, etc.). The transceiver unit is capable of both sending and receiving functions. When the transceiver unit performs the sending function, it may be called a sending unit (sometimes also called a sending module); when the transceiver unit performs the receiving function, it may be called a receiving unit (sometimes also called a receiving module). The sending unit and the receiving unit may be the same functional module, which is called the transceiver unit and can perform both sending and receiving functions; or, the sending unit and the receiving unit may be different functional modules, with the transceiver unit being a collective term for these functional modules.

[0030] For example, when the apparatus is used to perform the method described in any one of the first to second aspects, the apparatus may include a communication unit and a processing unit.

[0031] Fourthly, embodiments of this application also provide a communication device, including a processor, configured to execute a computer program (or computer-executable instructions) and / or, via logic circuitry, cause the device to perform the method as described in any possible implementation of any of the first to second aspects.

[0032] In one possible implementation, the communication device further includes a memory for storing the computer program or instructions.

[0033] In one possible implementation, the processor and memory are integrated together;

[0034] In another possible implementation, the memory is located outside the communication device.

[0035] The communication device also includes a communication interface for communicating with other devices, such as sending or receiving data and / or signals. Exemplarily, the communication interface may be a transceiver, circuit, bus, module, or other type of communication interface.

[0036] In one possible implementation, the communication device is a chip or chip system.

[0037] Fifthly, a computer-readable storage medium is provided for storing a computer program or instructions that, when executed, cause the method described in any possible implementation of any of the first to second aspects, and the method shown in any possible implementation of the first aspect, to be performed.

[0038] A sixth aspect provides a computer program product containing instructions that, when run on a computer, cause the method described in any possible implementation of any of the first to second aspects to be executed.

[0039] In a seventh aspect, embodiments of this application also provide a communication device for performing the execution described in any possible implementation of any of the first to second aspects.

[0040] Eighthly, a chip system is provided, comprising logic circuitry (or, as understood, a processor, which may include logic circuitry, etc.), and further comprising input / output interfaces. The input / output interfaces can be used for inputting information or for outputting information. The input / output interfaces can be the same interface, i.e., the same interface can implement both transmitting and receiving functions; or, the input / output interface includes an input interface and an output interface, the input interface being used to implement the receiving function, i.e., for receiving messages; and the output interface being used to implement the transmitting function, i.e., for transmitting messages. The logic circuitry can be used to perform operations other than the transmitting and receiving functions in any possible implementation of any of the first to second aspects described above; the logic circuitry can also be used to transmit information to the input / output interfaces or receive information from other communication devices from the input / output interfaces. The chip system can be used to implement the methods described in any possible implementation of any of the first to second aspects described above. The chip system can be composed of chips or can include chips and other discrete devices.

[0041] Optionally, the chip system may also include a memory, which can be used to store instructions, and the logic circuits can call the instructions stored in the memory to implement the corresponding functions.

[0042] Ninth aspect, a communication method is provided, which may include the method implemented by a first device as shown in the first aspect and any possible implementation thereof, and the method implemented by a second device as shown in the second aspect and any possible implementation thereof.

[0043] A tenth aspect provides a communication system that may include a first device and a second device. The first device may be used to implement the method shown in the first aspect and any possible implementation thereof, and the second device may be used to implement the method shown in the second aspect and any possible implementation thereof.

[0044] The technical effects brought about by the third to tenth aspects above can be found in the descriptions of the beneficial effects of the corresponding solutions in the first and second aspects above, and will not be repeated here. Attached Figure Description

[0045] Figure 1This is a schematic diagram of the architecture of a communication system applicable to the embodiments of this application;

[0046] Figure 2 This is a schematic diagram of a processing flow for the information source and the information sink in an embodiment of this application;

[0047] Figure 3(a) shows an 8×8 polarization transformation matrix provided in an embodiment of this application;

[0048] Figure 3(b) is a schematic diagram of the serial cancellation decoding calculation process provided in the embodiment of this application;

[0049] Figure 3(c) is a schematic diagram of the decoding path in the serial cancellation list decoding method provided in the embodiments of this application;

[0050] Figure 4 A flowchart illustrating a communication method provided in an embodiment of this application;

[0051] Figure 5 This is a schematic diagram of the structure of a communication device provided in an embodiment of this application;

[0052] Figure 6 This is a schematic diagram of the structure of a communication device provided in an embodiment of this application. Detailed Implementation

[0053] In the embodiments of this application, words such as "exemplarily" and "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design scheme described as an "example" in this application should not be construed as being more preferred or advantageous than other embodiments or design schemes. Specifically, the use of the term "example" is intended to present concepts in a concrete manner. In the embodiments of this application, "of," "relevant," and "corresponding" may sometimes be used interchangeably, and it should be noted that their intended meanings are consistent unless their distinction is emphasized.

[0054] The technical solutions of this application can be applied to various wireless communication systems, such as Universal Mobile Telecommunications System (UMTS), Wireless Local Area Network (WLAN), short-range wireless communication systems (such as sidelink, Wireless Fidelity (Wi-Fi), Bluetooth, etc.), wired networks, vehicle-to-everything (V2X) communication systems, device-to-device (D2D) communication systems, vehicle-to-everything (V2X) communication systems, 4th generation (4G) mobile communication systems (such as Long Term Evolution (LTE) systems), LTE Frequency Division Duplex (FDD) systems, LTE Time Division Duplex (TDD) systems, 5G mobile communication systems (such as New Radio (NR) systems), Future Communications systems, or other similar communication systems, and are not limited thereto. The embodiments of this application use... Figure 1 The communication system shown is used as an example for description. When the technical solutions of the embodiments of this application are applied to other communication systems, the devices, components, modules, etc. in the embodiments can be replaced with corresponding devices, components, modules in other communication systems without limitation.

[0055] Figure 1 This is a schematic diagram of the architecture of the communication system used in the embodiments of this application. Figure 1 As shown, the communication system includes an access network 100. Optionally, the communication system may also include a core network 200 and an Internet 300. The access network 100 may include at least one network device, such as... Figure 1 110a and 110b may also include at least one terminal device, such as Figure 1 The series consists of 120a-120j. Specifically, 110a is a base station, 110b is a micro-station, 120a, 120e, 120f, and 120j are mobile phones, 120b is a car, 120c is a fuel dispenser, 120d is a home access point (HAP) deployed indoors or outdoors, 120g is a laptop, 120h is a printer, and 120i is a drone. The same terminal device or network device can provide different functions in different application scenarios. For example... Figure 1The mobile phones included are 120a, 120e, 120f, and 120j. Mobile phone 120a can access base station 110a, connect to car 120b, communicate directly with mobile phone 120e, and access HAP. Car 120b can access HAP and communicate directly with mobile phone 120a. Mobile phone 120f can connect to micro-station 110b, connect to laptop 120g, and connect to printer 120h. Mobile phone 120j can control drone 120i.

[0056] The communication system provided in this application may also include artificial intelligence (AI) network elements to implement some or all AI-related operations. AI network elements can also be referred to as AI nodes, AI devices, AI entities, AI modules, AI models, or AI units, etc. The AI ​​network elements may be built into the network elements of the communication system. For example, an AI network element may be an AI module built into: access network equipment, core network equipment, cloud servers, or operation, administration, and maintenance (OAM) systems to implement AI-related functions. The OAM system may act as the network management system for core network equipment and / or access network equipment. Alternatively, the AI ​​network element may be an independently configured network element within the communication system. Optionally, the terminal or its built-in chip may also include an AI entity to implement AI-related functions.

[0057] (1) Network equipment

[0058] A network device is a network-side device with wireless transceiver capabilities. A network device can be a device in a radio access network (RAN) that provides wireless communication capabilities to terminal devices; this is called RAN equipment. The RAN can be an access network within the 3rd Generation Partnership Project (3GPP), such as 4G, 5G, or future networks. The RAN can also be an open RAN (O-RAN or ORAN), a cloud radio access network (CRAN), or a communication network combining two or more of these.

[0059] RAN equipment can also be a base station, an evolved NodeB (eNodeB), a transmission reception point (TRP), a next-generation NodeB (gNB) in a 5G mobile communication system, a base station in a future mobile communication system, or an access node in a WiFi system, etc.

[0060] RAN equipment can also be modules or units that perform some of the functions of a base station. For example, it can be a central unit (CU), a distributed unit (DU), or a radio unit (RU). The CU performs the functions of the radio resource control (RRC) and packet data convergence protocol (PDCP) of the base station, and can also perform the functions of the service data adaptation protocol (SDAP). The CU can be further divided into a CU control plane (CP) (i.e., CU-CP) and a CU user plane (UP) (i.e., CU-UP). The DU performs the functions of the radio link control (RLC) layer and medium access control (MAC) layer of the base station, and can also perform some or all of the physical layer functions. For specific descriptions of the above protocol layers, please refer to the relevant 3GPP technical specifications. The CU and DU can be set up separately, or they can be included in the same network element, such as in the baseband unit (BBU). The RU can be included in radio frequency equipment or radio frequency units, such as in a remote radio unit (RRU), an active antenna unit (AAU), or a remote radio head (RRH). In different systems, CU, DU, or RU may have different names, but those skilled in the art will understand their meaning. For example, in an ORAN system, CU can also be called O-CU (open CU), DU can also be called O-DU, and RU can also be called O-RU. Any of the units among CU (or CU-CP, CU-UP), DU, and RU in this application can be implemented through software modules, hardware modules, or a combination of software and hardware modules. RAN equipment can be a macro base station (such as...) Figure 1 110a in the text), can also be a micro base station or an indoor station (such as... Figure 1 In 110b), it can also be a relay node or a donor node, etc. The embodiments of this application do not limit the specific technology or device form used in the network equipment.

[0061] In the embodiments of this application, the functions of the network device can be executed by modules (such as chips) within the network device, or by a control subsystem that includes the functions of the network device. This control subsystem, which includes the functions of the network device, can be a control center in the aforementioned application scenarios such as smart grids, industrial control, intelligent transportation, and smart cities.

[0062] (2) Terminal equipment

[0063] A terminal device is a user-side device with wireless transceiver capabilities. Terminal devices can also be called terminals, user equipment (UE), mobile stations, mobile terminals, etc. Terminal devices can be widely used in various scenarios, such as D2D communication, V2X communication, machine-type communication (MTC), the Internet of Things (IoT), virtual reality, augmented reality, industrial control, autonomous driving, telemedicine, smart grids, smart furniture, smart offices, smart wearables, intelligent transportation, and smart cities. Terminal devices can be mobile phones, tablets, computers with wireless transceiver capabilities, wearable devices, vehicle devices (such as vehicle units, in-vehicle modules, in-vehicle chips, onboard units (OBUs) or telematics boxes (T-BOXs)), drones, helicopters, airplanes, ships, robots, robotic arms, smart home devices, satellite terminals, Internet of Things (IoT) terminals, virtual reality (VR) devices, augmented reality (AR) devices, smart point-of-sale (POS) machines, customer-premises equipment (CPE), light user equipment (UE), reduced capability UE (REDCAP UE), etc. In the embodiments of this application, the device used to implement the functions of the terminal device can be the terminal device itself, or a device capable of supporting the terminal device in implementing that function, such as a chip system or a combination of devices or components capable of implementing the functions of the terminal device. This device can be installed in the terminal device. The embodiments of this application do not limit the specific technology or specific device form used in the terminal device.

[0064] In this embodiment of the application, the functions of the terminal device can also be performed by modules (such as chips or modems) in the terminal device, or by a device containing the functions of the terminal device.

[0065] Network devices and terminal devices can be fixed in location or mobile. They can be deployed on land, including indoors or outdoors, handheld or vehicle-mounted; they can also be deployed on water; and they can also be deployed in the air on airplanes, balloons, and artificial satellites. The embodiments of this application do not limit the application scenarios of the network devices and terminal devices.

[0066] The roles of network devices and terminal devices can be relative, for example, Figure 1 The helicopter or drone 120i can be configured as a mobile network device. For terminal devices 120j that access the wireless access network 100 via 120i, terminal device 120i is a network device; however, for network device 110a, 120i is a terminal device, meaning that 110a and 120i communicate via a wireless air interface protocol. Of course, 110a and 120i can also communicate via a network device-to-network device interface protocol; in this case, 120i is also a network device relative to 110a. Therefore, both network devices and terminal devices can be collectively referred to as communication devices. Figure 1 110a and 110b can be referred to as communication devices with network equipment functions. Figure 1 The 120a-120j in the text can be referred to as communication devices with terminal equipment functions.

[0067] Network devices and terminal devices, network devices and network devices, and terminal devices can communicate through licensed spectrum, unlicensed spectrum, or both simultaneously, without limitation.

[0068] The network architecture and business scenarios described in this application are intended to more clearly illustrate the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided in the embodiments of this application. As those skilled in the art will know, with the evolution of network architecture and the emergence of new business scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0069] The following is an explanation of the relevant terms used in the embodiments of this application. Unless otherwise specified, these explanations are provided to support the meaning of the relevant terms and to make the embodiments of this application easier to understand, and should not be regarded as a strict limitation of the relevant terms within the scope of protection claimed by this application.

[0070] (1) Channel coding and channel decoding

[0071] Figure 2 This is a schematic diagram illustrating a processing flow between the information source and the information sink. For example... Figure 2 As shown, the transmitting end (i.e., the source) obtains the bit sequence to be encoded (i.e., the information bit sequence) through source coding, and then performs channel coding on the bit sequence to be encoded to obtain the encoded bit sequence. Correspondingly, after the receiving end (i.e., the sink) obtains the symbol sequence to be decoded, it performs channel decoding on the symbol sequence to be decoded to obtain the information bit sequence, and then performs source recovery on the information bit sequence to obtain useful information.

[0072] Since source coding does not consider interference resistance, if the bit sequence output from source coding is directly transmitted through the channel, noise interference in the channel will cause bit errors, reducing communication reliability. Therefore, channel coding, which encodes the bit sequence output from source coding again, can improve communication reliability. Channel decoding is the inverse process of channel coding.

[0073] There are various channel coding methods, such as polar coding or LDPC coding. Polar codes were selected as the control channel coding method in the 5G standard. Polar codes are a coding scheme that can be rigorously proven to "achieve" the Shannon channel capacity, and have the advantages of good decoding performance and low complexity. LDPC codes were selected as the data channel coding method in the 5G standard. LDPC codes are linear block codes with a sparse parity-check matrix, exhibiting good performance approaching the Shannon limit, low decoding complexity, and flexible structure.

[0074] (2) Modulation and demodulation

[0075] See Figure 2 As shown, the transmitting end can also map the encoded bit sequence to the modulation symbol sequence, and then transmit the modulation symbol sequence; correspondingly, the receiving end can receive the modulation symbol sequence and then demodulate it to obtain the symbol sequence to be decoded.

[0076] Modulation refers to the process by which the transmitting end maps the encoded bit sequence to a constellation based on a constellation diagram to obtain a modulated symbol sequence. Demodulation is the inverse process of modulation. Common modulation methods include quadrature amplitude modulation (QAM) and amplitude shift keying (ASK) modulation.

[0077] (3) Information bit sequence

[0078] An information bit sequence refers to a sequence of bits to be transmitted. For example, if the bits to be transmitted are 1, 0, 1, 0, 1, 1, 0, 0, 1, 0, 1, then the resulting information bit sequence is 10101100101. In this application, K represents the length of the information bit sequence. The information bits may include payload bits. Optionally, the information bits may also include check bits, such as cyclic redundancy check (CRC) bits.

[0079] (4) Code length

[0080] Code length refers to the length of the bit sequence to be transmitted after encoding the information bit sequence. The code length is greater than or equal to the length of the information bit sequence. In this application, E represents the code length.

[0081] In one possible implementation, the code length can be the length of the sequence obtained by rate matching the encoded bit sequence obtained by encoding the information bit sequence.

[0082] (5) Bitrate

[0083] The code rate is the ratio of the length of the information bit sequence (i.e., the number of information bits) to the code length. In this application, R represents the code rate, therefore R = K / E.

[0084] The length, code length, and code rate of the information bit sequence can be pre-configured by higher-layer signaling, MAC layer signaling, or downlink physical layer signals, and can also be obtained or calculated by the transmitting and receiving devices. For example, the transmitting and receiving devices can determine the code length based on the coding method, the frame structure used to transmit the information bits, the number of layers, and the modulation scheme. For example, the transmitting and receiving devices can obtain the code rate based on higher-layer signaling, MAC layer signaling, or downlink physical layer signals, or determine the code rate based on the modulation and coding scheme (MCS).

[0085] (6) Rate matching

[0086] Rate matching refers to removing some bits from the encoded bit sequence without transmitting them, or repeating some bits.

[0087] The rate matching method will be further explained in three categories below.

[0088] Punching: Punching refers to directly creating holes in certain bit positions within the encoded bit sequence without transmitting them, thus generating bit sequences of arbitrary length. On the decoding side, since there is no information at the corresponding punctured positions, the log-likelihood ratio (LLR) of the corresponding bit is set to 0.

[0089] Shortening: Shortening involves fixing certain bit positions in the encoded bit sequence so that they do not need to be transmitted. On the decoding side, since the corresponding "shortened" positions are known at the receiver (usually 0), the LLR of the corresponding bit is set to infinity.

[0090] Repetition: "Repetition" refers to obtaining a longer bit sequence by repeatedly sending a portion of the encoded bit sequence.

[0091] Taking polar codes as an example, the encoding length (i.e., the mother code length) of a polar code is an integer power of 2. The actual transmission length may be a non-encoded length. In this case, it is necessary to remove some bits from the encoded bit sequence without transmitting them, or to retransmit some bits.

[0092] (7) Polar codes

[0093] (7.1) Polar coding

[0094] Polar codes employ encoding strategies that utilize noiseless channels to transmit useful user information, or utilize noisy channels to transmit agreed-upon information or no information at all. The generator matrix of a polar code is G. N Its encoding process is x1 N =u1 N G N u1 N =(u1,u2,...,u N ) is a binary row vector of length N; x1 N It is the encoded bit sequence (also called codeword), u1 N With the generating matrix G N After multiplication, we get the encoded bit sequence; the multiplication process is the encoding process.

[0095] In one possible implementation, Defined as the Kronecker product of N matrices G2, for example... G N Also known as an Arikan polarization nucleus of length N or a canonical polarization nucleus.

[0096] It can be considered that, with the Arikan polar kernel, a polar code of length N can be obtained by coupling two polar codes of length N / 2. Furthermore, a polar code of length N / 2 can be considered as obtained by coupling two polar codes of length N / 4, and so on. With the Arikan polar kernel, SC decoding of a polar code of length N can be completed on the decoding side using Nlog(N) f operations and Nlog(N) g operations.

[0097] Another type of polarization kernel is the non-regular polarization kernel. The non-regular polarization kernel is constructed by arranging the polarization trellis connection method according to the channel state or the specific number of information bits K. It can accelerate polarization without increasing decoding complexity. The size of the coding matrix corresponding to the non-regular polarization kernel can be N*N, where N is the code length, and the value of N does not have to be an integer power of 2. The non-regular polarization kernel can be associated with the information bit length K; that is, the connection method of the N*N non-regular polarization kernel can be variable for different information bit lengths. For example, the coding matrix of the non-regular polarization kernel when N=5 and K=2 can be:

[0098]

[0099] Therefore, compared to regular polarization kernels, non-regular polarization kernels can select the connection method according to the information bit length K to improve the reliability of K information bits, thereby achieving better coding error correction performance. In this application, the size of the coding matrix can refer to the dimension of the coding matrix, that is, the number of rows and columns of the coding matrix.

[0100] During the encoding process of polar codes, u1 N A portion of the bits are used to carry information, called the information bit set, and the set of indices of these bits is denoted as A; the other portion of the bits are set to fixed values ​​agreed upon in advance by the receiver and the transmitter, called the fixed bit set or frozen bit set, and the set of its bit indices is denoted by the complement of A, denoted as A'. c These freeze bits are typically set to 0, but they can be set arbitrarily as long as the receiver and sender agree in advance.

[0101] Currently, in NR, the frozen bits and information bits of the polar code are determined based on the reliability sequence corresponding to the mother code length. The reliability sequence corresponding to the mother code length can be calculated offline to reduce the encoding complexity. The mother code length is an integer power of 2, which is the length of the bit sequence after polar code encoding; the mother code length can also be called the encoding length. Taking a mother code length of 8 as an example, assuming the reliability sequence is [0 1 2 4 3 5 6 7], the reliability of the bits from highest to lowest is: the bit corresponding to bit number 7, the bit corresponding to bit number 6, the bit corresponding to bit number 5, the bit corresponding to bit number 3, the bit corresponding to bit number 4, the bit corresponding to bit number 2, the bit corresponding to bit number 1, and the bit corresponding to bit number 0. Here, a bit can be understood as a bit sub-channel. The bit number can be understood as the index or identifier of the bit. For example, when constructing a polar code with a master code length of 8 and an information length of 4, the bits corresponding to bit number 7, bit number 6, bit number 5, and bit number 3 are selected from the end to the beginning as information bits, while the bits corresponding to bit number 4, bit number 2, bit number 1, and bit number 0 are selected as frozen bits.

[0102] Figure 3(a) shows an 8×8 polarization transformation matrix, where the left side can be understood as the side to be encoded, and the bits on the left are represented by u. The right side can be understood as the encoding side (or codeword side), and the bits on the right are represented by x. The process from left to right is the process of the transmitter encoding the bit sequence to be encoded. The information bits to be encoded are represented by the sequence u(0, 0, 0, 0, 0, 0, 1, 1). After the polarization transformation matrix, the encoded bits are represented by the sequence x(0, ​​1, 0, 1, 0, 1, 0, 1). Then, x is mapped to a modulation symbol for transmission in channel W. The bits corresponding to high channel reliability are used to map information bits, and the bits corresponding to low channel reliability are used to map frozen bits. As shown in Figure 3(a), {u0, u1, u2, u4} are frozen bits, i.e., the positions of frozen bits, and {u3, u5, u6, u7} are information bits, i.e., the positions of information bits. In this embodiment, information bits are also called information bits, and frozen bits are also called frozen bits.

[0103] Referring to Figure 3(a), in the encoding process, two adjacent columns constitute a coding layer. The left column of bits represents the input bits of the coding layer, and the right column represents the output bits. For example, in the leftmost coding layer, the input bit sequence is (0, 0, 0, 0, 0, 0, 1, 1), and the output bit sequence is (0, 0, 0, 0, 0, 0, 0, 1). The operation symbols in the middle of the coding layer... This represents the XOR operation, specifically... express The bits in the current row and An XOR operation between the bits in the same row. The bits on the right represent the result of the operation. For example, in the leftmost coding layer, the first input bit (value 0) and the second input bit (value 0) are processed... The operation yields the first output bit (with a value of 0).

[0104] (7.2) Polarization Decoding

[0105] There are several methods for decoding polar codes, such as SC decoding and successive cancellation list (SCL) decoding.

[0106] The SC decoding method refers to calculating the LLR of each decoded bit sequentially based on the LLR sequence corresponding to the bit sequence to be decoded, and making a bit-by-bit decision. When the decoded bit is an information bit, if the LLR of the decoded bit is greater than 0, then the decoded bit is 0; if the LLR of the decoded bit is less than 0, then the decoded bit is 1. When the decoded bit is a fixed bit, the decoding result is set to 0 regardless of the LLR value. Figure 3(b) is a schematic diagram of the SC decoding calculation process. Taking 4 decoded bits as an example, there are 8 calculation nodes in Figure 3(b), including 4 f nodes and 4 g nodes. The f nodes and g nodes correspond to the f operation and the g operation, respectively. The operation of the f node requires the two LLR inputs on its right side, and the operation of the g node requires the two LLR inputs on its right side and the output of the previous stage as inputs. Only after the input items are calculated can the output be calculated. According to the above calculation rules, the decoded bits obtained by calculating sequentially from the right side in Figure 3(b) are ①→②→③→④, and the decoding is completed.

[0107] The SCL decoding method refers to using the LLR sequence corresponding to the bit sequence to be decoded. When decoding each information bit, the decoding results corresponding to 0 and 1 are saved as two branch decoding paths (referred to as path splitting). Figure 3(c) shows a schematic diagram of the decoding paths in the SCL decoding method. As shown in Figure 3(c), each level represents one decoded bit. If the decoding result is 0, the path is developed along the left subtree; if the decoding result is 1, the path is developed along the right subtree. When the total number of decoding paths exceeds the preset path width L (generally L = 2, 4, 8, 16, or 32), the L paths with the best path metric (PM) value are selected, saved, and the path is further developed to decode subsequent bits. The PM value is used to judge the quality of the path, and the PM value is calculated using LLR. For each level of decoded bits, the PM values ​​of the L paths are sorted in ascending order, and the correct path is selected based on the PM value. This process is repeated until the last bit is decoded.

[0108] Currently, channel coding of polar codes can be performed by coupling short codes with long codes. For example, a 64-bit nonregular polar kernel can be constructed using four 16-bit sub-blocks, and a 64-bit codeword can be constructed based on this kernel. Alternatively, a 60-bit codeword can be constructed using four 15-bit sub-blocks. However, different code lengths and information bit counts correspond to different coding matrices; therefore, determining the appropriate number of information bits for each sub-block is a crucial problem to be solved.

[0109] To address the aforementioned issues, this application provides corresponding solutions.

[0110] The methods provided in the embodiments of this application are described in detail below. The methods provided in the embodiments of this application involve a first communication device and / or a second communication device. The first communication device is a signal transmitter, and the second communication device is a signal receiver. Unless otherwise specified, the term "first communication device" in this application can refer to a communication device (e.g., a network device, a terminal device, an encoding device, etc.), a component within that communication device (e.g., a processor, a chip, or a chip system, etc.), or a logic module or software capable of implementing all or part of the functions of the communication device. Similarly, the term "second communication device" in this application can refer to a communication device (e.g., a terminal device, a network device, a decoding device, etc.), a component within that communication device (e.g., a processor, a chip, or a chip system, etc.), or a logic module or software capable of implementing all or part of the functions of the communication device. For example, the first communication device may be a network device, and the second communication device may be a terminal device; or, the first communication device may be a terminal device, and the second communication device may be a network device.

[0111] In this application, the coding matrix can also be referred to as a non-regular kernel, a non-regular polarization kernel, etc.

[0112] The encoding length of a sub-block is the same as the encoding length of the encoding matrix corresponding to the sub-block. In the following text, the encoding length of a sub-block and the encoding length of the encoding matrix corresponding to the sub-block can be described interchangeably.

[0113] Figure 4 This is a flowchart illustrating a communication method provided in an embodiment of this application. The method includes the following steps:

[0114] S401, the first communication device determines the first bit set based on the rate matching set and the first sequence.

[0115] The rate matching set includes the index of at least one bit. For example, the rate matching set includes the index of at least one shortened or puncturing bit.

[0116] The first sequence includes at least one bit of index. The indexes in the first sequence are ordered in a specific sequence.

[0117] The first bit set includes the index of at least one bit. For example, the first bit set may include the indexes corresponding to I sub-blocks, where I is an integer greater than 1. For instance, the first bit set includes I subsets, where no two subsets overlap. These I subsets correspond one-to-one with the I sub-blocks. The i-th subset among the I subsets includes A... i Let there be a sequence number, i = {0, 1, ..., I-1}, A i It is an integer greater than or equal to 0.

[0118] The rate matching set, the first sequence, and the first bit set are introduced below.

[0119] 1. Rate matching set

[0120] In one possible implementation, the first communication device can determine the rate matching set based on the mother code length N, where N is an integer power of 2. Optionally, the mother code length N can be determined based on the encoded code length E, for example, N is greater than or equal to... For example, E=5, N=8; E=180, N=256, etc.

[0121] For example, the first communication device can determine the rate matching set by bit reversal shortening. For instance, the rate matching set includes the last NE bits of the bit reversal sequence. The value at the k-th position of the bit reversal sequence is... Where m = log(N), Let k be the binary representation of k. For example, when N=8, the bit reversal sequence is BR=[0,4,2,6,1,5,3,7]. When E=5, the rate matching set is the last 3 bits of BR [5,3,7].

[0122] One example is E=121, N=128, and the rate matching set is the last 7 bits of a 128-length bit reverse sequence [79,47,111,31,95,63,127].

[0123] The above method can obtain multiple sub-block code lengths that are not integer powers of 2 by shortening the bits in reverse order (that is, the coding length of the sub-block minus the number of rate-matching bits), thereby improving the performance gain of channel coding.

[0124] 2. First sequence

[0125] As described above, the first bit set may include the sequence numbers corresponding to the I sub-blocks. The first sequence can be used to determine the sequence number corresponding to each of the I sub-blocks in the first bit sequence.

[0126] In one exemplary embodiment, the first sequence may include one or more sequences, wherein one sequence may correspond to one code length. For example, I code matrices correspond to J code lengths (i.e., M0, M1, ..., M...). J-1 The first sequence includes J sequences, each of which corresponds one-to-one with a J encoding length, where J is an integer greater than 0 and not greater than 1.

[0127] In one example, J = 1, meaning that the encoding lengths of the aforementioned I sub-blocks are the same (e.g., M0, M1, ..., M...). J-1 If each of the I sub-blocks is equal to M, the first sequence includes a sequence. In this implementation, the sequences corresponding to the I sub-blocks are the same, or it can be understood that this sequence is used to determine the sequence number of each sub-block in the first bit sequence. The above method can reduce the encoding complexity.

[0128] In another example, J > 1, meaning the aforementioned I sub-blocks correspond to at least two encoding lengths, and the first sequence includes at least two sequences. In this implementation, the encoding length M... j This corresponds to the j-th sequence in the first sequence, or it can be understood as the j-th sequence being used to determine the encoding length M in the I sub-blocks. j The sub-block corresponds to the index in the first bit sequence. j = {0, 1, ..., J-1}.

[0129] Taking J=2 as an example, the I sub-blocks include at least one sub-block with a coding length of M0 and at least one sub-block with a coding length of M1. The first sequence includes sequence 0 and sequence 1, where coding length M0 corresponds to sequence 0, or can be understood as sequence 0 being used to determine the sequence number of the sub-block with coding length M0 in the first bit sequence. Coding length M1 corresponds to sequence 1, or can be understood as sequence 1 being used to determine the sequence number of the sub-block with coding length M1 in the first bit sequence.

[0130] The specific method for determining the sequence number of the sub-block in the first bit sequence will be introduced in the relevant description of the first bit set.

[0131] Optionally, the length of the j-th sequence in the first sequence can be greater than or equal to M. j / 2. The above method reduces the configuration overhead of the first bit set by storing a shorter first sequence.

[0132] Below are three examples of the j-th sequence.

[0133] With M j For example, with a value of 64, the j-th sequence can be [30, 37, 24, 39, 55, 34, 45, 28, 46, 60, 33, 25, 9, 13, 23, 58, 29, 19, 57, 63, 27, 53, 35, 43, 62, 51, 3, 49, 59, 11, 15, 47].

[0134] With M j For example, with a value of 32, the j-th sequence is [2, 13, 14, 28, 1, 26, 25, 31, 21, 3, 11, 30, 19, 17, 27, 15].

[0135] With M j For example, if the sequence is 16, the j-th sequence is [2, 13, 14, 1, 3, 11, 15, 12].

[0136] It should be noted that if the encoding lengths of the aforementioned I sub-blocks are the same, then M in the above three examples... j Alternatively, it can be replaced with M, where the j-th sequence can be replaced with the first sequence. That is, the encoding length of each of the I sub-blocks is M. When M = 64, the first sequence is M. j =64 corresponds to the j-th sequence; when M=32, the first sequence is M. j =32 corresponds to the j-th sequence; when M=16, the first sequence is M. j =16 corresponds to the j-th sequence.

[0137] It should be understood that the above examples are merely illustrative. In specific implementations, the first sequence may also include some of the sequence elements in the above examples, or the first sequence may include more sequence elements based on the above examples, or the first sequence may be a variation of the above examples, and so on.

[0138] 3. First bit sequence

[0139] In one possible implementation, as described above, the first bit set may include I subsets, and the i-th subset includes A i The number of indices in the first bit set that fall within the index range of the i-th sub-block out of the I sub-blocks (i.e., A) i The number of indices greater than or equal to the number of indices within the range of the i-th sub-block in the rate-matching set. This method ensures that the number of information bits in each sub-block does not exceed the code length of the rate-matched sub-block, thus improving transmission performance.

[0140] Taking I coding matrices with the same coding length M as an example, the sequence number range of the i-th sub-block is greater than or equal to i*M and less than (i+1)*M. The number of sequence numbers in the first bit set that are greater than or equal to i*M and less than (i+1)*M is greater than or equal to the number of sequence numbers in the rate matching set that are greater than or equal to i*M and less than (i+1)*M.

[0141] I coding matrices correspond to J coding lengths (i.e., M0, M1, ..., M). J-1 Taking J>1 as an example, the sequence number of the i-th sub-block is greater than or equal to 1. and less than Among them, H a Let H be the encoding length of the a-th sub-block, where H is the encoding length of the a-th sub-block. a The value of is {M0, M1, ..., M}. J-1 One of the bits in the first bit set. (The first bit set is greater than or equal to...) and less than The number of serial numbers (that is, A) i (greater than or equal to) in the rate matching set and less than The number of serial numbers.

[0142] The following is based on the number of indices within the range of the i-th sub-block in the I sub-blocks of the first bit set (i.e., A). i Taking the number of indices in the range of the i-th sub-block in the rate matching set as an example, we introduce how to determine the first bit sequence.

[0143] For the i-th sub-block, the number A of the corresponding sequence numbers of this sub-block in the first bit set i This can be determined based on a set of rate matches. For example, Ai The value of Ai can be the number of the sequence numbers in the range of the sequence numbers in the i-th sub-block of the rate matching set. Alternatively, it can be understood that the first communication device can determine the value of Ai based on the number of the sequence numbers in the range of the sequence numbers in the i-th sub-block of the rate matching set.

[0144] For example, with a mother code length of N = 128 and E = 121, the rate matching set is [79, 47, 111, 31, 95, 63, 127]. Assume I = 2, and the encoding length of each of the I sub-blocks is 64, i.e., M = 64. The sequence number range corresponding to the 0th sub-block is greater than or equal to 0 and less than 64, i.e., 0 to 63. The sequence number range corresponding to the 1st sub-block is greater than or equal to 64 and less than 128, i.e., 64 to 127. Based on the above rate matching set, the number of sequence numbers corresponding to the 0th sub-block in the first bit set, A0, is 3, and the number of sequence numbers corresponding to the 1st sub-block in the first bit set, A1, is 4.

[0145] Taking a mother code length of N=128 and E=121 as an example, the rate matching set is [79, 47, 111, 31, 95, 63, 127]. Assume I=4, the coding length of each of the I sub-blocks is 32, i.e., M=32. The sequence number range corresponding to the 0th sub-block is greater than or equal to 0 and less than 32, i.e., 0 to 31. The sequence number range corresponding to the 1st sub-block is greater than or equal to 32 and less than 64, i.e., 32 to 63. The sequence number range corresponding to the 2nd sub-block is greater than or equal to 64 and less than 96, i.e., 64 to 95. The sequence number range corresponding to the 3rd sub-block is greater than or equal to 96 and less than 128, i.e., 96 to 127. Based on the above rate matching set, the number of sequence numbers corresponding to the 0th sub-block in the first bit set is A0 = 1, the number of sequence numbers corresponding to the 1st sub-block in the first bit set is A1 = 2, the number of sequence numbers corresponding to the 2nd sub-block in the first bit set is A2 = 2, and the number of sequence numbers corresponding to the 3rd sub-block in the first bit set is A3 = 2.

[0146] Taking a mother code length of N=128 and E=121 as an example, the rate matching set is [79, 47, 111, 31, 95, 63, 127]. Assume I=8, the coding length of each of the I sub-blocks is 16, i.e., M=16. The sequence number range corresponding to the 0th sub-block is greater than or equal to 0 and less than 16, i.e., 0~15. The sequence number range corresponding to the 1st sub-block is greater than or equal to 16 and less than 32, i.e., 16~31. The sequence number range corresponding to the 2nd sub-block is greater than or equal to 32 and less than 48, i.e., 32~48. 7. The sequence number range corresponding to the 3rd sub-block is greater than or equal to 48 and less than 64, i.e., 48 to 63. The sequence number range corresponding to the 4th sub-block is greater than or equal to 64 and less than 80, i.e., 64 to 79. The sequence number range corresponding to the 5th sub-block is greater than or equal to 80 and less than 96, i.e., 80 to 95. The sequence number range corresponding to the 6th sub-block is greater than or equal to 96 and less than 112, i.e., 96 to 111. The sequence number range corresponding to the 7th sub-block is greater than or equal to 112 and less than 128, i.e., 112 to 127. Based on the aforementioned rate matching set, the number of sequence numbers corresponding to the 0th sub-block in the first bit set is A0 = 0, the number of sequence numbers corresponding to the 1st sub-block in the first bit set is A1 = 1, the number of sequence numbers corresponding to the 2nd sub-block in the first bit set is A2 = 1, the number of sequence numbers corresponding to the 3rd sub-block in the first bit set is A3 = 1, the number of sequence numbers corresponding to the 4th sub-block in the first bit set is A0 = 1, the number of sequence numbers corresponding to the 5th sub-block in the first bit set is A1 = 1, the number of sequence numbers corresponding to the 6th sub-block in the first bit set is A2 = 1, and the number of sequence numbers corresponding to the 7th sub-block in the first bit set is A3 = 1.

[0147] For the i-th sub-block, the specific sequence number (i.e., Ai sequence numbers) corresponding to this sub-block in the first bit set can be determined based on the rate matching set and the first sequence. For example, the number A of sequence numbers corresponding to the i-th sub-block in the first bit set can be determined based on the rate matching set. i And determine A based on the first sequence. i Serial number.

[0148] In one alternative approach, A i The sequence number can be A from back to front of the first sequence. i The value of each sequence number plus B i Definitely, B iLet be the index of the first bit of the i-th sub-block. The Ai indices from back to front in the first sequence can also be understood as the Ai indices from front to back in the reverse sequence of the first sequence. An alternative description is that the Ai indices can be determined by adding Bi to the values ​​of the Ai indices from front to back (or the first Ai indices) in the second sequence. The second sequence is obtained by reversing the order of the indices in the first sequence; that is, the second sequence is the reverse sequence of the first sequence. Specific examples can be derived by referring to the three examples of the first sequence, and will not be elaborated further here.

[0149] For example, taking a mother code length of N = 128 and E = 121 as an example, the rate matching set is [79, 47, 111, 31, 95, 63, 127]. Assuming I = 2, the encoding length of each of the I sub-blocks is 64, i.e., M = 64, and the first sequence is [30, 37, 24, 39, 55, 34, 45, 28, 46, 60, 33, 25, 9, 13, 23, 58, 29, 19, 57, 63, 27, 53, 35, 43, 62, 51, 3, 49, 59, 11, 15, 47]. According to the previous description, the number of sequence numbers corresponding to the 0th sub-block in the first bit set, A0, is 3. Therefore, the Ai sequence numbers corresponding to the 0th sub-block in the first bit set are the last 3 bits of the first sequence, i.e., [11, 15, 47]. The number of sequence numbers A1 corresponding to the first sub-block in the first bit set is 4. Therefore, the Ai sequence numbers corresponding to the first sub-block in the first bit set are the last 3 bits of the first sequence plus the sequence number 64 of the first bit of the first sub-block, i.e., [59, 11, 15, 47] + 64 = [123, 75, 79, 111]. Therefore, the first bit set includes [11, 15, 47, 123, 75, 79, 111].

[0150] Taking a mother code length of N=128 and E=121 as an example, the rate matching set is [79, 47, 111, 31, 95, 63, 127]. Assuming I=4, the encoding length of each of the I sub-blocks is 32, i.e., M=32. The first sequence is [2, 13, 14, 28, 1, 26, 25, 31, 21, 3, 11, 30, 19, 17, 27, 15]. According to the previous description, the number of sequence numbers corresponding to the 0th sub-block in the first bit set is A0, which is 1. Therefore, the Ai sequence numbers corresponding to the 0th sub-block in the first bit set are the last 1 bit of the first sequence, i.e.,

[15] . The number of sequence numbers corresponding to the 1st sub-block in the first bit set is A1, which is 2. Therefore, the Ai sequence numbers corresponding to the 1st sub-block in the first bit set are the last 2 bits of the first sequence plus the sequence number 32 of the first bit of the 1st sub-block, i.e., [27, 15] + 32 = [59, 47]. The second sub-block has 2 corresponding sequence numbers (A1). Therefore, the Ai corresponding sequence numbers of the second sub-block in the first bit set are the last two bits of the first sequence plus the sequence number 64 of the first bit of the second sub-block, i.e., [27, 15] + 64 = [91, 79]. The third sub-block has 2 corresponding sequence numbers (A1). Therefore, the Ai corresponding sequence numbers of the third sub-block in the first bit set are the last two bits of the first sequence plus the sequence number 96 of the first bit of the third sub-block, i.e., [27, 15] + 96 = [123, 111]. Therefore, the first bit set includes [15, 59, 47, 91, 79, 123, 111].

[0151] Taking the mother code length N=128 and E=121 as an example, the rate matching set is [79, 47, 111, 31, 95, 63, 127]. Assuming I=8, the coding length of each of the I sub-blocks is 16, i.e., M=16, and the first sequence is [2, 13, 14, 1, 3, 11, 15, 12]. According to the previous description, the number of sequence numbers corresponding to the 0th sub-block in the first bit set is A0, therefore, the number of sequence numbers corresponding to the 0th sub-block in the first bit set is none, that is, the 0th sub-block has no corresponding sequence number in the first bit set. The number of sequence numbers corresponding to the 1st sub-block in the first bit set is A1, therefore, the number of sequence numbers corresponding to the 1st sub-block in the first bit set is the last bit of the first sequence plus the sequence number 16 of the first bit of the 1st sub-block, i.e.,

[12] +16=

[28] . The number of sequence numbers corresponding to the second sub-block in the first bit set is A1 = 1. Therefore, the Ai sequence numbers corresponding to the second sub-block in the first bit set are the last bit of the first sequence plus the sequence number 32 of the first bit of the second sub-block, i.e.,

[12] + 32 =

[44] . The number of sequence numbers corresponding to the third sub-block in the first bit set is A1 = 1. Therefore, the Ai sequence numbers corresponding to the third sub-block in the first bit set are the last bit of the first sequence plus the sequence number 48 of the first bit of the third sub-block, i.e.,

[12] + 48 =

[60] . The number of sequence numbers corresponding to the fourth sub-block in the first bit set is A1 = 1. Therefore, the Ai sequence numbers corresponding to the fourth sub-block in the first bit set are the last bit of the first sequence plus the sequence number 64 of the first bit of the fourth sub-block, i.e.,

[12] + 64 =

[76] . The number of sequence numbers corresponding to the 5th sub-block in the first bit set is A1 = 1. Therefore, the Ai sequence numbers corresponding to the 5th sub-block in the first bit set are the last bit of the first sequence plus the sequence number 80 of the first bit of the 5th sub-block, i.e.,

[12] + 80 =

[92] . The number of sequence numbers corresponding to the 6th sub-block in the first bit set is A1 = 1. Therefore, the Ai sequence numbers corresponding to the 6th sub-block in the first bit set are the last bit of the first sequence plus the sequence number 96 of the first bit of the 6th sub-block, i.e.,

[12] + 96 =

[108] . The number of sequence numbers corresponding to the 7th sub-block in the first bit set is A1 = 1. Therefore, the Ai sequence numbers corresponding to the 7th sub-block in the first bit set are the last bit of the first sequence plus the sequence number 112 of the first bit of the 7th sub-block, i.e.,

[12] + 112 =

[124] . Therefore, the first bit set includes [28, 44, 60, 76, 92, 108, 124].

[0152] As can be seen from the examples above, at least one index in the rate matching set is not included in the first bit set in this application. For example, in the examples where M=64 and M=32, the rate matching set includes indices 31, 95, 63, and 127, but the first bit set does not include indices 31, 95, 63, and 127. In the example where M=16, all indices of the rate matching set, 79, 47, 111, 31, 95, 63, and 127, are not included in the first bit set. Unlike methods that exclude information bits corresponding to the rate matching set when allocating information bits, the above method excludes bits corresponding to the first bit set when allocating information bits. Since the reliability of bits corresponding to the first bit set is relatively low, this method can improve the reliability of information bits and help improve transmission performance.

[0153] Furthermore, as can be seen from the examples above, the reliability corresponding to at least one index in the first bit set is less than the reliability corresponding to any index in the rate matching set. For example, in the examples where M=64 and M=32, the rate matching set is [79, 47, 111, 31, 95, 63, 127], and the first bit set is [11, 15, 47, 123, 75, 79, 111]. Combining this with the first reliability ranking below, it can be seen that the reliability of indices 11, 15, and 75 in the first bit set is less than the reliability of [79, 47, 111, 31, 95, 63, 127]. In the example where M=16, the rate matching set is [79, 47, 111, 31, 95, 63, 127], and the first bit set is [28, 44, 60, 76, 92, 108, 124]. Combining this with the first reliability ranking below, it can be seen that the reliability of indices 28, 44, 60, and 76 in the first bit set is less than the reliability of [79, 47, 111, 31, 95, 63, 127].

[0154] Typically, shortening or puncturing bits in the rate matching set are mostly located towards the end (i.e., with larger sequence numbers). Therefore, sub-blocks with larger sequence numbers have more shortening or puncturing bits, resulting in a shorter code length after rate matching. However, the reliability sequence shows that bits with higher reliability are mostly located towards the end (i.e., with larger sequence numbers). In the design described above, the reliability of at least one sequence number in the first bit set is lower than the reliability of any sequence number in the rate matching set. Therefore, sub-blocks with smaller sequence numbers have at least one less information bit than sub-blocks with larger sequence numbers. As described earlier, sub-blocks with larger sequence numbers have a shorter code length after rate matching. Thus, the above design can increase the number of information bits in sub-blocks with shorter code lengths, thereby improving the code rate and information bit reliability of the corresponding sub-blocks, contributing to improved transmission performance.

[0155] For example, taking a mother code length N of 128 and a sub-block encoding matrix of 64, the rate matching set is [79,47,111,31,95,63,127]. It can be seen that the number of shortened or punctured bits in the sub-blocks with sequence numbers ranging from 0 to 63 is 3, and the number of shortened or punctured bits in the sub-blocks with sequence numbers ranging from 64 to 127 is 4. The code length of the sub-blocks with sequence numbers ranging from 0 to 63 after rate matching is greater than that of the sub-blocks with sequence numbers ranging from 64 to 127 after rate matching. Assume the first reliability sequence is [0, 1, 2, 4, 8, 16, 32, 3, 5, 64, 9, 6, 17, 10, 18, 12, 33, 65, 20, 34, 24, 36, 7, 66, 11, 40, 68, 19, 13, 48, 14, 72, 21, 35, 26, 80, 37, 25, 22, 38, 96, 67, 41, 28, 69, 42, 49, 74, 70, 44, 81, 50, 73, 15, 52, 23, 76, 82, 56, 27, 97, 39, 84, 29, 43, 98, 88, 30, 71, 45, 100, 51, 4 6, 75, 104, 53, 77, 54, 83, 57, 112, 78, 85, 58, 99, 86, 60, 89, 101, 31, 90, 102, 105, 92, 47, 106, 55, 113, 79, 108, 59, 114, 87, 116, 61, 91, 120, 62, 103, 93, 107, 94, 109, 115, 110, 117, 118, 121, 122, 63, 124, 95, 111, 119, 123, 125, 126, 127], wherein the first reliability sequence includes bit numbers sorted from low to high. It can be seen that most of the bits with higher reliability in the first reliability ranking have larger sequence numbers. Therefore, by ensuring that the reliability of at least one sequence number in the first bit set is less than the reliability of any sequence number in the rate matching set, the sub-block with sequence number range 0-63 can have at least one less information bit than the sub-block with sequence number range 64-127. As described above, the code length of the sub-block with sequence number range 64-127 after rate matching is relatively small. It can be seen that the number of information bits in the sub-block with smaller code length can be increased.

[0156] S402, the first communication device determines the number of information bits in I sub-blocks based on the first bit set and the first reliability sequence, where I is an integer greater than 1.

[0157] The first reliability sequence includes bit indices sorted by reliability from low to high or from high to low. The length of the first reliability sequence is N, or the length of the first reliability sequence is an integer power of 2 greater than N.

[0158] In one example, the information bits included in I sub-blocks consist of: the K most reliable bits (excluding the bits indicated by the first bit set) sorted according to the first reliability sequence from N bits, where K is the total number of information bits in the I sub-blocks. The information bits of the i-th sub-block of the I sub-blocks consist of: the number of bits among the K bits whose index falls within the index range of the i-th sub-block. The index range of the i-th sub-block can be found in the previous explanation of the index range of the i-th sub-block in the first bit set, and will not be repeated here.

[0159] The following explanation uses the first reliability sequence, which includes bit numbers sorted from low to high reliability, as an example.

[0160] For example, assuming N = 128, the first reliability sequence is [0, 1, 2, 4, 8, 16, 32, 3, 5, 64, 9, 6, 17, 10, 18, 12, 33, 65, 20, 34, 24, 36, 7, 66, 11, 40, 68, 19, 13, 48, 14, 72, 21, 35, 26, 80, 37, 25, 22, 38, 96, 67, 41, 28, 69, 42, 49, 74, 70, 44, 81, 50, 73, 15, 52, 23, 76, 82, 56, 27, 97, 39, 84, 29, 43, 98, 88]. 30, 71, 45, 100, 51, 46, 75, 104, 53, 77, 54, 83, 57, 112, 78, 85, 58, 99, 86, 60, 89, 101, 31, 90, 102, 105, 92, 47, 106, 55, 113, 79, 108, 59, 114, 87, 116, 61, 91, 120, 62, 103, 93, 107, 94, 109, 115, 110, 117, 118, 121, 122, 63, 124, 95, 111, 119, 123, 125, 126, 127).

[0161] Taking I sub-blocks as two sub-blocks with a coding length of 64 as an example, the first bit set is [11, 15, 47, 123, 75, 79, 111]. Assuming K = 40, the information bits included in I sub-blocks are 128 bits, excluding the 40 bits with the highest reliability from the first bit set, specifically including [99, 86, 60, 89, 101, 31, 90, 102, 105, 92, 106, 55, 113, 108, 59, 114, 87, 116, 61, 91, 120, 62, 103, 93, 107, 94, 109, 115, 110, 117, 118, 121, 122, 63, 124, 95, 119, 125, 126, 127].

[0162] The information bits of the 0th sub-block include [31, 60, 55, 59, 61, 62, 63], and the number of information bits is 7.

[0163] The information bits of the first sub-block include [99, 86, 89, 101, 90, 102, 105, 92, 106, 113, 108, 114, 87, 116, 91, 120, 103, 93, 107, 94, 109, 115, 110, 117, 118, 121, 122, 124, 95, 119, 125, 126, 127], and the number of information bits is 33.

[0164] Taking I sub-blocks as four sub-blocks with a coding length of 32 as an example, the first bit set includes [15, 59, 47, 91, 79, 123, 111]. Assuming K = 40, the information bits included in I sub-blocks include [85, 58, 99, 86, 60, 89, 101, 31, 90, 102, 105, 92, 106, 55, 113, 108, 114, 87, 116, 61, 120, 62, 103, 93, 107, 94, 109, 115, 110, 117, 118, 121, 122, 63, 124, 95, 119, 125, 126, 127].

[0165] The information bits of the 0th sub-block include

[31] , and the number of information bits is 1.

[0166] The information bits of the first sub-block include [58, 60, 55, 61, 62, 63], and the number of information bits is 6.

[0167] The information bits of the second sub-block include [85, 86, 89, 90, 92, 87, 93, 94, 95], and the number of information bits is 9.

[0168] The information bits of the third sub-block include [99, 101, 102, 105, 106, 113, 108, 114, 116, 120, 103, 107, 109, 115, 110, 117, 118, 121, 122, 124, 119, 125, 126, 127], and the number of information bits is 24.

[0169] Taking I sub-blocks as an example, which consist of eight sub-blocks with a coding length of 16, the first bit set includes [28, 44, 60, 76, 92, 108, 124]. Assuming K = 40, the information bits included in I sub-blocks are [99, 86, 89, 101, 31, 90, 102, 105, 47, 106, 55, 113, 79, 59, 114, 87, 116, 61, 91, 120, 62, 103, 93, 107, 94, 109, 115, 110, 117, 118, 121, 122, 63, 95, 111, 119, 123, 125, 126, 127].

[0170] The number of information bits in the 0th sub-block is 0.

[0171] The information bits of the first sub-block include

[31] , and the number of information bits is 1.

[0172] The information bits of the second sub-block include

[47] , and the number of information bits is 1.

[0173] The information bits of the third sub-block include [55, 59, 61, 62, 63], and the number of information bits is 5.

[0174] The information bits of the 4th sub-block include

[79] , and the number of information bits is 1.

[0175] The information bits of the 5th sub-block include [86, 89, 90, 87, 91, 93, 94, 95], and the number of information bits is 8.

[0176] The information bits of the 6th sub-block include [99, 101, 102, 105, 106, 103, 107, 109, 110, 111], and the number of information bits is 10.

[0177] The information bits of the 7th sub-block include [113, 114, 116, 120, 115, 117, 118, 121, 122, 119, 123, 125, 126, 127], and the number of information bits is 14.

[0178] S403, the first communication device determines I coding matrices based on the number of information bits in I sub-blocks.

[0179] Optionally, the first communication device can determine I coding matrices based on the code length (i.e., the coding length minus the number of rate-matched bits) and the number of information bits after I sub-block rate matching. For example, the coding matrix corresponding to the code length and the number of information bits can be determined by looking up a table.

[0180] For example, in the case of M=64 above, the number of information bits in the 0th sub-block is 7, and the code length after rate matching is 61. The number of information bits in the 1st sub-block is 33, and the code length after rate matching is 60.

[0181] In the example above where M=32, the number of information bits in the 0th sub-block is 1, and the code length after rate matching is 31. The number of information bits in the 1st sub-block is 6, and the code length after rate matching is 30. The number of information bits in the 2nd sub-block is 9, and the code length after rate matching is 30. The number of information bits in the 3rd sub-block is 24, and the code length after rate matching is 30.

[0182] In the example above where M=16, the 0th sub-block has 0 information bits, and the code length after rate matching is 16. The 1st sub-block has 1 information bit, and the code length after rate matching is 15. The 2nd sub-block has 1 information bit, and the code length after rate matching is 15. The 3rd sub-block has 5 information bits, and the code length after rate matching is 15. The 4th sub-block has 1 information bit, and the code length after rate matching is 15. The 5th sub-block has 8 information bits, and the code length after rate matching is 15. The 6th sub-block has 10 information bits, and the code length after rate matching is 15. The 7th sub-block has 14 information bits, and the code length after rate matching is 15.

[0183] S404, the first communication device encodes according to I encoding matrices to obtain the first bit sequence.

[0184] In one possible implementation, the first communication device can couple I encoding matrices to obtain a first encoding matrix, and encode according to the first encoding matrix to obtain a first bit sequence.

[0185] For example, the first encoding matrix G in this application N It can satisfy:

[0186]

[0187] Among them, G a Let G represent an encoding matrix of size a*a. N-a Let P represent a coding matrix of size (Na)*(Na). When a ≤ Na, P is a coding matrix of size G. N-a The s1,…,s a A matrix consisting of columns s1,…,s a All are positive integers less than or equal to Na. When a > Na, the s1,…,s-th elements of P are... N-a The matrix composed of columns is G N-a ,s1,…,s N-a All are positive integers less than or equal to a.

[0188] Optionally, when I = 2, G a G can be the first coding matrix among I coding matrices, and the value of 'a' can be the coding length of the first coding matrix among I coding matrices. N-a Let Na be the second coding matrix in the I coding matrices. The value of Na can be the coding length of the second coding matrix in the I coding matrices.

[0189] When I = 4, G a It can be obtained by coupling the first two coding matrices out of I coding matrices, and the value of 'a' can be the sum of the coding lengths of the first two coding matrices out of I coding matrices. G N-a The value of Na is obtained by coupling the last two coding matrices out of the I coding matrices. Na can be the sum of the coding lengths of the last two coding matrices out of the I coding matrices. The coupling method mentioned above can be found in Formula 1, and will not be explained further here.

[0190] When I = 8, G a It can be obtained by coupling the first two coding matrices out of four, and the value of 'a' can be the sum of the coding lengths of the first two coding matrices out of four. G N-a The value of Na is obtained by coupling the last four coding matrices in I coding matrices. Na can be the sum of the coding lengths of the last two coding matrices in the four coding matrices. Specifically, the first coding matrix is ​​obtained by coupling the first and second coding matrices in the I coding matrices; the second coding matrix is ​​obtained by coupling the third and fourth coding matrices in the I coding matrices; the third coding matrix is ​​obtained by coupling the fifth and sixth coding matrices in the I coding matrices; and the fourth coding matrix is ​​obtained by coupling the seventh and eighth coding matrices in the I coding matrices. The coupling methods described above can be found in Formula 1 and will not be elaborated further here.

[0191] By analogy, we can obtain the first encoding matrix when I = 16, 32, etc.

[0192] In another possible implementation, I sub-blocks can be encoded using I encoding matrices, and then the encoding results of the I sub-blocks can be coupled to obtain the first bit sequence. Optionally, the encoding results of the I sub-blocks can also adopt the coupling method of the I encoding matrices described above, as detailed above, and will not be elaborated here.

[0193] Optionally, in step S405, the first communication device transmits a first bit sequence. Correspondingly, the second communication device receives first information. The first information is the information obtained after the first bit sequence has been transmitted through the channel.

[0194] S406, the second communication device determines the first bit set based on the rate matching set and the first sequence.

[0195] The second communication device determines the first bit set in the same way as the first communication device, as described in the previous S401 description, and will not be repeated here.

[0196] S407, the second communication device determines the number of information bits in I sub-blocks based on the first bit set and the first reliability sequence, where I is an integer greater than 1.

[0197] The second communication device determines the number of information bits of I sub-blocks in the same way as the first communication device determines the number of information bits of I sub-blocks. For details, please refer to the relevant description in S402 above, and it will not be repeated here.

[0198] S408, the second communication device determines I coding matrices based on the number of information bits in I sub-blocks.

[0199] The second communication device determines the I encoding matrices in the same way as the first communication device determines the I encoding matrices. For details, please refer to the relevant description in S403 above, and it will not be repeated here.

[0200] It should be noted that this application does not limit the execution order of S406 to S408 and S405. S406 to S408 can be executed before S405, after S405, or simultaneously with S405.

[0201] S409, the second communication device decodes according to I coding matrices.

[0202] For example, the second communication device can couple I encoding matrices to obtain an encoding matrix, and then perform decoding based on that encoding matrix.

[0203] Optionally, the second communication device can decode the first information based on I encoding matrices.

[0204] In this application, the information bit allocation for each sub-block is obtained based on the reliability sequence and the first sequence, which allows for nested code length and code rate, resulting in stable performance. Furthermore, under regularized kernel polar codes, the number of information bits allocated within a sub-block of code length M-1 is less than that allocated within a sub-block of code length M. This application uses a non-regular kernel to improve the transmission performance of code blocks with sub-code lengths that are not powers of 2. Moreover, the information bit allocation method provided in this application can increase the number of information bits in a sub-block of code length M-1, thus contributing to improved transmission performance.

[0205] Based on the same concept as the method embodiments, this application provides a communication device, the structure of which can be as follows: Figure 5 As shown, it includes a processing module 501, and optionally, a communication module 502.

[0206] In one embodiment, the communication device can specifically be used to implement Figure 4 In the embodiments, the method executed by the first communication device can be the communication device itself (e.g., network device, terminal device, encoding device, etc.), or a chip or chipset in the communication device, or a part of the chip for performing related method functions. Specifically, the processing module 501 determines a first bit set based on a rate matching set and a first sequence, wherein the rate matching set includes at least one bit index, the first bit set includes at least one bit index, and the first sequence includes at least one bit index; determines the number of information bits in I sub-blocks based on the first bit set and a first reliability sequence, where I is an integer greater than 1; determines the I encoding matrices based on the number of information bits in the I sub-blocks; and performs encoding based on the I encoding matrices.

[0207] Optionally, the communication module 502 can be used to send the encoded results of the processing module 501.

[0208] In one embodiment, the communication device can specifically be used to implement Figure 4 In the embodiments, the method executed by the second communication device can be the communication device itself (e.g., network device, terminal device, encoding device, etc.), or a chip or chipset in the communication device, or a part of the chip used to perform related method functions. Specifically, the processing module 501 determines a first bit set based on a rate matching set and a first sequence, wherein the rate matching set includes at least one bit index, the first bit set includes at least one bit index, and the first sequence includes at least one bit index; determines the number of information bits in I sub-blocks based on the first bit set and a first reliability sequence, where I is an integer greater than 1; determines the I encoding matrices based on the number of information bits in the I sub-blocks; and performs decoding based on the I encoding matrices.

[0209] Optionally, the communication module 502 can be used to receive the first information. The processing module 501, when decoding according to the I encoding matrices, can specifically be used to decode the first information according to the I encoding matrices.

[0210] The module division in this application embodiment is illustrative and represents only one logical functional division. In actual implementation, other division methods may be used. Furthermore, the functional modules in the various embodiments of this application can be integrated into a single processor, exist as separate physical entities, or be integrated into a single module. The integrated modules described above can be implemented in hardware or as software functional modules. It is understood that the functions or implementations of the modules in the embodiments of this application can be further described in the relevant descriptions of the method embodiments.

[0211] In one possible approach, the communication device can be as follows: Figure 6 As shown, the device can be a communication device or a chip within a communication device, wherein the communication device can be the terminal device in the above embodiments or the network device in the above embodiments. The device includes a processor 601 and a communication interface 602, and may also include a memory 603. The processing module 501 can be the processor 601. The communication module 502 can be the communication interface 602.

[0212] The processor 601 can be a CPU, a digital processing unit, or something similar. The communication interface 602 can be a transceiver, an interface circuit such as a transceiver circuit, or a transceiver chip, etc. The device also includes a memory 603 for storing the program executed by the processor 601. The memory 603 can be non-volatile memory, such as a hard disk drive (HDD) or a solid-state drive (SSD), or it can be volatile memory, such as random-access memory (RAM). The memory 603 can be any other medium capable of carrying or storing desired program code in the form of instructions or data structures that can be accessed by a computer, but is not limited to this.

[0213] The processor 601 is used to execute the program code stored in the memory 603, specifically to perform the actions of the aforementioned processing module 501, which will not be described in detail here. The communication interface 602 is specifically used to perform the actions of the aforementioned communication module 502, which will not be described in detail here.

[0214] This application embodiment does not limit the specific connection medium between the communication interface 602, processor 601, and memory 603. This application embodiment... Figure 6 The memory 603, processor 601, and communication interface 602 are connected via a bus 604. Figure 6The connections between other components are shown in bold lines only and are not intended to be limiting. Buses can be categorized as address buses, data buses, control buses, etc. For ease of illustration, Figure 6 The bus is represented by a single thick line, but this does not mean that there is only one bus or one type of bus.

[0215] This application also provides a computer-readable storage medium for storing computer software instructions required to execute the processor, including a program required to execute the processor.

[0216] This application also provides a communication system, including... Figure 4 In the embodiments, the first communication device and Figure 4 The second communication device in the embodiment.

[0217] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0218] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to this application. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0219] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0220] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0221] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A communication method, characterized in that, include: A first bit set is determined based on a rate matching set and a first sequence, wherein the rate matching set includes at least one bit index, the first bit set includes at least one bit index, and the first sequence includes at least one bit index. The number of information bits in I sub-blocks is determined based on the first bit set and the first reliability sequence, where I is an integer greater than 1; I encoding matrices are determined based on the number of information bits in the I sub-blocks; Encode according to the I encoding matrices.

2. A communication method, characterized in that, include: A first bit set is determined based on a rate matching set and a first sequence, wherein the rate matching set includes at least one bit index, the first bit set includes at least one bit index, and the first sequence includes at least one bit index. The number of information bits in I sub-blocks is determined based on the first bit set and the first reliability sequence, where I is an integer greater than 1; I encoding matrices are determined based on the number of information bits in the I sub-blocks; Decoding is performed based on the I encoding matrices.

3. The method as described in claim 1 or 2, characterized in that, The reliability of at least one index in the first bit set is less than the reliability of any index in the rate matching set.

4. The method according to any one of claims 1-3, characterized in that, At least one sequence number in the rate matching set is not included in the first bit set.

5. The method according to any one of claims 1-4, characterized in that, The number of indexes in the first bit set that fall within the index range of the i-th sub-block in the I sub-blocks is greater than or equal to the number of indexes in the rate matching set that fall within the index range of the i-th sub-block, where i = {0, 1, ..., I-1}.

6. The method as described in claim 5, characterized in that, The encoding length of each of the I encoding matrices is M. The sequence number of the i-th sub-block is greater than or equal to i*M and less than (i+1)*M. The number of sequence numbers greater than or equal to i*M and less than (i+1)*M in the first bit set is greater than or equal to the number of sequence numbers greater than or equal to i*M and less than (i+1)*M in the rate matching set. M is an integer greater than 1.

7. The method according to any one of claims 1-6, characterized in that, The information bits included in the I sub-blocks include: The K most reliable bits after removing the bits indicated by the first bit set from N bits and sorting them according to the first reliability, where N is the length of the mother code and K is the total number of information bits in the I sub-blocks; The information bits of the i-th sub-block of the I sub-blocks include: the number of bits whose sequence number is within the sequence number range of the i-th sub-block among the K bits, where i = {0, 1, ..., I-1}.

8. The method according to any one of claims 1-7, characterized in that, The first bit set includes I subsets, and any two subsets in the I subsets have no intersection; Among them, the i-th subset of the I subsets includes A i A serial number, the A i The value of A is determined based on the rate matching set. i The sequence number is determined based on the rate matching set and the first sequence, where i = {0, 1, ..., I-1}.

9. The method as described in claim 8, characterized in that, The A i The sequence number is A, which is the first sequence from back to front. i The value of each sequence number plus B i It is confirmed that the B i It is the sequence number of the first bit of the i-th sub-block among the I sub-blocks.

10. The method according to any one of claims 1-9, characterized in that, The I encoding matrices correspond to J encoding lengths, the first sequence includes J sequences, and the J sequences correspond one-to-one with the J encoding lengths, where J is an integer greater than 0 and less than or equal to I; Wherein, the length of the j-th sequence in the first sequence is greater than or equal to M. j / 2, the M j Let j be the j-th encoding length among the J encoding lengths, where j = {0, 1, ..., J-1}.

11. The method as described in claim 10, characterized in that, M j =64, the j-th sequence is [30, 37, 24, 39, 55, 34, 45, 28, 46, 60, 33, 25, 9, 13, 23, 58, 29, 19, 57, 63, 27, 53, 35, 43, 62, 51, 3, 49, 59, 11, 15, 47].

12. The method as described in claim 10, characterized in that, M j =32, and the j-th sequence is [2, 13, 14, 28, 1, 26, 25, 31, 21, 3, 11, 30, 19, 17, 27, 15].

13. The method as described in claim 10, characterized in that, M j =16, and the j-th sequence is [2, 13, 14, 1, 3, 11, 15, 12].

14. A communication device, characterized in that, Includes units or modules for performing the method as described in any one of claims 1, 3-13.

15. A communication device, characterized in that, Includes units or modules for performing the method as described in any one of claims 2-13.

16. A communication device, characterized in that, Includes a processor configured to cause the communication device to implement the method as described in any one of claims 1, 3-13 by executing computer programs or instructions, and / or by logic circuitry.

17. The communication device according to claim 16, characterized in that, Includes a memory for storing the computer program or instructions.

18. The communication device according to claim 16 or 17, characterized in that, It also includes a communication interface for communicating with other devices.

19. A communication device, characterized in that, Includes a processor configured to cause the communication device to implement the method as described in any one of claims 2-13 by executing computer programs or instructions, and / or by logic circuitry.

20. The communication device according to claim 19, characterized in that, Includes a memory for storing the computer program or instructions.

21. The communication device according to claim 19 or 20, characterized in that, It also includes a communication interface for communicating with other devices.

22. A computer-readable storage medium, characterized in that, The storage medium stores a computer program or instructions, which, when executed by a communication device, implement the method as described in any one of claims 1, 3-13, or the method as described in any one of claims 2-13.

23. A computer program product, characterized in that, When the computer program product is executed by a computer, it causes the method as described in any one of claims 1, 3-13 or the method as described in any one of claims 2-13 to be performed.

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