A method, apparatus, device, and system for data processing

Abstract

The embodiment of the application discloses a data processing method, device and system, the method comprises: sending or acquiring W pieces of dual-polarization symbol streams, wherein each dual-polarization symbol stream comprises a plurality of superframes, in any one polarization direction, each subframe of each superframe comprises one pilot symbol in every continuous N PG symbols, W and N PG are integers greater than 1; in one transmission period, the position interval of pilot symbols in any two dual-polarization symbol streams in the W pieces of dual-polarization symbol streams is K times of (N PG / W), and K is a positive integer not equal to an integer multiple of W. When joint subcarrier recovery processing is performed at a receiving end, the pilot symbol interval used for carrier phase recovery processing is reduced compared to the traditional N PG , and the anti-dispersion capability is further improved, and the phase noise tolerance is better.

Description

Technical Field

[0001] This application relates to the field of communication technology, and in particular to a method, apparatus, device and system for data processing. Background Technology

[0002] Driven by 5G, cloud computing, big data, and artificial intelligence, high-speed optical transmission networks are developing towards higher capacity, packetization, and intelligence. Coherent optical communication systems utilize the amplitude, phase, polarization, or frequency of light waves to carry information. To combat optical signal distortion caused by dispersion, polarization-related impairments, noise, nonlinear effects, and other factors during transmission and to maintain long-distance transmission, coherent optical communication systems typically frame the sequence of symbols to be transmitted before sending them. This involves adding some pre-designed symbol sequences to make it easier for the receiver to recover the transmitted symbols.

[0003] Current transmission schemes are mainly used in single-carrier transmission scenarios of 400 gigabits per second (Gbps) or 800 Gbps, and cannot adapt to future scenarios using multi-subcarrier transmission. For example, there is 800 Gbps multi-subcarrier transmission using quadrature phase shift keying (QPSK) modulation, 1.2 terabits per second (Tbps) multi-subcarrier transmission using quadrature amplitude modulation (QAM), and 1.6 Tbps multi-subcarrier transmission using 16QAM modulation. Summary of the Invention

[0004] This application provides a data processing method, apparatus and system, and presents a processing scheme for multi-subcarrier transmission, which is beneficial to improving the quality of the recovered signal at the receiving end and can be applied to high-speed coherent transmission scenarios such as 1.2T and 1.6T.

[0005] In a first aspect, embodiments of this application provide a data processing method, comprising: performing delay processing on at least one of the acquired W first dual-polarization symbol streams to obtain a total of W dual-polarization symbol streams to be transmitted, wherein each of the W first dual-polarization symbol streams includes multiple superframes, and in any polarization direction, every consecutive N in each subframe of each superframe PG The symbol includes a pilot symbol, W and N. PG All are integers greater than 1; the delay value corresponding to a first dual-polarization symbol stream after delay processing is K×(N PG / W) double polarization symbols, where K is a positive integer not equal to an integer multiple of W.

[0006] Secondly, a data processing method is provided, the method comprising: acquiring W second dual-polarization symbol streams, wherein the W second dual-polarization symbol streams are obtained by delaying at least one of the W first dual-polarization symbol streams from the W first dual-polarization symbol streams; each of the W first dual-polarization symbol streams comprises multiple superframes, and in any polarization direction, every consecutive N in each subframe of each superframe... PG The symbol includes a pilot symbol, W and N. PG All are integers greater than 1; the delay value corresponding to a first dual-polarization symbol stream after delay processing is K×(N PG / W) double polarization symbols, where K is a positive integer not equal to an integer multiple of W.

[0007] It should be understood that if multiple dual-polarized symbol streams are delayed, the delay values ​​corresponding to the multiple dual-polarized symbol streams can be the same or different; for example, if W = 4, and two first dual-polarized symbol streams are delayed, then both first dual-polarized symbol streams can be delayed by (N). PG / 4) dual-polarization symbols; or a first dual-polarization symbol stream delayed by (N) PG / 4) dual-polarization symbols, the other first dual-polarization symbol stream is delayed by 2×(N) PG / 4) dual polarization symbols, which are not limited in this application.

[0008] In this embodiment, among the W dual-polarization symbol streams to be transmitted, in any polarization direction, there will always be at least one dual-polarization symbol stream in which the interval between each pilot symbol and any two adjacent pilot symbols in other dual-polarization symbol streams is less than N. PG The number of symbols. When the receiver performs joint subcarrier recovery processing, the pilot symbol spacing used for carrier phase recovery processing can be considered to be compared with the traditional N. PG It has been reduced to a certain extent, further improving the anti-dispersion capability and phase noise tolerance.

[0009] In conjunction with the first or second aspect, in a first possible implementation, the delay processing of at least one of the W first dual-polarized symbol streams specifically includes: delaying the first dual-polarized symbol stream i in the W first dual-polarized symbol streams by processing it ... i A dual-polarization symbol, M i =(N PG / W)×i+N PG ×a, where a is an integer.

[0010] It should be understood that the value of 'a' can be 0. In this case, the delay value corresponding to the delay processing 'i' is M. i A dual-polarization symbol, M i =(N PG For example, with W=2, there are two dual-polarized symbol streams, where i takes values ​​of 0 and 1. The delay value corresponding to delay processing 0 is 0 dual-polarized symbols, meaning the first dual-polarized symbol stream 0 does not undergo delay processing. The delay value corresponding to delay processing 1 is N. PG / 2 dual-polarization symbols, that is, a delay of N for the first dual-polarization symbol stream. PG / 2 double polarization symbols. Of course, a can also be other values, for example, a=2. Taking W=2 as an example, in this case, the delay value corresponding to delay processing 0 is 2×N. PG One double-polarized symbol, that is, a 0-delay of 2×N for the first double-polarized symbol stream. PG Each dual-polarization symbol has a delay value of N corresponding to delay processing 1. PG / 2+2×N PG One dual-polarization symbol, that is, a delay of N for the first dual-polarization symbol stream 1. PG / 2+2×N PG A double polarization symbol.

[0011] In this embodiment, each dual-polarization symbol stream undergoes different delay processing, or only one dual-polarization symbol stream is not delayed, while the other dual-polarization symbol streams undergo different delay processing. This ensures that, in any polarization direction, the interval between each pilot symbol in any adjacent dual-polarization symbol stream and any two adjacent pilot symbols in any other dual-polarization symbol stream is less than N. PG The number of symbols. When the receiver performs joint subcarrier recovery processing, the pilot symbol spacing used for carrier phase recovery processing can be considered to be compared with the traditional N. PG It has been reduced to a certain extent, further improving the anti-dispersion capability and phase noise tolerance.

[0012] Combining the first or second aspect and the first possible implementation mentioned above, in the second possible implementation, W is 2 and N is N. PG It is 64.

[0013] In conjunction with the second possible implementation described above, in the third possible implementation, at least one of the W first dual-polarization symbol streams is delayed to obtain a total of W dual-polarization symbol streams to be sent. Specifically, this includes delaying the first dual-polarization symbol stream 1 by 32 dual-polarization symbols to obtain the second dual-polarization symbol stream 1. The first dual-polarization symbol stream 0 is not delayed. The two dual-polarization symbol streams to be sent include the first dual-polarization symbol stream 0 and the second dual-polarization symbol stream 1.

[0014] In this embodiment, in any polarization direction, the interval between each pilot symbol in the second dual-polarization symbol stream 1 and its two adjacent pilot symbols is 64 symbols, and the interval between each pilot symbol and its two adjacent pilot symbols in the second dual-polarization symbol stream 0 is 32 symbols. This is less than the traditional 64 symbols. When the receiver performs joint subcarrier recovery processing, the interval between pilot symbols used for carrier phase recovery processing can be considered to be halved from the traditional 64 symbols to 32 symbols, further improving anti-dispersion capability and phase noise tolerance. The data processing scheme provided in this embodiment can be applied to future scenarios using multi-subcarrier transmission, such as 800Gbps multi-subcarrier transmission using QPSK modulation, 1.2Tbps multi-subcarrier transmission using 16QAM modulation, 1.6Tbps multi-subcarrier transmission using 16QAM modulation, and even higher speed transmission scenarios such as 2.4T / 3.2T.

[0015] Combining the first or second aspect and the first possible implementation mentioned above, in the fourth possible implementation, W is 4 and N is... PG It is 64.

[0016] In conjunction with the fourth possible implementation described above, in the fifth possible implementation, at least one of the W acquired first dual-polarization symbol streams is delayed to obtain a total of W dual-polarization symbol streams to be sent. Specifically, this includes: delaying the first dual-polarization symbol stream 1 by 16 dual-polarization symbols to obtain the second dual-polarization symbol stream 1; delaying the first dual-polarization symbol stream 2 by 32 dual-polarization symbols to obtain the second dual-polarization symbol stream 2; and delaying the first dual-polarization symbol stream 3 by 48 dual-polarization symbols to obtain the second dual-polarization symbol stream 3. The first dual-polarization symbol stream 0 is not delayed. The four dual-polarization symbol streams to be sent include the first dual-polarization symbol stream 0, the second dual-polarization symbol stream 1, the second dual-polarization symbol stream 2, and the second dual-polarization symbol stream 3.

[0017] In this embodiment, the interval between pilot symbols in two adjacent second dual-polarization symbol streams is 16 symbols in any polarization direction, which is less than the traditional 64 symbols. When the receiver performs joint subcarrier recovery processing, the interval between pilot symbols used for carrier phase recovery processing can be considered to be reduced from the traditional 64 symbols to one-quarter, i.e., 16 symbols, further improving anti-dispersion capability and phase noise tolerance. The data processing scheme provided in this embodiment can be applied to future scenarios using multi-subcarrier transmission, such as 800Gbps multi-subcarrier transmission using QPSK modulation, 1.2Tbps multi-subcarrier transmission using 16QAM modulation, 1.6Tbps multi-subcarrier transmission using 16QAM modulation, and even higher speed transmission scenarios such as 2.4T / 3.2T.

[0018] In conjunction with the first or second aspect and the above possible implementations, in the sixth possible implementation, the first dual-polarization symbol stream i includes an X-polarization symbol stream i and a Y-polarization symbol stream i; the delay processing i of the first dual-polarization symbol stream i in the W first dual-polarization symbol streams specifically includes: performing symbol delay processing i on the X-polarization symbol stream i and the Y-polarization symbol stream i respectively, wherein the delay value corresponding to the symbol delay processing i is M. i A symbol.

[0019] In conjunction with the first or second aspect and the above possible implementations, in the seventh possible implementation, the first dual-polarization symbol stream i includes a data stream XI-i of the I-path component in the X-polarization direction, a data stream XQ-i of the Q-path component in the X-polarization direction, a symbol stream YI-i of the I-path component in the Y-polarization direction, and a symbol stream YQ-i of the Q-path component in the Y-polarization direction; the delay processing i of the first dual-polarization symbol stream i in the W first dual-polarization symbol streams specifically includes: performing component delay processing XI-i on the data stream XI-i of the I-path component in the X-polarization direction, wherein the delay value corresponding to the component delay processing XI-i is M. i The I-path component of each dual-polarization symbol in the X-polarization direction; the Q-path component data stream XQ-i in the X-polarization direction is subjected to component delay processing XQ-i, where the delay value corresponding to component delay processing XQ-i is M. i The data stream YI-i of the dual-polarization symbols in the X-polarization direction is divided into Q-path components; the data stream YI-i of the I-path components in the Y-polarization direction is subjected to component delay processing YI-i, where the delay value corresponding to the component delay processing YI-i is M. i The data stream YQ-i of the dual-polarization symbols in the Y-polarization direction is divided into I-path components; the data stream YQ-i of the Q-path components in the Y-polarization direction is subjected to component delay processing YQ-i, where the delay value corresponding to the component delay processing YQ-i is M. i The Q-path component of a double-polarized symbol in the Y-polarization direction.

[0020] Combining the first or second aspect and the aforementioned possible implementations, in the eighth possible implementation, the W dual-polarization symbol streams to be transmitted are each carried on W subcarriers. These W subcarriers are multiplexed to obtain a single signal for transmission. In this case, the baud rate corresponding to each subcarrier is 1 / W of the transmitted signal baud rate. This scheme reduces the complexity of dispersion compensation, reduces the cost of equalization enhancement phase noise, and results in lower DSP power consumption.

[0021] In conjunction with the first or second aspect and the above possible implementations, in the ninth possible implementation, the dual polarization symbol is a dual polarization 16QAM symbol or a dual polarization QPSK symbol.

[0022] Thirdly, a data processing method is provided, the method comprising: delaying at least one of the acquired W first bit streams to obtain a total of W second bit streams, wherein the delay value corresponding to one of the delayed first bit streams is K×(N). PG / W) bit blocks, W and N PG All are integers greater than 1, and K is a positive integer not equal to an integer multiple of W; the obtained W second bit streams are subjected to dual-polarization symbol mapping to obtain W dual-polarization symbol streams, wherein each bit group is mapped to a dual-polarization symbol; each of the W dual-polarization symbol streams includes multiple superframes, and in any polarization direction, every consecutive N bits in each subframe of each superframe... PG Each symbol includes a pilot symbol.

[0023] Fourthly, a data processing method is provided, the method comprising: acquiring W dual-polarization symbol streams, wherein each of the W dual-polarization symbol streams includes multiple superframes, and in any polarization direction, every consecutive N subframes in each superframe... PG The symbol includes a pilot symbol, W and N. PG All are integers greater than 1; the W dual-polarization symbol streams are obtained by the transmitting end performing dual-polarization symbol mapping on the W second bit streams respectively, and the W second bit streams are obtained by the transmitting end performing delay processing on at least one of the acquired W first bit streams; wherein, the delay value corresponding to the first bit stream after delay processing is K×(N PG / W) bit blocks, where K is a positive integer not equal to an integer multiple of W; each bit block is mapped to a dual-polarization symbol.

[0024] It should be understood that if multiple first bitstreams are delayed, the delay values ​​corresponding to the multiple first bitstreams can be the same or different; for example, if W = 4, and two first bitstreams are delayed, then both first bitstreams can be delayed by (N). PG / 4) bit blocks; or a first bit stream delayed by (N) PG / 4) bit packets, the other first bit stream is delayed by 2×(N) PG / 4) bits are grouped together, but this application does not limit this to a specific number.

[0025] In this embodiment, each bit group is mapped to a dual-polarization symbol. Therefore, in any polarization direction, among the W dual-polarization symbol streams, there will always be at least one dual-polarization symbol stream where the interval between each pilot symbol and any two adjacent pilot symbols in other dual-polarization symbol streams is less than N. PGThe number of symbols. When the receiver performs joint subcarrier recovery processing, the pilot symbol spacing used for carrier phase recovery processing can be considered to be compared with the traditional N. PG It has been reduced to a certain extent, further improving the anti-dispersion capability and phase noise tolerance.

[0026] In conjunction with the third or fourth aspect, in the first possible implementation, the delay processing of at least one of the acquired W first bit streams specifically includes: delaying the first bit stream i in the W first bit streams by processing it ... i A bit block, M i =(N PG / W)×i+N PG ×a, where a is an integer.

[0027] It should be understood that the value of 'a' can be 0. In this case, the delay value corresponding to the delay processing 'i' is M. i A bit block, M i =(N PG For example, with W=2, there are two first bit streams, where i takes values ​​of 0 and 1. The delay value corresponding to delay processing 0 is 0 bit blocks, meaning that first bit stream 0 does not undergo delay processing, and the delay value corresponding to delay processing 1 is N. PG / 2 bits per group, that is, delaying the first bit stream by N. PG / 2 bits per group. Of course, 'a' can also be other values, for example, 'a=2'. Still using W=2 as an example, in this case, the delay value corresponding to delay processing 0 is 2×N. PG Each bit is grouped into 2 × N bits, meaning the first bit stream is delayed by 0. PG A bit group, with a delay value of N corresponding to delay processing 1. PG / 2+2×N PG A bit group, that is, a delay of N bits from the first bit stream. PG / 2+2×N PG Bits are grouped together.

[0028] In this embodiment, each bit group is mapped to a dual-polarization symbol. Therefore, each dual-polarization symbol stream undergoes different delay processing, or only one dual-polarization symbol stream is not delayed, while the others undergo different delay processing. This ensures that, in any polarization direction, the interval between each pilot symbol in any adjacent dual-polarization symbol stream and any two adjacent pilot symbols in other dual-polarization symbol streams is less than N. PG The number of symbols. When the receiver performs joint subcarrier recovery processing, the pilot symbol spacing used for carrier phase recovery processing can be considered to be compared with the traditional N.PG It has been reduced to a certain extent, further improving the anti-dispersion capability and phase noise tolerance.

[0029] Combining the third or fourth aspect and the first possible implementation mentioned above, in the second possible implementation, W is 2 and N. PG It is 64.

[0030] In conjunction with the second possible implementation described above, in the third possible implementation, at least one of the W first bit streams is delayed to obtain a total of W second bit streams. Specifically, this includes delaying the first bit stream 1 by 32 bits to obtain the second bit stream 1, wherein the first bit stream 0 is not delayed, and the two second bit streams include the first bit stream 0 and the second bit stream 1.

[0031] In this embodiment, each bit group is mapped to a dual-polarization symbol. Therefore, in any polarization direction, the interval between each pilot symbol in dual-polarization symbol stream 1 and its two adjacent pilot symbols is 64 symbols, and the interval between each pilot symbol and its two adjacent pilot symbols in dual-polarization symbol stream 0 is 32 symbols, which is less than the traditional 64. When the receiver performs joint subcarrier recovery processing, the interval of the pilot symbols used for carrier phase recovery processing can be considered to be halved from the traditional 64 symbols to 32 symbols, further improving anti-dispersion capability and phase noise tolerance. The data processing scheme provided in this embodiment can be applied to future scenarios using multi-subcarrier transmission, such as 800Gbps multi-subcarrier transmission using QPSK modulation, 1.2Tbps multi-subcarrier transmission using 16QAM modulation, 1.6Tbps multi-subcarrier transmission using 16QAM modulation, and even higher speed transmission scenarios such as 2.4T / 3.2T.

[0032] Combining the third or fourth aspect with the first possible implementation mentioned above, in the fourth possible implementation, W is 4 and N is... PG It is 64.

[0033] In conjunction with the fourth possible implementation described above, in the fifth possible implementation, at least one of the W first bitstreams is delayed to obtain a total of W second bitstreams. Specifically, this includes: delaying the first bitstream 1 by 16 bits to obtain the second bitstream 1; delaying the first bitstream 2 by 32 bits to obtain the second bitstream 2; and delaying the first bitstream 3 by 48 bits to obtain the second bitstream 3. The first bitstream 0 is not delayed. The four second bitstreams include the first bitstream 0, the second bitstream 1, the second bitstream 2, and the second bitstream 3.

[0034] In this embodiment, each bit group is mapped to a dual-polarization symbol. Therefore, in any polarization direction, the interval between pilot symbols in two adjacent dual-polarization symbol streams is 16 symbols, less than the traditional 64 symbols. When the receiver performs joint subcarrier recovery processing, the interval between pilot symbols used for carrier phase recovery processing can be considered to be reduced from the traditional 64 symbols to one-quarter, i.e., 16 symbols, further improving anti-dispersion capability and phase noise tolerance. The data processing scheme provided in this embodiment can be applied to future scenarios using multi-subcarrier transmission, such as 800Gbps multi-subcarrier transmission using QPSK modulation, 1.2Tbps multi-subcarrier transmission using 16QAM modulation, 1.6Tbps multi-subcarrier transmission using 16QAM modulation, and even higher speed transmission scenarios such as 2.4T / 3.2T.

[0035] Combining the third or fourth aspect and the aforementioned possible implementations, in the sixth possible implementation, the W dual-polarization symbol streams are each carried on W subcarriers. These W subcarriers are multiplexed to obtain a single signal for transmission. In this case, the baud rate corresponding to each subcarrier is 1 / W of the transmitted signal baud rate. This scheme reduces the complexity of dispersion compensation, lowers the cost of equalization enhancement phase noise, and results in lower DSP power consumption.

[0036] In combination with the third or fourth aspect and the above possible implementations, in the seventh possible implementation, the dual-polarization symbol is a dual-polarization 16QAM symbol, and the bit group includes 8 bits; or the dual-polarization symbol is a dual-polarization QPSK symbol, and the bit group includes 4 bits.

[0037] Fifthly, a data processing method is provided, the method being applied at a transmitting end, comprising: transmitting W dual-polarization symbol streams, wherein each of the W dual-polarization symbol streams includes multiple superframes, and in any polarization direction, every consecutive N subframes of each superframe... PG The symbol includes a pilot symbol, W and N. PG All are integers greater than 1; within one transmission period, in any two dual-polarization symbol streams of the W dual-polarization symbol streams, the positional interval of the pilot symbols in any polarization direction is (N PG / W) symbols K times, where K is a positive integer not equal to an integer multiple of W.

[0038] A transmission cycle can be understood as a transmission time. During this transmission time, in any polarization direction, the interval between the first pilot symbol of one dual-polarization symbol stream and the first pilot symbol of another dual-polarization symbol stream is (N). PG / W) symbols, K times, for example, W=2, N PG With K=64 and K=1, the interval between the first pilot symbol in the first dual-polarization symbol stream and the first pilot symbol in the other dual-polarization symbol stream is 32 symbols. That is, the first symbol (also the first pilot symbol) in the first dual-polarization symbol stream is sent together with the 33rd symbol in the other dual-polarization symbol stream.

[0039] In conjunction with the fifth aspect, in the first possible implementation of the fifth aspect, W is 2, and N is... PG It is 64.

[0040] In conjunction with the first possible implementation of the fifth aspect, in the second possible implementation of the fifth aspect, within one transmission cycle, in any polarization direction, the first pilot symbol in the dual-polarization symbol stream 0 is spaced 32 symbols apart from the first pilot symbol in the dual-polarization symbol stream 1. This can be achieved by delaying one of the symbol streams, or by delaying both symbol streams; this application does not limit this.

[0041] In conjunction with the fifth aspect, in the third possible implementation of the fifth aspect, W is 4, and N... PG It is 64.

[0042] In conjunction with the third possible implementation of the fifth aspect, in the fourth possible implementation of the fifth aspect, within one transmission cycle, in any polarization direction, the first pilot symbol in the dual-polarization symbol stream 0 is spaced 16 symbols apart from the first pilot symbol in the dual-polarization symbol stream 1; the first pilot symbol in the dual-polarization symbol stream 1 is spaced 16 symbols apart from the first pilot symbol in the dual-polarization symbol stream 2; and the first pilot symbol in the dual-polarization symbol stream 2 is spaced 16 symbols apart from the first pilot symbol in the dual-polarization symbol stream 3.

[0043] In this embodiment, the interval between pilot symbols in two adjacent second dual-polarization symbol streams is 16 symbols in any polarization direction, which is less than the traditional 64 symbols. When the receiver performs joint subcarrier recovery processing, the interval between pilot symbols used for carrier phase recovery processing can be considered to be reduced from the traditional 64 symbols to one-quarter, i.e., 16 symbols, further improving anti-dispersion capability and phase noise tolerance. The data processing scheme provided in this embodiment can be applied to future scenarios using multi-subcarrier transmission, such as 800Gbps multi-subcarrier transmission using QPSK modulation, 1.2Tbps multi-subcarrier transmission using 16QAM modulation, 1.6Tbps multi-subcarrier transmission using 16QAM modulation, and even higher speed transmission scenarios such as 2.4T / 3.2T.

[0044] Combining the fifth aspect and the aforementioned possible implementations, in the fifth possible implementation of the fifth aspect, the W dual-polarization symbol streams to be transmitted are respectively carried on W subcarriers. These W subcarriers are multiplexed to obtain a single signal for transmission. In this case, the baud rate corresponding to each subcarrier is 1 / W of the transmitted signal baud rate. This scheme can reduce the complexity of dispersion compensation, reduce the cost of equalization enhancement phase noise, and result in lower DSP power consumption.

[0045] In conjunction with the fifth aspect and the above possible implementations, in the sixth possible implementation of the fifth aspect, the dual polarization symbol is a dual polarization 16QAM symbol or a dual polarization QPSK symbol.

[0046] Sixthly, a data processing method is provided, applied at a receiving end, comprising: acquiring W dual-polarization symbol streams, wherein each of the W dual-polarization symbol streams includes multiple superframes, and in any polarization direction, every consecutive N subframes of each superframe... PG The symbol includes a pilot symbol, W and N. PG All are integers greater than 1; within one transmission period, in any two dual-polarization symbol streams of the W dual-polarization symbol streams, the positional interval of the pilot symbols in any polarization direction is (N PG / W) symbols K times, where K is a positive integer not equal to an integer multiple of W.

[0047] Optionally, W is 2, N PG The value is 64. At this point, within one transmission cycle, in any polarization direction, the first pilot symbol in the dual-polarization symbol stream 0 is spaced 32 symbols apart from the first pilot symbol in the dual-polarization symbol stream 1. This can be achieved by delaying one of the symbol streams, or by delaying both symbol streams; this application does not limit the implementation.

[0048] A seventh aspect provides a data processing apparatus, the apparatus comprising: a processing unit configured to perform delay processing on at least one of W acquired first dual-polarization symbol streams to obtain a total of W dual-polarization symbol streams to be transmitted, wherein each of the W first dual-polarization symbol streams comprises multiple superframes, and in any polarization direction, every N consecutive N subframes in each superframe... PG The symbol includes a pilot symbol, W and N. PG All are integers greater than 1; the delay value corresponding to a first dual-polarization symbol stream after delay processing is K×(N PG / W) double polarization symbols, where K is a positive integer not equal to an integer multiple of W.

[0049] In conjunction with the seventh aspect, in a first possible implementation of the seventh aspect, the processing unit is specifically configured to: perform delay processing i on the first dual-polarized symbol stream i in the W first dual-polarized symbol streams to obtain a dual-polarized symbol stream i to be sent, resulting in a total of W dual-polarized symbol streams to be sent, where 0 ≤ i ≤ W-1, and i is a positive integer, and the delay value corresponding to delay processing i is M. i A dual-polarization symbol, M i =(N PG / W)×i+N PG ×a, where a is an integer.

[0050] Combining the seventh aspect and the first possible implementation of the seventh aspect, in the second possible implementation of the seventh aspect, W is 2 and N is... PG It is 64.

[0051] In conjunction with the second possible implementation of the seventh aspect, in the third possible implementation of the seventh aspect, the processing unit is specifically used to: delay the first dual-polarized symbol stream 1 by 32 dual-polarized symbols to obtain the second dual-polarized symbol stream 1, wherein the first dual-polarized symbol stream 0 is not delayed, and the two dual-polarized symbol streams to be sent include the first dual-polarized symbol stream 0 and the second dual-polarized symbol stream 1.

[0052] Combining the seventh aspect and the first possible implementation of the seventh aspect, in the fourth possible implementation of the seventh aspect, W is 4, and N... PG It is 64.

[0053] In conjunction with the fourth possible implementation of the seventh aspect, in the fifth possible implementation of the seventh aspect, the processing unit is specifically used to: delay the first dual-polarization symbol stream 1 by 16 dual-polarization symbols to obtain the second dual-polarization symbol stream 1; delay the first dual-polarization symbol stream 2 by 32 dual-polarization symbols to obtain the second dual-polarization symbol stream 2; and delay the first dual-polarization symbol stream 3 by 48 dual-polarization symbols to obtain the second dual-polarization symbol stream 3. The first dual-polarization symbol stream 0 is not delayed. The four dual-polarization symbol streams to be sent include the first dual-polarization symbol stream 0, the second dual-polarization symbol stream 1, the second dual-polarization symbol stream 2, and the second dual-polarization symbol stream 3.

[0054] In conjunction with the above possible implementations, in the sixth possible implementation of the seventh aspect, the first dual-polarization symbol stream i includes an X-polarization symbol stream i and a Y-polarization symbol stream i; the processing unit is specifically configured to: perform symbol delay processing i on the X-polarization symbol stream i and the Y-polarization symbol stream i respectively, wherein the delay value corresponding to the symbol delay processing i is M. i A symbol.

[0055] In conjunction with the above possible implementations, in the seventh possible implementation of the seventh aspect, the first dual-polarization symbol stream i includes a data stream XI-i of the I-path component in the X-polarization direction, a data stream XQ-i of the Q-path component in the X-polarization direction, a symbol stream YI-i of the I-path component in the Y-polarization direction, and a symbol stream YQ-i of the Q-path component in the Y-polarization direction; the processing unit is specifically used to: perform component delay processing XI-i on the data stream XI-i of the I-path component in the X-polarization direction, wherein the delay value corresponding to the component delay processing XI-i is M. i The I-path component of each dual-polarization symbol in the X-polarization direction; the Q-path component data stream XQ-i in the X-polarization direction is subjected to component delay processing XQ-i, where the delay value corresponding to component delay processing XQ-i is M. i The data stream YI-i of the dual-polarization symbols in the X-polarization direction is divided into Q-path components; the data stream YI-i of the I-path components in the Y-polarization direction is subjected to component delay processing YI-i, where the delay value corresponding to the component delay processing YI-i is M. i The data stream YQ-i of the dual-polarization symbols in the Y-polarization direction is divided into I-path components; the data stream YQ-i of the Q-path components in the Y-polarization direction is subjected to component delay processing YQ-i, where the delay value corresponding to the component delay processing YQ-i is M. i The Q-path component of a double-polarized symbol in the Y-polarization direction.

[0056] In combination with the above possible implementations, in the eighth possible implementation of the seventh aspect, the W dual-polarization symbol streams to be transmitted are respectively carried on W subcarriers.

[0057] In combination with the above possible implementations, in the ninth possible implementation of the seventh aspect, the dual polarization symbol is a dual polarization 16QAM symbol or a dual polarization QPSK symbol.

[0058] Eighthly, a data processing apparatus is provided, the apparatus comprising a processing unit and a mapping unit; the processing unit is configured to perform delay processing on at least one of the acquired W first bit streams to obtain a total of W second bit streams, wherein the delay value corresponding to one of the delayed first bit streams is K×(N). PG / W) bit blocks, W and N PG All are integers greater than 1, and K is a positive integer not equal to an integer multiple of W; the mapping unit is used to perform dual-polarization symbol mapping on the obtained W second bit streams respectively to obtain W dual-polarization symbol streams, wherein each bit group is transformed into a dual-polarization symbol after dual-polarization symbol mapping; each of the W dual-polarization symbol streams includes multiple superframes, and in any polarization direction, every consecutive N in each subframe of each superframe PG Each symbol includes a pilot symbol.

[0059] In conjunction with the eighth aspect, in a first possible implementation of the eighth aspect, the processing unit is specifically configured to: perform a delay processing i on the first bit stream i in the W first bit streams to obtain a second bit stream i, resulting in a total of W second bit streams, where 0 ≤ i ≤ W-1, and i is an integer, and the delay value corresponding to the delay processing i is M. i A bit block, M i =(N PG / W)×i+N PG ×a, where a is an integer.

[0060] Combining the eighth aspect and its first possible implementation, in the second possible implementation of the eighth aspect, W is 2 and N is... PG It is 64.

[0061] In conjunction with the second possible implementation of the eighth aspect, in the third possible implementation of the eighth aspect, the processing unit is specifically used to: delay the first bit stream 1 by 32 bits to obtain the second bit stream 1, wherein the first bit stream 0 is not delayed, and the two second bit streams include the first bit stream 0 and the second bit stream 1.

[0062] Combining the eighth aspect and the first possible implementation of the eighth aspect, in the fourth possible implementation of the eighth aspect, W is 4, and N... PG It is 64.

[0063] In conjunction with the fourth possible implementation of the eighth aspect, in the fifth possible implementation of the eighth aspect, the processing unit is specifically used to: delay the first bit stream 1 by 16 bits to obtain the second bit stream 1; delay the first bit stream 2 by 32 bits to obtain the second bit stream 2; delay the first bit stream 3 by 48 bits to obtain the second bit stream 3, wherein the first bit stream 0 is not delayed, and the four second bit streams include the first bit stream 0, the second bit stream 1, the second bit stream 2, and the second bit stream 3.

[0064] In combination with the above possible implementations, in the sixth possible implementation of the eighth aspect, the W dual-polarization symbol streams are respectively carried on W subcarriers.

[0065] In combination with the above possible implementations, in the seventh possible implementation of the eighth aspect, the dual-polarization symbol is a dual-polarization 16QAM symbol, and the bit group includes 8 bits; or

[0066] The dual polarization symbol is a dual polarization QPSK symbol, and the bit group consists of 4 bits.

[0067] A ninth aspect provides a data processing apparatus, comprising: a transmitting unit for transmitting W dual-polarization symbol streams, wherein each of the W dual-polarization symbol streams comprises multiple superframes, and in any polarization direction, every consecutive N subframe of each superframe... PG The symbol includes a pilot symbol, W and N. PG All are integers greater than 1; within one transmission period, in any two dual-polarization symbol streams of the W dual-polarization symbol streams, the positional interval of the pilot symbols in any polarization direction is (N PG / W) symbols K times, where K is a positive integer not equal to an integer multiple of W.

[0068] Optionally, W is 2, N PG The value is 64. At this point, within one transmission cycle, in any polarization direction, the first pilot symbol in the dual-polarization symbol stream 0 is spaced 32 symbols apart from the first pilot symbol in the dual-polarization symbol stream 1. This can be achieved by delaying one of the symbol streams, or by delaying both symbol streams; this application does not limit the implementation.

[0069] A tenth aspect provides a data processing apparatus, the apparatus comprising: an acquisition unit configured to acquire W second dual-polarization symbol streams, wherein the W second dual-polarization symbol streams are obtained by a transmitting end performing delay processing on at least one of the W first dual-polarization symbol streams; each of the W first dual-polarization symbol streams comprises multiple superframes, and in any polarization direction, every consecutive N subframes in each superframe... PG The symbol includes a pilot symbol, W and N. PG All are integers greater than 1; the delay value corresponding to a first dual-polarization symbol stream after delay processing is K×(N PG / W) double polarization symbols, where K is a positive integer not equal to an integer multiple of W.

[0070] In conjunction with the tenth aspect, in a first possible implementation of the eighth aspect, the apparatus further includes a processing unit for parsing the acquired W second dual-polarization symbol streams. Other functions of the apparatus will not be elaborated upon in this application.

[0071] Eleventhly, a data processing apparatus is provided, the apparatus comprising: an acquisition unit, configured to acquire W dual-polarization symbol streams, wherein each of the W dual-polarization symbol streams comprises multiple superframes, and in any polarization direction, every N consecutive subframes within each superframe... PG The symbol includes a pilot symbol, W and N. PGAll are integers greater than 1; the W dual-polarization symbol streams are obtained by the transmitting end performing dual-polarization symbol mapping on the W second bit streams respectively, and the W second bit streams are obtained by the transmitting end performing delay processing on at least one of the acquired W first bit streams; wherein, the delay value corresponding to the first bit stream after delay processing is K×(N PG / W) bit blocks, where K is a positive integer not equal to an integer multiple of W; each bit block is mapped to a dual-polarization symbol.

[0072] In conjunction with the eleventh aspect, in a first possible implementation of the eighth aspect, the apparatus further includes a processing unit for parsing the acquired W dual-polarization symbol streams. Other functions of the apparatus will not be described in detail in this application.

[0073] In a twelfth aspect, a data processing apparatus is provided, comprising: an acquisition unit for acquiring W dual-polarization symbol streams, wherein each of the W dual-polarization symbol streams includes multiple superframes, and in any polarization direction, every N consecutive subframes of each superframe... PG The symbol includes a pilot symbol, W and N. PG All are integers greater than 1; within one transmission period, in any two dual-polarization symbol streams of the W dual-polarization symbol streams, the positional interval of the pilot symbols in any polarization direction is (N PG / W) symbols K times, where K is a positive integer not equal to an integer multiple of W.

[0074] Optionally, W is 2, N PG The value is 64. At this point, within one transmission cycle, in any polarization direction, the first pilot symbol in the dual-polarization symbol stream 0 is spaced 32 symbols apart from the first pilot symbol in the dual-polarization symbol stream 1. This can be achieved by delaying one of the symbol streams, or by delaying both symbol streams; this application does not limit the implementation.

[0075] In a thirteenth aspect, embodiments of this application provide a chip for performing the methods described in any of the implementations of the first to sixth aspects.

[0076] In a fourteenth aspect, embodiments of this application provide an optical module. The optical module includes a processor and an interface. The processor is used to execute the methods described in any of the implementations of the first to sixth aspects, and to acquire signals through the interface. For example, the interface is used to transmit signals from the processor or to transmit received signals to the processor.

[0077] In a fifteenth aspect, embodiments of this application provide a communication device. The communication device includes a host-side device and an optical module as described in the fourteenth aspect, the optical module being connected to the host-side device.

[0078] In a sixteenth aspect, embodiments of this application provide another device. This device includes a processor and an interface, the processor being used to execute the methods described in any of the implementations of the first to sixth aspects, and to acquire signals through the interface. For example, the interface is used to send signals from the processor or to transmit received signals to the processor. The device may be a router, switch, server, or optical transport network equipment, etc.

[0079] In a seventeenth aspect, embodiments of this application provide a communication system including a first communication device and a second communication device, wherein at least one of the first communication device and the second communication device is a communication device as described in the fifteenth aspect, and the first communication device and the second communication device are connected.

[0080] In an eighteenth aspect, this application provides a computer-readable storage medium storing instructions that, when executed by a computer, cause the method described in any of the implementations of the first to sixth aspects to be implemented.

[0081] In a nineteenth aspect, this application provides a computer program product including program instructions that, when executed, implement the method described in any of the implementations of the first to sixth aspects above.

[0082] The seventh aspect is an apparatus corresponding to the method provided in the first aspect; the eighth aspect is an apparatus corresponding to the method provided in the third aspect; the ninth aspect is an apparatus corresponding to the method provided in the fifth aspect; the tenth aspect is an apparatus corresponding to the method provided in the second aspect; the eleventh aspect is an apparatus corresponding to the method provided in the fourth aspect; the twelfth aspect is an apparatus corresponding to the method provided in the sixth aspect; and aspects thirteen to nineteen all refer to any one of the implementations of aspects one to six, the beneficial effects of which have been described previously and will not be repeated here. Attached Figure Description

[0083] Figure 1 This is a schematic diagram of a communication system used in an embodiment of this application;

[0084] Figure 2 This is a schematic diagram illustrating one implementation of dual polarization symbol mapping and framing in an embodiment of this application;

[0085] Figure 3 This is a schematic diagram illustrating another implementation method of dual polarization symbol mapping and framing by the sending DSP processor in this application embodiment;

[0086] Figure 4 This is a schematic diagram illustrating another implementation method of dual polarization symbol mapping and framing by the sending DSP processor in this application embodiment;

[0087] Figure 5 This is a schematic diagram illustrating another implementation of dual polarization symbol mapping and framing by the sending DSP processor in this application embodiment;

[0088] Figure 6 This is a flowchart of a data processing method according to an embodiment of this application;

[0089] Figure 7 This is a schematic diagram of a data processing method according to an embodiment of this application;

[0090] Figure 8 This is a schematic diagram of the structure of a superframe in an embodiment of this application;

[0091] Figure 9 The embodiments of this application include N SF A schematic diagram of the structure of a superframe with subframes;

[0092] Figure 10 This is a schematic diagram of a constellation point arrangement in an embodiment of this application;

[0093] Figure 11 This is a schematic diagram illustrating the implementation of a delay processing method in an embodiment of this application;

[0094] Figure 12 This is a schematic diagram illustrating another implementation of delayed processing in an embodiment of this application;

[0095] Figure 13 This is a schematic diagram illustrating another implementation of delay processing in an embodiment of this application;

[0096] Figure 14 This is a schematic diagram of another data processing method in an embodiment of this application;

[0097] Figure 15 This is a schematic diagram of a dual-polarization symbol stream delay result in an embodiment of this application;

[0098] Figure 16 This is a schematic diagram of another dual-polarization symbol stream delay result in an embodiment of this application;

[0099] Figure 17 This is a schematic diagram of yet another data processing method in the embodiments of this application;

[0100] Figure 18 This is a schematic diagram of another dual-polarization symbol stream delay result in the embodiments of this application;

[0101] Figure 19 This is a schematic diagram of another dual-polarization symbol stream delay result in an embodiment of this application;

[0102] Figure 20 This is a schematic diagram of yet another data processing method in an embodiment of this application;

[0103] Figure 21 This is a schematic diagram illustrating another implementation of delay processing in an embodiment of this application;

[0104] Figure 22 This is a schematic diagram of yet another data processing method in an embodiment of this application;

[0105] Figure 23 This is a schematic diagram of the structure of a data processing device in an embodiment of this application;

[0106] Figure 24 This is a schematic diagram of another structure of the data processing device in the embodiments of this application;

[0107] Figure 25 This is a schematic diagram of the structure of an optical module in one embodiment of this application;

[0108] Figure 26 This is a schematic diagram of the structure of a transmitting device in an embodiment of this application;

[0109] Figure 27 This is a schematic diagram of the receiving device in one embodiment of this application. Detailed Implementation

[0110] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0111] It should be noted that the terms "first," "second," etc., in this application specification, claims, and the accompanying drawings are used to distinguish similar objects, not to limit a specific order or sequence. It should be understood that the above terms can be used interchangeably where appropriate so that the embodiments described in this application can be implemented in a sequence other than that described in this application. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to these processes, methods, products, or devices.

[0112] This application provides a data processing method, apparatus, device, and system, and presents a framing scheme for multi-subcarrier transmission. This scheme is beneficial for improving the quality of the recovered signal at the receiving end, has good phase noise tolerance, and is well compatible with framing schemes of 400ZR+ (an optical communication transmission applied to metropolitan areas), 800ZR, and 800ZR+. It is also beneficial for hardware implementation and can be well applied to various coherent transmission scenarios in the future.

[0113] This application provides a communication system, which can be an optical communication system such as a metropolitan area telecommunications transmission system or a metropolitan area data center interconnection (DCI) system, and the communication system can be a coherent optical communication system.

[0114] The communication system includes a transmitter and a receiver, which establish a communication connection through a channel. Both the transmitter and receiver can be communication devices (such as routers, optical transmission devices (such as optical line terminals (OLTs) or optical network terminals (ONTs), optical modules, servers, etc.)).

[0115] The channel can be a wired channel, such as an optical fiber.

[0116] Taking an example where both the transmitter and receiver are optical modules in a communication device, the transmitter can send signals to the receiver via a channel, enabling communication between them. For instance, the transmitter can process a bit sequence to obtain a superframe, and then send an optical signal to the channel based on this superframe. The receiver can receive the optical signal sent by the transmitter from the channel, recover the superframe from the optical signal, and process the superframe to obtain the bit sequence. This receiving process is the reverse of the transmitting process.

[0117] Figure 1 This is a schematic diagram of a communication system used in an embodiment of this application. Figure 1 As shown, at the transmitting end, the source provides the data stream to be transmitted. The forward error correction (FEC) encoder receives this data stream and performs FEC encoding on it. The FEC-encoded codeword, combining the parity bits and information bits, is sent to the transmitting-end DSP processor for dual-polarization symbol mapping and framing. This data is then transmitted through the channel to the receiving end. At the receiving end, after receiving the distorted signal caused by noise or other impairments in the channel, it is sent to the receiving-end DSP processor for dispersion compensation, synchronization, and phase recovery operations. Then, it is decoded by the FEC decoder to recover the original data and send it to the destination. This framing process can also be called DSP framing.

[0118] It should be noted that the embodiments of this application consider digital subcarrier multiplexing (DSCM) technology. DSCM divides an optical signal (also called a channel) into multiple digital subcarriers, each carrying different carrier transmission information. Compared to traditional single-carrier transmission, each subcarrier in DSCM has a narrower bandwidth, making it more robust to high-bandwidth-related channel losses (such as dispersion and jitter). Therefore, the encoded data is typically distributed to W data streams for dual-polarization symbol mapping and framing, carried on W subcarriers, and multiplexed to obtain a single signal for transmission. In this case, the baud rate corresponding to each subcarrier is 1 / W of the transmitted signal baud rate. Digital subcarriers reduce the complexity of dispersion compensation and the overhead of enhanced equalization phase noise (EEPN), resulting in lower DSP power consumption. Optionally, W is an even number, and its value can be 2, 4, or 8, etc.

[0119] Figure 2 This is a schematic diagram illustrating one implementation of dual-polarization symbol mapping and framing in an embodiment of this application. For example... Figure 2 As shown, in one possible implementation, the transmitting DSP processor performs dual-polarization symbol mapping on the acquired data sequence. Typically, the acquired data sequence consists of information and a check sequence obtained through FEC encoding. Dual-polarization symbol mapping includes symbol mapping and polarization distribution. Symbol mapping methods include, but are not limited to, QAM methods. Generally, QAM modulation (also known as symbol mapping) involves symbol mapping multiple input bits to obtain multiple QAM symbols, and then polarizing these QAM symbols to obtain multiple dual-polarization (DP) symbols, i.e., DP-QAM symbols, such as DP-4QAM (also known as dual-polarization quadrature phase shift keying, DP-QPSK), DP-16QAM, DP-32QAM, and DP-64QAM. It should be understood that symbol mapping often uses Gray mapping, mapping multiple bits to one QAM symbol; in this case, the symbol mapping is simply called Gray mapping.

[0120] For ease of explanation, the two polarization directions will be consistently referred to as the X-polarization direction and the Y-polarization direction, respectively, where the X-polarization direction and the Y-polarization direction are orthogonal to each other. It should be understood that the X-polarization direction and the Y-polarization direction are not two specified polarization directions, but rather any two mutually orthogonal polarization directions. Furthermore, the transmitting DSP processor performs the following framing processing on a certain number of dual-polarization symbols: For example, it obtains a pre-framing dual-polarization symbol sequence containing multiple dual-polarization symbols; inserts a frame alignment word sequence (FAWSequence) and a training symbol sequence into the X-polarization direction and the Y-polarization direction, respectively; and retains at least one symbol sequence from the reserved symbols and the pilot symbols sequence, resulting in a post-framing dual-polarization symbol sequence. Here, the inserted symbol sequence can also be called a preset symbol sequence. The sequence comprises several components: a frame synchronization symbol sequence (simply called a frame synchronization sequence), a training symbol sequence (simply called a training sequence), a reserved symbol sequence (simply called a reserved sequence), and a pilot symbol sequence (simply called a pilot sequence). Frame synchronization symbols are used for frame synchronization alignment, training symbols are used for link training, pilot symbols are used for carrier phase recovery, and reserved symbols are reserved for future use and innovation. In some applications, certain reserved symbols may be used for feedback channel purposes. The values ​​of reserved symbols can be partially known and unchanging, or they can be randomized; the values ​​of reserved symbols can also be referred to as a pattern.

[0121] In this embodiment, the pre-framing dual-polarization symbol is also called the payload symbol, which includes FEC-encoded information and parity bits, and the resulting symbol (called the information symbol and parity symbol) is obtained through symbol mapping. The post-framing dual-polarization symbol sequence is called a data frame, or DSP frame.

[0122] In this embodiment, the data frame comprises multiple sub-frames. In some embodiments, the data frame may be referred to as a super-frame, and the frame synchronization symbol may also be referred to as a super-frame alignment signal. In other embodiments, the data frame may also be referred to as a multi-frame, the sub-frames are simply referred to as frames, the reserved symbol may also be referred to as fixed stuff (FS), and the frame synchronization symbol may also be referred to as a multi-frame alignment signal (MFAS). The data frame comprising multiple sub-frames can also be referred to as "a super-frame comprising multiple sub-frames"; it can also be referred to as "a multi-frame comprising multiple frames."

[0123] In the embodiments of this application, the data frame is uniformly referred to as a superframe. It should be understood that in a superframe (also known as a DSP frame or multiple frames), the symbols remaining after removing the payload symbols (also known as pre-frame symbols), training symbols, pilot symbols, and frame synchronization symbols are called reserved symbols.

[0124] It should be understood that a dual-polarization symbol can be represented by two symbols, one located in the X-polarization direction and the other in the Y-polarization direction. Each symbol can be represented by a complex number. For example, a symbol obtained using 16QAM modulation can be represented by any one of the following 16 complex numbers: ±1±1j, ±1±3j, ±3±1j, and ±3±3j, where ± indicates a positive or negative value, such as ±3 representing 3 or -3. As another example, a symbol obtained using QPSK modulation can be represented by any one of the following four complex numbers: ±1±1j. In some applications, the real and imaginary parts are normalized, but the essence remains unchanged.

[0125] It should be noted that a sequence with N0 dual-polarization symbols can be completely represented by two complex sequences of length N0, one representing the symbol in the X-polarization direction and the other representing the symbol in the Y-polarization direction. Each complex sequence of length N0 is represented by a sequence of N0 real parts (also called the I-path sequence) and a sequence of N0 imaginary parts (also called the Q-path sequence), where N0 is an integer greater than 1. Therefore, there are four different types of sequences, including the X-polarization I-path (in-phase component) sequence, the X-polarization Q-path (quadrature-phase component) sequence, the Y-polarization I-path sequence, and the Y-polarization Q-path sequence. The X-polarization I-path sequence is also called the X... I The component, the Q-path sequence in the X polarization direction, is also called X. Q The component, the Y-polarization direction I-path sequence, is also called the Y component. IThe component, the Q-path sequence in the Y-polarization direction, is also called the Y-axis. Q Quantity.

[0126] It should also be noted that after dual-polarization symbol mapping and framing, a dual-polarization symbol stream is obtained. A dual-polarization symbol stream can be represented by two symbol data streams: the first is the symbol data stream in the X-polarization direction, and the second is the symbol data stream in the Y-polarization direction. Alternatively, a dual-polarization symbol stream can also be represented by four data streams: the first is the data stream of the I-path component corresponding to the X-polarization direction (referred to as X...). I The second data stream is the data stream of the Q-path component in the X-polarization direction corresponding to the dual-polarization symbol stream (abbreviated as X). Q The third data stream is the data stream of the I-path component in the Y-polarization direction corresponding to the dual-polarization symbol stream (abbreviated as Y). I The fourth data stream is the data stream of the Q-path component in the Y-polarization direction corresponding to the dual-polarization symbol stream (abbreviated as Y). Q (Data flow).

[0127] It should be understood that Figure 2 In the dual-polarization symbol mapping and framing operations shown, framing (also known as DSP framing) is performed after dual-polarization symbol mapping; that is, framing is performed on the symbol level. Below are schematic diagrams of several other possible implementations of the originating DSP processor, where framing is performed before dual-polarization symbol mapping; that is, framing is performed on the bit level.

[0128] Figure 3 This is a schematic diagram illustrating another implementation method for dual-polarization symbol mapping and framing by the transmitting DSP processor in this application embodiment. For example... Figure 3 As shown, framing occurs before dual-polarization symbol mapping. For example, a pre-framing bit sequence containing multiple bits is obtained, a preset bit sequence is inserted, and dual-polarization symbol mapping is performed to obtain a post-framing dual-polarization symbol sequence. The preset bit sequence undergoes dual-polarization symbol mapping to obtain a preset symbol sequence; this preset bit sequence is also called the bits corresponding to the preset symbol sequence. It should be understood that the pre-framing bit sequence uses a method such as... Figure 3 The framed dual-polarization symbol sequence obtained by the implementation shown, and the sequence obtained by using the method described above, are similar to those obtained by using the method described above. Figure 2 The implementation shown yields the same double-polarization symbol sequence after framing.

[0129] Figure 4 This is a schematic diagram illustrating another implementation method of dual-polarization symbol mapping and framing by the sending DSP processor in this application embodiment. For example... Figure 4As shown, framing is performed before dual-polarization symbol mapping. For example, two pre-framing bit sequences, each containing multiple bits, are obtained. A first preset bit sequence and a second preset bit sequence are inserted into the first and second pre-framing bit sequences, respectively, and dual-polarization symbol mapping is performed to obtain the post-framing dual-polarization symbol sequence. The first preset bit sequence is symbol-mapped to obtain a preset symbol sequence in the X-polarization direction, and the second preset bit sequence is symbol-mapped to obtain a preset symbol sequence in the Y-polarization direction. The first preset bit sequence is also called the bit corresponding to the preset symbol sequence in the X-polarization direction, and the second preset bit sequence is also called the bit corresponding to the preset symbol sequence in the Y-polarization direction. It should be understood that the pre-framing bit sequence uses... Figure 4 The framed dual-polarization symbol sequence obtained by the implementation shown, and the sequence obtained by using the method described above, are similar to those obtained by using the method described above. Figure 2 The implementation shown yields the same double-polarization symbol sequence after framing.

[0130] Figure 5 This is a schematic diagram illustrating another implementation of dual-polarization symbol mapping and framing by the sending DSP processor in this application. For example... Figure 5 As shown, framing is performed before dual-polarization symbol mapping. For example, four pre-framing bit sequences, each containing multiple bits, are obtained. A first preset bit sequence, a second preset bit sequence, a third preset bit sequence, and a fourth preset bit sequence are inserted into the first, second, third, and fourth pre-framing bit sequences, respectively. Dual-polarization symbol mapping is then performed to obtain a single post-framing dual-polarization symbol sequence. The first preset bit sequence is symbol-mapped to obtain the I-path component of the preset symbol sequence in the X-polarization direction; the second preset bit sequence is symbol-mapped to obtain the Q-path component of the preset symbol sequence in the X-polarization direction; the third preset bit sequence is symbol-mapped to obtain the I-path component of the preset symbol sequence in the Y-polarization direction; and the fourth preset bit sequence is symbol-mapped to obtain the Q-path component of the preset symbol sequence in the Y-polarization direction. The first preset bit sequence is also called the preset symbol sequence in the X-polarization direction. I The bits corresponding to the components, the second preset bit sequence, also known as the preset symbol sequence, are in X. Q The bits corresponding to the components, the third preset bit sequence, also known as the preset symbol sequence, are in Y. I The bits corresponding to the components, the fourth preset bit sequence, also known as the preset symbol sequence, are in Y. Q The bits corresponding to the components. It should be understood that the bit sequence before framing uses, for example... Figure 5 The framed dual-polarization symbol sequence obtained by the implementation shown, and the sequence obtained by using the method described above, are similar to those obtained by using the method described above. Figure 2 The implementation shown yields the same double-polarization symbol sequence after framing.

[0131] It should be noted that this application does not limit the framing method used by the sending DSP processor, except as mentioned above. Figures 2 to 5 Besides the framing method described, other similar framing methods are also applicable to the embodiments of this application, and will not be described one by one here.

[0132] The following describes the process of data processing.

[0133] Figure 6 This is a flowchart of a data processing method according to an embodiment of this application. Figure 6 As shown, the data processing method includes steps S101 to S103.

[0134] Step S101: The transmitting end acquires W dual-polarization symbol streams, where W is an integer greater than 1.

[0135] In this embodiment, as Figure 7 As shown, after dual-polarization symbol mapping and framing operations, the transmitting end obtains W first dual-polarization symbol streams, namely first dual-polarization symbol stream 0, first dual-polarization symbol stream 1, ..., first dual-polarization symbol stream W-1. These dual-polarization symbol streams can also be referred to as dual-polarization symbol data streams. Each of the aforementioned W dual-polarization symbol streams includes multiple superframes, and each superframe is a collection of multiple dual-polarization symbols. These multiple superframes constitute a dual-polarization symbol stream for transmission.

[0136] The embodiments of this application do not limit the implementation method of generating superframes. For example, the above-described method can be used. Figures 2 to 5 The dual-polarization symbol mapping and framing method described herein is applicable to other similar dual-polarization symbol mapping and framing methods as well, and will not be described in detail here. It should be understood that a superframe includes symbols in two polarization directions; that is, a superframe includes dual-polarization symbols. The structure of the superframe is the same in both polarization directions. For example, a superframe includes a symbol sequence in the X-polarization direction and a symbol sequence in the Y-polarization direction. The structure of the superframe will be described below using one polarization direction as an example.

[0137] Figure 8 This is a schematic diagram of a superframe structure according to an embodiment of this application. Figure 8 As shown, a superframe includes N SF There are N subframes, each subframe comprising N subframes. S If there are N symbols, then the superframe includes N F A symbol, N F =N SF ×N S N S and N SF All are integers greater than 1. Subframes within a superframe are divided into two categories, referred to here as Category I subframes and Category II subframes. These two categories of subframes will be described separately below.

[0138] Figure 9 The embodiments of this application include N SF A schematic diagram of the structure of a superframe consisting of subframes. For example... Figure 9 Figure (a) shows the structure of the first type of subframe, which includes training symbols, pilot symbols, frame synchronization symbols, reserved symbols, and payload symbols. Typically, the first type of subframe is the first subframe in the superframe, but it can also be located in other positions within the superframe, such as the last subframe. All other subframes in the superframe besides the first type are considered second type subframes. Figure 9 As shown in (b), the second type of subframe differs from the first type of subframe. The second type of subframe includes training symbols, pilot symbols, and payload symbols, but does not include frame synchronization symbols and reserved symbols. It should be understood that the positions of the first and second type of subframes can also be changed, for example, the first type of subframe may be in the middle of the data or at the last position; this application does not limit this.

[0139] For both Type I and Type II subframes, each subframe includes training symbols and pilot symbols. Training symbols are used for link training and / or subframe synchronization, while pilot symbols are used for carrier phase recovery. The number of training symbols in a subframe is denoted as N in any polarization direction. TS Let N be the number of pilot symbols in the subframe. PE N TS and N PS All are integers greater than 1. Optionally, one symbol in a subframe may be both a training symbol and a pilot symbol, i.e. Figure 9 The symbol indicated by the dashed box in the middle, for example, the first training symbol in a training sequence can be the first symbol in a pilot sequence. N TS The training symbols include the symbols indicated by the dashed box, N. PS Each pilot symbol also includes the symbol indicated by the dashed box.

[0140] like Figure 9 The diagram shown illustrates the structure of a superframe, N TS N consecutive training symbols are arranged starting from the beginning of the subframe. TS In a series of consecutive training symbols, the symbol at the beginning position is both a training symbol and a pilot symbol. That is, the first symbol of a subframe is the first symbol of both the training symbol sequence and the pilot symbol sequence. In other words, the first symbol of the training symbol sequence is also the first symbol of the pilot symbol sequence, and the first symbol of the training symbol sequence and the first symbol of the pilot symbol sequence have the same value.

[0141] In this embodiment of the application, in a superframe, the first symbol is described as the 1st symbol, that is, the sequence number starts from 1.

[0142] It should be noted that frame synchronization symbols are used for synchronization between superframes. These symbols can be used together with training symbols for synchronization between superframes, or they can be used together with pilot symbols to achieve synchronization. It should be understood that frame synchronization symbols are arranged consecutively and can be adjacent to training symbols. Furthermore, there can be one or more symbol intervals between frame synchronization symbols and training symbols. Additionally, a portion of the reserved symbols can be fixed for other purposes, such as optical signal-to-noise ratio (OSNR) measurement, end-to-end (E2E) delay measurement, etc. Reserved symbols can also be located within one of multiple type II subframes, and this application does not impose any limitations on this. Pilot symbols and reserved symbols do not overlap, nor do pilot symbols and payload symbols overlap. That is, there is no symbol that is both a pilot symbol and a payload symbol, nor is there a symbol that is both a pilot symbol and a reserved symbol.

[0143] For each subframe in a superframe, every N consecutive N... PG Each symbol includes a pilot symbol located at a fixed position. N PG It is a multiple of 32, for example, N PG =32, 64, or 128. For example... Figure 9 As shown, N PG The value is 64. It should be understood that, due to each consecutive N... PG The position of the pilot symbols in a given symbol is fixed, therefore, there is an equal interval between two consecutive pilot symbols in a subframe. For example... Figure 9 As shown, the pilot symbols are located in every consecutive N PG The starting position of each symbol.

[0144] Optionally, the W dual-polarization symbol streams are obtained by distributing one bit stream to obtain W distributed bit streams, which are then obtained by dual-polarization symbol mapping and framing.

[0145] In some applications, 16QAM symbol mapping is used, with the sign values ​​of the 16 constellation points on the corresponding 16QAM constellation diagram being {±1±1j, ±1±3j, ±3±1j, ±3±3j}. For example... Figure 10 As shown in example (a), the four outermost constellation points in the constellation diagram are represented by hollow circles, namely -3-3j, -3+3j, 3-3j, and 3+3j, and the four innermost constellation points are represented by vertical circles, namely -1-1j, -1+1j, 1-1j, and 1+1j. Figure 10Example (b) provides a 16QAM symbol mapping method where a 16QAM symbol in the X-polarization direction or the Y-polarization direction is obtained by mapping 4 bits. For example, 0000 is mapped to -3-3j, 0101 is mapped to -1-1j, 0010 is mapped to -3+3j, 0111 is mapped to -1+1j, 1010 is mapped to 3+3j, 1111 is mapped to 1+1j, 1000 is mapped to 3-3j, and 1101 is mapped to 1-1j.

[0146] The aforementioned W first dual-polarization symbol streams are sent to a delay module for processing to obtain W second dual-polarization symbol streams, which serve as the W dual-polarization symbol streams to be transmitted. Specifically, at least one of the W first dual-polarization symbol streams can be delayed to obtain the W dual-polarization symbol streams to be transmitted; the delay value corresponding to the delayed first dual-polarization symbol stream is K×(N). PG / W) double-polarization symbols, where K is a positive integer not equal to an integer multiple of W. Alternatively, as... Figure 7 As shown, the first dual-polarized symbol stream i (0≤i≤W-1) is fed into delay processing i for processing, resulting in the output second dual-polarized symbol stream i. In some specific applications, the above delay processing i delays the input dual-polarized symbol stream by M. i Two polarization symbols, where M i =(N PG / W)×i+N PG ×a, where a is an integer. When a = 0, for the delay processing 0, the number of delayed double-polarized symbols M0 is 0, that is, the first double-polarized symbol stream 0 is not delayed and is directly used as the output second double-polarized symbol stream 0. a can also be other integers, which are not limited in this application.

[0147] Figure 11 A specific implementation of the delayed processing i is given. Delayed processing i includes M. i Each storage element, such as Figure 11 The symbol is represented by "D". Each memory cell "D" stores one dual-polarization symbol. For each operation, starting from the Mth... i -1 dual-polarization symbol is read from the rightmost memory cell and used as one dual-polarization symbol in the output dual-polarization symbol stream; from the 0th to the Mth... i - Shift the data (contents) of 2 storage units to the right by 1 double polarization symbol; write 1 double polarization symbol from the input double polarization symbol stream to the 0th storage unit (i.e., the leftmost storage unit).

[0148] Figure 12Another specific implementation of delay processing i is given. The input dual-polarization symbol stream is represented by two symbol streams, namely, the input X-polarization symbol stream and the input Y-polarization symbol stream. In this case, delay processing i delays the input X-polarization symbol stream and the input Y-polarization symbol stream respectively to obtain the output X-polarization symbol stream and the output Y-polarization symbol stream. For the X (or Y) polarization direction, delay processing i includes M i Each storage unit, such as Figure 12 China adopts "D" X (or "D") Y ") indicates. Each storage unit "D X (or "D") Y The symbol ") is used to store one symbol. This stored symbol can be understood as a dual-polarization symbol, one symbol in the X-polarization direction (or Y-polarization direction). For each operation, starting from the Mth... i -1 symbol is read from the rightmost memory cell and used as one symbol in the X-polarization direction (or Y-polarization direction) of the output dual-polarization symbol stream; from the 0th to the Mth... i - Shift the data of the two storage units to the right by one symbol; write one symbol in the X polarization direction (or Y polarization direction) of the input dual polarization symbol stream to the 0th storage unit (i.e., the leftmost storage unit).

[0149] Figure 13 Another specific implementation of the delay processing i is given. The input dual-polarization symbol stream is represented by four data streams, namely input X I Data stream (data stream of the input dual-polarization symbol stream in the I-path component of the X-polarization direction), input X Q Data stream (data stream of the Q-path component of the input dual-polarization symbol stream in the X-polarization direction), input Y I Data stream (data stream of the I-path component of the input dual-polarization symbol stream in the Y-polarization direction), input Y Q The data stream (is the data stream of the Q-path components of the input dual-polarization symbol stream in the Y-polarization direction). At this time, the delay processing i processes the input X... I Data stream, input X Q Data stream, input Y I Data stream, input Y Q The data stream is delayed to obtain the output X I Data stream, output X Q Data stream, output Y I Data stream, output Y Q Data flow. For X I Data stream (or X) Q Data stream, or Y I Data stream, or Y Q Data stream), delayed processing i includes M i Each storage unit, such as Figure 13 China adopts "D" XI (or "D") XQ ", or "D" YI ", or "D" YQ ") indicates. Each storage unit "D XI (or "D") XQ ", or "D" YI ", or "D" YQ The symbol ") is used to store one data point, which is the I-path component (or Q-path component, or I-path component, or Q-path component) of a dual-polarization symbol in the X-polarization direction. For each operation, starting from the M-th... i -1 data is read from the rightmost memory cell as the I-path component (or Q-path component, or I-path component, or Q-path component) in the X-polarization direction of the output dual-polarization symbol stream; from the 0th to the Mth... i - The data in the first two storage units is shifted one storage unit to the right; the I-path component (or Q-path component in the X-polarization direction, or I-path component in the Y-polarization direction, or Q-path component in the Y-polarization direction) of one dual-polarization symbol in the input dual-polarization symbol stream is written into the 0th storage unit (i.e., the leftmost storage unit).

[0150] It should be noted that for delay processing 0, the number of storage units can be 0, that is, the first dual-polarization symbol stream i=0 is not delayed, and is directly used as the output second dual-polarization symbol stream i=0.

[0151] Step S102: The transmitting end sends W dual-polarization symbol streams.

[0152] In this embodiment, the transmitting end carries W dual-polarization symbol streams on W subcarriers respectively, and then performs subcarrier multiplexing on the W subcarriers to obtain one signal, which is then transmitted by the transmitting end.

[0153] It should be noted that in W dual-polarization symbol streams, each dual-polarization symbol stream is carried on one subcarrier, and the W dual-polarization symbol streams are carried on W subcarriers, which typically use different wavelengths / frequencies. The W subcarriers are multiplexed to obtain a single signal for transmission. Considering that each subcarrier uses a different frequency, subcarrier multiplexing is also called frequency division multiplexing (FDM), and the data processing scheme is also called DSCM or FDM.

[0154] Step S103: The receiving end receives W dual-polarization symbol streams obtained through transmission and performs signal processing on the received W dual-polarization symbol streams.

[0155] In this embodiment, after receiving the optical signal, the receiving end processes the optical signal to obtain W dual-polarization symbol streams, and then... Figure 1 The description in the document describes signal processing of W dual-polarized symbol streams.

[0156] It should be noted that the receiving end demultiplexes the received signal to obtain W received sub-signals, each corresponding to W subcarriers. Each of the W subcarriers contains multiple received superframes. The superframes received by the receiving end are those transmitted through the channel, which can be understood as distorted signals affected by noise or other impairments in the channel. That is, the superframes received by the receiving end are different from those transmitted by the transmitting end; for example, the superframes received by the receiving end and those transmitted by the transmitting end are not aligned. Furthermore, a superframe corresponding to one subcarrier among the W subcarriers is not aligned with another superframe corresponding to a different subcarrier. The receiving end needs to perform frame synchronization based on frame synchronization symbols or training symbols and perform deskew processing on the data between subcarriers to obtain the corresponding W transmitted superframes. The specific operations after the receiving end receives the superframes are not described in detail in this application; please refer to [reference needed]. Figure 1 The system architecture diagram shown illustrates, for example, the signal processing performed by the receiving-end DSP processor on the received superframes, including operations such as dispersion compensation, synchronization, and phase recovery.

[0157] To better understand the embodiments of this application, some examples are introduced below based on the superframes (also known as data frames, or multiframes, or DSP frames) provided in the embodiments of this application.

[0158] Example 1:

[0159] Consider W = 2. For example... Figure 14 The first dual-polarized symbol stream 0 is not delayed and is directly used as the output second dual-polarized symbol stream 0; the first dual-polarized symbol stream 1 undergoes delay processing 1, with a delay M1 = N. PG / 2 dual-polarization symbols are used to obtain the second dual-polarization symbol stream 1. That is, in this embodiment, the second dual-polarization symbol stream 0 and the second dual-polarization symbol stream 1 are carried on two subcarriers respectively, and the subcarriers are multiplexed to obtain one signal for output. The first dual-polarization symbol stream 0 and the first dual-polarization symbol stream 1 contain multiple superframes.

[0160] Consider N PG =64, the total number of symbols N in any polarization direction in each superframe. F=87552.

[0161] Consider the first superframe in the first dual-polarization symbol stream 0 and the second superframe in the first dual-polarization symbol stream 1. In any polarization direction, consider the payload symbols (symbols before framing) in each superframe as N. CW =172032 / 2 = 86016 symbols. In some applications, the 86016 payload symbols are obtained through 16QAM modulation, i.e., 16QAM symbols. In other applications, the 86016 payload symbols are obtained through QPSK modulation, i.e., QPSK symbols.

[0162] The first and second superframes together contain 172,032 payload symbols, the same number as the payload symbols in the current 400ZR+, 800ZR, and 800ZR+ systems. It should be understood that the bit data corresponding to the payload symbols comes from data obtained through coding and interleaving. In other words, the framing scheme adopted is compatible with the current 400ZR+, 800ZR, and 800ZR+ coding and interleaving schemes, which is beneficial for hardware implementation.

[0163] Each superframe in the first (or second) superframe includes N SF = 12 subframes, and the total number of symbols N in one polarization direction F =87552. The number of pilot symbols N in each subframe along one polarization direction. PS =114, per N PG =The first symbol in the 64 symbols is the pilot symbol, and the number of training symbols N TS =11, each subframe contains a total of N S = 7296 symbols. Subframe 1 is the first subframe, and subframes 2 through 12 are the second to twelfth subframes. Table 1 shows some parameter combinations for the superframe (both the first and second superframes satisfy the conditions given in Table 1), including the number N of frame synchronization symbols in a superframe along a single polarization direction. FAW and the number of reserved symbols N RES In the embodiments of this application, the symbols remaining after removing the payload symbols, training symbols, pilot symbols, and frame synchronization symbols in a superframe can be referred to as reserved symbols.

[0164] Table 1

[0165] Serial Number <![CDATA[N CW ]]> <![CDATA[N SF ]]> <![CDATA[N PG ]]> <![CDATA[N PS ]]> <![CDATA[N S ]]> <![CDATA[N F ]]> <![CDATA[N TS ]]> <![CDATA[N FAW +N RES ]]> <![CDATA[N FAW ]]> <![CDATA[N RES ]]> 1 86016 12 64 114 7296 87552 11 48 10 38 2 86016 12 64 114 7296 87552 11 48 12 36 3 86016 12 64 114 7296 87552 11 48 14 34 4 86016 12 64 114 7296 87552 11 48 16 32 5 86016 12 64 114 7296 87552 11 48 18 30 6 86016 12 64 114 7296 87552 11 48 20 28 7 86016 12 64 114 7296 87552 11 48 22 26 8 86016 12 64 114 7296 87552 11 48 24 24 9 86016 12 64 114 7296 87552 11 48 26 22 10 86016 12 64 114 7296 87552 11 48 28 20 11 86016 12 64 114 7296 87552 11 48 30 18

[0166] It should be understood that Table 1 above provides a variety of possible superframe schemes, where the number of frame synchronization symbols N FAWAll numbers are even, effectively ensuring that the frame synchronization symbols can meet DC balance. Moreover, the relatively long number of frame synchronization symbols allows the receiving end to identify the position of the frame synchronization symbols better and more accurately during synchronization processing, making the transmission system more robust and reliable.

[0167] It should be noted that the number of symbols in this application can be understood as the number of dual-polarization symbols or the number of symbols in one polarization direction; moreover, the number of different symbols in both polarization directions is the same. For example, if there are 11 training symbols in one polarization direction, there are also 11 training symbols in the other polarization direction, resulting in 11 dual-polarization training symbols overall. Furthermore, the serial numbers in Table 1 are only used to distinguish different parameter combinations and do not constitute any other limitation. The following tables can be interpreted in the same way based on the above explanation, and will not be repeated in this application.

[0168] It should be understood that for a superframe using the parameter combinations in Table 1, the number of pilot symbols N PS =114, pilot spacing N PG =64, Number of training symbols N TS =11, each subframe includes N S =7296 symbols, all of which are equal to the parameters in the current 800ZR / 800ZR+ framing, which is well compatible with the current DSP framing scheme of 800ZR and 800ZR+ and facilitates hardware implementation.

[0169] It should be understood that when a superframe uses the parameter combination of item 7 in Table 1, such as Figure 15 As shown, the number of pilot symbols N in each superframe PS =114, pilot spacing N PG =64, Number of training symbols N TS =11, each subframe contains a total of N S = 7296 symbols, number of frame synchronization symbols N FAW =22 are all equal to the parameters in the 800ZR / 800ZR+ framing, which is more compatible with the DSP framing scheme of 800ZR and 800ZR+ and is more conducive to hardware implementation.

[0170] Consider N PG =64, Delay processing 1 delays the input dual-polarization symbol stream (first dual-polarization symbol stream 1) by M1=N. PG / 2 = 32 dual-polarization symbols yield the output of the second dual-polarization symbol stream 1. The second dual-polarization symbol data stream 0 and the second dual-polarization symbol data stream 1 are sent in parallel in the time dimension, as shown below. Figure 15As shown, taking the superframe within the dashed box as an example, the first pilot symbol of the second superframe is sent together with the 33rd symbol of the first superframe, and so on. In the second dual-polarization symbol stream 1, each pilot symbol is spaced 64 units apart from its adjacent counterparts, and 32 units apart from its adjacent counterparts in the second dual-polarization symbol stream 0. (Combined...) Figure 15 In the second dual-polarization symbol stream 1, the first pilot symbol in the second superframe is spaced 32 symbols apart from the first and second pilot symbols in the first superframe of the second dual-polarization symbol stream 0. This means the first pilot symbol in the second superframe is sent together with the 33rd symbol of the first superframe. Using the corresponding 33rd symbol in the first superframe as a reference, the interval between it and the first (1st) and second (65th) pilot symbols of that first superframe is 32 symbols, which is less than the traditional N. PG =64. When the receiver performs joint subcarrier recovery processing, the pilot symbol spacing used for carrier phase recovery processing can be considered to be halved from the traditional 64 symbols to 32 symbols, further improving anti-dispersion capability and phase noise tolerance. The data processing scheme provided in this implementation can be applied to future scenarios using multi-subcarrier transmission, such as 800Gbps multi-subcarrier transmission using QPSK modulation, 1.2Tbps multi-subcarrier transmission using 16QAM modulation, 1.6Tbps multi-subcarrier transmission using 16QAM modulation, and even higher speed transmission scenarios such as 2.4T / 3.2T.

[0171] Example 2:

[0172] Based on Example 1, consider W as 2 and N as... PG =64, the total number of symbols N in any polarization direction in a superframe. F =175104.

[0173] Consider the first superframe in the first dual-polarization symbol stream 0 and the second superframe in the first dual-polarization symbol stream 1. In any polarization direction, consider the payload symbols (symbols before framing) in each superframe as N. CW = 172032 symbols. In some applications, the 172032 payload symbols are obtained through 16QAM modulation, i.e., 16QAM symbols. In other applications, the 172032 payload symbols are obtained through QPSK modulation, i.e., QPSK symbols.

[0174] In any polarization direction, the total number of symbols N in the first superframe (or the second superframe) F =175104, Number of load symbols N CW =172032, number of frame synchronization symbols N FAW =22, retain the number of signs NRES =74, number of subframes N SF =24; each subframe contains a total of N S = 7296 symbols, number of pilot symbols N PS =114, pilot spacing N PG =64, Number of training symbols N TS =11. It should be understood that in the embodiments of this application, the number of symbols refers to the number of symbols in any polarization direction, and also refers to the number of dual-polarization symbols.

[0175] It should be understood that the framing scheme of the first or second superframe is completely consistent with the current DSP framing scheme of 800ZR and 800ZR+, has good compatibility, and is more conducive to hardware implementation.

[0176] Consider N PG =64, Delay processing 1 delays the input dual-polarization symbol stream (first dual-polarization symbol stream 1) by M1=N. PG / 2 = 32 dual-polarization symbols yield the output of the second dual-polarization symbol stream 1. The second dual-polarization symbol data stream 0 and the second dual-polarization symbol data stream 1 are sent in parallel in the time dimension, as shown below. Figure 16 As shown, taking the superframe within the dashed box as an example, the first pilot symbol of the second superframe is sent together with the 33rd symbol of the first superframe, and so on. In the second dual-polarization symbol stream 1, each pilot symbol is spaced 64 units apart from its adjacent counterparts, and 32 units apart from its adjacent counterparts in the second dual-polarization symbol stream 0. (Combined...) Figure 16 In the second dual-polarization symbol stream 1, the first pilot symbol in the second superframe is spaced 32 symbols apart from the first and second pilot symbols in the first superframe of the second dual-polarization symbol stream 0. This means the first pilot symbol in the second superframe is sent together with the 33rd symbol of the first superframe. Using the corresponding 33rd symbol in the first superframe as a reference, the interval between it and the first (1st) and second (65th) pilot symbols of that first superframe is 32 symbols, which is less than the traditional N. PG =64. When the receiver performs joint subcarrier recovery processing, the pilot symbol spacing used for carrier phase recovery processing can be considered to be halved from the traditional 64 symbols to 32 symbols, further improving anti-dispersion capability and phase-noise tolerance. The data processing scheme provided in this implementation can be applied to future scenarios using multi-subcarrier transmission, such as 800Gbps multi-subcarrier transmission using QPSK modulation, 1.2Tbps multi-subcarrier transmission using 16QAM modulation, 1.6Tbps multi-subcarrier transmission using 16QAM modulation, and even higher speed transmission scenarios such as 2.4T / 3.2T.

[0177] Example 3:

[0178] Consider W to be 4. For example... Figure 17 The first dual-polarized symbol stream 0 is not delayed and is directly used as the output second dual-polarized symbol stream 0; the first dual-polarized symbol stream 1 undergoes delay processing 1, with a delay M1 = N. PG / 4 dual-polarization symbols are used to obtain the output second dual-polarization symbol stream 1; the first dual-polarization symbol stream 2 is processed by delay 2, with delay M1 = N. PG / 2 dual-polarization symbols are used to obtain the second dual-polarization symbol stream 2; the first dual-polarization symbol stream 3 is processed by delay 3, with delay M1 = 3N. PG Four dual-polarization symbols are used to obtain the output second dual-polarization symbol stream 3. That is, in this embodiment, the second dual-polarization symbol stream 0, second dual-polarization symbol stream 1, second dual-polarization symbol stream 2, and second dual-polarization symbol stream 3 are each carried on four subcarriers and multiplexed to obtain one output signal. The first dual-polarization symbol stream 0, first dual-polarization symbol stream 1, first dual-polarization symbol stream 2, and first dual-polarization symbol stream 3 each contain multiple superframes.

[0179] Consider N PG =64, the total number of symbols N in any polarization direction in each superframe. F =87552.

[0180] Consider the first superframe in the first dual-polarization symbol stream 0, the second superframe in the first dual-polarization symbol stream 1, the third superframe in the first dual-polarization symbol stream 2, and the fourth superframe in the first dual-polarization symbol stream 3. In any polarization direction, consider N as the number of payload symbols (symbols before framing) in each superframe. CW = 86016 symbols. In some applications, the 86016 payload symbols are obtained through 16QAM modulation, i.e., 16QAM symbols. In other applications, the 86016 payload symbols are obtained through QPSK modulation, i.e., QPSK symbols.

[0181] Each superframe in the first (or second, third, or fourth) superframe includes N SF = 12 subframes, and the total number of symbols N in one polarization direction F =87552. The number of pilot symbols N in each subframe along one polarization direction. PS =114, per N PG =The first symbol in the 64 symbols is the pilot symbol, and the number of training symbols N TS =11, each subframe contains a total of N S= 7296 symbols. Subframe 1 is the first subframe, and subframes 2 through 12 are the second to twelfth subframes. The superframe parameters are shown in Table 1. It should be understood that for a superframe using the parameter combinations in Table 1, the number of pilot symbols N... PS =114, pilot spacing N PG =64, Number of training symbols N TS =11, each subframe includes N S =7296 symbols, all of which are equal to the parameters in the current 800ZR / 800ZR+ framing, which is well compatible with the current DSP framing scheme of 800ZR and 800ZR+ and facilitates hardware implementation.

[0182] It should be understood that when a superframe uses the parameter combination of item 7 in Table 1, such as Figure 18 As shown, the number of pilot symbols N in each superframe PS =114, pilot spacing N PG =64, Number of training symbols N TS =11, each subframe contains a total of N S = 7296 symbols, number of frame synchronization symbols N FAW =22 are all equal to the parameters in the 800ZR / 800ZR+ framing, which is more compatible with the DSP framing scheme of 800ZR and 800ZR+ and is more conducive to hardware implementation.

[0183] like Figure 18 As shown, consider N PG =64, Delay processing 1 delays the input dual-polarization symbol stream (first dual-polarization symbol stream 1) by M1=N. PG / 4 = 16 dual-polarization symbols yield the output second dual-polarization symbol stream 1. Delay processing 2 delays the input dual-polarization symbol stream (first dual-polarization symbol stream 2) by M2 = N. PG / 2 = 32 dual-polarization symbols are used to obtain the output second dual-polarization symbol stream 2. Delay processing 3 delays the input dual-polarization symbol stream (first dual-polarization symbol stream 3) by M1 = 3N. PG / 4 = 48 dual-polarization symbols are used to obtain the second dual-polarization symbol stream 3.

[0184] The second dual-polarization symbol data streams 0, 1, 2, and 3 are transmitted in parallel over time. In the second dual-polarization symbol stream 1, each pilot symbol is spaced 64 units apart from its adjacent counterparts, and the intervals between adjacent pilot symbols in the second dual-polarization symbol stream 0 are 16 and 48 units, respectively. Similarly, in the second dual-polarization symbol stream 2, each pilot symbol is spaced 64 units apart from its adjacent counterparts, and the intervals between adjacent pilot symbols in the second dual-polarization symbol stream 1 are 16 and 48 units, respectively. Likewise, in the second dual-polarization symbol stream 3, each pilot symbol is spaced 64 units apart from its adjacent counterparts, and the intervals between adjacent pilot symbols in the second dual-polarization symbol stream 2 are 16 and 48 units, respectively.

[0185] Consider four second-polarization symbol data streams that are sent in parallel in the time dimension, such as... Figure 18 As shown, taking the superframe within the dashed box as an example, the first pilot symbol of the fourth superframe is transmitted together with the 17th symbol of the third superframe, the 33rd symbol of the second superframe, and the 49th symbol of the first superframe, and so on. It can be seen that the equivalent pilot symbol interval of this multi-carrier transmission scheme is 16, which is less than the traditional N. PG =64. When the receiver performs joint subcarrier recovery processing, the pilot symbol spacing used for carrier phase recovery processing can be considered to be reduced from the traditional 64 symbols to one-quarter, or 16 symbols, further improving anti-dispersion capability and phase noise tolerance. The data processing scheme provided in this implementation can be applied to future scenarios using multi-subcarrier transmission, such as 800Gbps multi-subcarrier transmission using QPSK modulation, 1.2Tbps multi-subcarrier transmission using 16QAM modulation, 1.6Tbps multi-subcarrier transmission using 16QAM modulation, and even higher speeds such as 2.4T / 3.2T transmission scenarios.

[0186] Example 4:

[0187] Based on Example 3, considering W as 4 and N... PG =64, the total number of symbols N in any polarization direction in a superframe. F =175104.

[0188] Consider the first superframe in the first dual-polarization symbol stream 0, the second superframe in the first dual-polarization symbol stream 1, the third superframe in the first dual-polarization symbol stream 2, and the fourth superframe in the first dual-polarization symbol stream 3. In any polarization direction, consider N as the number of payload symbols (symbols before framing) in each superframe. CW= 172032 symbols. In some applications, the 172032 payload symbols are obtained through 16QAM modulation, i.e., 16QAM symbols. In other applications, the 172032 payload symbols are obtained through QPSK modulation, i.e., QPSK symbols.

[0189] In any polarization direction, the total number of symbols N in the first superframe (or the second superframe, the third superframe, or the fourth superframe) F =175104, Number of load symbols N CW =172032, number of frame synchronization symbols N FAW =22, retain the number of signs N RES =74, number of subframes N SF =24; each subframe contains a total of N S = 7296 symbols, number of pilot symbols N PS =114, pilot spacing N PG =64, Number of training symbols N TS =11. It should be understood that in the embodiments of this application, the number of symbols refers to the number of symbols in any polarization direction, and also refers to the number of dual-polarization symbols.

[0190] It should be understood that the framing scheme of the first, second, third, or fourth superframe is completely consistent with the current DSP framing scheme of 800ZR and 800ZR+, has good compatibility, and is more conducive to hardware implementation.

[0191] like Figure 19 As shown, consider N PG =64, Delay processing 1 delays the input dual-polarization symbol stream (first dual-polarization symbol stream 1) by M1=N. PG / 4 = 16 dual-polarization symbols yield the output second dual-polarization symbol stream 1. Delay processing 2 delays the input dual-polarization symbol stream (first dual-polarization symbol stream 2) by M2 = N. PG / 2 = 32 dual-polarization symbols are used to obtain the output second dual-polarization symbol stream 2. Delay processing 3 delays the input dual-polarization symbol stream (first dual-polarization symbol stream 3) by M1 = 3N. PG / 4 = 48 dual-polarization symbols are used to obtain the second dual-polarization symbol stream 3.

[0192] The second dual-polarization symbol data streams 0, 1, 2, and 3 are transmitted in parallel over time. In the second dual-polarization symbol stream 1, each pilot symbol is spaced 64 units apart from its adjacent counterparts, and the intervals between adjacent pilot symbols in the second dual-polarization symbol stream 0 are 16 and 48 units, respectively. Similarly, in the second dual-polarization symbol stream 2, each pilot symbol is spaced 64 units apart from its adjacent counterparts, and the intervals between adjacent pilot symbols in the second dual-polarization symbol stream 1 are 16 and 48 units, respectively. Likewise, in the second dual-polarization symbol stream 3, each pilot symbol is spaced 64 units apart from its adjacent counterparts, and the intervals between adjacent pilot symbols in the second dual-polarization symbol stream 2 are 16 and 48 units, respectively.

[0193] Consider four second-polarization symbol data streams that are sent in parallel in the time dimension, such as... Figure 19 As shown, taking the superframe within the dashed box as an example, the first pilot symbol of the fourth superframe is transmitted together with the 17th symbol of the third superframe, the 33rd symbol of the second superframe, and the 49th symbol of the first superframe, and so on. It can be seen that the equivalent pilot symbol interval of this multi-carrier transmission scheme is 16, which is less than the traditional N. PG =64. When the receiver performs joint subcarrier recovery processing, the pilot symbol spacing used for carrier phase recovery processing can be considered to be reduced from the traditional 64 symbols to one-quarter, or 16 symbols, further improving anti-dispersion capability and phase noise tolerance. The data processing scheme provided in this implementation can be applied to future scenarios using multi-subcarrier transmission, such as 800Gbps multi-subcarrier transmission using QPSK modulation, 1.2Tbps multi-subcarrier transmission using 16QAM modulation, 1.6Tbps multi-subcarrier transmission using 16QAM modulation, and even higher speeds such as 2.4T / 3.2T transmission scenarios.

[0194] It should be noted that the above embodiments are based on the consideration of... Figure 7 The data processing method shown here, in which the delay processing operation is performed after "dual polarization symbol mapping and framing", can also be used as follows: Figure 20 The equivalent execution method shown first frames the encoded bit data to obtain W first bit streams, namely first bit stream 0, first bit stream 1, ..., first bit stream W-1. Then, it performs delay processing to obtain W second bit streams. Finally, it performs dual-polarization symbol mapping to obtain W second dual-polarization symbol streams, which are used as the dual-polarization symbol streams to be transmitted. Figure 20 As shown, the first bitstream i (0≤i≤W-1) is fed into the delay processor i for processing, resulting in the output second bitstream i. In some specific applications, such as... Figure 21 As shown, delay processing i delays the input bitstream by M. i A number of bit blocks, of which Mi =(N PG / W)×i, each bit group is mapped to a dual-polarization symbol. For delay processing 0, the number of delayed bit groups M0 is 0, meaning the first bit stream 0 is not delayed and is directly used as the output second bit stream 0. When the dual-polarization symbol mapping uses DP-QPSK mapping, each bit group contains 4 bits, meaning delay processing i delays the input bit stream by 4×(N)×i. PG / W)×i bits, each bit group is mapped to a DP-QPSK symbol after DP-QPSK mapping; when the dual polarization symbol mapping uses DP-16QAM mapping, each bit group contains 8 bits, that is, the delay processing i delays the input bit stream by 8×(N) bits. PG / W)×i bits, each bit group is mapped by DP-16QAM to obtain a DP-16QAM symbol.

[0195] Example 5:

[0196] Consider W = 2. For example... Figure 22 The first bitstream 0 is not delayed and is directly used as the output second bitstream 0; the first bitstream 1 is delayed by 1, with a delay M1 = N. PG Two bit groups are used to obtain the second output bit stream 1. The second bit stream 0 and the second bit stream 1 are then subjected to dual-polarization symbol mapping to obtain the first dual-polarization symbol stream 0 and the first dual-polarization symbol stream 1 to be transmitted. That is, in this embodiment, the first dual-polarization symbol stream 0 and the first dual-polarization symbol stream 1 are carried on two subcarriers and multiplexed to obtain a single signal for output. Both the first dual-polarization symbol stream 0 and the first dual-polarization symbol stream 1 contain multiple superframes. Each bit group described above is mapped to a dual-polarization symbol.

[0197] Consider N PG =64, the total number of symbols N in any polarization direction in each superframe. F =87552. When the dual polarization symbol mapping uses DP-QPSK mapping, each bit group contains 4 bits, that is, delay processing 1 delays the first input bit stream 1 by 128 bits; when the dual polarization symbol mapping uses DP-QPSK mapping, each bit group contains 8 bits, that is, delay processing i delays the input bit stream by 256 bits.

[0198] Consider the first superframe in the first dual-polarization symbol stream 0 and the second superframe in the first dual-polarization symbol stream 1. In any polarization direction, consider the payload symbols (symbols before framing) in each superframe as N. CW=172032 / 2 = 86016 symbols. In some applications, the 86016 payload symbols are obtained through 16QAM modulation, i.e., 16QAM symbols. In other applications, the 86016 payload symbols are obtained through QPSK modulation, i.e., QPSK symbols.

[0199] The first and second superframes together contain 172,032 payload symbols, the same number as the payload symbols in the current 400ZR+, 800ZR, and 800ZR+ systems. It should be understood that the bit data corresponding to the payload symbols comes from data obtained through coding and interleaving. In other words, the framing scheme adopted is compatible with the current 400ZR+, 800ZR, and 800ZR+ coding and interleaving schemes, which is beneficial for hardware implementation.

[0200] Each superframe in the first (or second) superframe includes N SF = 12 subframes, and the total number of symbols N in one polarization direction F =87552. The number of pilot symbols N in each subframe along one polarization direction. PS =114, per N PG =The first symbol in the 64 symbols is the pilot symbol, and the number of training symbols N TS =11, each subframe contains a total of N S = 7296 symbols. Among them, subframe 1 is the first subframe, and subframes 2 to 12 are the second to twelfth subframes. The above superframe scheme can be well compatible with the current DSP framing schemes of 800ZR and 800ZR+, which is beneficial to hardware implementation.

[0201] The first dual-polarization symbol data stream 0 and the first dual-polarization symbol data stream 1 are transmitted in parallel in the time dimension. At this time, the first pilot symbol of the second superframe and the 33rd symbol of the first superframe are transmitted together, similar to Embodiment 1. In the first dual-polarization symbol stream 1, each pilot symbol is spaced 64 units apart from its adjacent counterpart, and 32 units apart from its adjacent counterpart in the first dual-polarization symbol stream 0. Combined with... Figure 15 In the first dual-polarization symbol stream 1, the first pilot symbol in the second superframe is spaced 32 symbols apart from the first and second pilot symbols in the first dual-polarization symbol stream 0. This means the first pilot symbol in the second superframe is sent together with the 33rd symbol of the first superframe. Using the corresponding 33rd symbol in the first superframe as a reference, the interval between it and the first (1st) and second (65th) pilot symbols of that first superframe is 32 symbols, which is less than the traditional N. PG=64. When the receiver performs joint subcarrier recovery processing, the pilot symbol spacing used for carrier phase recovery processing can be considered to be halved from the traditional 64 symbols to 32 symbols, further improving anti-dispersion capability and phase noise tolerance. The data processing scheme provided in this implementation can be applied to future scenarios using multi-subcarrier transmission, such as 800Gbps multi-subcarrier transmission using QPSK modulation, 1.2Tbps multi-subcarrier transmission using 16QAM modulation, 1.6Tbps multi-subcarrier transmission using 16QAM modulation, and even higher speed transmission scenarios such as 2.4T / 3.2T.

[0202] Example 6:

[0203] Based on Example 5, considering W as 2 and N as 2 PG =64, the total number of symbols N in any polarization direction in a superframe. F =175104.

[0204] Consider the first superframe in the first dual-polarization symbol stream 0 and the second superframe in the first dual-polarization symbol stream 1. In any polarization direction, consider the payload symbols (symbols before framing) in each superframe as N. CW = 172032 symbols. In some applications, the 172032 payload symbols are obtained through 16QAM modulation, i.e., 16QAM symbols. In other applications, the 172032 payload symbols are obtained through QPSK modulation, i.e., QPSK symbols.

[0205] In any polarization direction, the total number of symbols N in the first superframe (or the second superframe) F =175104, Number of load symbols N CW =172032, number of frame synchronization symbols N FAW =22, retain the number of signs N RES =74, number of subframes N SF =24; each subframe contains a total of N S = 7296 symbols, number of pilot symbols N PS =114, pilot spacing N PG =64, Number of training symbols N TS =11. It should be understood that in the embodiments of this application, the number of symbols refers to the number of symbols in any polarization direction, and also refers to the number of dual-polarization symbols.

[0206] It should be understood that the framing scheme of the first or second superframe is completely consistent with the current DSP framing scheme of 800ZR and 800ZR+, has good compatibility, and is more conducive to hardware implementation.

[0207] The first dual-polarization symbol data stream 0 and the first dual-polarization symbol data stream 1 are transmitted in parallel in the time dimension. At this time, the first pilot symbol of the second superframe and the 33rd symbol of the first superframe are transmitted together, similar to Embodiment 1. In the first dual-polarization symbol stream 1, each pilot symbol is spaced 64 units apart from its adjacent counterpart, and 32 units apart from its adjacent counterpart in the first dual-polarization symbol stream 0. Combined with... Figure 16 In the first dual-polarization symbol stream 1, the first pilot symbol in the second superframe is spaced 32 symbols apart from the first and second pilot symbols in the first dual-polarization symbol stream 0. This means the first pilot symbol in the second superframe is sent together with the 33rd symbol of the first superframe. Using the corresponding 33rd symbol in the first superframe as a reference, the interval between it and the first (1st) and second (65th) pilot symbols of that first superframe is 32 symbols, which is less than the traditional N. PG =64. When the receiver performs joint subcarrier recovery processing, the pilot symbol spacing used for carrier phase recovery processing can be considered to be halved from the traditional 64 symbols to 32 symbols, further improving anti-dispersion capability and phase noise tolerance. The data processing scheme provided in this implementation can be applied to future scenarios using multi-subcarrier transmission, such as 800Gbps multi-subcarrier transmission using QPSK modulation, 1.2Tbps multi-subcarrier transmission using 16QAM modulation, 1.6Tbps multi-subcarrier transmission using 16QAM modulation, and even higher speed transmission scenarios such as 2.4T / 3.2T.

[0208] Figure 23 This is a schematic diagram of a data processing device in an embodiment of this application. The data processing device is applied at the sending end, such as... Figure 23 As shown, the data processing device includes a processing unit 201 and a transmitting unit 202. The processing unit 201 is used to perform the framing processing, delay processing of multiple acquired dual-polarization symbol streams, delay processing of multiple acquired bit streams, and symbol mapping of the delayed bit streams as described in the above embodiments; the specific implementation methods have been described in previous embodiments and will not be repeated here. The transmitting unit 202 is used to perform the action of transmitting multiple dual-polarization symbol streams as described in the above embodiments. Since the transmitting end carries multiple dual-polarization symbol streams on multiple subcarriers respectively, and then multiplexes the multiple subcarriers to obtain one signal, the transmitting unit can also be used to transmit this one signal.

[0209] Figure 24 This is another schematic diagram of the data processing device in an embodiment of this application. This data processing device is applied at the receiving end, such as... Figure 24As shown, the data processing device includes a receiving unit 302, which is used to receive a single signal multiplexed by a subcarrier sent by the transmitting end. Optionally, the data processing device further includes a processing unit 301, which is used to obtain multiple dual-polarization symbol streams from the received single signal and then perform decoding and other operations on the dual-polarization symbol streams.

[0210] It should be understood that Figure 23 and Figure 24 The provided data processing device can also be implemented in other ways. For example, the unit division in the above device is only a logical functional division, and there may be other division methods in actual implementation. For example, multiple units or components may be combined or integrated into another system. In addition, the functional units in the various embodiments of this application may be integrated into one processing unit, or they may be independent physical units, or two or more functional units may be integrated into one processing unit. The integrated unit described above can be implemented in hardware or in the form of software functional units.

[0211] Figure 25 This is a schematic diagram of one structure of the optical module in an embodiment of this application. Figure 25 As shown, the optical module includes a processor 401 and an interface 402. The interface 402 can be a transceiver or an input / output interface, used to receive signals from other devices and transmit them to the processor 401, or to send signals from the processor 401 to other devices. Optionally, the optical module may also include a memory 403, which stores program instructions and data.

[0212] In one possible scenario, the optical module is applied at the transmitting end, and the processor 401 is used to perform the framing processing, delay processing of multiple dual-polarization symbol streams, delay processing of multiple bit streams, and symbol mapping of the delayed bit streams as described in the above embodiments. The specific implementation methods have been described in previous embodiments and will not be repeated here. For example, the processor 401 includes... Figure 23 The processing unit 201 is shown. As an example, processor 401 performs the operations described in the above embodiments to obtain W dual-polarization symbol streams, and sends these W dual-polarization symbol streams through interface 402. In this example, interface 402 can specifically refer to an electrical interface. As another example, processor 401 performs the operations described in the above embodiments to obtain W dual-polarization symbol streams. The modulator in the optical module performs electro-optic conversion and other signal processing based on these W dual-polarization symbol streams to obtain an optical signal, and then sends the optical signal through interface 402. In this example, interface 402 can specifically refer to an optical interface.

[0213] In another possible scenario, the optical module is applied to the receiving end, and the processor 401 is used to execute the operations of the receiving unit 302 in the above embodiment. In other words, the processor 401 includes... Figure 24 The processing unit 301 shown is described above. As an example, the interface receives an optical signal transmitted through a channel. The demodulator in the optical module performs signal processing such as photoelectric conversion on the optical signal to obtain W dual-polarization symbol streams. The processor 401 performs the operations described in the above embodiments on these W dual-polarization symbol streams. In this example, interface 402 specifically refers to an optical interface. As another example, the demodulator in the optical module performs signal processing such as photoelectric conversion on the received optical signal to obtain W dual-polarization symbol streams, and transmits these W dual-polarization symbol streams to the processor 401 through interface 402. The processor 401 performs the operations described in the above embodiments on these W dual-polarization symbol streams. In this example, interface 402 specifically refers to an electrical interface.

[0214] Typically, an optical module consists of optoelectronic devices, a processor, and an interface. The optoelectronic devices include transmitting and receiving devices. The transmitting end of the optical module converts electrical signals into optical signals and transmits them through optical fibers. The receiving end of the optical module receives the optical signals and converts them back into electrical signals.

[0215] It should be noted that the types of optical modules in this application embodiment include, but are not limited to, normal optical modules, near package optics (NPO) modules, and co-packaged optics (CPO) modules. Normal optical modules can perform functions including, but not limited to, digital signal processing (DSP) and clock data recovery (CDR). For example, a normal optical module converts analog signals to digital signals, performs DSP on the digital signals, and then converts them back to analog signals before sending them to the host device. Because DSP requires retiming, a normal optical module can also be called a retimed module. Normal optical modules connect to the host device via an attachment unit interface (AUI). NPO and CPO modules do not have pluggable physical packages and are closer to the host device. NPO and CPO modules can also be called optical engines. NPO or CPO technology is a technology that "packages" the host device (or host chip) and the optical engine. When NPO technology is used to encapsulate the host-side device and the optical engine, the optical engine can be called an NPO module. When CPO technology is used to encapsulate the host-side device and the optical engine, the optical engine can be called a CPO module.

[0216] Figure 26 This is a schematic diagram of the structure of a transmitting device in an embodiment of this application. Figure 26 As shown, the transmitting device includes a host-side device 501 and an optical module 502. The host-side device 501 transmits electrical signals to the optical module 502, which converts the electrical signals into optical signals and transmits them through a channel. For example, the host-side device 501 may specifically be a switch, router, or server. This transmitting device can be a communication device that includes the host-side device 501 and the optical module 502. It should also be understood that the transmitting devices in this embodiment are named based on the data flow direction and do not limit the function of the device; for example, the transmitting device may also have a receiving function.

[0217] Figure 27 This is a schematic diagram of the structure of a receiving device in an embodiment of this application. Figure 27As shown, the receiving device includes a host-side device 601 and an optical module 602. The optical module 602 is used to convert the received optical signal into an electrical signal and send the electrical signal to the host-side device 601. For example, the host-side device 601 may specifically be a switch, router, or server. The receiving device can be a communication device that includes the host-side device 601 and the optical module 602. It should also be understood that the receiving device in this embodiment is named based on the data flow direction and does not limit the function of the device. For example, the receiving device may also have a transmitting function.

[0218] This application also provides an Optical Transport Network (OTN) device, which includes line-side equipment and client-side equipment. The client-side equipment may also be referred to as a tributary-side equipment in some scenarios. The line-side equipment includes a processor and an interface. In one possible scenario, the OTN device is used at the transmitting end, and the processor is used to execute the operation of step 101 in the above embodiment. In another possible scenario, the OTN device is used at the receiving end, and the processor is used to execute the operation of step 103 in the above embodiment. The interface can be a transceiver or an input / output interface, used to receive signals from other devices besides the line-side equipment and transmit them to the processor, or to send signals from the processor to other devices besides the line-side equipment.

[0219] This application also provides a chip. The chip integrates circuitry for implementing the functions of the processor 401 described above, and one or more interfaces. As an example, the chip integrates a memory. As another example, when the chip does not integrate a memory, it can be connected to an external memory via the interface. The chip can perform the method steps of any one or more of the foregoing embodiments. Alternatively, the chip can implement the actions performed by the processing and transmission device in the foregoing embodiments based on program code stored in the memory.

[0220] As an example, the chip in the embodiments of this application can be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. A general-purpose processor can be a microprocessor, any conventional processor, or a processing circuit that implements a specific function.

[0221] This application also provides a computer-readable storage medium including a program or instructions that, when run on a computer, cause the method performed as described in the above method embodiments to be implemented.

[0222] It should be understood that the processor mentioned in the embodiments of this application can be implemented in hardware or software. When implemented in hardware, the processor can be a logic circuit, integrated circuit, etc. When implemented in software, the processor can be a general-purpose processor that reads software code stored in memory. The memory can exist independently and be connected to the processor, or the memory can be integrated with the processor.

[0223] As an example, the processor in the embodiments of this application can be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. A general-purpose processor can be a microprocessor, any conventional processor, or a processing circuit that implements a specific function.

[0224] In embodiments of this application, the memory may be random access memory (RAM), flash memory, read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, hard disks, portable hard disks, CD-ROMs, or any other form of storage medium known in the art. An exemplary storage medium is coupled to a processor, enabling the processor to read information from and write information to the storage medium. Of course, the storage medium may also be a component of the processor. The processor and storage medium may reside in an ASIC. Additionally, the ASIC may reside in a network device or a terminal device. Alternatively, the processor and storage medium may exist as discrete components in the network device or terminal device.

[0225] In the above embodiments, it can be implemented entirely or partially by software, hardware, firmware, or any combination thereof.

[0226] When implemented in hardware, the data processing method provided in this application embodiment may be implemented without reading software code or instructions. For example, it may be implemented by CPU, DSP, ASIC, FPGA, other programmable logic devices, transistor logic devices, hardware components, or any combination thereof.

[0227] When implemented using software, it can be implemented entirely or partially in the form of a computer program product. A computer program product includes one or more computer programs or instructions. When the computer program or instructions are loaded and executed on a computer, all or part of the processes or functions of the embodiments of this application are performed. The computer can be a general-purpose computer, a special-purpose computer, a computer network, a network device, a terminal device, or other programmable device. The computer program or instructions can be stored in or transmitted through a computer-readable storage medium. The computer-readable storage medium can be any available medium that a computer can access, or a data storage device such as a server integrating one or more available media. The available medium can be a magnetic medium, such as a floppy disk, hard disk, or magnetic tape; it can also be an optical medium, such as a Digital Versatile Disc (DVD); or it can be a semiconductor medium, such as a solid-state disk (SSD).

[0228] Finally, it should be noted that the above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A data processing method, characterized in that, The method includes: At least one of the acquired W first dual-polarization symbol streams is delayed to obtain a total of W dual-polarization symbol streams to be transmitted. Each of the W first dual-polarization symbol streams comprises multiple superframes. In any polarization direction, every N consecutive N subframes within each superframe... PG Each symbol includes a pilot symbol, W and N. PG All are integers greater than 1; the delay value corresponding to a first dual-polarization symbol stream after delay processing is K×(N PG / W) double polarization symbols, where K is a positive integer not equal to an integer multiple of W.

2. The method according to claim 1, characterized in that, The delay processing of at least one of the W first dual-polarization symbol streams specifically includes: The first dual-polarized symbol stream i in the W first dual-polarized symbol streams is delayed by i to obtain the dual-polarized symbol stream i to be sent, resulting in a total of W dual-polarized symbol streams to be sent, where 0 ≤ i ≤ W-1, and i is a positive integer, and the delay value corresponding to delay i is M. i A dual-polarization symbol, M i =(M PG / W)×i+N PG ×a, where a is an integer.

3. The method according to claim 1 or 2, characterized in that, W is 2, N PG It is 64.

4. The method according to claim 3, characterized in that, Delay processing is applied to at least one of the W acquired first dual-polarization symbol streams to obtain a total of W dual-polarization symbol streams to be transmitted, specifically including: The first dual-polarized symbol stream 1 is delayed by 32 dual-polarized symbols to obtain the second dual-polarized symbol stream 1. The first dual-polarized symbol stream 0 is not delayed. The two dual-polarized symbol streams to be sent include the first dual-polarized symbol stream 0 and the second dual-polarized symbol stream 1.

5. The method according to claim 1 or 2, characterized in that, W is 4, N PG It is 64.

6. The method according to claim 5, characterized in that, Delay processing is applied to at least one of the W acquired first dual-polarization symbol streams to obtain a total of W dual-polarization symbol streams to be transmitted, specifically including: The first dual-polarized symbol stream 1 is delayed by 16 dual-polarized symbols to obtain the second dual-polarized symbol stream 1; The first dual-polarized symbol stream 2 is delayed by 32 dual-polarized symbols to obtain the second dual-polarized symbol stream 2; The first dual-polarized symbol stream 3 is delayed by 48 dual-polarized symbols to obtain the second dual-polarized symbol stream 3. The first dual-polarized symbol stream 0 is not delayed. The four dual-polarized symbol streams to be sent include the first dual-polarized symbol stream 0, the second dual-polarized symbol stream 1, the second dual-polarized symbol stream 2, and the second dual-polarized symbol stream 3.

7. The method according to any one of claims 2-6, characterized in that, The first dual-polarization symbol stream i includes an X-polarization symbol stream i and a Y-polarization symbol stream i; the delay processing i of the first dual-polarization symbol stream i in the W first dual-polarization symbol streams specifically includes: Symbol delay processing i is performed on both the X-polarized symbol stream i and the Y-polarized symbol stream i, where the delay value corresponding to symbol delay processing i is M. i A symbol.

8. The method according to any one of claims 2-6, characterized in that, The first dual-polarization symbol stream i includes a data stream XI-i of the I-path component in the X-polarization direction, a data stream XQ-i of the Q-path component in the X-polarization direction, a symbol stream YI-i of the I-path component in the Y-polarization direction, and a symbol stream YQ-i of the Q-path component in the Y-polarization direction; The delay processing i of the first dual-polarization symbol stream i in the W first dual-polarization symbol streams specifically includes: The data stream XI-i of the I-path component in the X-polarization direction is subjected to component delay processing XI-i, where the delay value corresponding to component delay processing XI-i is M. i The I-path component of a dual-polarization symbol in the X-polarization direction; The data stream XQ-i of the Q-path component in the X-polarization direction is subjected to component delay processing XQ-i, where the delay value corresponding to component delay processing XQ-i is M. i The Q-path component of a double-polarized symbol in the X-polarization direction; The data stream YI-i with I components in the Y polarization direction is subjected to component delay processing YI-i, where the delay value corresponding to component delay processing YI-i is M. i The I-path component of a dual-polarization symbol in the Y-polarization direction; The data stream YQ-i of the Q-path component in the Y-polarization direction is subjected to component delay processing YQ-i, where the delay value corresponding to component delay processing YQ-i is M. i The Q-path component of a double-polarized symbol in the Y-polarization direction.

9. The method according to any one of claims 1-8, characterized in that, The W dual-polarization symbol streams to be transmitted are each carried on W subcarriers.

10. The method according to any one of claims 1-9, characterized in that, The dual polarization symbol is either a dual polarization 16QAM symbol or a dual polarization QPSK symbol.

11. A data processing method, characterized in that, The method includes: At least one of the W first bit streams is delayed to obtain a total of W second bit streams. The delay value corresponding to one of the delayed first bit streams is K×(N). PG / W) bit blocks, W and N PG All are integers greater than 1, and K is a positive integer not equal to an integer multiple of W; The obtained W second bit streams are subjected to dual-polarization symbol mapping to obtain W dual-polarization symbol streams, wherein each bit group is mapped to a dual-polarization symbol; each of the W dual-polarization symbol streams includes multiple superframes, and in any polarization direction, every consecutive N bits in each subframe of each superframe are... PG Each symbol includes a pilot symbol.

12. The method according to claim 11, characterized in that, The delay processing of at least one of the W acquired first bit streams specifically includes: The first bitstream i in the W first bitstreams is delayed by i to obtain the second bitstream i, resulting in a total of W second bitstreams, where 0 ≤ i ≤ W-1, and i is an integer. The delay value corresponding to the delay processing i is M. i N bit blocks, N i =(M PG / W)×i+N PG ×a, where a is an integer.

13. The method according to claim 11 or 12, characterized in that, W is 2, N PG It is 64.

14. The method according to claim 13, characterized in that, Delaying at least one of the W first bit streams obtained yields a total of W second bit streams, specifically including: The first bit stream 1 is delayed by 32 bits to obtain the second bit stream 1, wherein the first bit stream 0 is not delayed, and the two second bit streams include the first bit stream 0 and the second bit stream 1.

15. The method according to claim 11 or 12, characterized in that, W is 4, N PG It is 64.

16. The method according to claim 15, characterized in that, Delaying at least one of the W first bit streams obtained yields a total of W second bit streams, specifically including: The first bitstream 1 is delayed by 16 bits to obtain the second bitstream 1; The first bitstream 2 is delayed by 32 bits to obtain the second bitstream 2; The first bitstream 3 is delayed by 48 bits to obtain the second bitstream 3. The first bitstream 0 is not delayed. The four second bitstreams include the first bitstream 0, the second bitstream 1, the second bitstream 2, and the second bitstream 3.

17. The method according to any one of claims 11-16, characterized in that, The W dual-polarization symbol streams are carried on W subcarriers respectively.

18. The method according to any one of claims 11-17, characterized in that, The dual-polarization symbol is a dual-polarization 16QAM symbol, and the bit group includes 8 bits; or The dual polarization symbol is a dual polarization QPSK symbol, and the bit group consists of 4 bits.

19. A data processing method, characterized in that, The method includes: Obtain W second dual-polarization symbol streams, wherein the W second dual-polarization symbol streams are obtained by the transmitting end through delay processing of at least one of the W first dual-polarization symbol streams; each of the W first dual-polarization symbol streams includes multiple superframes, and in any polarization direction, every consecutive N in each subframe of each superframe... PG Each symbol includes a pilot symbol, W and N. PG All are integers greater than 1; the delay value corresponding to a first dual-polarization symbol stream after delay processing is K×(N PG / W) double polarization symbols, where K is a positive integer not equal to an integer multiple of W.

20. A data processing method, characterized in that, The method includes: Obtain W dual-polarization symbol streams, wherein each of the W dual-polarization symbol streams comprises multiple superframes, and in any polarization direction, every N consecutive subframes within each superframe... PG Each symbol includes a pilot symbol, W and N. PG All are integers greater than 1; The W dual-polarization symbol streams are obtained by the transmitting end performing dual-polarization symbol mapping on the W second bit streams respectively. The W second bit streams are obtained by the transmitting end performing delay processing on at least one of the acquired W first bit streams; wherein, the delay value corresponding to the first bit stream after delay processing is K×(N). PG / W) bit blocks, where K is a positive integer not equal to an integer multiple of W; each bit block is mapped to a dual-polarization symbol.

21. A data processing apparatus, characterized in that, The device includes: a processing unit, The processing unit is configured to perform delay processing on at least one of the acquired W first dual-polarization symbol streams, resulting in a total of W dual-polarization symbol streams to be transmitted. Each of the W first dual-polarization symbol streams comprises multiple superframes. In any polarization direction, every N consecutive N subframes within each superframe... PG Each symbol includes a pilot symbol, W and N. PG All are integers greater than 1; the delay value corresponding to a first dual-polarization symbol stream after delay processing is K×(N PG / W) double polarization symbols, where K is a positive integer not equal to an integer multiple of W.

22. The apparatus according to claim 21, characterized in that, The processing unit is specifically used for: The first dual-polarized symbol stream i in the W first dual-polarized symbol streams is delayed by i to obtain the dual-polarized symbol stream i to be sent, resulting in a total of W dual-polarized symbol streams to be sent, where 0 ≤ i ≤ W-1, and i is a positive integer, and the delay value corresponding to delay i is M. i A dual-polarization symbol, M i =(N PG / W)×i+N PG ×a, where a is an integer.

23. The apparatus according to claim 21 or 22, characterized in that, W is 2, N PG It is 64.

24. The apparatus according to claim 23, characterized in that, The processing unit is specifically used for: The first dual-polarized symbol stream 1 is delayed by 32 dual-polarized symbols to obtain the second dual-polarized symbol stream 1. The first dual-polarized symbol stream 0 is not delayed. The two dual-polarized symbol streams to be sent include the first dual-polarized symbol stream 0 and the second dual-polarized symbol stream 1.

25. The apparatus according to claim 21 or 22, characterized in that, W is 4, N PG It is 64.

26. The apparatus according to claim 25, characterized in that, The processing unit is specifically used for: The first dual-polarized symbol stream 1 is delayed by 16 dual-polarized symbols to obtain the second dual-polarized symbol stream 1; The first dual-polarized symbol stream 2 is delayed by 32 dual-polarized symbols to obtain the second dual-polarized symbol stream 2; The first dual-polarized symbol stream 3 is delayed by 48 dual-polarized symbols to obtain the second dual-polarized symbol stream 3. The first dual-polarized symbol stream 0 is not delayed. The four dual-polarized symbol streams to be sent include the first dual-polarized symbol stream 0, the second dual-polarized symbol stream 1, the second dual-polarized symbol stream 2, and the second dual-polarized symbol stream 3.

27. The apparatus according to any one of claims 22-26, characterized in that, The first dual-polarization symbol stream i includes an X-polarization symbol stream i and a Y-polarization symbol stream i; the processing unit is specifically used for: Symbol delay processing i is performed on both the X-polarized symbol stream i and the Y-polarized symbol stream i, where the delay value corresponding to symbol delay processing i is M. i A symbol.

28. The apparatus according to any one of claims 22-26, characterized in that, The first dual-polarization symbol stream i includes a data stream XI-i of the I-path component in the X-polarization direction, a data stream XQ-i of the Q-path component in the X-polarization direction, a symbol stream YI-i of the I-path component in the Y-polarization direction, and a symbol stream YQ-i of the Q-path component in the Y-polarization direction; the processing unit is specifically used for: The data stream XI-i of the I-path component in the X-polarization direction is subjected to component delay processing XI-i, where the delay value corresponding to component delay processing XI-i is M. i The I-path component of a dual-polarization symbol in the X-polarization direction; The data stream XQ-i of the Q-path component in the X-polarization direction is subjected to component delay processing XQ-i, where the delay value corresponding to component delay processing XQ-i is M. i The Q-path component of a double-polarized symbol in the X-polarization direction; The data stream YI-i with I components in the Y polarization direction is subjected to component delay processing YI-i, where the delay value corresponding to component delay processing YI-i is M. i The I-path component of a dual-polarization symbol in the Y-polarization direction; The data stream YQ-i of the Q-path component in the Y-polarization direction is subjected to component delay processing YQ-i, where the delay value corresponding to component delay processing YQ-i is M. i The Q-path component of a double-polarized symbol in the Y-polarization direction.

29. The apparatus according to any one of claims 21-28, characterized in that, The W dual-polarization symbol streams to be transmitted are each carried on W subcarriers.

30. The apparatus according to any one of claims 21-29, characterized in that, The dual polarization symbol is either a dual polarization 16QAM symbol or a dual polarization QPSK symbol.

31. A data processing apparatus, characterized in that, The device includes a processing unit and a mapping unit. The processing unit is configured to perform delay processing on at least one of the acquired W first bitstreams to obtain a total of W second bitstreams, wherein the delay value corresponding to one of the delayed first bitstreams is K×(N). PG / W) bit blocks, W and N PG All are integers greater than 1, and K is a positive integer not equal to an integer multiple of W; The mapping unit is used to perform dual-polarization symbol mapping on the obtained W second bit streams to obtain W dual-polarization symbol streams, wherein each bit group is mapped to a dual-polarization symbol; each of the W dual-polarization symbol streams includes multiple superframes, and in any polarization direction, every consecutive N bits in each subframe of each superframe are mapped to a dual-polarization symbol. PG Each symbol includes a pilot symbol.

32. The apparatus according to claim 31, characterized in that, The processing unit is specifically used for: The first bitstream i in the W first bitstreams is delayed by i to obtain the second bitstream i, resulting in a total of W second bitstreams, where 0 ≤ i ≤ W-1, and i is an integer. The delay value corresponding to the delay processing i is M. i A bit block, M i =(N PG / W)×i+N PG ×a, where a is an integer.

33. The apparatus according to claim 31 or 32, characterized in that, W is 2, N PG It is 64.

34. The apparatus according to claim 33, characterized in that, The processing unit is specifically used for: The first bit stream 1 is delayed by 32 bits to obtain the second bit stream 1, wherein the first bit stream 0 is not delayed, and the two second bit streams include the first bit stream 0 and the second bit stream 1.

35. The apparatus according to claim 31 or 32, characterized in that, W is 4, N PG It is 64.

36. The apparatus according to claim 35, characterized in that, The processing unit is specifically used for: The first bitstream 1 is delayed by 16 bits to obtain the second bitstream 1; The first bitstream 2 is delayed by 32 bits to obtain the second bitstream 2; The first bitstream 3 is delayed by 48 bits to obtain the second bitstream 3. The first bitstream 0 is not delayed. The four second bitstreams include the first bitstream 0, the second bitstream 1, the second bitstream 2, and the second bitstream 3.

37. The apparatus according to any one of claims 31-36, characterized in that, The W dual-polarization symbol streams are carried on W subcarriers respectively.

38. The apparatus according to any one of claims 31-37, characterized in that, The dual-polarization symbol is a dual-polarization 16QAM symbol, and the bit group includes 8 bits; or The dual polarization symbol is a dual polarization QPSK symbol, and the bit group consists of 4 bits.

39. A chip, characterized in that, The chip is used to perform the method as described in any one of claims 1-20.

40. An optical module, characterized in that, The optical module includes a processor and an interface, wherein the processor is used in the method as described in any one of claims 1-20 and acquires signals through the interface.

41. A communication device, characterized in that, The communication device includes a host-side device and an optical module as described in claim 40, wherein the optical module is connected to the host-side device.

42. A communication system, characterized in that, The communication system includes a first communication device and a second communication device, wherein at least one of the first communication device and the second communication device is the communication device as described in claim 41, and the first communication device and the second communication device are connected.

Images