A method and system for reconfigurable control of radio frequency front-end networks based on FPGA

Abstract

The application relates to the radio frequency technical field and discloses a reconfigurable control method and system for a radio frequency front-end network based on FPGA, which comprises the following steps: a reconfigurable radio frequency front-end network extracts control parameters from working parameters and maps the control parameters to the reconfigurable radio frequency front-end network; after detecting a synchronous pulse falling edge, local oscillator frequency point comparison and control output are completed; after the local oscillator state is stable, the working state configuration of the reconfigurable radio frequency front-end network is completed; a digital transceiver processor collects baseband receiving signals and respectively obtains link performance indexes of a reconfigurable receiving channel and link performance indexes of a reconfigurable transmitting channel; a system control unit updates receiving radio frequency link compensation parameters according to the link performance indexes of the reconfigurable receiving channel and updates transmitting radio frequency link compensation parameters according to the link performance indexes of the reconfigurable transmitting channel. The application realizes the rapid reconfiguration of the working state of the radio frequency front-end network.

Description

Technical Field

[0001] This application relates to the field of radio frequency technology, and in particular to a reconfigurable control method and system for an FPGA-based radio frequency front-end network. Background Technology

[0002] With the development of communication technology, radio frequency (RF) front-end networks, as the core module of satellite communication systems, play a crucial role in applications such as civilian navigation and disaster monitoring. Traditional RF front-end networks employ a single design, with each mission's electronic system limited to a fixed frequency band, resulting in single-function and independent equipment. As the communication spectrum expands into Q-band, Ka-band, and even EHF-band, the development of RF front-end networks with multi-band coverage and flexible reconfiguration capabilities has become an urgent need.

[0003] Currently, there are two main implementation methods for reconfigurable RF front-end networks: First, frequency band reconfiguration is achieved by combining multiple independent RF links with a switching network. However, this method results in high circuit cost and large area, making it unsuitable for miniaturized communication platforms. Second, reconfigurable filters and other devices are introduced into the RF link, and reconfiguration is achieved by dynamically adjusting parameters such as their operating frequency and bandwidth. This method shows promise in miniaturized platforms. However, the current reconfiguration control process has the following problems: First, when adjusting the filter center frequency, the phase delay of the current operating frequency will change abruptly, leading to a surge in the bit error rate. Second, the filter passband may experience short-term collapse or shift during the reconfiguration process, causing a sudden drop in signal amplitude or overshoot. In addition, changes in the input / output impedance of the filter before and after reconfiguration will lead to changes in the matching state with the preceding and following stages, and the delay difference of signal carriers in different frequency bands will also change, thus affecting key performance indicators such as the gain, VSWR, and error vector amplitude of the RF link.

[0004] Existing control methods mainly fall into two categories: First, "immediate response upon receiving control parameters." Due to the large number of communication nodes and significant bus transmission delay, RF link reconfiguration must wait for control parameter configuration to complete each time, which consumes a significant amount of normal operating time during rapid multi-band switching. Second, "timed configuration with pre-transmitted parameters." Because each device's clock is independent and contains errors, relative clock discrepancies develop after prolonged operation, leading to asynchronous mode switching and affecting the normal operation of the RF channel. Therefore, a novel reconfiguration control method for the RF front-end network is urgently needed to achieve rapid reconfiguration of the operating state without affecting system performance indicators. Summary of the Invention

[0005] To address the urgent need for multi-band coverage and flexible expansion of operating modes in current RF front-end networks, this application provides an FPGA-based reconfigurable control method and system for RF front-end networks. This method can maintain synchronization with the system's operating cycle, enabling rapid reconfiguration of the RF front-end network. Furthermore, it can configure channel compensation parameters based on the characteristics of different carrier signals in different frequency bands, implement adaptive gain control for the RF receiving channel, optimize RF link performance indicators, improve the dynamic range of the RF link in the RF front-end network, and optimize and upgrade the control strategy of the FPGA software according to different operating environments. This effectively solves the problems of high cost, large size, long reconfiguration time, and performance degradation after reconfiguration associated with traditional methods, thereby improving system efficiency and RF link performance.

[0006] This application discloses a reconfigurable control method for an FPGA-based radio frequency front-end network, which includes: Step 1: During the current working period T, the system control unit sends the working parameters for the T+1 period to the reconfigurable phased array, the reconfigurable RF front-end network, and the digital transceiver processor, and outputs the synchronization pulse for the current working period T. Step 2: When the falling edge of the synchronization pulse arrives, the reconfigurable phased array completes array reconfiguration, outputs RF receive signal to the reconfigurable RF front-end network, and transmits RF transmit signal output by the reconfigurable RF front-end network; in calibration mode, the reference calibration source outputs reference signal and calibration signal to the reconfigurable RF front-end network according to the calibration configuration parameters, and synchronously outputs clock signal to digital transceiver processor. Step 3: The reconfigurable RF front-end network receives RF received signals, reference signals, correction signals, and baseband transmit signals, and outputs baseband received signals to the digital transceiver processor and RF transmit signals to the reconfigurable phased array; the reconfigurable FPGA control unit of the reconfigurable RF front-end network parses the operating parameters according to the communication protocol, extracts the control parameters, and maps the control parameters to the reconfigurable receive channel and reconfigurable transmit channel of the reconfigurable RF front-end network; after detecting the falling edge of the synchronization pulse, it first completes the local oscillator frequency comparison and control output, and after the local oscillator state stabilizes, it sequentially completes the working state configuration of the reconfigurable receive channel, reconfigurable transmit channel, and RF channel switch network of the reconfigurable RF front-end network; Step 4: The digital transceiver processor acquires the baseband received signal, calculates the link performance indicators of the reconfigurable receive channel and the reconfigurable transmit channel respectively, and reports them to the system control unit; the system control unit updates the receive RF link compensation parameters based on the link performance indicators of the reconfigurable receive channel, and updates the transmit RF link compensation parameters based on the link performance indicators of the reconfigurable transmit channel; the digital transceiver processor simultaneously generates a baseband transmit signal and outputs it to the reconfigurable RF front-end network.

[0007] Further, step 1 includes: In normal operating mode, the system control unit does not send operating parameters to the reference calibration source; in calibration mode, the system control unit sends calibration configuration parameters to the reference calibration source and stops sending operating parameters to the reconfigurable phased array. The operating parameters include operating bandwidth, operating frequency band, channel gain, receive RF link compensation parameters, transmit RF link compensation parameters, gain control threshold, attenuation configuration value, and correction configuration parameters; the gain control threshold includes activation threshold and recovery threshold. The system control unit receives the RF link performance indicators reported by the digital transceiver processor, converts them to obtain updated receive RF link compensation parameters and transmit RF link compensation parameters, and adds them to the subsequently issued working parameters. The RF link performance indicators include the link performance indicators of the reconfigurable receive channel and the link performance indicators of the reconfigurable transmit channel.

[0008] Further, step 3 includes: The operating frequency point is generated based on the operating frequency band in the control parameters, and then the operating frequency point is converted into the local oscillator frequency point; the control parameters include operating bandwidth, operating frequency band, channel gain, receiving RF link compensation parameters, and transmitting RF link compensation parameters; the receiving RF link compensation parameters are used to configure the reconfigurable receiving channel, and the transmitting RF link compensation parameters are used to configure the reconfigurable transmitting channel; The reconfigurable FPGA control unit receives operating parameters and synchronization pulses from the system control unit via the control bus, parses the operating parameters, and generates path switch control signals and channel control signals. The reconfigurable FPGA control unit outputs path switch control signals to the RF channel switch network to control the RF channel switch network to select RF signal paths, thereby realizing path switching between the reconfigurable receiving channel and the reconfigurable transmitting channel. The reconfigurable FPGA control unit also independently sends channel control signals to the reconfigurable receiving channel and the reconfigurable transmitting channel, respectively. The channel control signals include receiving RF link compensation parameters and transmitting RF link compensation parameters, which are used to configure the gain and attenuation parameters of the reconfigurable receiving channel and the reconfigurable transmitting channel to complete the channel RF characteristic configuration.

[0009] Furthermore, upon detecting the falling edge of the synchronization pulse, the reconfigurable FPGA control unit compares the calculated local oscillator frequency with the current operating frequency of the local oscillator signal generation unit. Only when the two are inconsistent is the target frequency of the local oscillator signal generation unit reconfigured. After the local oscillator frequency stabilizes, the local oscillator output switch is turned on. After the local oscillator frequency stabilizes, the working status configuration of the reconfigurable receiving channel, reconfigurable transmitting channel, and RF channel switch network is completed sequentially. The system control unit issues the working parameters for the T+2 period in the T+1 period. If the local oscillator frequency calculated from the working parameters is consistent with the current operating frequency of the local oscillator signal generation unit, there is no need to execute the local oscillator signal generation unit frequency reconfiguration process, and the working status configuration of the reconfigurable receiving channel and reconfigurable transmitting channel is completed directly.

[0010] Furthermore, the configuration operations of the working parameters of the reconfigurable phased array, digital transceiver processor, and reconfigurable RF front-end network are all executed synchronously under the unified timing of the synchronization pulse.

[0011] Furthermore, it also includes the gain control process: The reconfigurable receiving channel acquires the radio frequency received signal and performs detection processing on it, outputting a detection voltage. The detection voltage is used as a detection signal input to the analog-to-digital converter of the reconfigurable FPGA control unit. The detection voltage represents the amplitude of the radio frequency received signal. The reconfigurable FPGA control unit acquires the detection voltage through the analog-to-digital converter and converts it to obtain a detection voltage value representing the amplitude of the detection voltage. In automatic gain control mode, the reconfigurable FPGA control unit filters the detected voltage value and compares it with the start-up threshold and recovery threshold values ​​issued by the system control unit. When the filtered detected voltage value is greater than the start-up threshold value, the reconfigurable FPGA control unit performs adaptive gain control on the reconfigurable receiving channel according to the attenuation configuration value. When the filtered detected voltage value is less than the recovery threshold value, the reconfigurable FPGA control unit turns off the attenuation control output of the reconfigurable receiving channel. In manual control mode, the reconfigurable FPGA control unit directly controls the reconfigurable receiving channel based on the fixed attenuation configuration value issued by the system. The system control unit adjusts the start-up threshold, recovery threshold, or sets multiple thresholds according to different operating modes, and adopts different amplitude gain control for different detection voltage ranges to improve the dynamic range of the RF front-end RF path.

[0012] Furthermore, it also includes performing a time-segmented iterative correction process: After detecting the falling edge of the synchronization pulse at time T and determining that the calibration mode has been entered, the reconfigurable FPGA control unit completes the configuration of the local oscillator frequency, local oscillator switch, reconfigurable receiving channel, reconfigurable transmitting channel, and RF channel switch network. The reference calibration source outputs the calibration signal according to the calibration configuration parameters. The digital transceiver processor collects the baseband received signal, calculates the link performance index of the reconfigurable receiving channel, and reports it to the system control unit through the control bus. The reported data serves as the basis for calculating the receiving RF link compensation parameters. During the T+1 time period, the system control unit superimposes the received RF link compensation parameters obtained in this conversion onto the working parameters for the T+2 time period and distributes them uniformly. Subsequently, the RF channel switching network is configured to loop back the RF transmission signal output from the reconfigurable transmit channel into the reconfigurable receive channel. The digital transceiver processor repeatedly collects the baseband received signal and calculates the link performance indicators of the reconfigurable transmit channel, iteratively obtaining the transmit RF link compensation parameters. The system traverses all frequency bands and all carriers to complete the correction and stores the optimal receive RF link compensation parameters and the optimal transmit RF link compensation parameters, thereby optimizing the RF phase delay, link gain, VSWR, and error vector amplitude of the reconfigurable receive channel and reconfigurable transmit channel under each frequency band and carrier.

[0013] Furthermore, it also includes the FPGA on-orbit reconfiguration and refresh step: The system control unit sends upgrade commands and FPGA configuration files to the reconfigurable FPGA control unit; the loading and refreshing FPGA inside the reconfigurable FPGA control unit receives the FPGA configuration file and stores it in memory; the loading and refreshing FPGA reads the FPGA configuration file in memory, performs configuration loading on the functional control FPGA, and completes the on-orbit reconfiguration; after the reconfiguration is completed, the loading and refreshing FPGA outputs a feedback signal to the system control unit to inform it of the reconfiguration result, and automatically starts timed refresh, so that the control logic can be updated without powering down and restarting the entire machine.

[0014] This application also discloses an FPGA-based reconfigurable control system for a radio frequency front-end network, which implements the aforementioned FPGA-based reconfigurable control method for a radio frequency front-end network. The system includes a system control unit, a reconfigurable phased array, a reference calibration source, a reconfigurable radio frequency front-end network, and a digital transceiver processor. The system control unit is connected to the system control unit, the reconfigurable phased array, the reference calibration source, the reconfigurable radio frequency front-end network, and the digital transceiver processor. The reference calibration source is connected to both the reconfigurable radio frequency front-end network and the digital transceiver processor. The reconfigurable phased array is connected to the reconfigurable radio frequency front-end network.

[0015] Furthermore, the reconfigurable RF front-end network includes a reconfigurable FPGA control unit, an RF channel switch network, at least one set of reconfigurable receiving channels, and at least one set of reconfigurable transmitting channels; each of the reconfigurable receiving channels and reconfigurable transmitting channels is equipped with a local oscillator signal generation unit; the reconfigurable FPGA control unit is connected to the RF channel switch network, each reconfigurable receiving channel, and each reconfigurable transmitting channel respectively.

[0016] Furthermore, the reconfigurable receiving channel includes a reconfigurable filter, an adjustable attenuator, a reconfigurable amplifier, and a controllable phase shifter connected in series. The reconfigurable transmit channel includes a controllable phase shifter, a reconfigurable filter, a reconfigurable amplifier, a mixer, and an adjustable attenuator connected in series.

[0017] Furthermore, the reconfigurable FPGA control unit includes a loading and refreshing FPGA, a function control FPGA, a memory, an analog-to-digital converter, an external interface driver module, and an internal interface driver module; the loading and refreshing FPGA is connected to the function control FPGA, the memory, and the external interface driver module respectively, and the function control FPGA is connected to the analog-to-digital converter and the internal interface driver module.

[0018] By adopting the above technical solution, this application has the following advantages: it can achieve rapid reconfiguration of the operating state of the radio frequency front-end network. This method needs to have the following characteristics: 1) It can receive the working parameter configuration issued by the system control unit, and after detecting the synchronization pulse, it can control the reconfigurable devices such as reconfigurable filters and reconfigurable amplifiers in the RF front-end network link, keep in sync with the system control cycle, and not occupy the normal working time of the system, so as to realize the rapid reconfiguration of the RF link working parameters; 2) It can perform channel correction based on the characteristics of different carrier signals in different frequency bands, store the compensation configuration parameters of each device in the RF link, and achieve RF link performance optimization; 3) It can quickly reconfigure the FPGA software for functional control and optimize and upgrade the control strategy of the FPGA software according to different working environments; 4) It can achieve adaptive gain control of RF signals, thereby improving the dynamic range of RF links in RF front-end networks. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments recorded in the embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings.

[0020] Figure 1This is a block diagram of a FPGA-based reconfigurable radio frequency front-end network control system according to an embodiment of this application. Figure 2 This is a block diagram of the reconfigurable radio frequency front-end network according to an embodiment of this application; Figure 3 This is a schematic diagram of a reconfigurable receiving channel according to an embodiment of this application; Figure 4 This is a schematic diagram of a reconfigurable transmission channel according to an embodiment of this application; Figure 5 This is a schematic diagram of the working timing of the reconfigurable radio frequency front-end network according to an embodiment of this application; Figure 6 This is a schematic diagram illustrating the rapid reconfiguration workflow of the reconfigurable RF front-end network according to an embodiment of this application. Figure 7 This is a schematic diagram of the timing of radio frequency parameter correction for a reconfigurable radio frequency front-end network according to an embodiment of this application. Figure 8 This is a schematic diagram of a reconfigurable receiving channel correction method according to an embodiment of this application; Figure 9 This is a schematic diagram of a reconfigurable transmission channel correction method according to an embodiment of this application; Figure 10 This is a schematic diagram illustrating the workflow of the reconfigurable RF front-end network acquiring RF link compensation parameters according to an embodiment of this application. Figure 11 This is a block diagram of the reconfigurable FPGA control unit according to an embodiment of this application; Figure 12 This is a schematic diagram illustrating the adaptive gain control workflow of the reconfigurable RF front-end network according to an embodiment of this application. Detailed Implementation

[0021] The present application will be further described in conjunction with the accompanying drawings and embodiments. The described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments obtained by those skilled in the art should fall within the protection scope of the embodiments of the present application.

[0022] This invention, based on FPGA control and a combination of synchronization pulses, realizes a rapid reconfiguration control function for reconfigurable RF front-end networks, which can effectively improve the efficiency of RF channel correction and the timeliness of operation.

[0023] See Figure 1 This application provides an embodiment of a FPGA-based reconfigurable control method for radio frequency front-end networks, comprising: Step 1: During the current working period T, the system control unit sends the working parameters for the T+1 period to the reconfigurable phased array, the reconfigurable RF front-end network, and the digital transceiver processor, and outputs the synchronization pulse for the current working period T. Step 2: When the falling edge of the synchronization pulse arrives, the reconfigurable phased array completes array reconfiguration, outputs RF receive signal to the reconfigurable RF front-end network, and transmits RF transmit signal output by the reconfigurable RF front-end network; in calibration mode, the reference calibration source outputs reference signal and calibration signal to the reconfigurable RF front-end network according to the calibration configuration parameters, and synchronously outputs clock signal to digital transceiver processor. Step 3: The reconfigurable RF front-end network receives RF received signals, reference signals, correction signals, and baseband transmit signals, and outputs baseband received signals to the digital transceiver processor and RF transmit signals to the reconfigurable phased array; the reconfigurable FPGA control unit of the reconfigurable RF front-end network parses the operating parameters according to the communication protocol, extracts the control parameters, and maps the control parameters to the reconfigurable receive channel and reconfigurable transmit channel of the reconfigurable RF front-end network; after detecting the falling edge of the synchronization pulse, it first completes the local oscillator frequency comparison and control output, and after the local oscillator state stabilizes, it sequentially completes the working state configuration of the reconfigurable receive channel, reconfigurable transmit channel, and RF channel switch network of the reconfigurable RF front-end network; Step 4: The digital transceiver processor acquires the baseband received signal, calculates the link performance indicators of the reconfigurable receive channel and the reconfigurable transmit channel respectively, and reports them to the system control unit; the system control unit updates the receive RF link compensation parameters based on the link performance indicators of the reconfigurable receive channel, and updates the transmit RF link compensation parameters based on the link performance indicators of the reconfigurable transmit channel; the digital transceiver processor simultaneously generates a baseband transmit signal and outputs it to the reconfigurable RF front-end network.

[0024] Optionally, step 1 includes: In normal operating mode, the system control unit does not send operating parameters to the reference calibration source; in calibration mode, the system control unit sends calibration configuration parameters to the reference calibration source and stops sending operating parameters to the reconfigurable phased array. The operating parameters include operating bandwidth, operating frequency band, channel gain, receive RF link compensation parameters, transmit RF link compensation parameters, gain control threshold, attenuation configuration value, and correction configuration parameters; the gain control threshold includes activation threshold and recovery threshold. The system control unit receives the RF link performance indicators reported by the digital transceiver processor, converts them to obtain updated receive RF link compensation parameters and transmit RF link compensation parameters, and adds them to the subsequently issued working parameters. The RF link performance indicators include the link performance indicators of the reconfigurable receive channel and the link performance indicators of the reconfigurable transmit channel.

[0025] Optionally, step 3 includes: The operating frequency point is generated based on the operating frequency band in the control parameters, and then the operating frequency point is converted into the local oscillator frequency point; the control parameters include operating bandwidth, operating frequency band, channel gain, receiving RF link compensation parameters, and transmitting RF link compensation parameters; the receiving RF link compensation parameters are used to configure the reconfigurable receiving channel, and the transmitting RF link compensation parameters are used to configure the reconfigurable transmitting channel; The reconfigurable FPGA control unit receives operating parameters and synchronization pulses from the system control unit via the control bus, parses the operating parameters, and generates path switch control signals and channel control signals. The reconfigurable FPGA control unit outputs path switch control signals to the RF channel switch network to control the RF channel switch network to select RF signal paths, thereby realizing path switching between the reconfigurable receiving channel and the reconfigurable transmitting channel. The reconfigurable FPGA control unit also independently sends channel control signals to the reconfigurable receiving channel and the reconfigurable transmitting channel, respectively. The channel control signals include receiving RF link compensation parameters and transmitting RF link compensation parameters, which are used to configure the gain and attenuation parameters of the reconfigurable receiving channel and the reconfigurable transmitting channel to complete the channel RF characteristic configuration.

[0026] Optionally, upon detecting the falling edge of the synchronization pulse, the reconfigurable FPGA control unit compares the calculated local oscillator frequency with the current operating frequency of the local oscillator signal generation unit. Only when the two are inconsistent, the target frequency of the local oscillator signal generation unit is reconfigured, and the local oscillator output switch is turned on after the local oscillator frequency stabilizes. After the local oscillator frequency stabilizes, the working status configuration of the reconfigurable receiving channel, reconfigurable transmitting channel, and RF channel switch network is completed in sequence. The system control unit issues the working parameters for the T+2 period in the T+1 period. If the local oscillator frequency calculated from the working parameters is consistent with the current operating frequency of the local oscillator signal generation unit, there is no need to execute the local oscillator signal generation unit frequency reconfiguration process, and the working status configuration of the reconfigurable receiving channel and reconfigurable transmitting channel is completed directly.

[0027] Optionally, the configuration operations of the operating parameters of the reconfigurable phased array, digital transceiver processor, and reconfigurable RF front-end network are all executed synchronously under the unified timing of the synchronization pulse.

[0028] Optionally, a gain control procedure is also included: The reconfigurable receiving channel acquires the radio frequency received signal and performs detection processing on it, outputting a detection voltage. The detection voltage is used as a detection signal input to the analog-to-digital converter of the reconfigurable FPGA control unit. The detection voltage represents the amplitude of the radio frequency received signal. The reconfigurable FPGA control unit acquires the detection voltage through the analog-to-digital converter and converts it to obtain a detection voltage value representing the amplitude of the detection voltage. In automatic gain control mode, the reconfigurable FPGA control unit filters the detected voltage value and compares it with the start-up threshold and recovery threshold values ​​issued by the system control unit. When the filtered detected voltage value is greater than the start-up threshold value, the reconfigurable FPGA control unit performs adaptive gain control on the reconfigurable receiving channel according to the attenuation configuration value. When the filtered detected voltage value is less than the recovery threshold value, the reconfigurable FPGA control unit turns off the attenuation control output of the reconfigurable receiving channel. In manual control mode, the reconfigurable FPGA control unit directly controls the reconfigurable receiving channel based on the fixed attenuation configuration value issued by the system. The system control unit adjusts the start-up threshold, recovery threshold, or sets multiple thresholds according to different operating modes, and adopts different amplitude gain control for different detection voltage ranges to improve the dynamic range of the RF front-end RF path.

[0029] Optionally, it also includes performing a time-segmented iterative correction process: After detecting the falling edge of the synchronization pulse at time T and determining that the calibration mode has been entered, the reconfigurable FPGA control unit completes the configuration of the local oscillator frequency, local oscillator switch, reconfigurable receiving channel, reconfigurable transmitting channel, and RF channel switch network. The reference calibration source outputs the calibration signal according to the calibration configuration parameters. The digital transceiver processor collects the baseband received signal, calculates the link performance index of the reconfigurable receiving channel, and reports it to the system control unit through the control bus. The reported data serves as the basis for calculating the receiving RF link compensation parameters. During the T+1 time period, the system control unit superimposes the received RF link compensation parameters obtained in this conversion onto the working parameters for the T+2 time period and distributes them uniformly. Subsequently, the RF channel switching network is configured to loop back the RF transmission signal output from the reconfigurable transmit channel into the reconfigurable receive channel. The digital transceiver processor repeatedly collects the baseband received signal and calculates the link performance indicators of the reconfigurable transmit channel, iteratively obtaining the transmit RF link compensation parameters. The system traverses all frequency bands and all carriers to complete the correction and stores the optimal receive RF link compensation parameters and the optimal transmit RF link compensation parameters, thereby optimizing the RF phase delay, link gain, VSWR, and error vector amplitude of the reconfigurable receive channel and reconfigurable transmit channel under each frequency band and carrier.

[0030] Optionally, it also includes an on-orbit reconfiguration and refresh step for the FPGA: The system control unit sends upgrade commands and FPGA configuration files to the reconfigurable FPGA control unit; the loading and refreshing FPGA inside the reconfigurable FPGA control unit receives the FPGA configuration file and stores it in memory; the loading and refreshing FPGA reads the FPGA configuration file in memory, performs configuration loading on the functional control FPGA, and completes the on-orbit reconfiguration; after the reconfiguration is completed, the loading and refreshing FPGA outputs a feedback signal to the system control unit to inform it of the reconfiguration result, and automatically starts timed refresh, so that the control logic can be updated without powering down and restarting the entire machine.

[0031] This application also provides an embodiment of an FPGA-based reconfigurable control system for a radio frequency front-end network, implementing the FPGA-based reconfigurable control method for a radio frequency front-end network described in the above embodiment. The system includes a system control unit, a reconfigurable phased array, a reference calibration source, a reconfigurable radio frequency front-end network, and a digital transceiver processor. The system control unit is connected to the system control unit, the reconfigurable phased array, the reference calibration source, the reconfigurable radio frequency front-end network, and the digital transceiver processor. The reference calibration source is connected to both the reconfigurable radio frequency front-end network and the digital transceiver processor. The reconfigurable phased array is connected to the reconfigurable radio frequency front-end network.

[0032] Optionally, the reconfigurable RF front-end network includes a reconfigurable FPGA control unit, an RF channel switching network, at least one set of reconfigurable receiving channels, and at least one set of reconfigurable transmitting channels; each reconfigurable receiving channel and each reconfigurable transmitting channel is equipped with a local oscillator signal generation unit; the reconfigurable FPGA control unit is connected to the RF channel switching network, each reconfigurable receiving channel, and each reconfigurable transmitting channel, respectively, as shown below. Figure 2 As shown.

[0033] Optionally, the reconfigurable receiving channel includes a reconfigurable filter, an adjustable attenuator, a reconfigurable amplifier, and a controllable phase shifter connected in series, such as... Figure 3 As shown; Figure 3 In the process, the local oscillator signal generation unit receives the reference signal from the reference correction source and generates the local oscillator signal; the frequency of the local oscillator signal output by the local oscillator signal generation unit is the current operating frequency of the local oscillator signal generation unit.

[0034] The reconfigurable transmit channel comprises, in series, a controllable phase shifter, a reconfigurable filter, a reconfigurable amplifier, a mixer, and an adjustable attenuator, such as... Figure 4 As shown.

[0035] Optionally, the reconfigurable FPGA control unit includes a loading and refreshing FPGA, a function control FPGA, a memory, an analog-to-digital converter, an external interface driver module, and an internal interface driver module; the loading and refreshing FPGA is connected to the function control FPGA, the memory, and the external interface driver module respectively, and the function control FPGA is connected to the analog-to-digital converter and the internal interface driver module.

[0036] Specifically, in combination Figure 11 As shown, the reconfigurable FPGA control unit includes a loading and refreshing FPGA, a function control FPGA, a memory, an analog-to-digital converter, and an external interface driver module.

[0037] The loading and refreshing FPGA is electrically connected to the function control FPGA, the memory, and the external interface driver module. The external interface driver module is connected to the system control unit. The loading and refreshing FPGA receives operating parameters, synchronization pulses, and reconfiguration parameters from the system control unit via the control bus through the external interface driver module. The reconfiguration parameters include FPGA configuration file read / write instructions and version switching instructions, used for on-orbit reconfiguration scenarios. The loading and refreshing FPGA parses the control parameters from the operating parameters and transmits them to the function control FPGA along with the synchronization pulses. When the loading and refreshing FPGA receives the reconfiguration parameters, it writes the FPGA configuration file corresponding to the FPGA configuration file read / write instructions into the memory. The memory stores program configuration data and RF link configuration parameters. The program configuration data includes the power-on initial configuration file and on-orbit reconfiguration data, whereby the on-orbit reconfiguration data is the FPGA configuration file used to update the function control FPGA logic. The loading and refreshing FPGA can read the data stored in the memory, use the power-on initial configuration file to complete the power-on initialization loading of the function control FPGA, or use the on-orbit reconfiguration data to read the configuration file data from the memory and write it into the function control FPGA upon the next power-on or upon receiving a version switching instruction, thus completing the on-orbit online refresh of the function control FPGA. The functional control FPGA is electrically connected to the analog-to-digital converter (ADC). Based on the received control parameters and synchronization pulses, the functional control FPGA generates path switch control signals and channel control signals, and directly outputs them to the RF channel switch network, the reconfigurable receiving channel, and the reconfigurable transmitting channel. The detector voltage output from the reconfigurable receiving channel is directly connected to the ADC. The ADC converts the analog detector voltage into a digital detector voltage value and transmits the value to the functional control FPGA.

[0038] For ease of understanding, this application provides a more specific embodiment: This invention, based on FPGA control and a combination of synchronization pulses, achieves rapid reconfiguration control of a reconfigurable RF front-end network, effectively improving RF channel calibration efficiency and operational timeliness. The overall solution block diagram is shown below. Figure 1 As shown.

[0039] The specific implementation steps of this invention are as follows: 1) Rapid reconfiguration of RF links The system control unit pre-sends operating parameters to the reconfigurable phased array, reconfigurable RF front-end network, and digital transceiver processor via a bus interface. The reconfigurable FPGA control unit in the reconfigurable RF front-end network parses control parameters such as operating bandwidth, operating frequency band, and channel gain according to communication protocol requirements, and maps them to the control pins of reconfigurable filters, reconfigurable amplifiers, adjustable attenuators, and controllable phase shifters in the RF receive and transmit channels, converting the operating frequency to the local oscillator frequency. Upon detecting the falling edge of the synchronization pulse sent by the system control unit, to reduce the impact of spurious signals generated during local oscillator locking on the RF link, the reconfigurable FPGA control unit first completes the local oscillator frequency control output for the local oscillator signal generation units in the reconfigurable receive and transmit channels, and then completes the configuration of the operating status of the reconfigurable receive channel, reconfigurable transmit channel, and RF channel switching network.

[0040] Reconfigurable RF front-end network operating timing, such as Figure 5 As shown. Wherein: Indicates the local oscillator frequency configuration time; This indicates the time required to wait for the local oscillator frequency output to stabilize and lock in place. Indicates the configuration time for the switching network, reconfigurable receive channel, and reconfigurable transmit channel; This indicates the normal operating time of the radio frequency link.

[0041] The system control unit sends configuration parameters for the reconfigurable phased array, reconfigurable RF front-end network, and digital transceiver processor for time period T+1 during time period T. Upon detecting the falling edge of the synchronization pulse at time T, the reconfigurable FPGA control unit first compares the sent local oscillator frequency with the current local oscillator operating frequency. Only if the sent local oscillator frequency is inconsistent with the current operating frequency will the operating frequency of the local oscillator signal generation unit be reconfigured. The configuration time is [time missing]. Furthermore, the local oscillator output switch will only be turned on after the local oscillator frequency has stabilized. The local oscillator frequency stabilization waiting time is [time missing]. After the local oscillator frequency stabilizes, the configuration output for the reconfigurable receive channel, reconfigurable transmit channel, and RF channel switching network is completed. The configuration time is [time missing]. The total configuration time is .

[0042] The system control unit sends out the operating parameters for time period T+2 during time period T+1. Since the local oscillator frequency sent this time matches the current operating frequency, there is no need to configure the local oscillator signal generation unit. Therefore, the total configuration time is... .

[0043] Rapid reconfiguration workflow for reconfigurable RF front-end networks, such as Figure 6 As shown.

[0044] The configuration of operating parameters for the reconfigurable phased array and digital transceiver processor, as well as the reconfigurable RF front-end network, are all performed under synchronization pulses. The system operates normally during the reconfiguration process, effectively avoiding the problem of sudden drop or overshoot in the RF link signal amplitude caused by reconfigurable devices during the reconfiguration process. The configuration of operating parameters does not affect the current operating mode, and rapid reconfiguration can be achieved.

[0045] 2) RF link performance optimization To address the degradation of key performance indicators in the RF link, such as phase delay, RF link gain, VSWR, and error vector amplitude, caused by changes in the operating state of reconfigurable devices, the system control unit performs channel calibration on the reconfigurable RF front-end network before testing or normal operation, taking into account the characteristics of different carrier signals in different frequency bands. Based on various performance indicators collected by the digital transceiver, RF link compensation parameters are calculated. After multiple calibrations, optimal parameters are obtained and stored in the system control unit. During normal operation, the system control unit sends the compensation configuration parameters of each device in the RF link to the reconfigurable RF front-end network via the control bus, thereby optimizing the performance indicators of the RF link.

[0046] The timing sequence for reconfigurable RF front-end network RF parameter correction is as follows: Figure 7 As shown. Among them, This indicates the time it takes for the digital transceiver to acquire and correct the signal.

[0047] The system control unit sends configuration parameters for the reference calibration source, reconfigurable RF front-end network, and digital transceiver for time period T+1 during time period T. Upon detecting the falling edge of the synchronization pulse at time T, the reconfigurable FPGA control unit determines that the system is in calibration mode and then... Within a given timeframe, the configuration and output of the local oscillator frequency, local oscillator switch, and the switching networks of the reconfigurable receive channel, reconfigurable transmit channel, and RF channel for the local oscillator signal generation unit in the reconfigurable receive channel and reconfigurable transmit channel are completed; the reference calibration source is configured according to the parameters in... After completing the calibration signal output, the digital transceiver processor... The system continuously acquires and processes signals from the receiving radio frequency link, obtains various performance parameters of the current signal, and reports them to the system control unit via the control bus as radio frequency link compensation parameters.

[0048] The system control unit adds the compensation parameters to the operating parameters and sends them out together during the T+1 period, and performs channel correction again. The digital transceiver processor performs the same process during the T+2 period. The receiving RF link is repeatedly sampled and processed to obtain new RF link performance parameters, which are then reported to the system control unit via the control bus. After multiple calibrations, the system control unit can obtain the optimal receiving RF link compensation parameters for a reconfigurable transmit channel with a specific carrier signal in a certain frequency band. Subsequently, the RF channel switching network can be configured to input the signal output from the reconfigurable transmit channel back into the reconfigurable receive channel after passing through the switching network. The signal is then sampled and processed again by the digital transceiver, and after multiple adjustments, the optimal transmit RF link compensation parameters for the reconfigurable transmit channel are obtained. By sequentially calibrating different carrier signals on different channels, the optimal RF link compensation parameters for different carrier signals in different frequency bands can be obtained, achieving optimal configuration of RF link performance indicators.

[0049] Reconfigurable receiver channel correction method such as Figure 8 As shown. The reconfigurable transmit channel correction method is as follows. Figure 9 As shown. The workflow for obtaining RF link compensation parameters in a reconfigurable RF front-end network is as follows: Figure 10 As shown.

[0050] 3) Rapid reconfiguration of FPGA software The reconfigurable FPGA control unit consists of a loading and refreshing FPGA, a function control FPGA, FLASH memory, and interface drivers. Its main functions are to implement external interface communication and internal control signal output and detection. It features on-orbit reconfiguration capabilities and can optimize and upgrade the FPGA software control strategy according to different operating environments. The function control FPGA software runs within the FPGA and its main functions include bus interface communication, synchronization pulse detection, local oscillator frequency control, local oscillator frequency switching, RF channel switch network control, reconfigurable receive channel control, and reconfigurable transmit channel control. Since it does not involve complex algorithm calculations, small-scale programmable logic devices (SLPs) are used in combination with interface drivers to expand control I / O, significantly reducing hardware costs. Furthermore, SLPs require smaller loading configuration files, resulting in shorter reconfiguration times during on-orbit reconfiguration and enabling rapid reconfiguration based on functional requirements.

[0051] The block diagram of the reconfigurable FPGA control unit is as follows: Figure 11 As shown.

[0052] 4) Adaptive gain control of RF received signal The detection voltage of the reconfigurable receiving channel is input as a detection signal to the analog-to-digital converter (ADC) detection port of the reconfigurable FPGA control unit. The functional control FPGA software detects the current channel signal amplitude in real time through the ADC chip and converts it into a detection voltage value. In automatic gain control mode, the functional control FPGA software filters the detection voltage value and then compares it with the entry and exit threshold values ​​issued by the system control unit. When the filtered detection voltage value is greater than the entry threshold, the functional control FPGA software implements adaptive gain control of the receiving channel according to the attenuation configuration value issued by the system control unit. When the filtered detection voltage value is less than the exit threshold, the functional control FPGA software shuts down the attenuation control output of the receiving channel. The system control unit can change the voltage threshold value or set multiple thresholds according to different operating modes to achieve different amplitude gain control for different detection voltage ranges, thereby improving the dynamic range of the RF front-end network RF link.

[0053] The workflow of adaptive gain control for reconfigurable RF front-end networks is as follows: Figure 12 As shown.

[0054] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application and not to limit them. Although this application has been described in detail with reference to the above embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the specific implementation of this application. Any modifications or equivalent substitutions that do not depart from the spirit and scope of this application should be covered within the protection scope of the claims of this application.

Claims

1. A reconfigurable control method for an FPGA-based radio frequency front-end network, characterized in that, include: Step 1: During the current working period T, the system control unit sends the working parameters for the T+1 period to the reconfigurable phased array, the reconfigurable RF front-end network, and the digital transceiver processor, and outputs the synchronization pulse for the current working period T. Step 2: When the falling edge of the synchronization pulse arrives, the reconfigurable phased array completes array reconfiguration, outputs RF receive signal to the reconfigurable RF front-end network, and transmits RF transmit signal output by the reconfigurable RF front-end network; in calibration mode, the reference calibration source outputs reference signal and calibration signal to the reconfigurable RF front-end network according to the calibration configuration parameters, and synchronously outputs clock signal to digital transceiver processor. Step 3: The reconfigurable RF front-end network receives RF received signals, reference signals, correction signals, and baseband transmitted signals, and outputs baseband received signals to the digital transceiver processor and RF transmitted signals to the reconfigurable phased array; the reconfigurable FPGA control unit of the reconfigurable RF front-end network parses the operating parameters according to the communication protocol, extracts the control parameters, and maps the control parameters to the reconfigurable receive channel and reconfigurable transmit channel of the reconfigurable RF front-end network. After detecting the falling edge of the synchronization pulse, the local oscillator frequency comparison and control output are completed first. After the local oscillator state stabilizes, the working status configuration of the reconfigurable receiver channel, reconfigurable transmitter channel, and RF channel switch network of the reconfigurable RF front-end network is completed in sequence. Step 4: The digital transceiver processor acquires the baseband received signal, calculates the link performance indicators of the reconfigurable receive channel and the reconfigurable transmit channel respectively, and reports them to the system control unit. The system control unit updates the receive RF link compensation parameters based on the link performance indicators of the reconfigurable receive channel, and updates the transmit RF link compensation parameters based on the link performance indicators of the reconfigurable transmit channel; the digital transceiver processor simultaneously generates a baseband transmit signal and outputs it to the reconfigurable RF front-end network.

2. The FPGA-based reconfigurable control method for radio frequency front-end networks according to claim 1, characterized in that, Step 1 includes: In normal operating mode, the system control unit does not send operating parameters to the reference calibration source; in calibration mode, the system control unit sends calibration configuration parameters to the reference calibration source and stops sending operating parameters to the reconfigurable phased array. The operating parameters include operating bandwidth, operating frequency band, channel gain, receive RF link compensation parameters, transmit RF link compensation parameters, gain control threshold, attenuation configuration value, and correction configuration parameters; the gain control threshold includes activation threshold and recovery threshold. The system control unit receives the RF link performance indicators reported by the digital transceiver processor, converts them to obtain updated receive RF link compensation parameters and transmit RF link compensation parameters, and adds them to the subsequently issued working parameters. The RF link performance indicators include the link performance indicators of the reconfigurable receive channel and the link performance indicators of the reconfigurable transmit channel.

3. The FPGA-based reconfigurable control method for radio frequency front-end networks according to claim 1, characterized in that, Step 3 includes: The operating frequency point is generated based on the operating frequency band in the control parameters, and then the operating frequency point is converted into the local oscillator frequency point; the control parameters include operating bandwidth, operating frequency band, channel gain, receiving RF link compensation parameters, and transmitting RF link compensation parameters; the receiving RF link compensation parameters are used to configure the reconfigurable receiving channel, and the transmitting RF link compensation parameters are used to configure the reconfigurable transmitting channel; The reconfigurable FPGA control unit receives operating parameters and synchronization pulses from the system control unit via the control bus, parses the operating parameters, and generates path switch control signals and channel control signals. The reconfigurable FPGA control unit outputs path switch control signals to the RF channel switch network to control the RF channel switch network to select RF signal paths, thereby realizing path switching between the reconfigurable receiving channel and the reconfigurable transmitting channel. The reconfigurable FPGA control unit also independently sends channel control signals to the reconfigurable receiving channel and the reconfigurable transmitting channel, respectively. The channel control signals include receiving RF link compensation parameters and transmitting RF link compensation parameters, which are used to configure the gain and attenuation parameters of the reconfigurable receiving channel and the reconfigurable transmitting channel to complete the channel RF characteristic configuration.

4. The FPGA-based reconfigurable control method for radio frequency front-end networks according to claim 1 or 3, characterized in that, When the falling edge of the synchronization pulse is detected, the reconfigurable FPGA control unit compares the calculated local oscillator frequency with the current operating frequency of the local oscillator signal generation unit; only when the two are inconsistent, the target frequency of the local oscillator signal generation unit is reconfigured, and the local oscillator output switch is turned on after the local oscillator frequency stabilizes. After the local oscillator frequency is stabilized, the working status configuration of the reconfigurable receiving channel, reconfigurable transmitting channel, and RF channel switching network is completed in sequence. The system control unit issues the working parameters for the T+2 period in the T+1 period. If the local oscillator frequency obtained by converting the working parameters is consistent with the current working frequency of the local oscillator signal generation unit, there is no need to execute the local oscillator signal generation unit frequency reconfiguration process, and the working status configuration of the reconfigurable receiving channel and reconfigurable transmitting channel can be completed directly.

5. The FPGA-based reconfigurable control method for radio frequency front-end networks according to claim 1, characterized in that, The configuration of operating parameters for the reconfigurable phased array, digital transceiver processor, and reconfigurable RF front-end network are all performed synchronously under the unified timing of the synchronization pulse.

6. The FPGA-based reconfigurable control method for radio frequency front-end networks according to claim 1, characterized in that, It also includes the gain control process: The reconfigurable receiving channel acquires the radio frequency received signal and performs detection processing on it, outputting a detection voltage. The detection voltage is used as a detection signal input to the analog-to-digital converter of the reconfigurable FPGA control unit. The detection voltage represents the amplitude of the radio frequency received signal. The reconfigurable FPGA control unit acquires the detection voltage through the analog-to-digital converter and converts it to obtain a detection voltage value representing the amplitude of the detection voltage. In automatic gain control mode, the reconfigurable FPGA control unit filters the detected voltage value and compares it with the start-up threshold and recovery threshold values ​​issued by the system control unit. When the filtered detected voltage value is greater than the start-up threshold value, the reconfigurable FPGA control unit performs adaptive gain control on the reconfigurable receiving channel according to the attenuation configuration value. When the filtered detected voltage value is less than the recovery threshold value, the reconfigurable FPGA control unit turns off the attenuation control output of the reconfigurable receiving channel. In manual control mode, the reconfigurable FPGA control unit directly controls the reconfigurable receiving channel based on the fixed attenuation configuration value issued by the system. The system control unit adjusts the start-up threshold, recovery threshold, or sets multiple thresholds according to different operating modes, and adopts different amplitude gain control for different detection voltage ranges to improve the dynamic range of the RF front-end RF path.

7. The FPGA-based reconfigurable control method for radio frequency front-end networks according to claim 1, characterized in that, It also includes performing time-segmented iterative correction procedures: After detecting the falling edge of the synchronization pulse at time T and determining that the calibration working mode has been entered, the reconfigurable FPGA control unit completes the configuration of the local oscillator frequency point, local oscillator switch, reconfigurable receiving channel, reconfigurable transmitting channel, and RF channel switch network. The reference calibration source outputs a calibration signal based on the calibration configuration parameters. The digital transceiver processor collects the baseband received signal, calculates the link performance index of the reconfigurable receiving channel, and reports it to the system control unit via the control bus. The reported data serves as the basis for calculating the receiving RF link compensation parameters. The system control unit will add the received radio frequency link compensation parameters obtained from this conversion to the working parameters of the T+2 period during the T+1 period and distribute them uniformly. Subsequently, an RF channel switching network is configured to loop back the RF transmit signal output from the reconfigurable transmit channel to the reconfigurable receive channel. The digital transceiver processor repeatedly acquires the baseband receive signal and calculates the link performance indicators of the reconfigurable transmit channel, iteratively obtaining the transmit RF link compensation parameters. It then traverses all frequency bands and all carriers to complete the correction and stores the optimal receive RF link compensation parameters and the optimal transmit RF link compensation parameters, thereby optimizing the RF phase delay, link gain, VSWR, and error vector amplitude of the reconfigurable receive channel and reconfigurable transmit channel under each frequency band and carrier.

8. The FPGA-based reconfigurable control method for radio frequency front-end networks according to claim 1, characterized in that, It also includes the FPGA on-orbit reconfiguration and refresh step: The system control unit sends upgrade commands and FPGA configuration files to the reconfigurable FPGA control unit; the loading and refreshing FPGA inside the reconfigurable FPGA control unit receives the FPGA configuration file and stores it in memory; the loading and refreshing FPGA reads the FPGA configuration file in memory, performs configuration loading on the functional control FPGA, and completes the on-orbit reconfiguration; after the reconfiguration is completed, the loading and refreshing FPGA outputs a feedback signal to the system control unit to inform it of the reconfiguration result, and automatically starts timed refresh, so that the control logic can be updated without powering down and restarting the entire machine.

9. A FPGA-based reconfigurable control system for a radio frequency front-end network, implementing the FPGA-based reconfigurable control method for a radio frequency front-end network as described in any one of claims 1-8, characterized in that, It includes a system control unit, a reconfigurable phased array, a reference calibration source, a reconfigurable RF front-end network, and a digital transceiver processor; the system control unit is connected to the system control unit, the reconfigurable phased array, the reference calibration source, the reconfigurable RF front-end network, and the digital transceiver processor respectively; the reference calibration source is connected to the reconfigurable RF front-end network and the digital transceiver processor respectively; the reconfigurable phased array is connected to the reconfigurable RF front-end network.

10. The FPGA-based reconfigurable RF front-end network control system according to claim 9, characterized in that, The reconfigurable RF front-end network includes a reconfigurable FPGA control unit, an RF channel switch network, at least one set of reconfigurable receiving channels, and at least one set of reconfigurable transmitting channels; each reconfigurable receiving channel and each reconfigurable transmitting channel is equipped with a local oscillator signal generation unit; the reconfigurable FPGA control unit is connected to the RF channel switch network, each reconfigurable receiving channel, and each reconfigurable transmitting channel respectively.

11. The FPGA-based reconfigurable RF front-end network control system according to claim 9, characterized in that, The reconfigurable receiving channel includes a reconfigurable filter, an adjustable attenuator, a reconfigurable amplifier, and a controllable phase shifter connected in series. The reconfigurable transmit channel includes a controllable phase shifter, a reconfigurable filter, a reconfigurable amplifier, a mixer, and an adjustable attenuator connected in series.

12. The FPGA-based reconfigurable RF front-end network control system according to claim 9, characterized in that, The reconfigurable FPGA control unit includes a loading and refreshing FPGA, a function control FPGA, a memory, an analog-to-digital converter, an external interface driver module, and an internal interface driver module. The loading and refreshing FPGA is connected to the function control FPGA, the memory, and the external interface driver module, respectively. The function control FPGA is connected to the analog-to-digital converter and the internal interface driver module.

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