Active copper-based interconnect system for computing circuits

Abstract

The present disclosure relates to active copper-based interconnect systems for computing circuits. A system includes a first circuit board comprising one or more first computing circuits. The system also includes an interconnect device coupled with the one or more first computing circuits. The interconnect device includes a linear re-driver configured to receive an electrical input signal from at least one of the one or more first computing circuits. The linear re-driver is also configured to augment the electrical input signal to form an augmented electrical signal. The linear re-driver is also configured to output the augmented electrical signal. The interconnect device is configured to provide the augmented electrical signal to one or more second computing circuits on a second circuit board through one or more wired connections. The augmentation of the electrical input signal compensates for known losses associated with the one or more wired connections.

Description

Technical Field

[0001] At least one embodiment relates to an interconnect system, such as an electrical signal interconnect system in a data center. For example, at least one embodiment relates to an active copper-based interconnect system. Background Technology

[0002] Computing circuits communicate with each other via interconnection systems. For example, electrical signals can be transmitted from one computing circuit to another via interconnection systems. Attached Figure Description

[0003] Various embodiments according to this disclosure will now be described with reference to the accompanying drawings, in which: Figure 1A-1B This is a schematic diagram of an example system architecture based on at least some embodiments; Figure 2 This is a schematic diagram of an example circuit board according to at least some embodiments; Figure 3 This is a perspective view of an example interconnect device according to at least some embodiments; Figure 4 It is a graph showing the relationship between signal amplitude and signal frequency according to at least some embodiments; Figure 5 This is a flowchart illustrating an example method of operating interconnect devices and providing electrical signals according to at least some embodiments; Figures 6A-6B The diagram illustrates a network architecture according to at least some embodiments; Figure 7 The diagram illustrates a distributed system according to at least some embodiments; Figure 8 An exemplary data center according to at least some embodiments is illustrated; Figure 9 The illustration depicts a computer system according to at least some embodiments; Figure 10 A block diagram of a computing system is schematically illustrated according to at least some embodiments; Figure 11 The illustration depicts an example computing environment according to at least one embodiment; Figure 12A-12B The illustration shows a view of a transceiver module operatively coupled to a network adapter according to at least some embodiments; Figure 13 Exemplary use cases of transceivers according to at least some embodiments are described. Detailed Implementation

[0004] High-performance computing (HPC) circuitry typically includes powerful graphics processing units (GPUs), central processing units (CPUs), data processing units (DPUs), and other components. Such HPC circuitry is typically implemented on printed circuit boards (PCBs) that also contain many other circuit components. GPUs, CPUs, DPUs, QPUs, PPUs, and / or other components can be integrated into computing servers (“servers”). In at least one embodiment, an artificial intelligence (AI) data center infrastructure platform is provided. Examples of AI data center infrastructure platforms include Nvidia® DGX™ SuperPOD™ and DGX™ Foundry. In at least one embodiment, the AI ​​data center infrastructure platform provides accelerated infrastructure and / or scalable performance, tailored for AI (e.g., machine learning (ML)) and other high-performance computing (HPC) workloads. In a data center, servers and / or other data center components are interconnected using physical interconnects. Copper cabling can be used for short-distance connections, while optical fiber (e.g., optical fibers) is typically used for long-distance connections. Optical-based connections use transceivers that convert signals in the electrical domain to signals in the optical domain and vice versa. Such transceivers can have high power consumption, high heat output, and high cost. Furthermore, optical transceivers are bulky and occupy valuable space. Copper-based connections do not use transceivers, resulting in lower power consumption, lower heat generation, and lower cost. Moreover, copper-based connections take up less space than optical transceivers, enabling higher interconnect density. However, traditional copper-based interconnects are not suitable for long-distance connections due to losses in copper cables and related connections.

[0005] While it may be impossible to maintain copper bandwidth (BW) expansion while preserving adequate bandwidth (BW) density, an alternative solution may be required that allows for further expansion of copper or active copper links. This disclosure leverages the performance and advantages of active copper to provide a new unified board configuration design that can accommodate both copper-based transceivers and optical transceivers. This design allows for flexible replacement of certain chips while maintaining the same PCB design, thus addressing bandwidth and density issues. This will allow for flexible control of board density using novel active copper architectures. This document provides an architecture that allows for the replacement of quad small form factor (QSFP) devices or at least some QSFP devices with an active copper architecture, thereby enabling design flexibility in this area. In at least one embodiment, this document provides a design that allows substantially the same PCB design to be adapted to the next bandwidth benchmark. Embodiments of this disclosure address the aforementioned problems by providing a flexible design capable of handling different transceiver types and bandwidths.

[0006] As described herein, copper-based transceivers can offer significant advantages, including lower latency and power consumption compared to optical transceivers. Copper-based transceivers may not require retimers, which is beneficial for system performance. Losses on copper traces are substantial, making it difficult to achieve reasonable performance over short distances. However, copper is more economical and lighter than optical solutions, making it the preferred option for short-distance connections within data centers. However, due to the limitations of copper, optics are typically used for long-distance transmission. In some embodiments, copper-based transceivers use linear re-drivers as amplifiers to shape and / or enhance signals to maintain the performance of the copper connection. Linear re-drivers can overcome signal attenuation and / or ensure reliable data transmission over copper connections. In some embodiments, a linear re-driver receives a signal, shapes it, and / or enhances it to overcome obstacles in the connection and / or ensure clear signal at the receiving end.

[0007] The modular design of this circuit board allows customers to choose between the MBAC solution or transceiver described herein based on their needs (e.g., selecting a suitable hybrid of onboard active copper cable (MBAC) and transceiver to optimize performance and cost for their network configuration), with the system capable of compensating for any losses. In some embodiments, the system can compensate for all losses, ensuring efficient operation of the selected configuration (MBAC or transceiver). In some embodiments, users can decide on a per-connection basis whether to use a built-in solution (e.g., MBAC) or a traditional solution. This interchangeability makes implementation more flexible. In some embodiments, the location of components may vary depending on the implementation. In some embodiments, an innovation of this disclosure is the ability to predict and compensate for the circuit board's response at high frequencies. This capability is crucial for ensuring the circuit board's performance in high-frequency environments. In some embodiments, the circuit board operates between two Nvidia services and allows users to choose between implementing an MBAC solution or a transceiver solution. This flexibility may be a feature of the circuit board design. In some embodiments, mounting a linear heavy driver on the motherboard can significantly increase system density. This increase in density can support higher data rates and more connections. This approach reduces latency by minimizing signal travel distance. Reduced latency can support high-performance applications. In some embodiments, the frequency response of the linear re-driver is matched to the service requirements. This matching ensures that signals are processed correctly and their integrity is maintained. The selected device is closely matched to the optimal frequency response required by the MBAC solution. This close matching improves the performance and reliability of the solution.

[0008] Various aspects of this disclosure address the aforementioned problems, deficiencies, and other challenges by providing a system utilizing long-distance copper-based interconnects. In some embodiments, the interconnect system as described herein can be used to connect associated servers via a switchboard. In one embodiment, the interconnect system is suitable for connecting a network interface card (NIC) to a switch, connecting a switch to another switch (e.g., connecting a GPU), and / or differential active copper components. As described herein, a linear re-driver included in the interconnect system receives an input electrical signal and amplifies (e.g., amplifies, modulates, etc.) that signal. The amplified signal is output along the copper-based interconnect and received by the connected device. The signal amplification and / or modulation is performed to overcome known losses in the copper-based interconnect. In some embodiments, the internal losses at the transmitting and receiving ends, as well as the losses in the connection between the transmitting and receiving ends, are modeled and known. Therefore, the signal can be selectively amplified (e.g., amplified) to compensate for known signal losses. Furthermore, the linear re-driver can also modulate the signal (e.g., analog signal modulation, etc.) to compensate for frequency-related conduction and dielectric losses in the signal transmission path. In some embodiments, the linear re-driver is integrated into the cable (e.g., located at the cable end). In some embodiments, the linear re-driver is included in a module directly coupled to the circuit board (e.g., located on a server board, switching board, etc.). Because copper-based interconnects (including the linear re-driver) are smaller than conventionally used optical transceivers, interconnect density on the circuit board can be significantly increased without sacrificing functionality or cost by using the interconnect systems described in the embodiments herein. In some embodiments, the circuit board uses a combination of copper-based interconnects and conventional optical transceivers (e.g., ports receiving conventional optical transceivers) according to the end-user's design specifications. The combination of copper-based interconnects and other transceivers (e.g., conventional optical transceivers, etc.) can be customized according to specific embodiments to meet given specifications.

[0009] The advantages of this disclosure include, but are not limited to, increasing the density of interconnect devices on a circuit board without sacrificing cost and / or functionality. Since the active copper-based interconnect systems disclosed herein may be smaller than conventional interconnect systems currently in use, in some embodiments, a greater number of copper-based interconnect devices can be included on the circuit board than in conventional methods. Accordingly, computing circuitry on the circuit board can send and / or receive a greater number of electrical signals. Furthermore, the interconnect systems described herein can effectively increase the distance over which electrical signals can be transmitted via copper-based cables without sacrificing signal integrity. Therefore, more expensive electrical signal communication options (e.g., via fiber optics) can be replaced, resulting in cost savings in environments such as data centers. The interconnect systems described herein also save power compared to other signal communication methods such as fiber optics. In addition, the interconnect systems described herein can simplify electrical connections on a PCB, reduce device density on the PCB, and lower costs. Furthermore, the interconnect systems described herein are at least partially “customizable” in some embodiments, meaning that the configuration of the interconnect system can be tailored to meet a given specification, for example, by including a combination of active copper-based interconnect devices and / or conventional interconnect devices on the circuit board.

[0010] Linear active low-power and low-latency solutions using MBAC modules can reduce the power and heat dissipation issues of retiming copper cabling or optical solutions, while virtually eliminating their increased end-to-end latency for AI and HPC applications. The use of 224G copper solutions also reduces the cost of the solution compared to traditional optical modules such as TRCV. Furthermore, the supply chain availability of optical modules required by rapidly expanding AI data centers may not meet demand. Therefore, using MBAC solutions allows for rack cabling (e.g., up to 3 meters long) using copper and / or analog heavy-duty drives instead of optical modules.

[0011] Some embodiments of this disclosure relate to a multi-chip module (MCM) having a central master die and a plurality of peripheral MCM slots configured to mechanically receive and electrically connect mezzanine packages, which may include co-packaged optics (CPO) packages and / or co-packaged copper (CPC) packages. Each mezzanine package may include a package substrate comprising a connector portion configured to engage the MCM slots and a body portion extending beyond the periphery of the MCM substrate. The body portion of the mezzanine package may be configured to receive optics and / or integrated circuits (e.g., via mezzanine sockets), thereby allowing connections to be established between the optics and / or integrated circuits, the RF copper cable connector, and / or the master die of the MCM. Because the mezzanine packages extend beyond the periphery of the MCM substrate, the physical size of the MCM substrate can be kept small, thereby reducing costs and avoiding the aforementioned manufacturing challenges. Furthermore, several optics and integrated circuits can be connected via the mezzanine packages, occupying relatively inexpensive space around the periphery of the MCM substrate. In this article, "co-packaged optics" (or "CPO") and "co-packaged copper" (or "CPC") can refer to advanced heterogeneous integration of optics with silicon or copper with silicon, either of which can be achieved on a single package substrate. CPO can employ pluggable optical modules including optical engines (OEs) for converting optical signals to electrical signals and vice versa. CPO can also consist of optical components on a photonic die and electronic components on an electrical die.

[0012] Figure 1AThis is a schematic diagram of an example system architecture 100A according to at least some embodiments. In some embodiments, computing circuits 102A and 102B are communicatively coupled to each other via the active copper-based interconnect system described herein. Computing circuit 102A may be disposed on circuit board 110A. Circuit board 110A may be a circuit board for a first server, a first switch, etc., for example in a data center. Computing circuit 102B may be disposed on circuit board 110B. Circuit board 110B may be a circuit board for a second server, a second switch, etc. Circuit boards 110A and / or 110B may each be a PCB on which multiple components are disposed. These components may include computing components, power supply components, and / or communication components (e.g., communication ports, interconnect devices, etc.). In some embodiments, circuit board 110B may be located remotely from circuit board 110A. For example, circuit boards 110A and 110B may be spatially separated. For example, circuit boards 110A and 110B may be located in the same data center server room, different data center server rooms, or different data center areas. In one example, circuit board 110A is located in a first blade server chassis on a rack in a data center, while circuit board 110B is located in a second blade server chassis on the same rack or another rack within the data center (e.g., in the same row or a different row). In one embodiment, circuit board 110A and circuit board 110B may be separated by a distance of more than three meters, etc. In some embodiments, circuit board 110A and circuit board 110B may be separated by a distance of more than five meters, more than eight meters, etc.

[0013] Computing circuits 102A and 102B may include one or more graphics processing units (GPUs), central processing units (CPUs), data processing units (DPUs), and / or other computing components. Computing circuits 102A and 102B may communicate with each other via one or more interconnect devices. In some embodiments, electrical signals are transmitted from computing circuit 102A to computing circuit 102B via interconnect device 104A and cable connection 130A. In some embodiments, electrical signals are transmitted from computing circuit 102B to computing circuit 102A via interconnect device 104B and cable connection 130B. In one embodiment, the same cable connection and interconnect device can be used to transmit and / or receive electrical signals bidirectionally. Electrical signals can be transmitted at high speed. In some embodiments, the electrical signal transmission rate of each channel exceeds 100 gigabytes per second (GB). For example, each communication channel can transmit 100 GB of data per second from one computing circuit to another. A single cable connection (e.g., cable connection 130A) can constitute a channel. Therefore, 100 GB of data per second can be transmitted from computing circuit 102A to computing circuit 102B via interconnect device 104A and / or cable connection 130A.

[0014] In some embodiments, interconnect device 104A is an active module for performing signal enhancement and / or signal conditioning. In embodiments, signal enhancement and / or signal conditioning may include signal amplification, signal attenuation, signal modulation, signal filtering, and / or signal modification. In some embodiments, interconnect device 104A receives an electrical input signal from computing circuitry 102A. Interconnect device 104A may enhance and / or condition the received electrical input signal and output the enhanced signal to computing circuitry 102B via cable connection 130A. In some embodiments, interconnect device 104A includes a linear re-driver for enhancing the input signal and forming the enhanced signal. Interconnect device 104A may be configured to operate at high speeds. For example, interconnect device 104A may be configured to operate at a rate exceeding 100 GB / s per channel. In some embodiments, interconnect device 104A is configured to operate at a rate between approximately 100 GB / s per channel and approximately 200 GB / s per channel. In some embodiments, interconnect device 104A may be configured to operate at a rate exceeding 200 GB / s per channel. In some embodiments, interconnect device 104A is configured to operate at a rate of approximately 200 GB / s to approximately 300 GB / s per channel. In some embodiments, interconnect device 104A is configured to operate at a rate of approximately 224 GB / s per channel.

[0015] Linear re-drivers can be used to improve the quality of high-speed data signals. Linear re-drivers can perform signal conditioning, such as equalization. Equalization can include compensating for signal degradation (e.g., loss of high-frequency components) caused by long-distance signal transmission (e.g., via cables or traces). In some embodiments, linear re-drivers perform de-emphasis and / or pre-emphasis, which may include adjusting the signal amplitude at specific frequencies to cancel inter-symbol interference. Linear re-drivers can perform signal amplification. In some embodiments, linear re-drivers amplify signals (e.g., signals expected to be attenuated) to ensure that the signal remains within a voltage threshold level that can be correctly detected at the receiver after attenuation. In some embodiments, linear re-drivers amplify the input signal in a manner that preserves the original characteristics of the signal (e.g., amplitude and / or shape) at the receiver without introducing significant distortion and / or noise. In some embodiments, linear re-drivers may not re-clock the signal and may allow the signal to pass through with minimal delay.

[0016] The signal enhancement provided (e.g., by a linear re-driver) can overcome known losses in cable connection 130A. In one embodiment, the enhanced electrical signal attenuates as it travels from interconnect device 104A to computing circuit 102B (e.g., via cable connection 130A). Furthermore, signal attenuation may also occur between computing circuit 102A and interconnect device 104A. The interconnect device can compensate for this signal attenuation based on an understanding of the amount of loss and / or distortion between computing circuit 102A and interconnect device 104A and / or between interconnect device 104A and computing circuit 102B. Losses in cable connection 130A can be determined based on the distance / length of cable connection 130A and the losses of traces at both ends of the PCB (e.g., at PCB 110A and / or PCB 110B). Losses can be determined based on cable type and / or cable connector type. Losses can be determined based on interconnect type (e.g., by port type). For example, a first type of port may have a first loss, and a second type of port may have a second loss. These losses can be determined in advance through methods such as testing and / or modeling.

[0017] In some embodiments, cable connection 130A includes a copper-based cable for transmitting electrical signals. As used herein, the term "copper-based" may include embodiments of interconnect cables having a copper core (e.g., for transmitting electrical signals). In some embodiments, a copper-based cable is a coaxial cable having a copper portion for transmitting electrical signals. In some embodiments, interconnect device 104A may condition an input signal and output the conditioned signal to computing circuit 102B via cable connection 130A. The signal may attenuate during transmission from interconnect device 104A to computing circuit 102B. The attenuated electrical signal received by computing circuit 102B corresponds to the input signal received by interconnect device 104A from computing circuit 102A and / or the original signal output by computing circuit 120A. For example, the signal received by computing circuit 102B via cable connection 130A may be substantially the same as the signal provided from computing circuit 102A to interconnect device 104A. Interconnect device 104A can condition and / or enhance the signal so that the signal received by computing circuit 102B is substantially the same as the signal provided by computing circuit 102A.

[0018] Interconnect device 104B can perform similar operations to interconnect device 104A to provide electrical signals from computing circuit 102B to computing circuit 102A via cable connection 130B.

[0019] Electrical signals can be provided from computing circuit 102A to computing circuit 102B in the form of single-ended signals and / or differential pair signals. For single-ended signals, one interconnect device amplifies and / or conditions the signal. For differential pair signals, two interconnect devices can amplify and / or condition the signal. One interconnect device can amplify and / or condition the first signal of the differential pair, while the second interconnect device can amplify and / or condition the second signal of the differential pair. For example... Figure 1A As shown, the electrical signal transmitted from interconnect device 104A to computing circuit 102B via cable connection 130A can constitute at least a portion of the differential pair signal. Similarly, the electrical signal transmitted from interconnect device 104B to computing circuit 102A via cable connection 130B can also constitute at least a portion of the differential pair signal.

[0020] Figure 1B This is a schematic diagram of an example system architecture 100B according to at least some embodiments. In some embodiments, rack 120A is disposed adjacent to rack 120B in a data center. Each of racks 120A and 120B may accommodate multiple computing bays, such as server 124 and / or switch bays 122A, 122B. Server 124 and / or switch bays 122A, 122B are interconnected via copper-based connections 126. In some embodiments, interconnect devices coupled and / or integrated with switch bays 122A, 122B may amplify and / or amplify electrical signals traveling between switch bays 122A, 122B. For example, an interconnect device coupled to switch bay 122A may receive electrical signals (e.g., signals from server 124 in rack 120A). The interconnect device may amplify and / or amplify the signals (e.g., via a linear re-driver) and then provide the amplified and / or amplified signals to the respective switch bay 122B via copper-based connections 126. Switch tray 122B can receive the signal, and switch tray 122B provides the received signal to server 124 (e.g., server 124 in rack 120B). In some embodiments, a plurality of copper base connections 126 communicatively couple switch tray 122A to switch tray 122B. The plurality of copper base connections 126 can couple each switch tray 122A to each corresponding switch tray 122B. Switch trays 122A, 122B may include interconnect devices as described herein for each copper base connection 126.

[0021] Figure 2This is a schematic diagram of an example circuit board 200 according to at least some embodiments. In some embodiments, the circuit board 200 forms at least a portion of a switch bracket. In some embodiments, computing circuitry 202 is disposed on PCB 210. Computing circuitry 202 may include one or more GPUs, CPUs, DPUs, and / or other computing units. PCB 210 may form at least a portion of a server or switch, such as a server or switch in a data center. In some embodiments, PCB 210 includes a port 208 to facilitate communication between computing circuitry 202 and one or more other computing circuits disposed on one or more other PCBs. One or more switches 207 may be configured to direct electrical signals from computing circuitry 202 to port 208, for example, through electrical traces on PCB 210. In some embodiments, port 208 forms a receptacle for receiving transceivers and / or cable ends. For example, in some embodiments, port 208 may be configured to receive an optical transceiver 205. The optical transceiver 205 may be a pluggable transceiver configured to receive an electrical input signal (e.g., a signal from computing circuitry 202), generate an optical signal indicating the electrical input signal, and provide the optical signal to one or more other computing circuits via optical fiber 231.

[0022] In some embodiments, PCB 210 includes a plurality of ports 208. Each port 208 may serve two or more GPUs of computing circuitry 202. In some embodiments, PCB 210 includes up to 18 ports 208 to serve connections to up to 36 GPUs. Transceivers 205 may be inserted into each port 208 to send and / or receive electrical signals (e.g., optical signals indicating electrical signals) for the GPUs. In one embodiment, each transceiver 205 may be flexibly interchangeable (e.g., swapped) with interconnect device 204B, as described below. To expand computing circuitry 202 to include more GPUs, more ports 208 may be needed to transmit more electrical signals through more communication channels. In some embodiments, the number of communication channels will be doubled. In some embodiments, computing circuitry 202 may include up to 72 GPUs. PCB 210 may include up to 36 ports 208 to provide connectivity services for GPUs. There may not be enough space on PCB 210 to allow ports 208 to serve connections for a larger number of GPUs. In some embodiments, PCB 210 includes interconnect device 204A to provide connectivity services for GPUs. Interconnect device 204A can be smaller than port 208 and its associated transceiver 205 and / or interconnect device 204B, thereby allowing for higher device density on PCB 210.

[0023] In some embodiments, port 208 may be configured to receive interconnect device 204B. Interconnect device 204B may be an optical transceiver, or something similar to the one described above. Figure 1A The interconnect devices 104A and 104B are electrical interconnects. In some embodiments, interconnect device 204B is a pluggable transceiver. In some embodiments, interconnect device 204B forms a cable termination configured to couple to a receptacle of port 208. Thus, in some embodiments, port 208 may receive an optical transceiver, or may receive an electrical interconnect configured to be inserted into a port of the same type as that available for an optical transceiver. Interconnect device 204B receives electrical input signals (e.g., electrical input signals from computing circuitry 202). Interconnect device 204B may perform active functions to amplify and / or condition the received electrical input signals. In some embodiments, interconnect device 204B includes a linear re-driver for amplifying the received input signals. In some embodiments, the linear re-driver may be integrated into the cable termination of interconnect device 204B. Interconnect device 204B may provide the amplified electrical signal to another computing circuit (e.g., computing circuitry located on another PCB) via interconnect cable 230. The enhancement and / or conditioning provided by the linear re-driver can compensate for known signal characteristics (e.g., losses) on the traces and / or electrical components on the interconnect cable 230 and / or PCB 210 and / or on the receiver's PCB. In some embodiments, the interconnect cable 230 is a copper-based communication cable as described herein. In some embodiments, each port 208 may be configured to receive the optical transceiver 205 and the interconnect device 204B at different times.

[0024] In some embodiments, electrical signals from computing circuitry 202 can be transmitted to remote computing circuitry (e.g., circuitry on a remote circuit board) without using port 208. In some embodiments, interconnect device 204A may be directly coupled to PCB 210. In some embodiments, interconnect device 204A is located approximately in the center of PCB 210. Alternatively, interconnect device 204A may be located near the periphery of PCB 210. In some embodiments, interconnect device 204A is an MBAC solution. PCB 210 may include a port for receiving a harness electrically coupled to at least one interconnect device 204A. In some embodiments, interconnect device 204A is coupled to a port on PCB 210, and a connector is coupled to the port to transmit electrical signals to and / or from interconnect device 204A. Interconnect device 204A may transmit electrical signals to remote computing circuitry via interconnect cable 230. Interconnect device 204A may be an active module that integrates a linear re-driver that receives electrical input signals from computing circuitry 202 and performs signal enhancement and / or signal conditioning on the input signals. Interconnect device 204A may provide output signals to computing circuitry on other circuit boards via interconnect cable 230. In some embodiments, interconnect device 204A includes a linear re-driver for performing signal enhancement and / or signal conditioning, similar to interconnect device 204B described above. In some embodiments, the enhancement and / or conditioning of the input signals may compensate for known signal characteristics (e.g., signal loss) in interconnect cable 230. In some embodiments, each interconnect device 204A includes at least one connection configured to receive electrical signals from one or more remote computing circuits. For example, and in some embodiments, interconnect device 204A may include a receiver for receiving signals from computing circuitry on another circuit board via one of the interconnect cables 230. Interconnect device 204A may provide the received signals to computing circuitry 202. In some embodiments, interconnect device 204A may be a transceiver capable of sending and receiving electrical signals for computing circuitry 202.

[0025] In some embodiments, a first portion of the interconnect capability of PCB 210 may be provided by port 208, and a second portion of the interconnect capability of PCB 210 may be provided by active modules (e.g., interconnect device 204A) on PCB 210 itself. In some embodiments, the interconnect capability of PCB 210 is provided solely by port 208. In some embodiments, the interconnect capability of PCB 210 is provided solely by active modules (e.g., interconnect device 204A) on PCB 210 itself. PCB 210 can be at least partially customizable by the number and / or location of ports 208 along with the inclusion of one or more active interconnect modules. In embodiments where the PCB is to be connected to a conventional optical transceiver 205, the PCB may include one or more ports 208. Interconnect device 204A and associated copper-based cable connections can provide the remaining portion of the PCB's interconnect capability. Including ports 208 and interconnect device 204A on PCB 210 can strike a balance between interconnect capability, board density, and / or cost factors.

[0026] Figure 3 This is a perspective view of an example interconnect device 304 according to at least some embodiments. The interconnect device 304 may be formed as a paddle card configured to couple to a host card (e.g., a host PCB). In some embodiments, the interconnect device 304 may be coupled to a PCB. Pads on the bottom of the body 306 may be electrically coupled to traces on the PCB to transmit signals to and / or from computing circuitry on the PCB. In some embodiments, computing circuitry on the PCB provides an electrical input signal to the interconnect device 304 (e.g., via one or more conductive traces in the PCB and / or the pads on the bottom of the body 306). This electrical input signal may be provided to a linear re-driver 332 of the interconnect device 304. The linear re-driver 332 may amplify and / or condition the electrical input signal to form an enhanced electrical signal. The amplification and / or conditioning provided by the linear re-driver 332 to the electrical input signal may compensate for known signal behaviors in the coupled interconnect cables, such as losses in the interconnect cables.

[0027] Enhanced and / or conditioned electrical signals may be provided to bus 334 by linear re-driver 332. Multiple interconnects 330 may be coupled to each bus 334. Each interconnect 330 may be coupled to a copper-based interconnect cable for transmitting electrical signals from interconnect device 304 to one or more remote computing circuits. In some embodiments, each interconnect 330 represents a channel (e.g., a communication channel). Interconnect device 304 may be configured to receive electrical signals from one or more remote computing circuits. In one embodiment, interconnect device 304 may receive signals via at least one interconnect 330. The received signals may be provided to the computing circuits via associated bus 334 (e.g., coupled to interconnect 330) and one or more conductive traces of interconnect device 304. This signal may be provided to electrical connections on a PCB that communicatively connect interconnect device 304 to computing circuits on the PCB.

[0028] Figure 4This is a diagram 400 showing the relationship between signal amplitude and signal frequency according to at least some embodiments. In some embodiments, the linear re-driver of the interconnect device as described herein can operate according to various settings corresponding to known losses in the interconnect cable (e.g., copper-based cable). Different operating settings can be selected based on known losses in the associated interconnect cable. Known losses can be based on cable characteristics such as, for example, length and / or construction. Known losses can also be based on traces, electrical components, inductor losses, capacitor losses, etc., within the PCB at the transmitting end and the PCB at the receiving end. These losses may be known after testing and / or experimentation. In some embodiments, the linear re-driver is used to modify the input electrical signal to meet a target response (e.g., a target frequency response). The target response may vary due to losses at the interconnect cable, the transmitting PCB, the receiving PCB, etc. Therefore, loss characteristics and / or frequency response may be unique for a particular pair of: the location of the first server / switch, the port used from the first server / switch, the location of the second server / switch, the port used for the second server / switch, and / or cable characteristics. For example, in a first operating setting, the linear re-driver can modify the input signal to correspond to a target response 462A. Due to defects and / or operational limitations, the linear re-driver may provide an output signal corresponding to frequency response 462B. In a second operating setting, to compensate for further losses, the linear re-driver may modify the input signal to correspond to the target response 464A. The linear re-driver can then output a corresponding signal with frequency response 464B. Again, due to defects and / or operational limitations of the linear re-driver, the frequency response of the output signal may not match the target response. However, the frequency response of the output signal can be an approximation of the target response. In similar examples, to compensate for further losses, the linear re-driver may operate according to a third or fourth operating setting. The third operating setting may correspond to the target response 466A and an output signal with frequency response 466B. The fourth operating setting may correspond to the target response 468A and an output signal with frequency response 468B.

[0029] Figure 5 This is a flowchart of an example method 500 for operating interconnect devices according to at least some embodiments. Although a specific order is shown in the figure, the order of the processes can be modified unless otherwise stated. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes can be performed in different orders, and some processes can be performed in parallel. Furthermore, one or more processes may be omitted in various embodiments. Therefore, not all processes are necessary in every embodiment. Other process flows are also possible.

[0030] In block 510, the interconnect device receives a first electrical input signal from at least one of one or more first computing circuits. The interconnect device may be integrated with one or more first computing circuits on the same PCB. In some embodiments, one or more first computing circuits include one or more GPUs, CPUs, DPUs, and / or other computing units, etc. One or more first computing circuits may provide the first electrical input signal to the interconnect device via one or more electrical connections on the PCB.

[0031] In block 520, the interconnect device amplifies the first electrical input signal to form an enhanced electrical signal. In some embodiments, the linear re-driver of the interconnect device performs one or more signal conditioning and / or signal enhancement operations on the first electrical input signal to form the enhanced electrical signal. The enhancement of the first electrical input signal may be based on known losses in the wired connection. For example, the enhanced electrical signal may overcome known losses. In some embodiments, the boost amount provided to the first electrical input signal may be defined by user input indicating the port used to send and / or receive the signal, the identifiers of the sender and / or receiver of the signal, the length and / or type of the wired connection, etc. In some embodiments, the boost amount is determined according to a lookup table used to determine the conditioning operation to be performed based on a set of inputs (e.g., port, server ID, distance, etc.).

[0032] In block 530, interconnecting devices provide enhanced electrical signals to one or more second computing circuits via one or more wired connections. The one or more second computing circuits may be located remotely to the one or more first computing circuits. In some embodiments, the one or more wired connections comprise copper-based cables (e.g., cables with copper cores, cables with copper elements for transmitting electrical signals, etc.). The enhancement and / or conditioning provided by the linear re-driver (in block 520) can compensate for known signal characteristics in the one or more wired connections, such as losses in the wired connections.

[0033] Servers and data centers The following figures illustrate, but are not limited to, exemplary network servers and data center-based systems that can be used to implement at least one embodiment.

[0034] Data centers may include multiple network switches in a specific topology, such as a fat tree topology, a thin fly topology, or a dragonfly topology. The specifications and composition of the network switches in the topology affect the overall network performance of the data center (e.g., bandwidth capacity). In at least one embodiment, an artificial intelligence (AI) data center infrastructure platform is provided. Examples of AI data center infrastructure platforms include Nvidia® DGX. TMSuperPOD TM and DGX TM Foundry. In at least one embodiment, the AI ​​data center infrastructure platform provides accelerated infrastructure and / or scalable performance tailored for AI, such as machine learning (ML) and other high-performance computing (HPC) workloads.

[0035] Data center environment example Data centers and high-performance computing clusters, as described above, are typically formed by various computing components or networked devices, and communication networks formed by electrical and / or optical equipment can be used to enable communication between these networked devices. For example, see reference... Figures 6A-6B Network architecture 600 may include a data center 602, a communication network 604, and one or more network devices 606. Network architecture 600 may illustrate a general computing architecture, within which more specific systems and / or subsystems may operate.

[0036] For example, data center 602 may be a centralized facility designed to house computing resources and related components. Data center 602 can operate to support the infrastructure required for advanced computing tasks to achieve efficient, secure, and reliable operation. Data center 602 may include building and structural components, including power, cooling systems, fire suppression systems, and physical security measures configured to maintain optimal operating conditions and / or protect equipment from environmental hazards and unauthorized access. Example data center 602 may include high-performance servers or compute nodes typically arranged in racks and connected via high-speed networks as described herein, such as... Figure 6B The illustration depicts a high-performance server or computing node. These servers may include processors (e.g., central processing units (CPUs), graphics processing units (GPUs), data processing units (DPUs), etc.), memory (e.g., RAM), and storage solutions (e.g., hard disk drives (HDDs), solid-state drives (SSDs), etc.). The hardware configuration can be designed for parallel processing and high throughput to meet the demands of high-performance computing (HPC) applications.

[0037] Data center 602 may include high-speed network devices (such as network switches, routers, firewalls, etc.) to facilitate fast and secure data transfer between the data center 602 (e.g., between servers or compute nodes) and external networks. Data center 602 can facilitate communication between servers or compute nodes by ensuring efficient data exchange, minimizing latency, and maximizing bandwidth through a network topology. The network topology specifies how various network devices (such as switches and routers) interconnect to enable data flow. By implementing an efficient network topology, data center 602 can support high-performance computing tasks. Examples of various network topologies may include hierarchical networking topologies, such as fat-tree topologies, thin-fly topologies, dragonfly topologies, etc.

[0038] Communication network 604 can communicatively couple data center 602 to one or more network devices 606 and other external devices for data exchange and connectivity. Examples of communication network 604 may include Internet Protocol (IP) networks, Ethernet, InfiniBand (IB) networks, Fibre Channel networks, the Internet, cellular communication networks, wireless communication networks, combinations thereof (e.g., Ethernet Fibre Channel), variations thereof, etc. The ability of communication network 604 to combine many network types and configurations allows data center 602 to adapt to a variety of application requirements, from general data communication to dedicated HPC tasks. As described herein, communication network 604 can utilize various optical components to establish communication links between components in architecture 600 (e.g., communicatively coupled between components in architecture 700). Thus, communication network 604 may include various optical devices, transceivers, modules, active copper interconnect systems, etc., configured to generate electrical and / or optical signals (e.g., providing transmitter functionality) and / or receive electrical and / or optical signals (e.g., providing receiver functionality).

[0039] One or more network devices 606 may include various computing devices capable of transmitting and receiving signals via communication network 604. The range of network devices 606 can range from personal computing devices to complex server configurations. Examples include personal computers (PCs), laptops, tablets, smartphones, and servers. One or more network devices 606 can facilitate user interaction with data center 602, allowing data to be entered, retrieved, and processed from remote locations. In addition to individual computing devices, one or more network devices 606 may also include collections of servers or collections of additional data centers. For example, these could be other data centers similar to or identical to data center 602. This interconnection can allow the formation of distributed computing environments to improve redundancy, load balancing, and disaster recovery capabilities. By linking multiple data centers, network architecture 600 can leverage geographically dispersed resources to optimize performance and ensure high availability.

[0040] As described herein, data center 602 and / or one or more network devices 606 may include storage devices and processing circuitry for performing computational tasks, such as controlling data flow within and on communication network 604. The processing circuitry may include software, hardware, or a combination thereof. For example, the processing circuitry may include memory containing executable instructions and a processor (e.g., a microprocessor) that executes those instructions. Memory may correspond to any suitable type of memory device or collection of memory devices configured to store instructions. Non-limiting examples of suitable memory devices include flash memory, random access memory (RAM), read-only memory (ROM), variations thereof, combinations thereof, or similar technologies. In certain embodiments, memory and processor may be integrated into a common device, such as a microprocessor with integrated memory. Additionally or alternatively, the processing circuitry may include hardware components such as application-specific integrated circuits (ASICs). Other non-limiting examples of processing circuitry include integrated circuit (IC) chips, CPUs, GPUs, microprocessors, field-programmable gate arrays (FPGAs), collections of logic gates or transistors, resistors, capacitors, inductors, and diodes. Some or all of the processing circuitry in a processing circuit system may be mounted on a printed circuit board (PCB) or an assembly of PCBs. It should be understood that any suitable type of electrical component or assembly of electrical components may be suitable for inclusion in the processing circuitry system.

[0041] Additionally, although not explicitly shown, this disclosure envisions that data center 602 and one or more network devices 606 may include one or more communication interfaces for facilitating wired and / or wireless communication between each other and other unillustrated elements of network architecture 600. These communication interfaces may include a variety of technologies, including but not limited to Ethernet ports, fiber optic connections, Wi-Fi® transceivers, Bluetooth® modules, and cellular communication modules for integration and interoperability among various components within network architecture 600.

[0042] Furthermore, this disclosure envisions that network architecture 600 may include additional components and functionalities. For example, the network architecture may include, but is not limited to, additional processing units, dedicated accelerators (such as tensor processing units or TPUs), enhanced security modules, and redundant power supplies. Including these elements may be intended to ensure that network architecture 600 is robust, scalable, and capable of meeting various operational requirements. Any changes, modifications, or adaptations of the elements falling within the spirit and scope of this disclosure are considered to be covered by this disclosure. This includes any combination, sub-combination, or enhancement of the various elements to achieve improvements in performance, reliability, and efficiency in network architecture 600.

[0043] Figure 7A distributed system 700 according to at least some embodiments is illustrated. In at least one embodiment, the distributed system 700 includes one or more client computing devices 702, 704, 706, and 708, which are configured to execute and operate client applications, such as web browsers, proprietary clients, and / or variations thereof, via one or more networks 710. In at least one embodiment, a server 712 may be communicatively coupled to remote client computing devices 702, 704, 706, and 708 via network 710. In some embodiments, the server 712 includes a PCB having one or more power connectors as described above. In some embodiments, the server 712 receives electrical energy via a power supply system as described above.

[0044] In at least one embodiment, server 712 may be adapted to run one or more services or software applications, such as services and applications that can manage single sign-on (SSO) access session activity across multiple data centers. In at least one embodiment, server 712 may also provide other services or software applications, which may include non-virtual and virtual environments. In at least one embodiment, these services may be provided as web-based services, cloud services, or in a Software as a Service (SaaS) model to users of client computing devices 702, 704, 706, and / or 708. In at least one embodiment, users operating client computing devices 702, 704, 706, and / or 708 may, in turn, interact with server 712 using one or more client applications to utilize the services provided by these components.

[0045] In at least one embodiment, software components 718, 720, and 722 of system 700 are deployed on server 712. In at least one embodiment, one or more components of system 700 and / or the services provided by these components may also be implemented by one or more client computing devices 702, 704, 706, and / or 708. In at least one embodiment, a user operating a client computing device can utilize one or more client applications to use the services provided by these components. In at least one embodiment, these components may be implemented in hardware, firmware, software, or a combination thereof. It should be understood that system configurations can take many different forms, which may differ from those of distributed system 700. Therefore, Figure 7 The embodiments shown are merely one example of a distributed system for implementing the system described in the embodiments, and are not intended to limit other forms.

[0046] In at least one embodiment, client computing devices 702, 704, 706, and / or 708 may include various types of computing systems. In at least one embodiment, the client computing device may include a portable handheld device (e.g., iPhone®, cellular phone, iPad®, computing tablet device, personal digital assistant (PDA)) or wearable device (e.g., Google Glass® head-mounted display) running software such as Microsoft Windows Mobile® and / or various mobile operating systems such as iOS, Windows Phone, Android, BlackBerry 10, Palm OS, and / or variants thereof. In at least one embodiment, the device may support various applications, such as various internet-related applications, email, SMS service applications, and may use various other communication protocols. In at least one embodiment, the client computing device may also include a general-purpose personal computer, such as a personal computer and / or laptop running various versions of Microsoft Windows®, Apple Macintosh®, and / or Linux operating systems. In at least one embodiment, the client computing device may be a workstation computer running various commercial UNIX® or UNIX-like operating systems, including but not limited to various GNU / Linux operating systems such as Google Chrome OS. In at least one embodiment, the client computing device may further include electronic devices such as thin client computers, internet-enabled gaming systems (e.g., a Microsoft Xbox game console with or without Kinect® gesture input devices), and / or personal messaging devices capable of communicating via network 710. Although Figure 7 The distributed system 700 in the diagram shows four client computing devices, but in practice, it can support any number of client computing devices. Other devices, such as those with sensors, can interact with the server 712.

[0047] In at least one embodiment, network 710 in distributed system 700 can be any type of network, as long as the network can support data communication using various available protocols, including but not limited to TCP / IP (Transmission Control Protocol / Internet Protocol), SNA (System Network Architecture), IPX (Internet Packet Switching), AppleTalk, and / or variations thereof. In at least one embodiment, network 710 can be a local area network (LAN), an Ethernet-based network, a token ring network, a wide area network, the Internet, a virtual network, a virtual private network (VPN), an intranet, an extranet, a public switched telephone network (PSTN), an infrared network, a wireless network (e.g., a network operating under the Institute of Electrical and Electronics Engineers (IEEE) 802.11 protocol suite, Bluetooth®, and / or any other wireless protocol), and / or any combination of these and / or other networks.

[0048] In at least one embodiment, server 712 may consist of one or more general-purpose computers, special-purpose servers (including, by way of illustration, PC (personal computer) servers, UNIX® servers, mid-range servers, mainframe computers, rack servers, etc.), server groups, server clusters, or any other suitable arrangement and / or combination. In at least one embodiment, server 712 may include one or more virtual machines running a virtual operating system, or other computing architectures involving virtualization. In at least one embodiment, one or more flexible pools of logical storage devices may be virtualized to maintain the server's virtual storage devices. In at least one embodiment, server 712 may use software-defined networking to control the virtual network. In at least one embodiment, server 712 may be adapted to run one or more services or software applications.

[0049] In at least one embodiment, server 712 can run any operating system, as well as any commercially available server operating system. In at least one embodiment, server 712 can also run any of a variety of other server applications and / or middleware applications, including HTTP (Hypertext Transfer Protocol) servers, FTP (File Transfer Protocol) servers, CGI (Common Gateway Interface) servers, JAVA® servers, database servers, and / or variations thereof. In at least one embodiment, exemplary database servers include, but are not limited to, commercial database servers and / or variations thereof provided by companies such as Oracle, Microsoft, Sybase, and IBM (International Business Machines Corporation).

[0050] In at least one embodiment, server 712 may include one or more applications for analyzing and integrating data feeds and / or event updates received from users of client computing devices 702, 704, 706, and 708. In at least one embodiment, data feeds and / or event updates may include, but are not limited to, Twitter® feeds, Facebook® updates, or real-time updates received from one or more third-party information sources, as well as continuous data streams that may include real-time events related to sensor data applications, financial market data, network performance measurement tools (e.g., network monitoring and traffic management applications), clickstream analysis tools, vehicle traffic monitoring, and / or variations thereof. In at least one embodiment, server 712 may also include one or more applications for displaying data feeds and / or real-time events via one or more display devices of client computing devices 702, 704, 706, and 708.

[0051] In at least one embodiment, the distributed system 700 may further include one or more databases 714 and 716. In at least one embodiment, the databases may provide a mechanism for storing information such as user interaction information, usage pattern information, adaptation rule information, and other information. In at least one embodiment, databases 714 and 716 may be located in different locations. In at least one embodiment, one or more of databases 714 and 716 may reside on a non-transitory storage medium local to server 712 (and / or within server 712). In at least one embodiment, databases 714 and 716 may be located remotely to server 712 and communicate with server 712 via a network-based connection or a dedicated connection. In at least one embodiment, databases 714 and 716 may reside in a storage area network (SAN). In at least one embodiment, any necessary files required for performing the functions of server 712 may be stored locally and / or remotely on server 712 as needed. In at least one embodiment, databases 714 and 716 may include relational databases, such as databases capable of storing, updating, and retrieving data in response to SQL-formatted commands.

[0052] Figure 8 An exemplary data center 800 according to at least some embodiments is shown. In at least one embodiment, the data center 800 includes, but is not limited to, a data center infrastructure layer 810, a framework layer 820, a software layer 830, and an application layer 840.

[0053] like Figure 8As shown, in at least one embodiment, the data center infrastructure layer 810 may include a resource orchestrator 812, packet computing resources 814, and node computing resources (“nodes CR”) 816(1)-816(N), where “N” represents any positive integer. In at least one embodiment, the nodes CR 816(1)-816(N) may include, but are not limited to, any number of central processing units (“CPUs”) or other processors (including accelerators, field-programmable gate arrays (“FPGAs”), graphics processors, etc.), memory devices (e.g., dynamic read-only memory), storage devices (e.g., solid-state drives or disk drives), network input / output (“NW I / O”) devices, network switches, virtual machines (“VMs”), power modules, and cooling modules, etc. In at least one embodiment, one or more of the nodes CR 816(1)-816(N) may be servers having one or more of the aforementioned computing resources.

[0054] In at least one embodiment, the packet computing resource 814 may include multiple node CR packets housed within one or more racks (not shown), or multiple racks housed within data centers (not shown) in different geographical locations. Individual node CR packets within the packet computing resource 814 may include packet computing, networking, memory, or storage resources that can be configured or allocated to support one or more workloads. In at least one embodiment, several node CRs, including CPUs or processors, may be grouped within one or more racks to provide computing resources to support one or more workloads. In at least one embodiment, the one or more racks may also include any number of power modules, cooling modules, and network switches, in any combination thereof.

[0055] In at least one embodiment, resource orchestrator 812 may be configured or otherwise control one or more nodes CR 816(1)-816(N) and / or grouped computing resources 814. In at least one embodiment, resource orchestrator 812 may include a software design infrastructure (“SDI”) management entity for data center 800. In at least one embodiment, resource orchestrator 812 may include hardware, software, or some combination thereof.

[0056] In at least one embodiment, such as Figure 8As shown, the framework layer 820 includes, but is not limited to, a job scheduler 832, a configuration manager 834, a resource manager 836, and a distributed file system 838. In at least one embodiment, the framework layer 820 may include a framework of software 852 supporting the software layer 830 and / or one or more applications 842 of the application layer 840. In at least one embodiment, the software 852 or application 842 may respectively include web-based service software or applications, such as services or applications provided by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, the framework layer 820 may be, but is not limited to, a free and open-source software web application framework, such as Apache Spark™ (hereinafter referred to as "Spark"), which can utilize the distributed file system 838 for large-scale data processing (e.g., "big data"). In at least one embodiment, the job scheduler 832 may include a Spark driver to facilitate the scheduling of workloads supported by the various layers of the data center 800. In at least one embodiment, the configuration manager 834 may be able to configure different layers, such as the software layer 830 and the framework layer 820, including Spark and the distributed file system 838, to support large-scale data processing. In at least one embodiment, resource manager 836 may be able to manage cluster or group computing resources mapped to or allocated to support distributed file system 838 and job scheduler 832. In at least one embodiment, cluster or group computing resources may include group computing resources 814 at data center infrastructure layer 810. In at least one embodiment, resource manager 836 may coordinate with resource orchestrator 812 to manage these mapped or allocated computing resources.

[0057] In at least one embodiment, the software 852 included in the software layer 830 may include the software used by at least a portion of the nodes CR 816(1)-816(N) of the framework layer 820, the grouped computing resources 814, and / or the distributed file system 838. One or more types of software may include, but are not limited to, internet web search software, email virus scanning software, database software, and streaming video content software.

[0058] In at least one embodiment, the application 842 included in the application layer 840 may include one or more types of applications that are at least partially available to the nodes CR 816(1)-816(N) of the framework layer 820, the group computing resources 814, and / or the distributed file system 838. In at least one embodiment, these application types may include, but are not limited to, CUDA applications, 5G network applications, artificial intelligence applications, data center applications, and / or variations thereof.

[0059] In at least one embodiment, any of the configuration manager 834, resource manager 836, and resource orchestrator 812 can implement any number and type of self-modification operations based on any amount and type of data obtained in any technically feasible manner. In at least one embodiment, the self-modification operations can enable the data center operator of data center 800 to avoid making potentially erroneous configuration decisions and may avoid using underutilized and / or poorly performing portions of the data center.

[0060] Figure 9 A computer system 900 according to at least one embodiment is illustrated. In at least one embodiment, the computer system 900 is configured to implement the various processes and methods described throughout this disclosure.

[0061] In at least one embodiment, the computer system 900 includes, but is not limited to, at least one central processing unit (“CPU”) 902 connected to a communication bus 910 implemented using any suitable protocol, such as PCI (“Peripheral Component Interconnect”), PCI-Express (“PCI-Express”), AGP (“Accelerated Graphics Port”), HyperTransport, or any other bus or one or more point-to-point communication protocols. In at least one embodiment, the computer system 900 includes, but is not limited to, main memory 904 and control logic (e.g., implemented in hardware, software, or a combination thereof), and data is stored in main memory 904, which may be in the form of random access memory (“RAM”). In at least one embodiment, a network interface subsystem (“network interface”) 922 provides an interface to other computing devices and networks for receiving data from the computer system 900 and transferring data to other systems.

[0062] In at least one embodiment, the computer system 900 includes, but is not limited to, an input device 908, a parallel processing system 912, and a display device 906, which may be implemented using conventional cathode ray tube (“CRT”), liquid crystal display (“LCD”), light-emitting diode (“LED”), plasma display, or other suitable display technologies. In at least one embodiment, user input is received from the input device 908, such as a keyboard, mouse, touchpad, microphone, etc. In at least one embodiment, each of the foregoing modules may reside on a single semiconductor platform to form the processing system.

[0063] In at least one embodiment, a computer program in the form of machine-readable executable code or computer control logic algorithms is stored in main memory 904 and / or secondary memory. If executed by one or more processors, the computer program enables system 900 to perform various functions according to at least one embodiment. Memory 904, storage devices, and / or any other storage devices are possible examples of computer-readable media. In at least one embodiment, secondary storage devices can refer to any suitable storage device or system, such as hard disk drives and / or removable storage drives, representing floppy disk drives, magnetic tape drives, optical disk drives, digital versatile disc (“DVD”) drives, recording devices, Universal Serial Bus (“USB”) flash memory, etc. In at least one embodiment, the architecture and / or functionality of the various preceding figures are implemented in the context of: CPU 902; parallel processing system 912; integrated circuits having at least a portion of the capabilities of two CPUs 902; chipsets (e.g., groups of integrated circuits designed to operate and be marketed as units for performing related functions); and any suitable combination of one or more integrated circuits.

[0064] In at least one embodiment, the architecture and / or functionality of the various preceding figures are implemented within the context of general-purpose computer systems, circuit board systems, game console systems dedicated to entertainment purposes, special-purpose systems, etc. In at least one embodiment, computer system 900 may take the form of a desktop computer, laptop computer, tablet computer, server, supercomputer, smartphone (e.g., wireless handheld device), personal digital assistant (“PDA”), digital camera, vehicle, head-mounted display, handheld electronic device, mobile phone device, television, workstation, game console, embedded system, and / or any other type of logic.

[0065] In at least one embodiment, the parallel processing system 912 includes, but is not limited to, multiple parallel processing units (“PPUs”) 914 and associated memory 916. In at least one embodiment, the PPUs 914 are connected to a host processor or other peripheral devices via interconnects 918 and switches 920 or multiplexers. In at least one embodiment, the parallel processing system 912 distributes computational tasks across the parallelizable PPUs 914—for example, as part of distributing computational tasks across multiple graphics processing units (“GPUs”) thread blocks. In at least one embodiment, although such shared memory may incur a performance penalty compared to using memory and registers residing locally on the PPUs 914, memory can be shared and accessed (e.g., for read and / or write access) across some or all of the PPUs 914. In at least one embodiment, the operation of the PPUs 914 is synchronized using commands such as _syncthreads(), where all threads in a block (e.g., threads executing across multiple PPUs 914) must reach a certain point in code execution before continuing execution.

[0066] Figure 10 This is a schematic block diagram of a computing system 1000 (e.g., a data center or high-performance computing (HPC) cluster) according to embodiments described herein. According to at least one embodiment, system 1000 includes multiple subsystems, such as multiple processing devices, multiple network devices, and multiple networks coupled to each other. The computing system 1000 is designed with multiple integrated circuits (referred to as processing devices), each of which may include one or more CPUs and GPUs, thereby forming a powerful and flexible architecture.

[0067] Various processing devices are interconnected via NVLink or other high-speed interconnects to enable high-speed communication between subsystems; and are also connected via NICs or DPUs to ensure efficient data transfer across computing system 1000 and one or more external networks 1030, 1036. In this example, system 1000 includes a packet switch 1048 that connects NIC / DPU 1028 to network 1030 and a packet switch 1050 that connects NIC / DPU 1032 to network 1036.

[0068] Seamless data exchange and parallel processing are enabled through NVLink-coupled processing devices, thereby improving overall computing performance. The processing devices connect to multiple networks via one or more Network Interface Controllers (NICs) or Data Processing Units (DPUs), allowing the system to handle complex multi-network tasks with high bandwidth and low latency. This configuration is ideal for demanding applications requiring significant processing power, such as artificial intelligence (AI), machine learning (ML), and data-intensive computing, while ensuring robust connectivity and scalability across diverse networking environments. The integrated circuits of the Computing System 1000 may include one or more CPUs and one or more GPUs.

[0069] Figure 10 An example architecture of a multi-GPU architecture is also demonstrated. As illustrated, the computing system 1000 includes a processing device 1002 with a multi-GPU architecture. Specifically, the processing device 1002 may be a system-on-a-chip and includes multiple subsystems such as a CPU 1006, a GPU 1008, and a GPU 1010. The CPU 1006 may be coupled to the GPU 1008 via die-to-die (D2D) or chip-to-chip (C2C) interconnects 1012 (such as a ground reference signaling interconnect (GRS interconnect)). The CPU 1006 may be coupled to the GPU 1010 via a D2D or C2C interconnect 1014. The CPU 1006 may also be coupled to the GPU 1008 and GPU 1010 via a PCIe interconnect.

[0070] The CPU 1006 can be coupled to one or more NICs or DPUs, which in turn are coupled to one or more networks. For example, as Figure 10 As illustrated, CPU 1006 is coupled to a first NIC / DPU 1026, which is coupled to network 1030. CPU 1006 is also coupled to a second NIC / DPU 1028, which is coupled to network 1030 via switch 1048. For example, NIC / DPU 1026 and NIC / DPU 1028 can be coupled to network 1030 via Ethernet (ETH), NVLINK, or InfiniBand (IB) connections.

[0071] The computing system 1000 also includes a processing device 1004 with a multi-GPU architecture. Specifically, the processing device 1004 includes multiple subsystems, including a CPU 1016, a GPU 1018, and a GPU 1020. The CPU 1016 can be coupled to the GPU 1018 via a D2D or C2C interconnect 1022. The CPU 1016 can be coupled to the GPU 1020 via a D2D or C2C interconnect 1024. The CPU 1016 can also be coupled to the GPU 1018 and GPU 1020 via a PCIe interconnect. The CPU 1016 can be coupled to one or more NICs or DPUs, which in turn are coupled to one or more networks. For example, as... Figure 10 As illustrated, CPU 1016 is coupled to a first NIC / DPU 1032, which is coupled to network 1036. CPU 1016 is also coupled to a second NIC / DPU 1034, which is coupled to network 1036 via switch 1050. NIC / DPU 1032 and NIC / DPU 1034 can be coupled to network 1036 via Ethernet (ETH), NVLINK, or InfiniBand (IB) connections.

[0072] In at least one embodiment, processing device 1002 and processing device 1004 can communicate with each other via NIC / DPU 1038 (such as via PCIe interconnect). Processing device 1002 and processing device 1004 can also communicate with each other via high-bandwidth communication interconnect 1040 (such as NVLink interconnect or other high-speed interconnect). Figure 10 The packet switches in the diagram can include, for example, Nvidia Quantum-2 switches. The NIC / DPU in the diagram can include, for example, Nvidia Bluefield DPUs.

[0073] In some embodiments, any network device of system 1000 (e.g., any of NIC / DPU 1026, 1028, 1032, 1034, and 1038, and / or any of switches 1048 and 1050, etc.) can communicate via a copper-based connection using the interconnect devices described herein. For example, any network device can use the interconnect devices to send and / or receive electrical signals via a copper-based connection, which can amplify and / or amplify the received signals to overcome losses in the copper-based connection.

[0074] Figure 11 An example computing environment 1100 according to at least one embodiment is illustrated. Figure 11An example computing environment 1100 is illustrated, in which forward pass-off to available memory can be performed. It should be understood that embodiments of this disclosure can also be used in alternative environments, and specific discussions of components are provided by way of non-limiting examples and may include equivalents. Furthermore, various features are omitted for clarity and brevity. Additionally, the systems and methods can be used with a variety of different architectures. Example computing environment 1100 may include server 1102, which can be used to perform HPC workloads such as AI training or machine learning model training. In one embodiment, server 1102 may be an application instance or a compute node. Server 1102 may include CPU 1110 associated with a switch 1120, such as a Peripheral Component Interconnect Fast (PCIe) switch, which can control at least some data transfers via communication paths interconnecting various components. In one embodiment, CPU 1110 may include a root complex processor.

[0075] PCIe switch 1120 may also be associated with GPU 1130 and DPU 1140, and may transfer data between at least some of CPU 1110, GPU 1130, DPU 1140, and other components. In one embodiment, PCIe switch 1120 may be associated with more than one GPU or more than one DPU. In another embodiment, PCIe switch 1120 may be located within DPU 1140. PCIe switch 1120 may manage the transfer of at least some of the data between CPU 1110, GPU 1130, and DPU 1140. In another embodiment, the number of GPUs associated with PCIe switch 1120 may be equal to the number of DPUs associated with PCIe switch 1120. In at least one embodiment, server 1102 may include, but is not limited to, any number of CPUs 1110, PCIe switch 1120, GPUs 1130, and / or DPUs 1140 in any combination. For example, in at least one embodiment, server 1102 may include eight, sixteen, thirty-two, and / or more GPUs 1130. In at least one embodiment, various components (including but not limited to) are interconnected. Figure 11 The communication paths of the CPU 1110, PCIe switch 1120, GPU 1130 and DPU 1140 can be implemented using any suitable protocol, such as peripheral component interconnect (PCI) based protocols (e.g., PCIe) or other bus or point-to-point communication interfaces and / or one or more protocols (e.g., NV-Link high-speed interconnect or interconnect protocols)).

[0076] DPU 1140 may include a network interface controller (NIC) 1142, DDR memory 1144, and a non-volatile memory fast (NVMe) device 1146. NIC 1142 is capable of interfaced with network 1104, which may also interface (e.g., via fabric) with additional NVMe devices available to DPU 1140. In one embodiment, DPU 1140 may not include NVMe device 1146. In another embodiment, NVMe device 1146 may reside on server 1102 instead of DPU 1140. In yet another embodiment, computing environment 1100 may include more than one NVMe device 1146, such as a first NVMe device in DPU 1140 and a second first NVMe device on server 1102 directly associated with PCIe switch 1120. In one embodiment, DPU 1140 may not include DDR memory 1144 and may include compute storage service (CSS) in place of DDR memory 1144, or may include compute storage service (CSS) in addition to DDR memory 1144. For example, computing environment 1100 may include DPU compute storage (CS) memory 1106 available to DPU 1140 as part of the CSS. Network 1104 is capable of interfaced with DPU CS memory 1106 via NIC 1142 according to any suitable interface protocol, such as Remote Direct Memory Access (RDMA) via Ethernet, InfiniBand, Fibre Channel, etc.

[0077] The total memory available for data storage in the computing environment 1100 can be expanded by using DPU 1140 on system nodes. DPU 1140 can access memory pools 1150 already available on server 1102, such as dual data rate (DDR) memory, onboard NVMe devices, architecture-based NVMe devices, and CS. Memory pool 1150 may include at least one of DDR memory 1144, NVMe devices 1146, and DPU CS memory 1106. DPU 1140 is also able to access available memory of other DPUs that are part of pool 1150, and other DPUs can access available memory of DPU 1140, such as pool 1150. This available memory can be accessed and used for data storage without adding computing resources (such as compute nodes), which would be required with other solutions. Server 1102 can be supplied with an available pool 1150 accessible to DPU 1140 to expand the total memory available for data storage, such as reducing the data storage load on CPU 1110 or GPU 1130, which can actually increase the utilization of the memory they use for processing. For example, during AI training, model states, residual states, activation functions, and checkpoints can be stored or offloaded to pool 1150 accessible to DPU 1140.

[0078] Figure 12A and 12B Top and perspective views are illustrated respectively of a transceiver module operatively coupled to a network adapter (in this example, a network interface controller (NIC) 1200) according to an embodiment of the present disclosure. Figure 12A and Figure 12B As shown, the transceiver module may include a first optical module 1201, a second optical module 1203, an adapter 1210, and a dual-port NIC 1220 for the server. Both the first optical module 1201 and the second optical module 1203 may be dual-fiber transceivers configured for full-duplex communication, allowing communication between a source (e.g., a server) and a target (e.g., a leaf switch) in both directions. The adapter 1210 may be a linked physical component configured to link the first optical module 1201 and the second optical module 1203 for the purpose of sending data to and receiving data from the leaf switch.

[0079] In some embodiments, adapter 1210 can be configured to operate in two configurations, such as a first configuration and a second configuration. In one aspect, the first configuration can be a default operating configuration, wherein the first optical module 1201 can be operationally active. The second configuration can be an emergency configuration implemented when the first optical module 1201 experiences an operational failure. When such a failure is detected, the second optical module 1203, which was originally operationally inactive or idle, can become operationally active and handle all network traffic initially handled by the first optical module 1201.

[0080] In some embodiments, transceiver module 1200 can be configured to operate in a leaf-spine architecture. A leaf-spine architecture is a data center network topology that may include two switching layers (spine and leaf). The leaf layer may include access switches (leaf switches) that aggregate traffic from servers and are directly connected to the backbone or network core. Spine switches interconnect all leaf switches in a full mesh topology, and access switches are located in the leaf layer and aggregate traffic from servers. Thus, in one embodiment, to ensure reliable downlink operation, transceiver module 1200 can be configured to operate between the server and the leaf layer. Specifically, as... Figure 12A and Figure 12B As shown, adapter 1210 can be operatively coupled to first optical module 1201 and second optical module 1203, and first optical module 1201 and second optical module 1203 can be operatively coupled to dual-port NIC 1220 of the server.

[0081] In various embodiments, the NIC 1200 may include one or more processing circuits as detailed above; the processing circuits may include a firmware loaded according to the techniques described above.

[0082] Figure 13 Exemplary use cases of transceiver 1302 (e.g., optical transceiver) according to some embodiments are depicted. To name just a few examples, transceiver 1302 can be used in computing system 1304 (e.g., in a server farm or within a server computer system), vehicle 1306 (e.g., a car, truck, train, or airplane), and (or in a robot in a factory) robot 1308. Transceiver 1302 is particularly useful for high-speed communication in environments subject to high levels of electromagnetic interference (EMI).

[0083] Other variations are within the spirit of this disclosure. Therefore, while the disclosed technology is susceptible to various modifications and alternative constructions, certain illustrated embodiments are shown in the accompanying drawings and have been described in detail above. However, it should be understood that this disclosure is not intended to be limited to the one or more specific forms disclosed, but rather is intended to cover all modifications, alternative constructions, and equivalents falling within the spirit and scope of this disclosure as defined in the appended claims.

[0084] Unless otherwise stated herein or obviously contradicted by the context, the use of the terms “a,” “an,” “the,” and similar pronouns in the context of describing the disclosed embodiments (particularly in the context of the appended claims) should be interpreted as encompassing both singular and plural forms, rather than as definitions of the terms. Unless otherwise indicated, the terms “comprising,” “having,” “including,” and “containing” should be interpreted as open-ended terms (meaning “including, but not limited to”). When unmodified and referring to a physical connection, “connection” should be interpreted as partially or completely contained in, attached to, or combined with, even with intervening elements. Unless otherwise indicated herein, statements of value ranges herein are intended only as a way of referring to each individual value falling within that range separately, and each individual value is incorporated into the specification as if it were individually stated herein. In at least one embodiment, unless otherwise specified or contradicted by the context, the use of the terms “set” (e.g., “item set”) or “subset” should be interpreted as a non-empty set comprising one or more members. Furthermore, unless otherwise specified or contradicted by the context, the term "subset" of the corresponding set does not necessarily refer to an appropriate subset of the corresponding set, but rather the subset and the corresponding set can be equal.

[0085] Unless explicitly stated otherwise or otherwise clearly contradicted by the context, connectives (such as phrases of the form "at least one of A, B, and C" or "at least one of A, B, and C") are otherwise understood, in conjunction with the context, to generally refer to items, terms, etc., and can be any non-empty subset of the set A or B or C, or A and B and C. For example, in an illustrative example of a set with three members, the connective phrases "at least one of A, B, and C" and "at least one of A, B, and C" refer to any of the following sets: {A}, {B}, {C}, {A, B}, {A, C}, {B, C}, {A, B, C}. Thus, such connectives are generally not intended to imply that certain embodiments require the separate presence of at least one of A, at least one of B, and at least one of C. Additionally, unless explicitly stated or contradicted by the context, the term "multiple" indicates a plural state (e.g., "multiple items" indicates multiple items). In at least one embodiment, the number of items in the multiple is at least two, but may be more if explicitly indicated or indicated by the context. Furthermore, unless otherwise stated or clearly understood from the context, the phrase “based on” means “at least partially based on” rather than “based on only”.

[0086] Unless otherwise indicated herein or otherwise clearly contradicted by the context, the operations of the processes described herein may be performed in any suitable order. In at least one embodiment, processes such as those described herein (or variations and / or combinations thereof) are executed under the control of one or more computer systems configured with executable instructions and are implemented by hardware or a combination thereof as code (e.g., executable instructions, one or more computer programs, or one or more applications) that executes jointly on one or more processors. In at least one embodiment, the code is stored on a computer-readable storage medium, for example, in the form of a computer program comprising a plurality of instructions executable by one or more processors. In at least one embodiment, the computer-readable storage medium is a non-transitory computer-readable storage medium that does not include transient signals (e.g., propagation of transient electrical or electromagnetic transmissions) but includes non-transitory data storage circuitry (e.g., buffers, caches, and queues) within a transceiver that includes transient signals. In at least one embodiment, code (e.g., executable code or source code) is stored in a set of one or more non-transitory computer-readable storage media having executable instructions (or other memory for storing executable instructions) stored thereon. These executable instructions, when executed by one or more processors of a computer system (i.e., as a result of execution), cause the computer system to perform the operations described herein. In at least one embodiment, the set of non-transitory computer-readable storage media comprises multiple non-transitory computer-readable storage media, and one or more individual non-transitory storage media lack the complete code; instead, the multiple non-transitory computer-readable storage media collectively store the complete code. In at least one embodiment, the executable instructions are executed such that different instructions are executed by different processors.

[0087] Therefore, in at least one embodiment, the computer system is configured to implement one or more services that perform the operations of the processes described herein, either individually or collectively, and such a computer system is configured with suitable hardware and / or software to enable the performance of the operations. Furthermore, the computer system implementing at least one embodiment of this disclosure is a single device, while in another embodiment it is a distributed computer system comprising multiple devices operating in different ways, such that the distributed computer system performs the operations described herein, and that a single device does not perform all the operations.

[0088] Unless otherwise required, the use of any and all examples or exemplary language (e.g., “such as”) provided herein is intended only to better illustrate embodiments of this disclosure and is not intended to limit the scope of this disclosure. The language in the specification should not be construed as indicating that any unclaimed element is essential to the practice of this disclosure.

[0089] In the specification and claims, the terms “coupled” and “connected” along with their derivatives may be used. It should be understood that these terms are not intended to be synonyms for each other. Rather, in specific examples, “connected” or “coupled” can be used to indicate that two or more elements are in direct or indirect physical or electrical contact with each other. “Coupled” can also mean that two or more elements are not in direct contact with each other, but still cooperate or interact with each other.

[0090] Unless otherwise specifically stated, it should be understood that throughout this specification, terms such as “processing,” “calculating,” “operating,” “determining,” etc., refer to the actions and / or processes of a computer or computing system or similar electronic computing device that manipulate and / or transform data representing physical (such as electronic) quantities within the registers and / or memory of the computing system into other data representing physical quantities within the memory, registers, or other such information storage, transmission, or display devices of the computing system.

[0091] Similarly, the term "processor" can refer to any device or part of a device that processes electronic data from registers and / or memory and transforms that electronic data into other electronic data that can be stored in registers and / or memory. A "computing platform" can include one or more processors. As used herein, a "software" process can include, for example, software and / or hardware entities that perform work over time, such as tasks, threads, and intelligent agents. Furthermore, each process can refer to multiple processes for executing instructions sequentially or in parallel, continuously or intermittently. In at least one embodiment, the terms "system" and "method" are used interchangeably herein, provided that the system can embody one or more methods, and the method can be considered a system.

[0092] In this document, reference may be made to obtaining, acquiring, receiving, or inputting analog or digital data into a subsystem, computer system, or computer implementation machine. In at least one embodiment, the process of obtaining, acquiring, receiving, or inputting analog and digital data can be accomplished in various ways, such as by receiving data as a parameter of a function call or a call to an application programming interface. In at least one embodiment, the process of obtaining, acquiring, receiving, or inputting analog or digital data can be accomplished by transmitting data via a serial or parallel interface. In at least one embodiment, the process of obtaining, acquiring, receiving, or inputting analog or digital data can be accomplished by transmitting data from a providing entity to an acquiring entity via a computer network. In at least one embodiment, reference may also be made to providing, outputting, transmitting, sending, or presenting analog or digital data. In various examples, the process of providing, outputting, transmitting, sending, or presenting analog or digital data can be implemented by transmitting data as an input or output parameter of a function call, an application programming interface, or an inter-process communication mechanism.

[0093] While the description herein illustrates exemplary embodiments of the technology, other architectures may also be used to implement the described functionality and are intended to fall within the scope of this disclosure. Furthermore, although a specific allocation of responsibilities has been defined above for descriptive purposes, various functions and responsibilities may be allocated and divided differently depending on the circumstances.

[0094] Furthermore, although the subject matter has been described in language specific to structural features and / or methodological actions, it is to be understood that the subject matter claimed in the appended claims is not necessarily limited to the specific features or actions described. Rather, the specific features and actions are disclosed as exemplary forms for implementing the claims.

Claims

1. A system comprising: A first circuit board, which includes one or more first computing circuits; as well as Interconnect devices coupled to the one or more first computing circuits, wherein the interconnect devices include: The linear redrive is configured as follows: Receive a first electrical input signal from at least one of the one or more first computing circuits; Amplify the first electrical input signal to form an enhanced electrical signal; and The enhanced electrical signal is output, wherein the interconnecting device is configured to provide the enhanced electrical signal to one or more second computing circuits on a second circuit board via one or more wired connections, and wherein the enhancement of the first electrical input signal compensates for known losses associated with the one or more wired connections.

2. The system of claim 1, further comprising: An optical transceiver coupled to one or more first computing circuits, wherein the optical transceiver is configured to: Receive a second electrical input signal from at least one of the one or more first computing circuits; Generate an optical signal that indicates the second electrical input signal; as well as The optical signal is provided to at least one of the one or more second computing circuits on the second circuit board or one or more third computing circuits on the third circuit board.

3. The system as described in claim 1, wherein, The linear re-drive is integrated at the cable end of the interconnect device, which is coupled to the one or more first computing circuits through a port on the first circuit board.

4. The system as claimed in claim 1, wherein, The linear re-drive is integrated in a module coupled to the first circuit board.

5. The system as described in claim 4, wherein, The module is located in the middle of the first circuit board.

6. The system as claimed in claim 1, wherein, The interconnecting device is configured to provide the enhanced electrical signal to the one or more second computing circuits via copper-based interconnecting cables.

7. The system as claimed in claim 1, wherein, The one or more computing circuits include multiple switches configured to guide electrical signals.

8. The system of claim 1, wherein, The enhanced electrical signal attenuates during transmission to the one or more second computing circuits, and the attenuated electrical signal received by the one or more second computing circuits corresponds to the first electrical input signal.

9. The system of claim 1, wherein, The interconnect devices are configured to operate at a rate between approximately 100 gigabytes per second per channel and approximately 200 gigabytes per second per channel.

10. The system of claim 1, wherein, The first electrical input signal constitutes at least a portion of the differential pair signal.

11. The system of claim 1, wherein, The interconnecting device further includes: At least one connection is configured to receive electrical signals from the one or more second computing circuits.

12. The system of claim 1, wherein, The system includes a flexible design configured to output one or more enhanced electrical signals using a combination of at least one of a pluggable transceiver or an onboard active copper cable MBAC solution.

13. An interconnect device, comprising: The linear redrive is configured as follows: Receive a first electrical input signal from at least one first computing circuit; Amplify the first electrical input signal to form an enhanced electrical signal; as well as The enhanced electrical signal is output, wherein the interconnecting device is configured to provide the enhanced electrical signal to one or more second computing circuits via one or more wired connections, and wherein the enhancement of the first electrical input signal compensates for known losses associated with the one or more wired connections.

14. The interconnect device of claim 13, further comprising: The cable end is configured to be coupled to the at least one first computing circuit via a port on a circuit board associated with the at least one first computing circuit.

15. The interconnect device of claim 13, wherein, The interconnecting device is configured to provide the enhanced electrical signal to the one or more second computing circuits via copper-based interconnecting cables.

16. The interconnect device of claim 13, wherein, The enhanced electrical signal attenuates during transmission to the one or more second computing circuits, and the attenuated electrical signal received by the one or more second computing circuits corresponds to the first electrical input signal.

17. The interconnect device of claim 13, wherein, The interconnect devices are configured to operate at a rate between approximately 100 gigabytes per second per channel and approximately 200 gigabytes per second per channel.

18. The interconnect device of claim 13, wherein, The first electrical input signal constitutes at least a portion of the differential pair signal.

19. The interconnect device of claim 13, further comprising: At least one connection, the at least one connection being configured to receive electrical signals from the one or more second computing circuits.

20. A data center, comprising: A first circuit board, the first circuit board including one or more first computing circuits; The second circuit board includes one or more second computing circuits; as well as Interconnect devices, the interconnect devices being coupled between the one or more first computing circuits and the one or more second computing circuits; The interconnecting device includes: The linear redrive is configured as follows: Receive a first electrical input signal from at least one of the one or more first computing circuits; Amplify the first electrical input signal to form an enhanced electrical signal; and The enhanced electrical signal is output, wherein the interconnecting device is configured to provide the enhanced electrical signal to the one or more second computing circuits via one or more wired connections, and wherein the enhancement of the first electrical input signal compensates for known losses associated with the one or more wired connections.

21. The data center of claim 20, further comprising: An optical transceiver coupled to one or more first computing circuits, wherein the optical transceiver is configured to: Receive a second electrical input signal from at least one of the one or more first computing circuits; Generate an optical signal that indicates the second electrical input signal; as well as The optical signal is provided to at least one of the one or more second computing circuits on the second circuit board or one or more third computing circuits on the third circuit board.

22. The data center of claim 20, wherein, The linear re-drive is integrated into one of the following components: The cable end of the interconnecting device is coupled to the one or more first computing circuits via a port on the first circuit board; or An active module coupled to the first circuit board.

23. The data center of claim 20, wherein, The one or more wired connections include copper-based interconnect cables.

24. The data center of claim 20, wherein, The enhanced electrical signal attenuates during transmission to the one or more second computing circuits, and the attenuated electrical signal received by the one or more second computing circuits corresponds to the first electrical input signal.

25. The data center of claim 20, wherein, The interconnect devices are configured to operate at a rate between approximately 100 gigabytes per second per channel and approximately 200 gigabytes per second per channel.

26. The data center of claim 20, wherein, The first electrical input signal constitutes at least a portion of the differential pair signal.

27. The data center of claim 20, wherein, The interconnecting device further includes: At least one connection, the at least one connection being configured to receive electrical signals from the one or more second computing circuits.

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