Signal transmission device and gate drive device

Abstract

A signal transmission device and a gate drive device. In the signal transmission device, an AC coupling section transmits a signal received from a primary side circuit. A secondary side circuit receives the signal transmitted by the AC coupling section. A detection section outputs a detection signal related to a noise level at the time of transmission of the transmitted signal, based on a variation in a terminal voltage formed based on a current flowing through a terminal of at least one of a first reference potential terminal of the primary side circuit insulated by the AC coupling section and a second reference potential terminal of the secondary side circuit. In the detection section, a first discriminator compares the terminal voltage with a predetermined potential on the positive side. A second discriminator compares the terminal voltage with a predetermined potential on the negative side. A first encoding section performs encoding of information related to a slew rate of the terminal voltage, based on a comparison result of the first discriminator. A second encoding section performs encoding of information related to the slew rate of the terminal voltage, based on a comparison result of the second discriminator.

Description

[0001] Related applications

[0002] This application enjoys priority based on Japanese Patent Application No. 2025-047049 (filed on March 21, 2025). This application incorporates the entire contents of the basic application by reference to that basic application. Technical Field

[0003] Embodiments of the present invention relate to a signal transmission device and a gate driving device. Background Technology

[0004] Signal transmission devices that use isolators to transmit signals between insulated areas are known. However, due to noise between the insulation grounding points, errors may occur during transmission between insulated areas. Summary of the Invention

[0005] Embodiments of the present invention provide a signal transmission device and a gate driving device capable of detecting information related to the noise level during transmission of a signal between insulators.

[0006] The signal transmission device of this embodiment includes a primary side circuit, an AC coupling unit, a secondary side circuit, and a detection unit. The AC coupling unit transmits a signal received from the primary side circuit. The secondary side circuit receives the signal transmitted by the AC coupling unit. The detection unit outputs a detection signal related to the noise level during signal transmission based on the variation of the terminal voltage formed by the current flowing on at least one of the terminals of the primary side circuit (insulated from the AC coupling unit) and the secondary side circuit (insulated from the AC coupling unit). The detection unit includes one or more first identifiers, one or more second identifiers, a first encoding unit, and a second encoding unit. The first identifier compares the terminal voltage with a predetermined potential on the positive side. The second identifier compares the terminal voltage with a predetermined potential on the negative side. Based on the comparison result of the first identifier, the first encoding unit encodes information related to the slew rate of the terminal voltage. Based on the comparison result of the second identifier, the second encoding unit encodes information related to the slew rate of the terminal voltage.

[0007] The gate driving device of the embodiment includes: a primary-side circuit for modulating and transmitting a gate signal; an AC coupling unit for transmitting a signal received from the primary-side circuit; a secondary-side circuit for demodulating the gate signal transmitted by the AC coupling unit and supplying it to the gate of a switching element; and a detection unit for outputting a detection signal related to the noise level during transmission of the transmitted signal based on a change in terminal voltage formed by a current flowing at at least one of a first reference potential terminal of the primary-side circuit and a second reference potential terminal of the secondary-side circuit, which are insulated from the AC coupling unit, and the secondary-side circuit controlling the slew rate of the gate signal based on the detection signal. Attached Figure Description

[0008] Figure 1 This is a block diagram illustrating the signal transmission device of this embodiment.

[0009] Figure 2 It means Figure 1 The diagram shows an example of the equivalent circuit of the AC coupling section.

[0010] Figure 3 This is a diagram showing another equivalent circuit example of the AC coupling section.

[0011] Figure 4 This is a diagram showing an example of the equivalent circuit of the signal transmission unit.

[0012] Figure 5 This is a graph representing the voltage and voltage amplitude of CMT noise between grounding points.

[0013] Figure 6 This is a block diagram showing an example of the output signal of the CMT detection unit in this embodiment.

[0014] Figure 7 This is a block diagram illustrating another example of the output signal of the CMT detection unit in an embodiment.

[0015] Figure 8 This is a block diagram illustrating an example of the configuration of the CMT detection unit in this embodiment.

[0016] Figure 9 This is a flowchart illustrating a processing example of the direction selection unit.

[0017] Figure 10 The diagram shows the amplifier output when CMT noise is input.

[0018] Figure 11 The diagram shows the output of another amplifier when CMT noise is input.

[0019] Figure 12 This is a timing diagram representing an example of the response when CMT noise with positive slew rate is applied.

[0020] Figure 13 This is a timing diagram representing an example of the response when CMT noise with negative side slew rate is applied.

[0021] Figure 14 This is a circuit diagram showing a more detailed configuration example of the CMT detection unit.

[0022] Figure 15 A graph showing an example of the response when CMT noise with positive slew rate is applied.

[0023] Figure 16 The figure shows an example of the response when CMT noise with negative side slew rate is applied.

[0024] Figure 17 This is a diagram showing an example of the logic circuit for the direction selection unit.

[0025] Figure 18 It is a truth table for positive and negative signals.

[0026] Figure 19 It is a timing diagram when CMT noise with a positive slope is applied, resulting in waveform distortion.

[0027] Figure 20 This diagram shows an example of the configuration of an isolation amplifier, which is a signal transmission device according to the first embodiment.

[0028] Figure 21 This is a diagram showing another configuration example of an isolation amplifier as a signal transmission device in the first embodiment.

[0029] Figure 22 This is a diagram showing an example of a gate driving device.

[0030] Figure 23 This is a diagram illustrating an example of the transient response of the drain voltage.

[0031] Figure 24 This is a block diagram showing the configuration of the high-power side.

[0032] Figure 25 This is a timing diagram representing a processing example on the high-power side.

[0033] Explanation of reference numerals in the attached figures

[0034] 16n: Negative-side comparison part,

[0035] 16a~16e: Recognizer,

[0036] 16p: Front-to-side comparison section,

[0037] 20n: Negative-side coding section,

[0038] 20p: Front and side encoding section,

[0039] 22: Direction selection unit,

[0040] 100: Signal transmission device,

[0041] 102: Gate driving device,

[0042] 200: Control Department

[0043] 300: Signal Transmission Unit

[0044] 302: Primary side chip,

[0045] 304: AC coupling section,

[0046] 400: CMT Inspection Department

[0047] T1: First reference potential terminal,

[0048] T2: Second reference potential terminal Detailed Implementation

[0049] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. Furthermore, in the following description, the same or similar components will be labeled with the same reference numerals, and descriptions of components already described once will be appropriately omitted.

[0050] [First Implementation Method]

[0051] Figure 1 This is a block diagram illustrating the signal transmission device 100 of this embodiment. (e.g.) Figure 1 As shown, the signal transmission device 100 is an example of an isolator using a transformer. The signal transmission device 100 includes a control unit 200, a signal transmission unit 300, and a CMT detection unit 400.

[0052] The control unit 200 is, for example, a microprocessor (MPU), which outputs the signal Vin to the signal transmission unit 300. The signal transmission unit 300 has a primary-side chip 302, an AC coupling unit 304, and a secondary-side chip 306.

[0053] The primary-side chip 302 is, for example, a transmitting circuit. The primary-side chip 302 transmits the signal Vin to the secondary-side chip 306 via AC coupling section 304. In this embodiment, the primary-side chip 302 corresponds to the primary-side circuit.

[0054] The AC coupling unit 304 transmits the signal Vin generated by the primary-side chip 302 to the secondary-side chip 306. This AC coupling unit 304 is, for example, a transformer. The primary-side ground G1 of the primary-side chip 302 and the secondary-side ground G2 of the secondary-side chip 306 are galvanically isolated by the AC coupling unit 304. However, while the AC coupling unit 304 in this embodiment is a transformer, it is not limited to this. For example, the AC coupling unit 304 could also be an electrically insulated miniature capacitor or an optically insulated device.

[0055] The secondary-side chip 306 is, for example, a receiving circuit. The secondary-side chip 306 outputs the signal received via the AC coupling unit 304 as a signal Vout. Furthermore, in this embodiment, the secondary-side chip 306 corresponds to a secondary-side circuit.

[0056] Sometimes, abrupt electrical fluctuations occur between the separated primary-side ground G1 and secondary-side ground G2. These fluctuations are sometimes referred to as common-mode transient (CMT) noise. Hereinafter, the primary-side ground G1 will be referred to as ground G1, and the secondary-side ground G2 will be referred to as ground G2.

[0057] The signal transmission device 100 sometimes experiences errors during data transmission between insulation layers due to large CMT noise between grounding G1 and grounding G2. Previously, during data transmission, since CMT noise was not sensed, errors in data transmission went undetected. This resulted in reduced reliability of data transmission.

[0058] Therefore, the CMT detection unit 400 senses the generation of CMT noise and its level. Thus, the CMT detection unit 400 can determine whether the level of the CMT noise exceeds an allowable value that greatly increases the probability of a transmission error. In this embodiment, the CMT detection unit 400 corresponds to a detection unit.

[0059] Figure 2 It means Figure 1 The diagram shows an example of the equivalent circuit of the AC coupling unit 304. Figure 2 This example illustrates an AC coupling unit 304 that includes a transformer. Specifically, the transformer is insulated and coupled between terminals T1 and T2 of the primary-side chip 302 and terminals T3 and T4 of the secondary-side chip 306. Thus, terminals T1 and T3 are connected to ground, which serves as their respective reference potentials.

[0060] Furthermore, the primary side GND is set to G1, the secondary side GND is set to G2, the primary side inductance of the transformer is set to L1, the secondary side inductance is set to L2, the primary side parasitic resistance is set to Rp1, the secondary side parasitic resistance is set to Rp2, and the parasitic capacitance between the inductors is set to C1. For simplicity, an equivalent circuit is shown using the example of parasitic capacitance forming the inductance at the inductor terminals. In this way, the transformer brings the inductors, referenced to the potentials of the first reference potential terminal T1 and the second reference potential terminal T3, closer together, transmitting signals from the primary side chip 302 to the secondary side chip 306 or from the secondary side chip 306 to the primary side chip 302.

[0061] The CMT detection unit 400 detects CMT noise. Specifically, the CMT detection unit 400 outputs a signal corresponding to the voltage fluctuation between the first reference potential terminal T1 of the primary-side chip 302 and the second reference potential terminal T3 of the secondary-side chip 306, which are isolated by the AC coupling unit 304. Further details of the CMT detection unit 400 will be described later.

[0062] Figure 3 This is a diagram showing another equivalent circuit example of the AC coupling section 304. Figure 3 The diagram shows an equivalent circuit example using a transformer with a center tap in the AC coupling section 304. Specifically, it is an example of a transformer where the center tap is connected to the primary side ground G1 via terminal T1 and to the secondary side ground G2 via terminal T3. For example, an on / off keying (OOK) differential signal output from a (not shown) drive circuit is input to T2 and T2', and output from T4 and T4' to a (not shown) detector circuit via the AC coupling section 304.

[0063] like Figure 2 , Figure 3 As shown, when the GND potential of each ground G1 and G2 changes, an in-phase signal is generated, and current flows through the parasitic capacitance C1. This is called CMT noise.

[0064] exist Figure 3 In the case of a transformer, the signals from terminals T2 and T2' are summed to detect the in-phase signal of T2 and T2'. Similarly, the signals from terminals T4 and T4' are summed to detect the in-phase signal of T4 and T4'. The following explanation uses a transformer as an example, but is not limited to this.

[0065] Figure 4 This diagram illustrates an equivalent circuit example of the signal transmission unit 300. The primary-side chip 302 is connected to the primary-side G1 via the first terminal T1. A resistor R1 is connected between the first terminal T1 and the second terminal T2. The secondary-side chip 306 is connected to the secondary-side G2 via the third terminal T3. A resistor R2 is connected between the third terminal T3 and the fourth terminal T4.

[0066] Furthermore, the CMT detection unit 400 is connected to both ends of resistor R2. Capacitor C1 represents the capacitance parasitic between the insulation layers of the transformer shown by the dashed line. That is, capacitor C1 corresponds to parasitic capacitance C1 (refer to...). Figure 2 , Figure 3 Furthermore, CMT noise is a steep signal, therefore inductors L1 and L2 (refer to...) Figure 2 , Figure 3 The impedance of L1 and L2 increases, so for the sake of simplicity, we will ignore the inductors L1 and L2 in the explanation.

[0067] Figure 5 This is a graph representing the CMT noise voltage VCMT relative to ground G2 and the voltage amplitude VR at node na of the secondary-side chip, also relative to ground G2. The horizontal axis represents time, and the vertical axis represents the CMT noise voltage VCMT and the voltage amplitude VR at node na. Figure 5 The example given is a voltage VCMT with slew rate k periodically applied between grounds G1 and G2. Furthermore, in the following, CMT noise will sometimes be referred to simply as CMT, and the voltage VCMT of CMT noise will be referred to simply as VCMT.

[0068] like Figure 5 As shown, when the voltage VCMT rises from negative to positive during the time intervals t0~t1 and t5~t6, the voltage amplitude VR at node na becomes equation (1).

[0069]

[0070] As mentioned above, R1 and R2 represent resistances, R = R1 + R2, and C1 represents the parasitic capacitance of the transformer. The slew rate k represents the voltage change of VCMT per unit time.

[0071] If t >> RC1, then it becomes equation (2). That is, when the transient response shown in equation (1) becomes a steady state, it becomes the voltage amplitude VR shown in equation (2).

[0072]

[0073] On the other hand, when the CMT noise VCMT decreases from positive to negative during the period from time t3 to t4, the voltage amplitude VR at node na becomes equation (3).

[0074]

[0075] If t >> RC1, then it becomes equation (4).

[0076]

[0077] Thus, the voltage amplitude VR at node na becomes a pulse with an amplitude corresponding to the slew rate k.

[0078] Figure 6 This is a block diagram illustrating an example of the output signal of the CMT detection unit 400 in this embodiment. When CMT noise is generated, the CMT detection unit 400 detects the magnitude of the CMT noise and outputs a flag signal (FLAG) when the noise level is above a predetermined value. A subsequent processing unit or the like can perform processing corresponding to the flag signal (FLAG). Thus, since it is impossible to determine whether a transmission error has occurred at the receiving end, the reliability of the data can be determined based on the flag signal (FLAG).

[0079] Figure 7 This is a block diagram illustrating another example of the output signal of the CMT detection unit 400 in this embodiment. When CMT noise is generated, the CMT detection unit 400 outputs a slew rate signal with information related to the slew rate, based on the magnitude of the CMT noise.

[0080] As mentioned above, CMT noise is equivalent to a sharp potential change in GND on the primary or secondary side. The amplitude of the detected CMT noise is shown in equations (2) and (4) and is equivalent to the slew rate k of the detected CMT.

[0081] For example, when the CMT detection unit 400 is used for gate drivers, etc., it is necessary to set the following predetermined method so that electromagnetic radiation caused by in-phase potential fluctuations does not affect other measuring instruments, etc. Electromagnetic radiation is related to the slew rate; to reduce electromagnetic radiation, it is only necessary to reduce the slew rate. When the slew rate is reduced, the amplitude of CMT noise decreases (see below). Figure 23 ).

[0082] Therefore, if the slew rate can be sensed by observing the CMT noise amplitude, then since the radio wave radiation is likely to be above the specified value when the slew rate is above the specified value, the gate driver side can be notified of the slew rate that reduces CMT noise.

[0083] Figure 8 This is a block diagram showing an example of the configuration of the CMT detection unit 400 according to this embodiment. The CMT detection unit 400 includes a voltage conversion unit 10, a noise suppression unit 12, an amplification unit 14, a positive side comparison unit 16p, a negative side comparison unit 16n, a positive side storage unit 18p, a negative side storage unit 18n, a positive side encoding unit 20p, a negative side encoding unit 20n, a direction selection unit 22, a selection unit 24, a first delay circuit unit 26, a holding unit 28, and a second delay circuit unit 30.

[0084] The voltage conversion unit (SR to Amplitude) 10 is a module that converts CMT noise into voltage amplitude. The voltage conversion unit 10 corresponds, for example, to the resistor R2 connected to the CMT detection unit 400 (see reference). Figure 4 ) or resistor R1 (refer to) Figure 4 ).

[0085] The noise suppression unit (HPF) 12 is, for example, a high-pass filter that suppresses low-frequency noise. If the low-frequency noise is low, the noise suppression unit (HPF) 12 may not be necessary.

[0086] The amplifier section (AMP) 14 is an amplification stage. The amplifier section 14 is set with a gain corresponding to the detected CMT noise.

[0087] The positive comparator (COMPARATOR) 16p is the slew rate with positive CMT noise (reference). Figure 5 The comparator used during operation. The positive side comparator 16p compares the CMT noise level with the magnitude of the multi-level positive level.

[0088] The negative-side comparator 16n has the same configuration as the positive-side comparator 16p. The negative-side comparator 16n operates at a slew rate where CMT noise is negative (refer to...). Figure 5 The comparator used during the comparison process. The negative-side comparator 16n compares the CMT noise level with the magnitude of multiple negative levels. Furthermore, in this embodiment, the positive-side comparator 16p and the negative-side comparator 16n correspond to the identification unit.

[0089] As described above, the polarity of the output of the voltage conversion unit 10 changes according to the polarity of the slew rate. Therefore, a positive side comparison unit 16p corresponding to the positive amplitude polarity and a negative side comparison unit 16n corresponding to the negative amplitude polarity are used.

[0090] The positive-side storage unit (LATCH) 18p consists of multiple latch circuits corresponding to the positive-side comparison unit 16p. The positive-side storage unit 18p stores the comparison results of the positive-side comparison unit 16p. The timing for latch clearing the multiple latch circuits will be described later.

[0091] The negative-side storage unit (LATCH) 18n consists of multiple latch circuits corresponding to the negative-side comparison unit 16n. The negative-side storage unit 18n stores the comparison results of the negative-side comparison unit 16n. The timing for latching and clearing the multiple latch circuits will be described later.

[0092] The positive-side encoding unit 20p encodes the storage result of the positive-side storage unit 18p. Similarly, the negative-side encoding unit 20n encodes the storage result of the negative-side storage unit 18n. Furthermore, in this embodiment, the positive-side encoding unit 20p corresponds to the first encoding unit, and the negative-side encoding unit 20n corresponds to the second encoding unit. In this embodiment, the positive-side encoding unit 20p and the negative-side encoding unit 20n are corresponding encoding units.

[0093] The direction selection unit 22 determines whether the CMT noise is a positive or negative pulse. That is, the direction selection unit 22 outputs the slew rate of the selected CMT noise (refer to...). Figure 5 The positive and negative selection signals.

[0094] The selection unit 24 selects the encoding result of the positive side encoding unit 20p or the negative side encoding unit 20n according to the selection signal of the direction selection unit 22, and outputs it to the holding unit 28.

[0095] The first delay circuit section 26 adjusts the output timing of the selection section 24 and the signal input timing of the holding circuit 28. The first delay circuit section 26 is, for example, a buffer, which delays the output signal of the direction selection section 22 and outputs it to the holding section 28.

[0096] The holding unit 28 holds the encoding result selected by the selection unit 24. The holding unit 28 holds the encoding result selected by the selection unit 24 after a delay via the first delay circuit unit 26. Through the delay of these two modules, the transient response of CMT noise converges and becomes approximately constant.

[0097] The second delay circuit section 30 delays the output signal of the first delay circuit section 26, resetting the positive-side storage section 18p and the negative-side storage section 18n. That is, the latches of the positive-side storage section 18p and the negative-side storage section 18n perform latch clearing on multiple latch circuits at the timing of the positive / negative determination signal input from the direction selection section 22. Thus, the positive-side storage section 18p and the negative-side storage section 18n are latched and cleared based on the transmission delay formed by the three delay-generating circuit sections 24, 26, and 30, entering a state of waiting for the next transient signal of CMT noise.

[0098] Furthermore, in circuits that provide a positive power supply to GND, it is difficult to detect and process signals below GND. Therefore, the processing after the noise suppression unit 12 uses a differential circuit, where positive and negative signals are processed by substituting differential signals.

[0099] Alternatively, it can be configured to include a noise suppression unit 12 and an amplification unit 14 as needed. For example, as shown in equations (2) and (4), the detected voltage amplitude VR is proportional to the slew rate k. Therefore, when it is desired to detect only CMT noise with a high slew rate k, signal processing can sometimes be performed without using the amplification process of the amplification unit 14.

[0100] Furthermore, the number of comparators required for the positive-side comparator 16p and the negative-side comparator 16n is determined based on the resolution of the detected slew rate (details are described later). Figure 14 For example, when the slew rate to be detected is divided into four, three comparators (comp) are required.

[0101] Thus, one feature of the CMT detection unit 400 in this embodiment is that it operates based on the CMT noise itself as a trigger. That is, if CMT noise is input, the states of the positive comparison unit 16p and the negative comparison unit 16n change. This change is input to the positive storage unit 18p, the negative storage unit 18n, the direction selection unit 22, and the first delay circuit unit 26, and a predetermined result is held by the holding unit 28. Furthermore, after a predetermined time, the positive storage unit 18p and the negative storage unit 18n are cleared, and the next CMT noise detection period begins. In addition, it is also characterized by having a direction selection unit 22 that determines the polarity of the CMT noise and switches the path according to the polarity. As a result, the processing can be separated into polarity-corresponding processes, the circuit is simplified, and thus the speed can be further improved.

[0102] Figure 9 This is a flowchart illustrating a processing example of the direction selection unit 22. For example... Figure 9 As shown, the direction selection unit 22 receives the output results of the positive side comparison unit 16p and the negative side comparison unit 16n (step S100).

[0103] Next, the direction selection unit 22 uses the output results of the positive comparison unit 16p and the negative comparison unit 16n to determine whether the CMT noise is positive or negative (step S102). If the CMT noise is positive, the positive comparison unit 16p reacts; if the CMT noise is negative, the negative comparison unit 16n reacts. Thus, the direction selection unit 22 uses the stored information of the reset positive storage unit 18p and negative storage unit 18n to determine whether the CMT noise is positive or negative.

[0104] Next, the direction selection unit 22 holds the determination result fixed for a certain period of time. Thus, the direction selection unit 22 outputs a signal containing information indicating positive or negative for a certain period of time in a manner that keeps the determination result unchanged (step S104).

[0105] Next, after a certain period of time (step S106), the direction selection unit 22 unlocks (step S108) to prepare for the CMT noise that will be generated next. The unlocking can be performed using the second delay circuit unit 30 (see...). Figure 8 The signal is used to execute the decision. Locking the decision result for a certain period of time is to prevent false decisions caused by distortion generated in the amplifier output.

[0106] use Figure 10 , Figure 11 The causes of distortion in the amplifier output are explained. Figure 10 This is a graph showing the amplifier output when CMT noise is input. Figure 11 This is a graph showing the output of another amplifier when CMT noise is input. The horizontal axis represents time, and the vertical axis represents voltage. Figure 10 The image shows the output results when the cutoff (fc) frequency of the noise suppression unit 12 is set to 200kHz. Figure 11 The output results are shown when the cutoff (fc) frequency of the noise suppression unit 12 is set to 10MHz.

[0107] Thresholds th1 and th2 are examples of threshold voltages for the positive-side comparator 16p and the negative-side comparator 16n. If the output voltage of the noise suppression unit 12 is above threshold th1, the positive-side comparator 16p changes from L to H. On the other hand, if it is below threshold th2, the negative-side comparator 16n changes from L to H.

[0108] When the cutoff frequency is set to 200kHz, if CMT noise is applied, the positive threshold th1 is exceeded, and CMT noise with a positive slew rate is detected. After the CMT noise is applied, the voltage returns to the original DC voltage Dv (e.g., 1.2V). On the other hand, when the HPF cutoff frequency is set to 10MHz, the DC voltage Dv is in a state roughly the same as the 200kHz case until it exceeds the positive threshold th1. However, since the bandwidth of the cutoff frequency is wider, the CMT noise exceeds the negative threshold th2 after the CMT noise ends. Therefore, the direction selection unit 22 determines that a negative slew rate (-k) has been input. To prevent this, the direction selection unit 22 has a function to lock the determination for a certain period of time after it is determined that the threshold has been exceeded.

[0109] Here, refer to Figure 8 Use Figure 12 , Figure 13 The diagram illustrates a processing example of the CMT detection unit 400 in this embodiment. Figure 12This is a timing diagram showing an example of the response when CMT noise with positive slew rate is applied. From top to bottom, the following are shown: CMT noise input to voltage conversion unit 10, detection pulse (PULSE) input to noise suppression unit 12, amplified pulse (AMP) output from amplification unit 14, output values ​​(P1 to Pn) of positive side comparison unit 16p, stored values ​​(L1 to Ln) of positive side storage unit 18p, output signal (nCLEAR) of second delay circuit unit 30, output signal (SELECT) of direction selection unit 22, output signal (DATA SET) of first delay circuit unit 26, and output signal (D0 to D0n-1) of holding unit 28.

[0110] First, the response when positive-side slew rate (CMT) noise is applied will be explained. At time t10, the voltage conversion unit 10 is input with CMT noise and begins output corresponding to the time derivative. The amplification unit 14 outputs the time derivative of the CMT noise as a rectangular pulse waveform (see reference). Figure 5 ).

[0111] The positive-side comparison unit 16p compares the voltage amplitude VR of the rectangular pulse waveform with n threshold voltages P1 to Pn.

[0112] At time t12, the voltage amplitude VR of the rectangular pulse waveform exceeds one of the n threshold voltages P1 to Pn. Consequently, the positive-side comparator 16p changes from L to H corresponding to the threshold voltages P1 to Pn exceeded by the amplitude voltage Vr. For example, if the voltage amplitude VR is P4, then P1, P2, P3, and P4 change from L to H, while P5 and above remain at L. This indicates that the voltage amplitude VR is between P4 and P5.

[0113] The output value of the positive comparison unit 16p is input to the next-level positive storage unit 18p. Information representing L or H is set in the stored values ​​(L1 to Ln) of the corresponding latches. Furthermore, the latches are not strictly necessary, but they prevent changes in the decision result when performing logic determinations with short detection pulse widths.

[0114] On the other hand, the stored values ​​(L1 to Ln) of the latches in the next-level negative-side storage unit 18n are all L. Therefore, the output signal (SELECT) of the direction selection unit 22 selects the positive-side storage unit 18p that outputs H. In this case, the output signal (SELECT) of the direction selection unit 22 changes from H to L.

[0115] The positive encoding unit 20p generates a code corresponding to the stored values ​​(L1 to Ln) of the latch in the positive storage unit 18p. The selection unit 24 selects the code of the positive encoding unit 20p according to the output signal (SELECT) of the direction selection unit 22.

[0116] At time t14, if the delay time delay2 of the first delay circuit section 26 has elapsed, the holding section 28 holds the code Do to Dn-1 representing the positive voltage amplitude Vr of the positive side of the positive side encoding section 20p and outputs it to the next stage.

[0117] At time t16, when the CMT noise becomes constant, the output of the detection pulse (PULSE) of the voltage conversion unit 10 becomes low. Then, at time t18, the output of the positive comparison unit 16p becomes L.

[0118] At time t20, if the delay time delay3 of the second delay circuit section 30 passes after the delay time delay2, the output signal (nCLEAR) of the second delay circuit section 30 changes from high to low and is input to the positive storage section 18p. As a result, the stored values ​​(L1 to Ln) of the latches in the positive storage section 18p are latched and reset, and the output signal of the first delay circuit section 26 also becomes L. Then, at time t22, the output signal (nCLEAR) of the second delay circuit section 30 changes from low to high, and the next process begins.

[0119] Figure 13 This is a timing diagram showing an example of the response when CMT noise with negative slew rate is applied. From top to bottom, the following are shown: CMT noise input to voltage conversion unit 10, detection pulse (PULSE) input to noise suppression unit 12, amplified pulse (AMP) output from amplification unit 14, output values ​​(N1 to Nn) of negative side comparison unit 16n, stored values ​​(L1 to Ln) of negative side storage unit 18p, output signal (nCLEAR) of second delay circuit unit 30, output signal (SELECT) of direction selection unit 22, output signal (DATA SET) of first delay circuit unit 26, and output signals (D0 to D0n-1) of holding unit 28.

[0120] exist Figure 13 In the example of response when CMT noise is applied at the negative side slew rate, it is explained that... Figure 12 The response examples are different.

[0121] At time t30, the voltage conversion unit 10 approaches the end of the CMT noise input, and at time t32, it begins the output corresponding to the time derivative. The amplification unit 14 begins to output the time derivative of the CMT noise as a rectangular pulse waveform on the negative side (see reference). Figure 5 ).

[0122] The negative-side comparison unit 16n compares the voltage amplitude -VR of the rectangular pulse waveform on the negative side with n threshold voltages N1 to Nn.

[0123] At time t34, the voltage amplitude -VR of the rectangular pulse waveform on the negative side exceeds one of the n threshold voltages N1 to Nn. Consequently, the negative-side comparator 16n changes from L to H corresponding to the threshold voltages N1 to Nn exceeded by the voltage amplitude -VR. For example, if the voltage amplitude -VR is N4, then N1, N2, N3, and N4 change from L to H, while N5 and above remain at L. This indicates that the voltage amplitude -VR is between N4 and N5.

[0124] The output value of the negative-side comparison unit 16n is input to the negative-side storage unit 18n of the next stage. Information representing L or H is set in the stored values ​​(L1 to Ln) of the corresponding latches. Furthermore, the latches are not strictly necessary, but they prevent the determination result from changing when performing logic determination with a short detection pulse width.

[0125] On the other hand, the stored values ​​(L1 to Ln) of the latches in the next-level positive storage unit 18p are all L. Therefore, the output signal (SELECT) of the direction selection unit 22 selects the negative storage unit 18n, which outputs H. In this case, the output signal (SELECT) of the direction selection unit 22 changes from L to H.

[0126] The negative-side encoding unit 20n generates a code corresponding to the stored values ​​(L1 to Ln) of the latch in the negative-side storage unit 18n. The selection unit 24 selects the code of the negative-side encoding unit 20n according to the output signal (SELECT) of the direction selection unit 22.

[0127] At time t36, if the delay time delay2 of the first delay circuit section 26 has elapsed, the holding section 28 holds the code Do~Dn-1 representing the voltage amplitude -VR on the negative side of the negative side storage section 18n and outputs it to the next stage.

[0128] At time t38, when the CMT noise becomes constant, the output of the detection pulse (PULSE) of the voltage conversion unit 10 becomes low. Furthermore, at time t40, the output of the negative-side comparator 16n becomes L.

[0129] At time t42, if the delay time delay3 of the second delay circuit section 30 has elapsed after delay2, the output signal (nCLEAR) of the second delay circuit section 30 changes from high to low and is input to the positive storage section 18p. As a result, the stored values ​​(N1 to Nn) of the latch in the negative storage section 18n are latched and reset, and the output signal of the first delay circuit section 26 also becomes L. Then, at time t44, the output signal (nCLEAR) of the second delay circuit section 30 changes from low to high, and the next processing begins.

[0130] Figure 14This is a circuit diagram showing a more detailed configuration example of the CMT detection unit 400. (Example) Figure 14 As shown, a digital-to-analog converter (DAC) 32 and a bias power supply 34 are also added.

[0131] The noise suppression unit 12 is configured to set the cutoff (fc) frequency via, for example, a 3-bit signal. The amplification unit 14 has multiple amplifiers 14a to 14d. Thus, the amplification unit 14 can perform amplification of 2, 4, 8, or 20 times. Furthermore, sometimes the same reference numerals are used to denote the same configuration on both the positive and negative sides, and the description of one side is omitted.

[0132] The positive-side comparator 16p has identifiers 16a to 16e corresponding to the plurality of amplifiers 14a to 14d. The identifiers 16a to 16e compare whether the output value of the amplifier 14 exceeds a reference threshold by 1, 2, 4, 8, or 20 times. Then, if it exceeds the reference threshold, a high-level signal H is output, and if it does not exceed the reference threshold, a low-level signal L is output.

[0133] The positive-side storage unit 18p has latches 18a-18e corresponding to the recognizers 16a-16e of the positive-side comparison unit 16p, and stores the output values ​​of the recognizers 16a-16e. Similarly, the negative-side storage unit 18n has latches 18a-18e corresponding to the recognizers 16a-16e of the negative-side comparison unit 16n, and stores the output values ​​of the recognizers 16a-16e.

[0134] The positive-side encoding unit 20p encodes the values ​​of latches 18a to 18e in the positive-side storage unit 18p. Similarly, the negative-side encoding unit 20n encodes the values ​​of latches 18a to 18e in the negative-side storage unit 18n.

[0135] The first delay circuit section 26 includes a positive delay circuit 26p and a negative delay circuit 26n. The positive delay circuit 26p and the negative delay circuit 26n include a logic OR element 26a and two buffers 26b and 26c. The output of the first-stage buffer 26b is input to the direction selection section 22, and the output of the second-stage buffer 26c is input to the selection section 24.

[0136] The selection unit 24 has multiple multiplexers 24a-24c that input signals from the positive-side encoding unit 20p and the negative-side encoding unit 20n, and a multiplexer 24d that inputs the output signals of the second-stage buffers of the positive-side delay circuit 26p and the negative-side delay circuit 26n. Each multiplexer 24a-24d selects either the positive-side or negative-side signal according to the signal from the direction selection unit 22.

[0137] The holding section 28 has D flip-flops 28a to 28d. The D flip-flops 28a to 28d store the output values ​​of the corresponding multiplexers 24a to 24d.

[0138] The digital-to-analog converter (DAC) 32 converts the values ​​of the D flip-flops 28a to 28d in the holding unit 28 into digital signals. The bias power supply 34 sets the reference threshold values ​​for the comparators 16a to 16e in the positive-side comparator 16p and the comparators 16a to 16e in the negative-side comparator 16n. With this configuration, the amplitude of the CMT noise can be quantified.

[0139] Figure 15 , Figure 16 It means Figure 14 Timing diagram of the processing example of the CMT detection unit 400. Figure 15 This is a graph showing an example of the response when CMT noise is applied to the positive slew rate. Figure 16 This is a graph showing an example of the response when CMT noise is applied to the negative side slew rate.

[0140] Reference Figure 14 Explanation will be provided. In Figure 15 In this respect, the output signals posi sel and posi data set of the two buffers 26b and 26c in the added positive-side delay circuit 26p are similar to those of the circuit in question. Figure 12 The difference lies in the fact that at time t12, the high-level signal H is held in one of the latches 18a to 18e in the positive-side storage section 18p.

[0141] At time t13, after a delay of time delay1 from time t12, buffer 26b outputs the output signal posi sel to direction selection unit 22. As a result, direction selection unit 22 sets the selection signal SELECT from 1 to 0, and outputs the selection signal SELECT that selects the positive side signal to multiple multiplexers 24a to 24c of selection unit 24.

[0142] At time t14, after a delay of 2 seconds from time t13, buffer 26c outputs the output signal posi dataset to the D flip-flops 28a-28d of the holding unit 28. Thus, the D flip-flops 28a-28c of the holding unit 28 hold the data on the positive side. Other processing and... Figure 12 same.

[0143] Reference Figure 14 Explanation will be provided. In Figure 16 In, with Figure 13 The difference lies in the addition of two buffers 26b and 26c in the negative-side delay circuit 26n, which output signals Nega sel and Nega data set. That is, at time t33, a high-level signal H is maintained in one of the latches 18a to 18e in the negative-side storage section 18n.

[0144] At time t34, after a delay of time delay1 from time t33, the buffer 26b of the delay circuit 26n outputs the output signal Negasel to the direction selection unit 22. As a result, the direction selection unit 22 sets the selection signal SELECT from 0 to 1, and outputs the selection signal SELECT that selects the signal on the negative side to the multiple multiplexers 24a to 24c of the selection unit 24.

[0145] At time t36, after a delay of time delay2 from time t34, the buffer 26c of the delay circuit 26n outputs the output signal Nega data set to the D flip-flops 28a-28d of the holding unit 28. Thus, the D flip-flops 28a-28c of the holding unit 28 hold the data on the negative side. Other processing and... Figure 13 same.

[0146] Figure 17 This is a diagram showing an example of the logic circuit for the direction selection unit 22. It includes multiple XOR gates 22a and 22b and multiple NAND gates 22c to 22f. The positive-side delay circuit 26b (see reference...) Figure 14 The output value of ) is set to the positive signal Posi sel, and the negative side delay circuit 26b (refer to) is set to the positive signal Posi sel. Figure 14 The output value of the positive side comparator 16p is set to the negative signal Negasel. When any one of the outputs of the positive side comparator 16p is high (H), it is set to 1; when all are low (L), it is set to 0. Similarly, when any one of the outputs of the negative side comparator 16n is high (H), it is set to 1; when all are low (L), it is set to 0.

[0147] The logic circuit of the direction selection unit 22 inputs a positive signal Posi sel and a negative signal Nega sel to the XOR gate 22a, and inputs a positive signal Posi sel and a negative signal Nega sel to the XOR gate 22b.

[0148] Input the output signal of XOR gate 22a and the positive signal Posi sel to NAND gate 22c. Input the output signal of XOR gate 22b and the negative signal Nega sel to NAND gate 22d.

[0149] The output signals of NAND gate 22c and XOR gate 22f are input to XOR gate 22e. The output signals of NAND gate 22d and XOR gate 22e are input to XOR gate 22f.

[0150] Figure 18 This is a truth table for the positive signal Posi sel and the negative signal Nega sel. Figure 18 In this context, Posi represents the positive signal Posi sel, and Nega represents the negative signal Nega sel.

[0151] When CMT noise is applied, if the applied slope is positive, the voltage first changes to the positive side; if waveform distortion exists, the voltage then changes to the negative side. The opposite occurs if the applied slope is negative. Therefore, if the signal that changes first is prioritized, waveform distortion will not be falsely detected. Thus, in the direction selection unit 22 of this embodiment, the signal that changes first is prioritized over the positive-side transition from L to H transition from L to H transition from negative-side transition.

[0152] like Figure 18 As shown, when both signals Posi sel and Negasel are 1, the signal SELECT is held. That is, if one of the signals Posi sel or Negasel becomes a high-level signal H (i.e., 1), and then the other becomes a high-level signal H (i.e., 1), then both Posi sel and Negasel become high-level signals H (i.e., 1), so the signal SELECT is held. Therefore, the values ​​of the D flip-flops 28a to 28d in the holding unit 28 are held.

[0153] Similarly, when both Posi sel and Negasel are 0, the SELECT signal is held. That is, when both Posi sel and Negasel are low-level signals (L, i.e., 0), the SELECT signal is held. In other words, without the application of CMT noise, the values ​​of the D flip-flops 28a to 28d in the holding unit 28 are held.

[0154] Conversely, when the signal Posi sel is a low-level signal L (0) and the signal Negasel is a high-level signal H (1), the signal SELECT becomes the selection on the Negasel side (1).

[0155] Conversely, when signal Posi sel is high (H, i.e., 1) and signal Negasel is low (L, i.e., 0), signal SELECT becomes the selection of signal Posi sel (i.e., 0). Thus, when one signal Posi sel is 1 and the other Negasel is 0, the signal on the positive or negative side is selected. Afterwards, even if both signals Posi sel and Negasel become 1 within a predetermined time, the selected signal remains in its selected state.

[0156] Figure 19 This is an example of a timing diagram showing waveform distortion caused by applying CMT noise with a positive slope. At least one of the stored values ​​(L1 to Ln) of the latches in the positive side memory section 18p becomes high at level H. Then, at time t50, the delay1 output of the positive side buffer 26b changes from L to H.

[0157] Next, at time t52, after a delay time dely2 from time t50, the delay2 output of the positive buffer 26c changes from a low-level signal L to a high-level signal H. As a result, the direction selection unit 22 outputs a signal direct to the selection unit 24 and the holding unit 28 to select the data in the positive storage unit 18p. Then, the holding unit 28 selects and stores the data in the positive storage unit 18p.

[0158] Next, at time t58, the output signal nCLEAR after passing through the second delay circuit section 30p on the positive side is input to latches 18a to 18e of the positive storage section 18p after a delay time delay3, and the latches 18a to 18e of the positive storage section 18p are unlocked. As a result, the signal Posi sel changes from H to L.

[0159] On the other hand, waveform distortion occurs, and at least one of the stored values ​​(L1 to Ln) of the latch in the negative-side storage unit 18n becomes a high level H. At time t54, the delay1 output of the negative-side buffer 26b changes from a low level signal L to a high level signal H. As a result, a high level H is input to the direction selection unit 22 from both the positive and negative-side buffers 26b. Thus, a high level signal H is input from the negative-side buffer 26b with a time difference. In this case, from the determination of the positive-side data until the delay time delay3 has elapsed, the signals Posi sel and Nega sel are high level signals H, therefore the direction selection unit 22 acts as a SELECT signal (see reference). Figure 18 The output indicates the held signal. Therefore, the negative side data becomes invalid. In this way, by using a delay time of delay3 to ensure the stability of waveform distortion and other effects caused by CMT noise, misjudgments can be prevented.

[0160] In addition, time t60 is the time after a delay of 1 from time t58, and time t62 is the time after a delay of 2 from time t60.

[0161] Furthermore, at time t64, the output signal nCLEAR after passing through the second delay circuit section 30n on the negative side is input to latches 18a to 18e of the negative side storage section 18n after a delay time delay3 at time t56, and the latches 18a to 18e of the negative side storage section 18n are unlocked. As a result, the signal Negasel changes from H to L.

[0162] Figure 20This diagram illustrates an example configuration of the isolation amplifier in the signal transmission device 100 as described in the first embodiment. The signal transmission device 100 is a device capable of using CMT noise as an indicator of the reliability of data transmission between insulators. The primary-side chip 302 of the signal transmission device 100 includes a modulator 302a, and the secondary-side chip 306 includes a demodulator 306a, a CMT detection unit 400, and a reliability generation unit 402.

[0163] Modulator 302a modulates the input signal Vin. For example, modulator 302a increases the frequency of the input signal Vin. Modulator 302a outputs the modulated input signal Vin to demodulator 306a via AC coupling unit 304.

[0164] The demodulator 306a de-frequencyizes the high-frequency signal input via the AC coupling unit 304. Furthermore, in this embodiment, the high-frequency conversion of the input signal Vin is referred to as modulation, and the de-frequency conversion is referred to as demodulation.

[0165] The CMT detection unit 400 outputs a digital monitoring signal containing information about the amplitude of the CMT noise to the reliability generation unit 402. The reliability generation unit 402 generates a reliability signal Sr containing information about the reliability that decreases as the absolute value of the CMT noise amplitude increases, and outputs it to the subsequent processing unit.

[0166] The subsequent processing unit can use reliability information based on CMT noise to perform actions such as discarding, retransmitting, or retaining the transmitted data. The processing corresponding to the reliability information can be arbitrarily configured according to the system.

[0167] Figure 21 This diagram illustrates another configuration example of the isolation amplifier in the signal transmission device 100 as described in the first embodiment. The signal transmission device 100 is a device capable of using CMT noise as an indicator of the reliability of data transmission between insulators. Figure 20 The difference between the signal transmission device 100 shown is that the primary side chip 302 of the signal transmission device 100 also includes a CMT detection unit 400 and a reliability generation unit 402.

[0168] like Figure 21 As shown, the CMT detection unit 400 of the primary side chip 302 detects the CMT noise Sig308, which indicates that GND1 is transitioning to a negative voltage relative to GND2, and the CMT detection unit 400 of the secondary side chip 306 detects the CMT noise Sig310, which indicates that GND1 is transitioning to a positive voltage relative to GND2.

[0169] In this case, it is not necessary to determine the pulse on the negative side; CMT noise Sig308 and Sig310 can be detected simply by detecting the pulse on one side. As a result, the operating margin of the detection unit 40 can be increased, the circuit can be simplified, and the detection range can be expanded.

[0170] [Second Implementation]

[0171] The gate driving device 102 of the second embodiment differs from the signal transmission device 100 of the first embodiment in that it performs gate driving. Hereinafter, the differences from the signal transmission device 100 of the first embodiment will be described.

[0172] Figure 22 This diagram illustrates an example of a gate driving device. (For example...) Figure 22 As shown, the half-bridge circuit, which is configured to control the gate drive device 102, consists of a high-side (HS) switch element 500 and a low-side (LS) switch element 502 connected in series. The connection point between the switch elements 500 and 502 is connected to the ground terminal (second reference potential terminal) G3 of the secondary-side chip 3060a.

[0173] The CMT detection unit 400 generates a signal corresponding to the voltage fluctuation between the gate terminal (first reference potential terminal) G1 of the primary-side chip 3020a and the ground terminal G3 of the secondary-side chip 3060a. The CMT noise, based on the drain voltage at the connection point of the switching elements 500 and 502, is related to the time derivative of the voltage or current fluctuation during switching; a larger time derivative results in greater noise. Therefore, CMT noise is in a trade-off relationship with the losses of the half-bridge circuit (power element).

[0174] The control unit 2000 controls the voltage or current variation time derivative during switching based on the magnitude of the amplitude voltage Vr of the CMT noise detected by the CMT detection unit 400.

[0175] Figure 23 This is a graph showing an example of the transient response of the drain voltage. The drain voltage L10 under high slew rate and L12 under low slew rate represent the drain voltage of the switching element 500. The horizontal axis represents time, and the vertical axis represents voltage.

[0176] Furthermore, amplitude voltage L20 represents the amplitude voltage L20 when the slew rate is high, and amplitude voltage L22 when the slew rate is low, as detected by the detection unit 400. The control unit 2000 controls the gate drive current of the drive circuits 3062a (gate driver) and 3062b (gate driver) based on the values ​​of amplitude voltages L20 and L22 detected by the detection unit 400. That is, when the control unit 2000 determines that the CMT noise ratio is higher than specified based on the value of amplitude voltage L20, it reduces the drive current and increases the drive time. This reduces the slew rate of the pulse width modulation (PWM) signal.

[0177] On the other hand, if the CMT noise ratio is determined to be lower than specified based on the value of amplitude voltage L22, the drive current is reduced and the drive time is increased. This increases the slew rate of the pulse width modulation (PWM) signal.

[0178] By using feedback control based on the output signal of the CMT detection unit 400, the slew rate of the drain voltage of the switching element 500 can be controlled.

[0179] [Third Implementation Method]

[0180] The gate driving device 102 of the third embodiment differs from the signal transmission device 100 of the second embodiment in that the control circuit 3022a performs timing control of the power supply to the CMT detection unit 400. Hereinafter, the differences from the signal transmission device 102 of the second embodiment will be explained.

[0181] Figure 24 This is a block diagram showing the configuration of the high power side (HS). It differs from the signal transmission device 102 of the second embodiment in that it also includes a power control unit 3064a.

[0182] The power control unit 3064a controls the power supply to the CMT detection unit 400 based on the drive suppression signal (standby) of the gate control circuit 3022a.

[0183] Figure 25 This is a timing diagram illustrating a processing example on the high power side (HS). From top to bottom, it shows the pulse width modulation (PWM) signal supplied to the high power side (HS), the drive suppression signal (standby) of the gate control circuit 3022a, the gate control signal (gate drive) output by the drive circuit 3062a, the CMT noise (CMT), and the detection timing (CMT det) of the CMT detection unit 400.

[0184] At time t70, the gate control circuit 3022a, based on the rise of the PWM signal, sets the drive suppression signal (standby) to a low level and outputs it to the power control unit 3064a. The power control unit 3064a supplies power to the detection unit 40 for a predetermined period starting from time t70. As a result, the detection unit 40 detects the voltage amplitude of CMT noise generated during time t72, which is based on the rise of the gate control signal (gate drive). Then, at time t74, it sets the drive suppression signal (standby) to a high level.

[0185] Similarly, at time t76, the gate control circuit 3022a, based on the falling PWM signal, sets the drive suppression signal (standby) low and outputs it to the power control unit 3064a. The power control unit 3064a supplies power to the detection unit 40 for a predetermined period starting from time t76. Thus, the detection unit 40 detects the voltage amplitude of CMT noise generated during time t78, based on the falling gate control signal (gate drive). Then, at time t80, it sets the start signal (standby) high.

[0186] In this way, by supplying power to the detection unit 40 in accordance with the period during which CMT noise is generated, the power consumption of the detection unit 40 can be suppressed.

[0187] Several embodiments of the present invention have been described, but these embodiments are provided as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope or spirit of the invention, and are included within the scope of the invention as described in the claims and its equivalents.

Claims

1. A signal transmission device, characterized in that, have: Primary side circuit; An AC coupling unit transmits the transmitted signal received from the primary side circuit; The secondary side circuit receives the transmitted signal transmitted by the AC coupling section; as well as The detection unit outputs a detection signal related to the noise level during the transmission of the transmitted signal, based on the variation in terminal voltage formed by the current flowing at at least one of the first reference potential terminal of the primary side circuit insulated by the AC coupling unit and the second reference potential terminal of the secondary side circuit. The detection unit has: One or more first identifiers compare the terminal voltage with a predetermined potential on the positive side; One or more second identifiers compare the terminal voltage with a predetermined potential on the negative side; The first encoding unit encodes information related to the slew rate of the terminal voltage based on the comparison result of the first recognizer. as well as The second encoding unit performs encoding of information related to the slew rate of the terminal voltage based on the comparison result of the second identifier.

2. The signal transmission device according to claim 1, characterized in that, In the detection unit, based on the occurrence of a state change in at least one of the first and second identifiers, at least one of the first and second encoding units begins to encode the polarity of the slew rate of the terminal voltage and the magnitude of the slew rate.

3. The signal transmission device according to claim 2, characterized in that, The detection unit also has: The direction selection unit outputs a selection signal that selects one of the first encoding unit and the second encoding unit, corresponding to the one that generated the comparison between the first recognition unit and the second recognition unit. as well as The selection unit selects one of the first recognizer and the second recognizer based on the selection signal.

4. The signal transmission device according to claim 3, characterized in that, The direction selection unit selects the first identifier and the second identifier that first generates the comparison process.

5. The signal transmission device according to claim 3, characterized in that, The direction selection unit maintains the output of the selection signal for a preset period when the selection signal is output.

6. The signal transmission device according to claim 1, characterized in that, The first encoding unit performs encoding of information representing the magnitude of the slew rate indicating positive polarity. The second encoding unit performs encoding of information representing the magnitude of the slew rate of the negative polarity.

7. The signal transmission device according to claim 1, characterized in that, Based on the comparison results of the first and second identifiers, the detection unit outputs a slewing rate signal containing information related to the slewing rate as the detection signal.

8. The signal transmission device according to claim 1, characterized in that, The AC coupling section is a transformer that transmits signals from the primary side circuit to the secondary side circuit or from the secondary side circuit to the primary side circuit by bringing inductors, which are referenced to the potentials of the first reference potential terminal and the second reference potential terminal, closer together.

9. A gate driving device, characterized in that, have: The primary-side circuit modulates and transmits the gate signal; An AC coupling unit transmits signals received from the primary-side circuit. The secondary side circuit demodulates the gate signal transmitted by the AC coupling section and supplies it to the gate of the switching element; as well as The detection unit outputs a detection signal related to the noise level during signal transmission, based on the variation in terminal voltage formed by the current flowing at at least one of the first reference potential terminal of the primary side circuit insulated by the AC coupling unit and the second reference potential terminal of the secondary side circuit. The secondary-side circuit controls the slew rate of the gate signal based on the detection signal.

10. The gate driving device according to claim 9, characterized in that, The gate signal is a pulse width modulation signal, and the gate driving device further includes a control unit that controls the amount of power supplied to the detection unit based on the timing of at least one of the rise and fall of the pulse.

11. The gate driving device according to claim 9, characterized in that, The detection unit has: One or more first identifiers compare the terminal voltage with a predetermined potential on the positive side; One or more second identifiers compare the terminal voltage with a predetermined potential on the negative side; The first encoding unit encodes information related to the slew rate of the terminal voltage based on the comparison result of the first recognizer. as well as The second encoding unit performs encoding of information related to the slew rate of the terminal voltage based on the comparison result of the second identifier.

12. The gate driving device according to claim 11, characterized in that, In the detection unit, based on the occurrence of a state change in at least one of the first and second identifiers, at least one of the first and second encoding units begins to encode the polarity of the slew rate of the terminal voltage and the magnitude of the slew rate.

13. The gate driving device according to claim 12, characterized in that, The detection unit also has: The direction selection unit outputs a selection signal that selects one of the first encoding unit and the second encoding unit, corresponding to the one that generated the comparison between the first recognition unit and the second recognition unit. as well as The selection unit selects one of the first recognizer and the second recognizer based on the selection signal.

14. The gate driving device according to claim 13, characterized in that, The direction selection unit selects the first identifier and the second identifier that first generates the comparison process.

15. The gate driving device according to claim 13, characterized in that, The direction selection unit maintains the output of the selection signal for a preset period when the selection signal is output.

16. The gate driving device according to claim 11, characterized in that, The first encoding unit performs encoding of information representing the magnitude of the slew rate indicating positive polarity. The second encoding unit performs encoding of information representing the magnitude of the slew rate of the negative polarity.

17. The gate driving device according to claim 11, characterized in that, Based on the comparison results of the first and second identifiers, the detection unit outputs a slewing rate signal containing information related to the slewing rate as the detection signal.

18. The gate driving device according to claim 9, characterized in that, The AC coupling section is a transformer that transmits signals from the primary side circuit to the secondary side circuit or from the secondary side circuit to the primary side circuit by bringing inductors, which are referenced to the potentials of the first reference potential terminal and the second reference potential terminal, closer together.

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