FPGA-based heterogeneous computing power unified configuration system and method

Abstract

The application relates to the technical field of edge computing, and discloses a heterogeneous computing power unified configuration system and method based on FPGA, the system adopts a two-layer architecture of "centralized management and edge execution", and comprises a central configuration node and a heterogeneous robot node.The central configuration node takes a master control FPGA as a core, externally connects an SSD as a centralized configuration warehouse, integrates an AI computing power pool and a safe communication and authentication unit, and the heterogeneous robot node comprises a subordinate reconfigurable hardware.Through an adaptive closed loop of "perception, decision, configuration and execution", the application realizes software definition, millisecond-level dynamic reconfiguration and unified management of the bottom computing power of a heterogeneous robot cluster, and solves the problems of hardware function solidification, low configuration efficiency and computing power cooperation difficulty.

Description

Technical Field

[0001] This invention relates to the field of edge computing technology, and in particular to a unified configuration system and method for heterogeneous computing power based on FPGA. Background Technology

[0002] As robot swarms evolve towards heterogeneity, intelligence, and collaboration, traditional centralized software configuration methods can no longer meet the demands of dynamic and complex scenarios. Existing technologies suffer from the following key bottlenecks: 1. Fragmented Configuration and Inefficient Management: Heterogeneous robot clusters contain nodes based on different processor architectures (ARM, x86) and reconfigurable hardware (FPGA, dedicated AI accelerator cards). Updating firmware, bitstreams, or AI models requires multiple specialized tools and independent processes, making large-scale deployment, rollback, and unified operation and maintenance of clusters extremely difficult, taking anywhere from hours to days.

[0003] 2. Fixed Hardware Functions and Lack of Dynamism: The core perception and control functions of robots are usually deeply bound to specific hardware. For example, once the bitstream of an image processing pipeline written for an FPGA is fixed, it cannot be remotely and dynamically reconfigured according to changes in the task (such as switching from "daytime inspection" to "nighttime reconnaissance"), which severely limits the flexibility of the hardware and its adaptability to the task.

[0004] 3. Fragmentation of perception, decision-making, and configuration: In the existing architecture, environmental perception, central decision-making, and underlying hardware configuration belong to different subsystems, forming an open loop. Although the system can perceive environmental changes and make decisions, it cannot directly and quickly translate these decisions into reconfiguration instructions for the robot's "physical capabilities" (underlying hardware functions), and thus cannot achieve an adaptive closed loop of "perception-decision-configuration-execution".

[0005] 4. Lack of security and reliability in the configuration process: In complex network environments such as military and emergency situations, traditional software distribution methods face the risk of configuration packages being tampered with, forged, or stolen, and lack a strong authentication mechanism for the identity of configuration nodes, resulting in security vulnerabilities for the entire cluster.

[0006] Therefore, there is an urgent need for an integrated system architecture that can unify the management of heterogeneous computing power at the hardware level and achieve secure, dynamic, and closed-loop configuration. Summary of the Invention

[0007] The purpose of this invention is to provide a unified configuration system and method for heterogeneous computing power based on FPGA, which solves the problems of fixed hardware functions, low configuration efficiency and difficulty in computing power coordination in the prior art.

[0008] To achieve the above objectives, in a first aspect, the present invention provides a unified configuration system for heterogeneous computing power based on FPGA, including a central configuration node and heterogeneous robot nodes; the central configuration node is an independent hardware device, including a unified configuration management unit, an AI computing power pool, and a secure communication and authentication unit; The unified configuration management unit is based on the main control field programmable gate array and connected to an external solid-state drive. It is used to call the corresponding function configuration file in the solid-state drive according to the target robot platform type and encapsulate it into a configuration data stream that conforms to the target platform processor boot interface protocol. The AI ​​computing power pool integrates at least two artificial intelligence computing chips with different architectures for performing data fusion, environmental modeling or intelligent decision-making tasks; The secure communication and authentication unit is used for secure data communication and identity authentication with an external robot cluster. The heterogeneous robot node includes subordinate reconfigurable hardware for receiving and executing configuration data streams from the central configuration node to change or load its hardware functionality.

[0009] The functional configuration file includes at least one of the following: FPGA full configuration or partial reconfiguration bitstream file, artificial intelligence model file, and robot operating system image file.

[0010] The main control field-programmable gate array is also configured as a data preprocessing and fusion unit, used to perform hardware-level real-time decoding, time synchronization and feature extraction on the multi-source perception data streams transmitted back from the heterogeneous robot nodes, and distribute the processed data to the AI ​​computing power pool.

[0011] The data preprocessing and fusion unit within the main control field-programmable gate array, the AI ​​computing power pool, and the unified configuration management unit form a closed-loop data path via an on-chip high-speed bus or an off-chip high-speed bus; this enables the processed perception data to drive intelligent decision-making and trigger the generation and distribution of new configuration data streams.

[0012] The secure communication and authentication unit includes a hardware security module, which is used to encrypt and digitally sign the issued configuration data stream, and to perform identity authentication on the robot node requesting configuration based on a digital certificate.

[0013] The subordinate reconfigurable hardware is a subordinate FPGA or an AI accelerator card that supports dynamic reconfiguration. The bitstream file in the configuration data stream is used to trigger partial dynamic reconfiguration of the slave reconfigurable hardware. The central configuration node and the heterogeneous robot nodes are connected via a deterministic low-latency network; The differential bitstream file in the configuration data stream follows a partial dynamic reconfiguration protocol, enabling the slave reconfigurable hardware to complete the logical reconfiguration of a specified functional module within milliseconds without interrupting global functionality. The protocol simulation and encapsulation engine within the main control field-programmable gate array has hardware description logic that supports dynamic loading and updating to adapt to the startup interface protocol of newly added robot processor types. The main control field-programmable gate array, the solid-state drive, and the AI ​​computing power pool are interconnected via a high-speed bus with PCIeGen3 or higher standards.

[0014] Secondly, a unified configuration method for heterogeneous computing power based on FPGA, used in the unified configuration system for heterogeneous computing power based on FPGA described in the first aspect, includes the following steps: Receive configuration task instructions, determine the target robot node and required functions; schedule the corresponding function configuration file from SSD according to the target node platform identifier; The main control FPGA calls the corresponding hardware protocol simulation logic according to the boot interface type of the target node processor, and converts the scheduled function configuration file into a configuration data stream that meets its timing requirements. The configuration data stream is encrypted and signed for integrity, and then sent to the target robot node through a secure communication interface array to configure its heterogeneous computing unit. The system receives and processes the perception data transmitted back from the robot nodes, uses the AI ​​computing power pool to perform environmental modeling and decision-making, and generates new configuration or control instructions based on the decision results by the main control FPGA, before returning to the first step.

[0015] This invention relates to an FPGA-based heterogeneous computing power unified configuration system. The system adopts a two-layer architecture of "centralized management and edge execution," comprising a central configuration node and heterogeneous robot nodes. The central configuration node is based on a main control FPGA, with an external SSD serving as a centralized configuration repository, integrating an AI computing power pool and a secure communication and authentication unit. The heterogeneous robot nodes contain subordinate reconfigurable hardware. This invention achieves software definition, millisecond-level dynamic reconfiguration, and unified management of the underlying computing power of heterogeneous robot clusters through an adaptive closed loop of "perception-decision-configuration-execution," solving the problems of fixed hardware functions, low configuration efficiency, and difficulties in computing power coordination. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below.

[0017] Figure 1 This is a schematic diagram of the overall architecture.

[0018] Figure 2 This is the internal logic diagram of the central configuration node.

[0019] Figure 3 This is a schematic diagram of the FPGA-based heterogeneous computing power unified configuration system provided by the present invention.

[0020] Figure 4 This is a schematic diagram illustrating an application scenario of an embodiment.

[0021] Figure 5 This is a flowchart of the FPGA-based heterogeneous computing power unified configuration method provided by the present invention.

[0022] In the diagram: 1-Central configuration node, 2-Heterogeneous robot node, 11-Unified configuration management unit, 12-AI computing power pool, 13-Secure communication and authentication unit. Detailed Implementation

[0023] The embodiments of the present invention are described in detail below. Examples of the embodiments are shown in the accompanying drawings. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present invention, but should not be construed as limiting the present invention.

[0024] Please see Figures 1 to 4 In a first aspect, the present invention provides a unified configuration system for heterogeneous computing power based on FPGA, including a central configuration node 1 and a heterogeneous robot node 2; the central configuration node 1 is an independent hardware device, including a unified configuration management unit 3, an AI computing power pool 12 and a secure communication and authentication unit 13; The unified configuration management unit 3 is based on the main control field programmable gate array and connected to an external solid-state drive. It is used to call the corresponding function configuration file in the solid-state drive according to the target robot platform type and encapsulate it into a configuration data stream that conforms to the target platform processor boot interface protocol. The AI ​​computing power pool 12 integrates at least two artificial intelligence computing chips with different architectures for performing data fusion, environmental modeling or intelligent decision-making tasks. The secure communication and authentication unit 13 is used for secure data communication and identity authentication with an external robot cluster. The heterogeneous robot node 2 includes subordinate reconfigurable hardware for receiving and executing configuration data streams from the central configuration node 1 to change or load its hardware functions.

[0025] Furthermore, the functional configuration file includes at least one of the following: FPGA full configuration or partial reconfiguration bitstream file, artificial intelligence model file, and robot operating system image file.

[0026] Furthermore, the main control field-programmable gate array is also configured as a data preprocessing and fusion unit, used to perform hardware-level real-time decoding, time synchronization and feature extraction on the multi-source perception data stream transmitted back from the heterogeneous robot node 2, and distribute the processed data to the AI ​​computing power pool 12.

[0027] Furthermore, the data preprocessing and fusion unit within the main control field-programmable gate array, the AI ​​computing power pool 12, and the unified configuration management unit 3 form a closed-loop data path through an on-chip high-speed bus or an off-chip high-speed bus; enabling the processed perception data to drive intelligent decision-making and thereby trigger the generation and distribution of new configuration data streams.

[0028] Furthermore, the secure communication and authentication unit 13 includes a hardware security module for encrypting and digitally signing the issued configuration data stream, and for performing identity authentication on the robot node requesting configuration based on a digital certificate.

[0029] Furthermore, the slave reconfigurable hardware is a slave FPGA or an AI accelerator card that supports dynamic reconfiguration; The bitstream file in the configuration data stream is used to trigger partial dynamic reconfiguration of the slave reconfigurable hardware. The central configuration node 1 and the heterogeneous robot node 2 are connected via a deterministic low-latency network; The differential bitstream file in the configuration data stream follows a partial dynamic reconfiguration protocol, enabling the slave reconfigurable hardware to complete the logical reconfiguration of a specified functional module within milliseconds without interrupting global functionality. The protocol simulation and encapsulation engine within the main control field-programmable gate array has hardware description logic that supports dynamic loading and updating to adapt to the startup interface protocol of newly added robot processor types. The main control field-programmable gate array, the solid-state drive, and the AI ​​computing pool 12 are interconnected via a high-speed bus with PCIe Gen3 or higher standards.

[0030] In this embodiment, the system adopts a two-layer architecture of "centralized management and edge execution", including a central configuration node 1 and multiple heterogeneous robot nodes 2.

[0031] Central Configuration Node 1: This node is a dedicated hardware device integrating high-speed computing, massive storage, secure communication, and protocol conversion capabilities. It is the core hub of the system, and its internal logic is as follows: Figure 2 As shown. Specifically includes: Unified Configuration Management Unit 3: This unit uses the main control FPGA as the core for intelligent control and protocol conversion, with an external high-capacity solid-state drive (SSD) serving as a centralized configuration repository. The SSD stores encrypted and version-managed full-function configuration files, including: FPGA full configuration / partial reconfiguration bitstream files optimized for different robot platforms, lightweight artificial intelligence (AI) model files, and robot operating system image files. The main control FPGA embeds a programmable hardware protocol simulation and packaging engine, which pre-loads or can dynamically load hardware description logic for various processor and reconfigurable hardware boot interface protocols (SPI Flash, eMMC, SelectMAP, etc.). Based on the hardware identifier of the target robot node, the engine accurately simulates its timing at the hardware level, converting the files in the SSD into a configuration data stream that the target hardware can receive and directly boot in real time. AI Computing Pool 12: This pool works in conjunction with the main control FPGA via a high-speed interconnect bus (such as PCIe). It integrates at least two AI acceleration chips with different architectures (e.g., GPUs for parallel computing-intensive tasks such as 3D reconstruction, and NPUs for low-power, low-latency real-time inference). The computing power pool accepts unified task scheduling from the main control FPGA, performing environmental modeling (such as visual SLAM, point cloud stitching), semantic understanding, and cluster collaborative decision-making computation after data fusion. The data preprocessing and fusion unit, integrated within the main control FPGA, utilizes its hardware parallelism to perform hardware-level real-time decoding, timestamp synchronization and alignment, coordinate transformation, and feature extraction on multi-source, high-speed, heterogeneous raw data streams (such as camera video streams, LiDAR point cloud streams, and IMU data) transmitted from robot nodes, forming standardized fused data frames. This significantly reduces the I / O and preprocessing burden on the backend AI computing power pool 12. The secure communication and authentication unit 13 includes multi-mode physical interfaces (Ethernet, wireless private network) and integrated or external hardware security modules (HSM). The HSM uses national cryptographic algorithms SM2 / SM4 or equivalent to encrypt and digitally sign the issued configuration data streams and perform strong identity authentication based on digital certificates for robot nodes initiating configuration requests, ensuring end-to-end security and trustworthiness during the configuration process.

[0032] Heterogeneous robot node 2: such as quadruped robots, unmanned tracked vehicles, drones, etc. Its key feature is the integrated subordinate reconfigurable hardware, which can be a standalone subordinate FPGA, system-on-a-chip (SoC), or a dedicated AI accelerator card supporting dynamic function loading. This hardware acts as a receiving and execution terminal, specifically responsible for receiving, verifying, and loading the configuration data stream issued by the central configuration node 1. When the data stream is a differential bitstream file, it can trigger online partial reconfiguration of the subordinate reconfigurable hardware, switching specific functional modules (such as switching the communication module from Ethernet to wireless mesh) within milliseconds without interrupting the overall robot operation.

[0033] Example

[0034] System Deployment: The central configuration node is deployed at the ground command post. The exploration cluster consists of two quadruped robots (equipped with high-definition wide-angle cameras and LiDAR) and one unmanned tracked vehicle (equipped with a high-precision 3D laser scanner).

[0035] Task flow: Mission Initialization: The commander issues the "Underground Pipeline Corridor Exploration" command. The central node parses the command, determines that the mission requires the participation of all 3 robots, and configures the "Underground Mode" function package for each type of robot.

[0036] Unified Dynamic Configuration: The central node's main control FPGA works in parallel, scheduling a customized differential bitstream for the quadruped robot ("low-light enhanced vision processing") and a control model for "narrow space gait," as well as a configuration package customized for the unmanned tracked vehicle ("high-precision point cloud scanning and stitching") from the SSD. The protocol simulation engine within the main control FPGA, based on the hardware identifier of each target node, calls the corresponding startup protocol hardware logic (such as QSPI, eMMC, etc.) in parallel, converting static files into a configuration data stream conforming to the target hardware loading timing. This configuration stream is distributed through an integrated low-latency onboard data link module. In one specific implementation, this data link uses a gigabit onboard MESH network with time synchronization capabilities, with measured end-to-end communication latency consistently below 30ms. After the configuration stream arrives, each robot's slave FPGA receives its dedicated differential bitstream portion through the SelectMAP interface. From receiving the first frame of configuration data, online partial reconfiguration of specific functional modules (such as the vision preprocessing module) can be completed within approximately 60ms, without interrupting the operation of the robot's main processor and its core functions such as motion control. In this way, the entire heterogeneous cluster can complete the global function switch from receiving instructions to being ready within 2 minutes.

[0037] Collaborative Exploration and Real-Time Modeling: Robots enter the corridor. A quadruped robot, leveraging its agility, quickly explores the path ahead, transmitting video and lightweight point clouds; an unmanned tracked vehicle follows behind, performing high-precision scanning. The transmitted data undergoes time-space alignment via the central FPGA before being fed into the AI ​​computing pool. A GPU cluster handles real-time visual SLAM, while an NPU cluster performs point cloud refinement and semantic segmentation (identifying pipes, valves, and cracks). The two are fused to generate a centimeter-accurate, semantically annotated 3D real-world map of the corridor, displayed in real-time on the command screen.

[0038] Obstacle Encounter Dynamic Reconstruction and Decision-Making: The map shows a collapsed obstacle ahead, allowing only a quadruped robot to pass. The decision-making unit (located in the NPU of the heterogeneous AI computing pool) generates an 'obstacle crossing' instruction, which is passed to the task planner (i.e., the configuration task generation logic) of the main control FPGA. The planner immediately generates a new configuration task with the quadruped robot as the target and includes an 'obstacle crossing bitstream' identifier, triggering a new round of the S1-S3 process.

[0039] Mission extension: Upon discovering a suspected leak point, the decision-making unit orders the nearest unmanned tracked vehicle to load the "Gas Detection and Fine Scanning" configuration package and proceed to the location for detailed operations.

[0040] This embodiment fully demonstrates how the present invention seamlessly integrates heterogeneous configuration, real-time perception, intelligent decision-making, and dynamic reconfiguration to form a highly autonomous, collaborative, and adaptive intelligent cluster system.

[0041] Please see Figure 5 Secondly, a unified configuration method for heterogeneous computing power based on FPGA, used in the unified configuration system for heterogeneous computing power based on FPGA described in the first aspect, includes the following steps: S1 receives the configuration task instruction, determines the target robot node and the required functions, and schedules the corresponding function configuration file from SSD according to the target node platform identifier. Specifically, it receives task instructions from the upper layer (such as "collaborative search"). It parses the instructions to determine the set of robot nodes participating in the task and the required functional modes for each node. Based on the unique identifier of the target node platform, it schedules the corresponding set of version-verified functional configuration files from the SSD configuration repository.

[0042] The main control FPGA in S2 calls the corresponding hardware protocol simulation logic according to the boot interface type of the target node processor, and converts the scheduled function configuration file into a configuration data stream that meets its timing requirements. Specifically, the main control FPGA reads the hardware interface type of the target node and calls the corresponding hardware description logic in the built-in protocol simulation engine. This engine, at the FPGA logic level, accurately reproduces the physical timing and communication protocols during the boot and loading process of the target processor or reconfigurable hardware, and encapsulates the scheduled static configuration file into a configuration data stream conforming to its timing specifications in real time. This process is completed in hardware, with a deterministic latency that is far lower than that of software simulation.

[0043] S3 encrypts and performs integrity signature on the configuration data stream, and sends it to the target robot node through a secure communication interface array to configure its heterogeneous computing unit. Specifically, the Hardware Security Module (HSM) encrypts the encapsulated configuration data stream and attaches a digital signature based on the private key. The data stream is then transmitted to the target robot node via a secure communication interface using a reliable transmission protocol. After the node verifies the signature and decrypts the data, the configuration data stream is loaded into its subordinate reconfigurable hardware, completing the function injection or switching.

[0044] S4 receives and processes the perception data transmitted back by the robot node, uses the AI ​​computing power pool 12 to perform environmental modeling and decision-making, and the main control FPGA generates new configuration or control instructions based on the decision results, and returns to the first step.

[0045] Specifically, the configured robot performs tasks and transmits sensory data back. The data undergoes real-time hardware-level processing via the data preprocessing and fusion unit of the main control FPGA.

[0046] The processed, standardized data is distributed to a heterogeneous AI computing power pool 12. The computing power pool performs parallel computations according to task assignments; for example, GPUs perform large-scale point cloud map construction, while NPUs perform real-time obstacle recognition and classification.

[0047] Based on the generated environmental semantic model and cluster status, the heterogeneous AI computing power pool 12 outputs decision information to the main control FPGA. The configuration task generation logic running within the main control FPGA parses this decision information and determines whether the robot's capabilities need to be changed. If so, it immediately generates a new configuration task instruction and returns to step S1, thus forming a rapid adaptive closed loop of "perception-decision-configuration-execution".

[0048] Beneficial effects

[0049] 1. It realizes the "software definition" and millisecond-level reconfiguration of hardware functions: By uniformly distributing standardized configuration data streams, especially differential bit streams, through the central node, it is possible to remotely and online dynamically rewrite the logical functions of the robot's underlying reconfigurable hardware, enabling fixed physical hardware to have the "soft" capability to change on demand, fundamentally solving the problem of function solidification.

[0050] 2. An integrated adaptive closed loop of "configuration-perception-decision" has been constructed: the dynamic configuration capability of hardware is deeply embedded into the real-time perception and intelligent decision-making loop. The system can not only understand the environment, but also directly and quickly "reshape" the robot's physical capabilities to adapt to the environment, realizing a qualitative change from "observing the world" to "changing itself to cope with the world".

[0051] 3. Significantly improve cluster operation and maintenance efficiency and task response speed: Through centralized and parallel hardware-level configuration, the deployment, switching, or upgrade time of dozens of heterogeneous robots can be reduced from hours to minutes or even seconds. A unified configuration source and security mechanism ensure the consistency, reliability, and security of large-scale cluster configurations, making it particularly suitable for rapid and dynamic scenarios such as emergency response and military missions.

[0052] 4. Offers excellent compatibility and forward-looking capabilities: The architecture based on FPGA hardware protocol simulation is not dependent on specific processor models or operating systems. For future new robot platforms, compatibility can be achieved simply by adding the hardware interface description logic to the protocol engine library of the central node and storing the corresponding configuration file, resulting in extremely strong system lifecycle and investment protection.

[0053] The above-disclosed embodiments are merely one or more preferred embodiments of this application and should not be construed as limiting the scope of this application. Those skilled in the art can understand that all or part of the processes for implementing the above embodiments and equivalent changes made in accordance with the claims of this application still fall within the scope of this application.

Claims

1. A unified configuration system for heterogeneous computing power based on FPGA, characterized in that, It includes a central configuration node and heterogeneous robot nodes; the central configuration node is an independent hardware device, including a unified configuration management unit, an AI computing power pool, and a secure communication and authentication unit; The unified configuration management unit is based on the main control field programmable gate array and connected to an external solid-state drive. It is used to call the corresponding function configuration file in the solid-state drive according to the target robot platform type and encapsulate it into a configuration data stream that conforms to the target platform processor boot interface protocol. The AI ​​computing power pool integrates at least two artificial intelligence computing chips with different architectures for performing data fusion, environmental modeling or intelligent decision-making tasks; The secure communication and authentication unit is used for secure data communication and identity authentication with an external robot cluster. The heterogeneous robot node includes subordinate reconfigurable hardware for receiving and executing configuration data streams from the central configuration node to change or load its hardware functionality.

2. The FPGA-based heterogeneous computing power unified configuration system as described in claim 1, characterized in that, The functional configuration file includes at least one of the following: FPGA full configuration or partial reconfiguration bitstream file, artificial intelligence model file, and robot operating system image file.

3. The FPGA-based heterogeneous computing power unified configuration system as described in claim 2, characterized in that, The main control field-programmable gate array is also configured as a data preprocessing and fusion unit, used to perform hardware-level real-time decoding, time synchronization and feature extraction on the multi-source perception data streams transmitted back from the heterogeneous robot nodes, and distribute the processed data to the AI ​​computing power pool.

4. The FPGA-based heterogeneous computing power unified configuration system as described in claim 3, characterized in that, The data preprocessing and fusion unit within the main control field-programmable gate array, the AI ​​computing power pool, and the unified configuration management unit form a closed-loop data path via an on-chip high-speed bus or an off-chip high-speed bus; enabling the processed perception data to drive intelligent decision-making and thereby trigger the generation and distribution of new configuration data streams.

5. The FPGA-based heterogeneous computing power unified configuration system as described in claim 4, characterized in that, The secure communication and authentication unit includes a hardware security module, which is used to encrypt and digitally sign the issued configuration data stream, and to perform identity authentication on the robot node requesting configuration based on a digital certificate.

6. The FPGA-based heterogeneous computing power unified configuration system as described in claim 5, characterized in that, The subordinate reconfigurable hardware is a subordinate FPGA or an AI accelerator card that supports dynamic reconfiguration; the bitstream file in the configuration data stream is used to trigger partial dynamic reconfiguration of the subordinate reconfigurable hardware; the central configuration node and the heterogeneous robot node are connected through a deterministic low-latency network; the differential bitstream file in the configuration data stream follows a partial dynamic reconfiguration protocol, enabling the subordinate reconfigurable hardware to complete the logical reconfiguration of a specified functional module within milliseconds without interrupting global functions; The protocol simulation and encapsulation engine within the main control field-programmable gate array has hardware description logic that supports dynamic loading and updating to adapt to the startup interface protocol of newly added robot processor types. The main control field-programmable gate array, the solid-state drive, and the AI ​​computing power pool are interconnected via a high-speed bus with PCIe Gen3 or higher standards.

7. A method for unified configuration of heterogeneous computing power based on FPGA, used in the unified configuration system for heterogeneous computing power based on FPGA as described in any one of claims 1-6, characterized in that, Includes the following steps: Receive configuration task instructions, determine the target robot node and required functions; schedule the corresponding function configuration file from SSD according to the target node platform identifier; The main control FPGA calls the corresponding hardware protocol simulation logic according to the boot interface type of the target node processor, and converts the scheduled function configuration file into a configuration data stream that meets its timing requirements. The configuration data stream is encrypted and signed for integrity, and then sent to the target robot node through a secure communication interface array to configure its heterogeneous computing unit. The system receives and processes the perception data transmitted back from the robot nodes, uses the AI ​​computing power pool to perform environmental modeling and decision-making, and generates new configuration or control instructions based on the decision results by the main control FPGA, before returning to the first step.

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