Method for measuring quality of espi bus signals and measuring device therefor

Abstract

The application provides an ESPI bus signal quality measurement method and a measurement device thereof, wherein the method is applied to a handshake management circuit module, the handshake management circuit module is electrically connected with an ESPI interface on a host device, and the method comprises the following steps: when the host device and a slave device communicate through an ESPI bus, the ESPI bus is listened to, and the listened ESPI bus signal is sampled to obtain sampling data; and whether the quality of the ESPI bus signal is abnormal is confirmed by judging whether the sampling data conforms to an ESPI protocol specification. The application can improve the precision of ESPI bus signal quality measurement.

Description

Technical Field

[0001] This invention relates to the field of communication technology, and in particular to a method and apparatus for measuring the quality of ESPI bus signals. Background Technology

[0002] ESPI (Enhanced Serial Peripheral Interface) is the mainstream bus for communication between PCH (Platform Controller Hub) and SIO (Super I / O Controller). It supports full-state management and adapts to the low-power and remote management needs of modern PCs (Personal Computers), playing a crucial role in tasks such as firmware updates in shutdown mode and fault diagnosis. ESPI can also be extended to communicate with slave devices, making it one of the important buses in modern PCs.

[0003] The quality of the ESPI bus signal determines the stability of communication between the PCH (Platform Controller Hub) and SIO (Super IO), which in turn affects the overall system startup, power management, I / O control, and remote maintenance. It is a critical link at the "lifeline level" of the PC platform. Its signal quality failure can spread from "hidden bit errors" to "system failure", affecting the entire process of product development, mass production, and operation and maintenance.

[0004] Current methods for measuring the quality of ESPI bus signals typically involve capturing the instantaneous waveform of the ESPI bus signal using an oscilloscope probe in a single pass, and then manually judging the signal quality according to the ESPI bus standard. However, this method not only requires manual intervention, reducing measurement efficiency and increasing measurement errors, but also introduces noise easily through the oscilloscope probe, further affecting measurement accuracy. Summary of the Invention

[0005] To address the aforementioned issues, the present invention provides a method and apparatus for measuring the quality of the ESPI bus signal. Compared to existing methods that rely on manual judgment of ESPI bus signal quality using an oscilloscope probe, the present invention utilizes a handshake management circuit module to test the ESPI bus signal quality, thereby improving the accuracy of ESPI bus signal quality measurement.

[0006] In a first aspect, the present invention provides a method for measuring the quality of ESPI bus signals. The method is applied to a handshake management circuit module, which is electrically connected to an ESPI interface on a host device. The method includes:

[0007] When the master device and slave device communicate via the ESPI bus, the ESPI bus is monitored and the monitored ESPI bus signals are sampled to obtain sampled data. The quality of the ESPI bus signal is confirmed by determining whether the sampled data conforms to the ESPI protocol specification.

[0008] Optionally, when the master device and slave device communicate via the ESPI bus, the steps of listening to the ESPI bus and sampling the listened ESPI bus signals to obtain sampled data include: When the master and slave devices communicate via the ESPI bus, the high-impedance buffer of the handshake management circuit module copies the ESPI bus signal from the ESPI bus to obtain the sampled data.

[0009] Optionally, when the master and slave devices communicate via the ESPI bus, the step of copying the ESPI bus signal from the ESPI bus through the high-impedance buffer of the handshake management circuit module to obtain the sampled data includes: When the master and slave devices communicate via the ESPI bus, the ESPI clock signal and protocol frame data signal on the ESPI bus are copied through a high-impedance buffer to obtain sampled data.

[0010] Optionally, the handshake management circuit module includes an FPGA, the method is applied to the FPGA, and the FPGA is configured with a reference clock with a frequency higher than that of the ESPI clock signal. The steps to determine whether the quality of the ESPI bus signal is abnormal by judging whether the sampled data conforms to the ESPI protocol specification include: Evaluation data is obtained by analyzing the sampled data; the evaluation data includes one or more of the following parameters corresponding to the ESPI bus signal: noise tolerance parameter, clock jitter parameter, high level parameter, and low level parameter. Based on the evaluation data, confirm whether the frequency, duty cycle, clock jitter, drift, noise margin, high and low levels of the ESPI clock signal, as well as the noise margin, high and low levels of the protocol frame data signal, are abnormal.

[0011] Optionally, the steps to determine whether the quality of the ESPI bus signal is abnormal by judging whether the sampled data conforms to the ESPI protocol specification include: Based on the frequency of the ESPI clock signal, a set of phase-shifted multi-phase sampling clocks is generated, which cover the entire cycle of the ESPI clock signal. The protocol frame data signal is sampled in parallel using a multi-phase sampling clock to obtain multiple level values ​​of the protocol frame data signal at different time points within one cycle of the ESPI clock signal. The effective sampling window is calculated based on the setup and hold times specified in the ESPI protocol. Verify that all level values ​​fall within the valid sampling window, and determine whether the protocol frame data signal is abnormal based on the verification results.

[0012] Optionally, the steps for calculating the effective sampling window based on the setup and hold times specified in the ESPI protocol include: The effective sampling window is defined as the time interval between the setup time before the rising edge of the ESPI clock signal and the time interval after the rising edge of the ESPI clock signal.

[0013] Optionally, before the step of generating a set of phase-shifted multi-phase sampling clocks based on the frequency of the ESPI clock signal, the method further includes: Generate a local sampling clock for the handshake management circuit module that is synchronized with the ESPI clock signal; Synchronize the protocol frame data signal to the local sampling clock domain of the handshake management circuit module.

[0014] Optionally, the method further includes: The judgment result of determining whether the quality of the ESPI bus signal is abnormal by judging whether the sampled data conforms to the ESPI protocol specification is quantified into multi-field information that includes at least an abnormal flag bit and an abnormal parameter type identifier; Multi-field information is sent to the host computer via serial port.

[0015] Optionally, the handshake management circuit module is electrically connected to the host computer via a UART interface; The steps for sending multi-field information to the host computer via serial port include: The multi-field information is packaged into a continuous byte stream according to the UART data frame format and sent to the host computer via serial port.

[0016] In a second aspect, the present invention provides a measuring device for the quality of an ESPI bus signal, the measuring device being used to implement the method as described in any of the first aspects.

[0017] The method and apparatus for measuring the quality of the ESPI bus signal provided in this invention test the quality of the ESPI bus signal between the master device and the slave device by connecting the handshake management circuit module to the ESPI interface on the master device without relying on an oscilloscope. This avoids the noise interference introduced by using an oscilloscope for measurement, thus improving both the efficiency and accuracy of the ESPI bus signal quality measurement. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic flowchart illustrating a method for measuring the quality of an ESPI bus signal according to an embodiment of this application. Figure 2 This is a schematic structural block diagram of an ESPI bus signal quality measurement method apparatus according to an embodiment of this application in its working state; Figure 3 This is a schematic circuit diagram of the ESPI interface in a master device according to an embodiment of this application; Figure 4 This is a schematic circuit diagram of an LDO chip according to an embodiment of this application. Detailed Implementation

[0020] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0021] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0022] It should also be understood that the terms “including / comprise” or “have” specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof.

[0023] In a first aspect, one embodiment of the present invention provides a method for measuring the quality of ESPI bus signals, combined with Figure 1 and Figure 2 The method is applied to a handshake management circuit module, which is electrically connected to the ESPI interface on the host device via a cable. The method includes steps S101 to S102.

[0024] Step S101: When the master device and the slave device communicate through the ESPI bus, listen to the ESPI bus and sample the listened ESPI bus signals to obtain sampled data.

[0025] Step S102: Confirm whether the quality of the ESPI bus signal is abnormal by judging whether the sampled data conforms to the ESPI protocol specification.

[0026] The method for measuring the ESPI bus signal quality provided in this embodiment tests the ESPI bus signal quality between the master and slave devices by connecting the handshake management circuit module to the ESPI interface on the master device, without relying on an oscilloscope. This not only improves the efficiency of ESPI bus signal quality measurement, but also improves the accuracy of ESPI bus signal quality measurement.

[0027] In this embodiment, the handshake management circuit module uses an FPGA as a bridge to acquire and measure the ESPI bus signals between the master device and the slave device in the form of a monitoring device; the master device is equipped with a PCH for communicating with the slave device.

[0028] Understandably, the ESPI bus can operate in Master / Slave mode. In this mode, the Master controls the Slave's CS# (Chip Select) pin to communicate with it, sending control commands and sending data. At any given time, only one CS# pin can be enabled on the Master, and the Master can only communicate with the Slave connected to that enabled CS# pin. Only one Master is allowed on an ESPI bus, but one or more Slaves are permitted. Like other buses, the CS# signal only allows the Master to control the output.

[0029] Specifically, in combination Figure 2 and Figure 3 The definitions of the ESPI bus signals are as follows: ESPI_IO[3:0]: 4-bit bidirectional data bus. In the scenario of FPGA analyzing ESPI bus signals, it is the input terminal for FPGA to capture protocol frame data signals (ESPI_DATA). FPGA can capture bidirectional data from PCH to peripheral and from peripheral to PCH. ESPI_CLK: ESPI clock signal; ESPI_ALERT#: Device alarm signal; ESPI_CS#: Chip select signal, active low. When input to the FPGA, it can be used to indicate whether the FPGA has started or stopped capturing ESPI bus signals. ESPI_RST#: Reset signal, an optional signal used to synchronize the ESPI bus reset state.

[0030] The ESPI bus is brought out using a pin header on the main device. Combined with... Figure 2 and Figure 3 In this configuration, the FPGA's core voltage VCCINT is 1.0V; the FPGA's I / O voltage VCCO is 3.3V, which can be powered from the motherboard; and the FPGA's auxiliary voltage VCCAUX is 1.8V, requiring independent power from the corresponding measurement device. For the 1.8V required by the ESPI bus, this embodiment obtains it through the VCC3_3SB pin on the main device and the LDO (Low Dropout Linear Regulator) chip U2, combined with... Figure 4 .

[0031] In a further optional embodiment of this embodiment, when the master device and the slave device communicate through the ESPI bus, the step of listening to the ESPI bus and sampling the listened ESPI bus signal to obtain sampled data includes: when the master device and the slave device communicate through the ESPI bus, copying the ESPI bus signal from the ESPI bus through a high-impedance buffer in the FPGA to obtain sampled data.

[0032] In this embodiment, when the master device and slave device communicate via the ESPI bus, the FPGA uses a built-in high-impedance tri-state buffer to replicate the ESPI bus signal. The ESPI bus signal between the master device and slave device is passively monitored by connecting it to the high-impedance input pin of the FPGA, avoiding load interference to the ESPI bus between the master device and slave device. At the same time, the high-impedance tri-state buffer synchronously replicates the ESPI bus signal and the high-impedance state of the ESPI bus signal, making the driving and high-impedance switching timing of the replicated ESPI bus completely consistent with the ESPI bus between the master device and slave device, effectively eliminating bus contention and completely restoring the electrical characteristics and transmission waveform of the ESPI bus.

[0033] Understandably, in monitor mode, the communication between the PCH and the slave device is completely autonomous. The FPGA simply replicates the ESPI bus signals on the ESPI bus through a high-impedance buffer, thus achieving non-intrusive offloading monitoring. This eliminates the need to send any signals to the PCH or respond to any commands issued by the PCH, improving the efficiency of ESPI bus signal acquisition.

[0034] It should be noted that after the FPGA is powered on and the PCH completes its reset (RSMRST# signal is released), it begins to monitor the ESPI bus signals on the ESPI bus. The entire process can be divided into the following stages: During the system power-on reset phase: the PCH outputs RSMRST# at a low level, and the ESPI bus is idle; the FPGA IO pin is configured as a high-impedance input, waiting for the RESET# signal to be released, and the sampling clock is initialized to synchronize with the ESPI CLK.

[0035] During the PCH initialization of the ESPI bus: the PCH sends the ESPI clock signal and the CS# strobe signal, and enumerates the slave devices; the FPGA starts sampling all signals such as the ESPI clock signal, the CS# strobe signal, IO0 / IO1, etc., and decodes the ESPI frame header, address, and data of the protocol frame data signal.

[0036] Normal communication phase: PCH interacts bidirectionally with slave devices; FPGA continuously captures all ESPI bus transactions (read / write / interrupt), and FPGA can also cache captured data and / or parse protocols in real time.

[0037] System hibernation / shutdown: The PCH stops outputting the ESPI clock signal, the ESPI bus enters a low-power state, the FPGA can reduce the sampling frequency, only monitor the wake-up signal, or enter a low-power mode.

[0038] In a further optional embodiment of this embodiment, when the master device and the slave device communicate through the ESPI bus, the step of copying the ESPI bus signal from the ESPI bus through the high-impedance buffer in the FPGA to obtain the sampled data includes: when the master device and the slave device communicate through the ESPI bus, copying the ESPI clock signal and protocol frame data signal on the ESPI bus through the high-impedance buffer to obtain the sampled data.

[0039] In a further optional embodiment of this example, as specified in the ESPI specification, the standard frequency of the ESPI clock signal output by the PCH should be 33MHz, and the duty cycle should be between 45% and 55%. If the frequency of the ESPI clock signal deviates or the duty cycle exceeds the specified range, it will cause the sampling timing window to shrink, thereby leading to data errors.

[0040] In this embodiment, the FPGA is configured with a reference clock whose frequency is higher than that of the ESPI clock signal, and the accuracy of the reference clock is also higher than that of the ESPI clock signal. For example, the frequency of the ESPI clock signal is 100MHz and the period is 10ns, which is used as the counting reference for the edge detection logic of the FPGA to capture the rising and falling edges of eSPI_CLK as the start and end trigger signals for cycle counting.

[0041] The steps to determine whether the quality of the ESPI bus signal is abnormal by judging whether the sampled data conforms to the ESPI protocol specification include: analyzing the sampled data to obtain evaluation data; judging whether the frequency, duty cycle, clock jitter, drift, noise margin, high level and low level of the ESPI clock signal, as well as the noise margin, high level and low level of the protocol frame data signal are abnormal based on the evaluation data.

[0042] The evaluation data includes one or more of the following parameters corresponding to the ESPI bus signal: noise tolerance parameter, clock jitter parameter, high-level parameter, and low-level parameter. In this embodiment, the evaluation data is obtained by analyzing the sampled data, specifically by analyzing the copied ESPI clock signal and protocol frame data signal.

[0043] It is understood that the evaluation data can be obtained using existing technologies, and this embodiment will not elaborate on this. The duty cycle of the ESPI clock signal = (total high-level time of the ESPI clock signal / clock period of the ESPI clock signal) × 100%. In this embodiment, the FPGA counts the high-level values ​​of the ESPI clock signal in one reference clock cycle, and calculates the total value of high and low levels in one reference clock cycle. The high-level count is divided by the total value and converted into a percentage to obtain the current duty cycle of the ESPI clock signal.

[0044] The jitter of the ESPI clock signal is the fluctuation of the short-term clock cycle. In this embodiment, the rising time difference of the ESPI clock signal is statistically analyzed by the FPGA. If the jitter exceeds ±10% of the ESPI clock cycle, it will reduce the reliability of the FPGA's sampling of the ESPI bus signal. The jitter of the ESPI clock signal is a short-term deviation of a single clock cycle in the ESPI clock signal from the ideal cycle. It can be determined by quickly, randomly, with small amplitude, and continuously obtaining the standard deviation and peak-to-peak value of N cycles. This embodiment does not impose any limitations on this.

[0045] ESPI clock signal drift refers to the slow, long-term change in the ESPI clock signal frequency, which is mostly caused by power supply ripple or temperature variations. It is necessary to monitor the stability of the ESPI clock signal's clock period under different operating conditions. The ESPI clock signal's clock period changes slowly and systematically over time divided by temperature, exhibiting a long-term average variation trend.

[0046] It should be noted that the ideal period for a 33MHz ESPI clock signal is 30.303ns. Signal jitter is essentially the degree to which the actual value of a continuous period deviates from the ideal value. FPGAs can detect this through the following steps: Continuously collect N consecutive ESPI_CLK cycles, such as 1024 cycles, and store them in the FPGA's internal RAM (Random Access Memory) or FIFO (First In First Out) queue; calculate the average value of these N cycles to eliminate random errors; then, calculate the deviation of each cycle from the average value, and count the peak-to-peak jitter, i.e., the maximum deviation minus the minimum deviation or the root mean square jitter (RMS); then compare it with the ESPI specification threshold, requiring the peak-to-peak jitter to be ≤10% of the ideal cycle, i.e., ≤3ns, otherwise it is judged as jitter exceeding the standard.

[0047] Peak-to-peak value is the core indicator for judging jitter, and it is more intuitive than RMS; in the ESPI specification, the peak-to-peak jitter of a 33MHz clock needs to be ≤3ns.

[0048] ESPI clock signal drift can be understood as a "slow change in the average value of the clock cycle". FPGA can detect this by statistically analyzing the average value of the ESPI clock cycle over different time periods, as follows: The ESPI clock signal time is divided into multiple "large windows," such as each large window containing 1024 eSPI_CLK cycles, approximately 31μs. The average value of each cycle within a large window is calculated. The change in the average value of adjacent windows is compared, or the slope of the average value over a long period (e.g., 1000 large windows) is calculated. If the rate of change of the average value exceeds a threshold, such as a change of >0.1ns per 1ms cycle, it is determined that the drift exceeds the limit. This embodiment uses a circular buffer to write addresses in a loop to implement "sliding window statistics," continuously updating the latest 1024 cycle values ​​to ensure the real-time performance of the detection. This achieves "always using the latest N clock cycles for real-time jitter calculation," discarding old and invalid data in the ESPI clock signal, thus balancing the real-time performance of the acquired data with the number of eSPI_CLK cycles acquired in the large window.

[0049] Before comparing changes in the mean or calculating the slope of the mean, the mean can be smoothed first. The smoothing process is as follows: first calculate the periodic mean of the small window, then analyze the changes in the periodic mean, and finally filter out the effects of jitter. It should be noted that drift and jitter of the ESPI clock signal must be determined separately.

[0050] Understandably, a small window is a split of a large window, used for mean filtering and jitter removal of the signal. For example, a small window might be 64 eSPI_CLK cycles, then a large window would be composed of 16 small windows. In this embodiment, the time conversion is: 1024 33MHz cycles ≈ 31μs, 1000 large windows ≈ 31ms. The core of drift is the "trend," not a single-point fluctuation; therefore, the "rate of change of the mean," i.e., the slope of the mean, is used as the basis for drift determination.

[0051] In the ESPI bus signal, the high level must be ≥0.7×VDD, such as the high level corresponding to a 1.8V ESPI bus signal being ≥1.26V; the low level (VOL) must be ≤0.3×VDD, such as the low level corresponding to a 1.8V ESPI bus signal being ≤0.54V. If the level in the ESPI bus signal does not meet the requirements, it will lead to logic recognition errors, such as misjudging a high level as a low level.

[0052] For the input pins of the FPGA, this embodiment defines a voltage threshold at the hardware level. For example, under the 1.8V level standard, a level greater than 1.1V is usually considered a high level, and a level less than 0.5V is considered a low level. At the software / logic level, it is only necessary to compare the signal value of the input pin with "1" (the logical representation of a high level) to determine whether it is a high level.

[0053] In level standard matching, FPGA pins need to be configured to the same level standard as the ESPI bus signals, such as 3.3V LVCMOS (Low-Voltage Complementary Metal-Oxide-Semiconductor, widely used in FPGA low-voltage digital logic level standards) or 1.8V LVCMOS. Otherwise, the FPGA cannot correctly identify high / low levels at the hardware level.

[0054] In high-level pulse detection, it is necessary to detect the "moment when the high level appears", rather than a continuous high level. This can be achieved by "beating and inverting", such as is_high_pulse=input_sig_sync2&~input_sig_sync1. This embodiment will not elaborate on this.

[0055] To test the signal noise tolerance, it is necessary to measure the difference between the corresponding signal level and the threshold. The smaller the noise tolerance, the weaker the anti-interference ability. The influence of the device load on the signal can be judged by comparing the level changes under no load and with load.

[0056] The essence of noise margin is the comparison between the effective voltage level and the logic threshold range. For example, it is stipulated that "the high level must be higher than Vih (minimum input high level) + noise margin, and the low level must be lower than Vil (maximum input low level) - noise margin". The FPGA determines whether the acquired signal is within this effective range through logic design.

[0057] If the shunted monitoring ESPI bus signal is a digital logic level, such as LVCMOS 3.3V, the FPGA does not require ADC conversion and directly determines the noise margin based on the "level settling time". The core steps involved include the following: Asynchronous signal synchronization: The external ESPI bus signal is asynchronous (not synchronized with the FPGA's system clock). First, the ESPI bus signal is "stamped" through two levels of registers inside the FPGA to synchronize it with the FPGA's system clock domain, thereby eliminating metastability and avoiding misjudgment of subsequent levels.

[0058] It should be noted that noise margin is expressed as the "minimum time for level stability"—that is, only when the signal level remains stable for a period exceeding this minimum time is it considered valid. Level transitions shorter than this minimum time are considered noise glitches.

[0059] The relative noise margin of the specific ESPI bus signal can be determined through stability counting, as follows: An internal counter is set up in the FPGA. When the level of the synchronized ESPI bus signal changes, the counter is immediately reset to zero. If the level of the ESPI bus signal remains unchanged, the counter starts to accumulate. The counting unit of the counter is the system clock cycle. When the counter value reaches the number of clock cycles corresponding to the noise margin time, for example, if the noise margin is 10ms and the clock frequency in the synchronized ESPI bus signal is 50MHz, the counter needs to count 500,000 times to determine that the level is a "valid level". If the level changes again before the counter reaches the threshold (500,000), the counter is reset to zero and the level is never determined to be valid, thus filtering out noise glitches.

[0060] Regarding the maintenance of the level state, once the FPGA determines that the level is valid high or low, the FPGA will maintain the determination result until the signal level stabilizes again for more than the noise margin time and then jumps, thereby avoiding frequent switching of the decision signal output by the FPGA.

[0061] In a further optional embodiment of this example, the FPGA uses a "multi-phase clock sampling" method to sample ESPI_DATA at multiple points within one cycle of ESPI_CLK, thereby verifying whether the setup time Tsu and hold time Th are abnormal.

[0062] Specifically, the steps for determining whether the quality of the ESPI bus signal is abnormal by judging whether the sampled data conforms to the ESPI protocol specification include steps S1021 to S1024.

[0063] Step S1021: Based on the frequency of the ESPI clock signal, generate a set of phase-shifted multi-phase sampling clocks.

[0064] The multi-phase sampling clock covers the entire cycle of the ESPI clock signal; the phase of the multi-phase sampling clock can be 0°, 90°, 180°, 270°, or a more refined 16-phase, which is not limited in this embodiment.

[0065] Step S1022: Use a multi-phase sampling clock to sample the protocol frame data signal in parallel, and obtain multiple level values ​​of the protocol frame data signal at different time points within one cycle of the ESPI clock signal. For example, 16-phase sampling corresponds to 16 sampling points, covering the clock cycle from 0 to 360°.

[0066] Step S1023: Calculate the effective sampling window based on the setup time and hold time specified in the ESPI protocol.

[0067] In a further optional embodiment of this embodiment, the step of calculating the effective sampling window according to the setup time and hold time of the ESPI protocol specification includes: taking the time period of setup before the rising edge of the ESPI clock signal and the time period of hold time after the rising edge of the ESPI clock signal as the effective sampling window.

[0068] For example, if the period of ESPI_CLK is T, and the ESPI protocol requires Tsu=2ns, Th=1ns, and the clock frequency=100MHz, then the effective sampling window is: 2ns before the rising edge of ESPI_CLK (setup time) to 1ns after the rising edge (hold time), corresponding to a clock phase of "20% of the period before the rising edge" to "10% of the period after the rising edge".

[0069] Step S1024: Verify whether all level values ​​fall within the valid sampling window, and determine whether the protocol frame data signal is abnormal based on the verification results.

[0070] This embodiment employs a set of sampling clocks with uniformly offset phases to perform high-density parallel sampling of the eSPI data signal, transforming the abstract time parameters (Tsu and Th) into quantifiable phase windows, i.e., effective sampling windows. By verifying the consistency of sampled values ​​within the effective sampling window, it determines whether the ESPI clock signal is abnormal. Essentially, it transforms "time domain stability verification" into "phase domain sampling point analysis," reducing the complexity and labor costs of ESPI bus signal quality measurement, and improving the accuracy and efficiency of ESPI bus signal quality measurement.

[0071] In a further optional embodiment of this example, before the step of generating a set of phase-shifted multi-phase sampling clocks based on the frequency of the ESPI clock signal, the method further includes performing clock synchronization processing and data synchronization processing on the ESPI bus signals respectively. The clock synchronization processing includes: generating a local sampling clock for the handshake management circuit module synchronized with the ESPI clock signal; the data synchronization processing includes: synchronizing the protocol frame data signal to the local sampling clock domain of the handshake management circuit module.

[0072] This embodiment eliminates register metastability by completing clock synchronization and data synchronization processing, thereby ensuring the basic stability of FPGA acquisition of ESPI bus signals.

[0073] In a further optional embodiment of this embodiment, the method further includes: quantifying the judgment result of whether the quality of the ESPI bus signal is abnormal by determining whether the sampled data conforms to the ESPI protocol specification into multi-field information containing at least an abnormal flag bit and an abnormal parameter type identifier; and sending the multi-field information to the host computer in the form of a serial port.

[0074] By sending the judgment results to the host computer, operators can quickly and clearly understand the quality of the ESPI bus signal. If a problem occurs in the interaction between the master and slave devices, it can be directly located to determine whether the problem is with the ESPI bus signal.

[0075] In a further optional embodiment of this example, the handshake management circuit module is electrically connected to the host computer via a UART interface. The step of sending multi-field information to the host computer in serial form includes: packaging the multi-field information into a continuous byte stream according to the UART data frame format, and sending it to the host computer in serial form.

[0076] In this embodiment, the FPGA encapsulates each measurement result of the signal for frequency, duty cycle, clock jitter, drift, noise margin, high level and low level into a fixed format frame structure and sends it to the host computer. After parsing, the host computer can directly display or store the measurement results.

[0077] The format of the frame structure is defined as follows:

[0078] In the table above, 0x2E: the serial port ID connecting the FPGA to the host computer; Indicator type: For example, the indicator of high level is defined as 0x03; Data length: The length of bytes after quantizing the judgment result of each indicator; Valid data: The actual data transmitted, the quantized bytes of the judgment result for each indicator; Parity bit: Used for simple error detection, such as odd parity or even parity; Stop bit: Logic 1, indicating the end of the data frame.

[0079] The host computer connects to the serial port tool and program on the FPGA. After receiving the byte stream, it first identifies the start character 0x7E, then extracts the data according to the field length, verifies whether there are any abnormalities, and finally parses out the judgment result of the monitoring indicators.

[0080] The method for measuring the quality of the ESPI bus signal provided by this invention achieves hardware-level monitoring and processing of the ESPI bus signal by inserting a handshake management circuit module between the PCH and the ESPI slave device.

[0081] Secondly, one embodiment of the present invention provides a measurement device for the quality of ESPI bus signals, combined with... Figure 2 The measuring device is used to implement the method as described in any of the first aspects.

[0082] In this embodiment, the measuring device includes a handshake management circuit module as described in the first aspect.

[0083] In a further optional embodiment of this embodiment, the measuring device may also include a host computer as described in the first aspect.

[0084] In the description of this specification, the references to terms such as "some embodiments," "other embodiments," "ideal embodiments," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example that are included in at least one embodiment or example of this application. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0085] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0086] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method for measuring the quality of an ESPI bus signal, characterized in that, The method is applied to a handshake management circuit module, which is electrically connected to the ESPI interface on the host device. The method includes: When the master device and the slave device communicate via the ESPI bus, the ESPI bus is monitored and the monitored ESPI bus signals are sampled to obtain sampled data; The quality of the ESPI bus signal is confirmed to be abnormal by determining whether the sampled data conforms to the ESPI protocol specification.

2. The method according to claim 1, characterized in that, The step of listening to the ESPI bus and sampling the listened ESPI bus signals to obtain sampled data when the master device and slave device communicate via the ESPI bus includes: When the master device and the slave device communicate through the ESPI bus, the sampling data is obtained by copying the ESPI bus signal from the ESPI bus through the high-impedance buffer of the handshake management circuit module.

3. The method according to claim 2, characterized in that, The step of copying the ESPI bus signal from the ESPI bus through the high-impedance buffer of the handshake management circuit module to obtain the sampled data when the master device and the slave device communicate through the ESPI bus includes: When the master device and the slave device communicate through the ESPI bus, the sampled data is obtained by copying the ESPI clock signal and protocol frame data signal on the ESPI bus through the high-impedance buffer.

4. The method according to claim 3, characterized in that, The handshake management circuit module includes an FPGA, the method is applied to the FPGA, and the FPGA is configured with a reference clock with a frequency higher than that of the ESPI clock signal. The step of determining whether the quality of the ESPI bus signal is abnormal by judging whether the sampled data conforms to the ESPI protocol specification includes: The sampled data is analyzed to obtain evaluation data; the evaluation data includes one or more of the following parameters corresponding to the ESPI bus signal: noise tolerance parameter, clock jitter parameter, high level parameter, and low level parameter. Based on whether the evaluation data conforms to the ESPI protocol specification, confirm whether the frequency, duty cycle, clock jitter, drift, noise margin, high level and low level of the ESPI clock signal, as well as the noise margin, high level and low level of the protocol frame data signal, are abnormal.

5. The method according to claim 3, characterized in that, The step of determining whether the quality of the ESPI bus signal is abnormal by judging whether the sampled data conforms to the ESPI protocol specification includes: Based on the frequency of the ESPI clock signal, a set of phase-shifted multi-phase sampling clocks is generated, which cover the entire cycle of the ESPI clock signal; The protocol frame data signal is sampled in parallel using the multi-phase sampling clock to obtain multiple level values ​​of the protocol frame data signal at different time points within one cycle of the ESPI clock signal; The effective sampling window is calculated based on the setup and hold times specified in the ESPI protocol. Verify that all the stated level values ​​fall within the valid sampling window, and determine whether the protocol frame data signal is abnormal based on the verification results.

6. The method according to claim 5, characterized in that, The step of calculating the effective sampling window based on the setup and hold times specified in the ESPI protocol includes: The effective sampling window is defined as the time interval between the setup time before the rising edge of the ESPI clock signal and the time interval between the hold time after the rising edge of the ESPI clock signal.

7. The method according to claim 5, characterized in that, Before the step of generating a set of phase-shifted multi-phase sampling clocks based on the frequency of the ESPI clock signal, the method further includes: Generate a local sampling clock for the handshake management circuit module that is synchronized with the ESPI clock signal; The protocol frame data signal is synchronized to the local sampling clock domain of the handshake management circuit module.

8. The method according to any one of claims 1 to 7, characterized in that, The method further includes: The judgment result of determining whether the quality of the ESPI bus signal is abnormal by judging whether the sampled data conforms to the ESPI protocol specification is quantified into multi-field information that includes at least an abnormality flag bit and an abnormality parameter type identifier. The multi-field information is sent to the host computer via serial port.

9. The method according to claim 8, characterized in that, The handshake management circuit module is electrically connected to the host computer via a UART interface; The step of sending the multi-field information to the host computer via serial port includes: The multi-field information is packaged into a continuous byte stream according to the UART data frame format and sent to the host computer via serial port.

10. A device for measuring the quality of an ESPI bus signal, characterized in that, The measuring device is used to implement the method as described in any one of claims 1 to 9.

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