A hardware BFD link detection method and system based on trend prediction and multi-dimensional evaluation

Abstract

The application discloses a kind of hardware BFD link detection method and system based on trend prediction and multidimensional evaluation, belong to network communication technical field.The application integrates BFD processing engine in switching chip, executes the transceiving processing and state machine maintenance of BFD message in hardware mode, without central processing unit packet by packet participation;Based on sliding window, BFD message transmission delay sample is maintained in real time, delay mean and standard deviation are calculated in real time recursively, and fault determination threshold is dynamically updated;By monitoring delay change trend, priority is pre-promoted, link health degree is evaluated in multiple dimensions by combining delay, jitter and packet loss rate, and a hierarchical decision-making system is constructed, including pre-promotion, multi-level priority adjustment, priority rollback, long-term no improvement determination and link protection switchover.The application can effectively improve the accuracy and reliability of network fault detection.

Description

Technical Field

[0001] This invention relates to the field of network communication technology, and specifically to a hardware BFD link detection method and system based on trend prediction and multi-dimensional evaluation. Background Technology

[0002] BFD is an international standard protocol for rapid network link detection, providing a lightweight, short-duration, fast fault detection service for various upper-layer control protocols. BFD establishes sessions on network devices at both ends of the link and periodically sends detection messages to the other end to quickly detect interface faults, link faults, and node forwarding engine faults along the forwarding path.

[0003] In existing technologies, BFD is mainly implemented through two approaches: pure software implementation and a combination of software and hardware. The pure software implementation maintains the BFD session through software programming, with the central processing unit (CPU) handling all aspects of BFD message transmission, reception, parsing, and state machine maintenance. The combined software and hardware approach, on the other hand, uses software to call the software development kit (SDK) of a dedicated BFD chip, allowing the chip to implement some of the BFD session maintenance functions.

[0004] Patent application CN102064981A discloses a bidirectional forwarding detection method and system. This scheme detects packet loss rate by using the sequence number carried in BFD packets, and detects latency and jitter by using timestamps. The detection results are then compared with thresholds set by the service and reported. However, this scheme is entirely software-based, with BFD protocol processing handled by a software protocol stack. This results in CPU processing latency and software scheduling jitter, making it difficult to meet the millisecond-level detection accuracy requirements.

[0005] Existing technologies already include mature approaches that offload BFD processing to hardware. Hardware-offloaded BFD moves the detection process to an application-specific integrated circuit (ASIC), where hardware handles packet transmission and reception, tracks timeouts, and determines session status in real time. After the control plane initializes the BFD session configuration, it sends parameters to the forwarding chip via a software development kit (SDK). The chip hardware directly identifies and processes BFD packets, and the central processing unit (CPU) no longer participates in processing each packet. The IETF has released a draft standard for the YANG data model for hardware BFD offloaded session management, further demonstrating the maturity of this technology.

[0006] However, existing hardware BFD solutions primarily focus on offloading BFD message transmission and reception and state machine maintenance from the central processing unit to hardware, and still have shortcomings in adaptive adjustment of detection thresholds, predictive assessment of link quality, and tiered response decision-making. Existing solutions often employ fixed threshold mechanisms for fault diagnosis, lacking the ability to adaptively adjust thresholds based on real-time statistics; detection decisions are mostly based on single-point judgments of the current state, lacking proactive intervention mechanisms based on trend prediction; and link quality assessments are mostly based on single indicators, lacking multi-dimensional comprehensive assessment and tiered response capabilities.

[0007] Therefore, it is evident that the existing technology lacks an adaptive BFD link detection scheme that can realize hardware-based processing of the entire BFD protocol process, calculate dynamic thresholds based on real-time sliding window recursion, and has trend prediction and multi-dimensional evaluation capabilities. Summary of the Invention

[0008] The present invention aims to provide a hardware BFD link detection scheme based on trend prediction and multi-dimensional evaluation, thereby overcoming the technical problems of central processing unit processing latency, fixed threshold mechanism and lack of predictive evaluation capability in existing BFD detection schemes.

[0009] To achieve the above objectives, the present invention provides the following technical solution:

[0010] Solution 1: The present invention provides a hardware BFD link detection method based on trend prediction and multi-dimensional evaluation, comprising:

[0011] Hardware processing steps: A BFD processing engine is integrated into the switching chip. The BFD processing engine performs the sending and receiving of BFD messages and the maintenance of the state machine in hardware. The sending and receiving of BFD messages and the maintenance of the state machine do not require the central processing unit to participate in each packet.

[0012] Dynamic threshold calculation steps: Based on a sliding window, maintain the transmission delay samples of the most recent N BFD messages in real time, calculate the delay statistical feature value in real time according to the transmission delay samples, and update the fault judgment threshold in real time according to the delay statistical feature value.

[0013] Trend prediction step: Monitor the changing trend of transmission delay values ​​of multiple consecutive BFD messages. When the predicted delay value based on the changing trend meets the preset conditions, trigger the priority pre-boost signal.

[0014] Multi-dimensional evaluation steps: Obtain multiple quality parameters of the link, and calculate the health score of the current link based on the multiple quality parameters;

[0015] Hierarchical decision-making and execution steps: Based on the priority pre-boost signal, the health score, and the fault determination threshold, hierarchical decision-making is performed: when the priority pre-boost signal is triggered, the transmission priority of the BFD message is increased; when the health score is in different preset ranges, the corresponding level of priority boost is performed; when the health score meets preset fault conditions, the number of consecutive packet losses reaches a preset threshold, or the transmission delay value exceeds the fault determination threshold, link protection switching is triggered.

[0016] In one embodiment of this method, during the hardware processing step, the BFD processing engine performs the following hardware processing operations:

[0017] The sequence number generation unit generates a sequence number for each BFD message to be sent based on a hardware counter, and writes the sequence number into the header of the BFD message.

[0018] The message transceiver unit interacts with the on-chip cache via direct memory access, sending BFD messages with the sequence number and receiving BFD messages sent by the peer.

[0019] The received BFD messages are parsed in real time by the message parsing unit, and the sequence number and timestamp information in the BFD messages are extracted.

[0020] The sequence number verification unit compares the extracted received message sequence number with the expected sequence number to determine message continuity and detect continuous packet loss.

[0021] The timestamps for sending and receiving each BFD message are recorded using a timestamp recording unit.

[0022] The delay calculation unit calculates the one-way delay value of each BFD message based on the sending timestamp and the receiving timestamp;

[0023] The state of the BFD session is maintained through the state maintenance unit.

[0024] In one embodiment of this method, in the dynamic threshold calculation step, the delay statistical feature value is calculated in real time based on the Welford algorithm. The delay statistical feature value includes the delay mean μ and the delay standard deviation σ.

[0025] In one embodiment of this method, in the dynamic threshold calculation step, the fault determination threshold is μ±Kσ, where μ is the mean delay, σ is the standard deviation of the delay, and K is a configurable parameter.

[0026] In one embodiment of this method, the plurality of quality parameters include latency parameters, jitter parameters, and packet loss rate parameters; the health score is calculated using a normalized weighted summation model.

[0027] In one embodiment of this method, the preset condition in the trend prediction step is: the transmission delay value shows a monotonically increasing trend and the delay value predicted based on the monotonically increasing trend exceeds the warning threshold within a preset period.

[0028] In one embodiment of this method, in the hierarchical decision-making and execution steps, the link protection switching is executed by notifying the control plane via a hardware interrupt.

[0029] In one embodiment of this method, the step of hierarchical decision-making and execution, which involves increasing the transmission priority of a BFD message, includes modifying the differential service code point field value of the BFD message.

[0030] Solution 2: The present invention also provides a hardware BFD link detection system based on trend prediction and multi-dimensional evaluation, including a BFD processing engine, a dynamic threshold calculation module, a trend prediction module, a multi-dimensional evaluation module, and a hierarchical decision and execution module, all of which are integrated into the switching chip.

[0031] In one embodiment of this system solution, the BFD processing engine includes:

[0032] A sequence number generation unit generates a sequence number for each BFD message to be sent based on a hardware counter, and writes the sequence number into the header of the BFD message.

[0033] The message transceiver unit interacts with the on-chip cache via direct memory access, sends BFD messages with the sequence number, and receives BFD messages sent by the peer.

[0034] The message parsing unit parses the received BFD messages in real time and extracts the sequence number and timestamp information from the BFD messages.

[0035] The sequence number verification unit compares the extracted received message sequence number with the expected sequence number to determine message continuity and detect continuous packet loss.

[0036] A timestamp recording unit records the sending timestamp and receiving timestamp of each BFD message;

[0037] A delay calculation unit calculates the one-way delay value of each BFD message based on the sending timestamp and the receiving timestamp;

[0038] A state maintenance unit maintains the BFD session state.

[0039] This invention implements full-process hardware processing of the BFD protocol through a hardware BFD processing engine, avoiding CPU processing latency and software scheduling jitter; it uses a sliding window to dynamically push thresholds in real time, enabling fault determination thresholds to adapt to changes in network status; it achieves early intervention through trend prediction; it achieves precise graded response through multi-dimensional health assessment; it avoids long-term occupation of high-priority resources through a priority fallback mechanism; and it distinguishes between temporary congestion and fundamental link failure through a long-term no-improvement determination mechanism. The synergistic effect of these technical features enables accurate, real-time, predictive detection and graded response to BFD link status. Attached Figure Description

[0040] The present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0041] Figure 1 This is a block diagram illustrating the structural principle of the BFD processing engine in this invention.

[0042] Figure 2 This is a block diagram of the overall architecture of the hardware BFD link detection system based on trend prediction and multi-dimensional evaluation in this invention.

[0043] Figure 3 This is a flowchart illustrating the dynamic threshold calculation steps in this invention.

[0044] Figure 4 This is a schematic diagram illustrating the collaborative decision-making between the trend prediction step and the multi-dimensional evaluation step in this invention.

[0045] Figure 5 This is a schematic diagram of the decision-making logic of the hierarchical decision-making and execution steps in this invention. Detailed Implementation

[0046] To make the technical means, creative features, objectives and effects of this invention easier to understand, the invention will be further described below with reference to specific illustrations.

[0047] This invention presents a hardware-accelerated Bidirectional Forwarding Detection (BFD) link state detection scheme. It implements full-process hardware processing of the BFD protocol through a hardware BFD processing engine, avoiding CPU processing latency and software scheduling jitter. This invention integrates the BFD processing engine into the switching chip, realizing full-process hardware processing of BFD packets from generation, sending, receiving, parsing, verification, timestamp recording, latency calculation to state machine maintenance. During the steady-state detection phase after BFD session establishment, the entire BFD packet transmission and reception process and state machine maintenance path do not require CPU participation on a packet-by-packet basis. The CPU is only responsible for initial configuration and parameter distribution during session establishment, and receives hardware interrupt notifications and executes corresponding routing policy adjustments when the session state changes.

[0048] Furthermore, the present invention also uses a sliding window to recursively push the dynamic threshold in real time, enabling the fault determination threshold to adapt to changes in network state. The present invention maintains latency samples of the most recent N BFD packets in real time using a sliding window, and calculates the mean latency μ and standard deviation σ in real time using a recursive algorithm to dynamically update the fault determination threshold. Compared with existing threshold calculation methods based on long-period historical data statistics, the threshold of the present invention can be updated in real time with each frame of network state change.

[0049] Furthermore, the present invention achieves precise graded response through trend prediction and multi-dimensional health assessment. This invention introduces two pre-processing steps—trend prediction and multi-dimensional health assessment—on top of the traditional "detection → judgment → execution" approach. Early intervention is achieved by monitoring latency trends; a refined graded response is achieved by calculating link health scores based on multiple link quality parameters. Furthermore, the graded decision-making system of this invention also includes a priority fallback mechanism and a long-term no-improvement judgment mechanism, making the decision-making logic more comprehensive.

[0050] Based on the above technical mechanism, this invention provides a hardware BFD link detection method based on trend prediction and multi-dimensional evaluation. This detection method includes the following five steps:

[0051] Step S1, Hardware Processing Steps:

[0052] This step provides an integrated BFD processing engine in the switching chip, which performs BFD message generation, sending, receiving, parsing, verification, timestamp recording, delay calculation, and state machine maintenance operations in hardware.

[0053] In the steady-state detection phase after the BFD session is established, the above operations do not require the central processing unit to participate on a packet-by-packet basis.

[0054] This step provides high-precision, low-latency raw data for subsequent threshold calculations, trend predictions, multi-dimensional evaluations, and hierarchical decisions, serving as the data foundation layer for the entire detection method. This step continuously outputs raw data such as the latency value, sequence number, and timestamp of the BFD message as input for subsequent steps.

[0055] Step S2, Dynamic Threshold Calculation Steps:

[0056] This step uses a sliding window to maintain real-time transmission delay samples of the N most recent BFD messages, calculates the mean delay μ and standard deviation σ in real time, and then calculates and updates the fault determination threshold accordingly, storing the threshold in a hardware register. This step is used to establish an adaptive judgment benchmark that can change in real time with the network status.

[0057] Step S2 obtains the delay value of each BFD message from step S1 as the input sample for the sliding window; the fault judgment threshold output by this step is used as one of the judgment conditions for link protection switching in step S5.

[0058] Step S3, Trend Prediction Step:

[0059] This step monitors the changing trend of transmission delay values ​​for multiple consecutive BFD messages. When the delay value predicted based on the changing trend meets preset conditions, a priority pre-elevation signal is triggered. This step is used to achieve early intervention, taking preventative measures before the link quality deteriorates to the point of triggering a fault determination.

[0060] Step S3 obtains the delay values ​​of multiple consecutive BFD messages from step S1 as input for trend analysis; the priority pre-boost signal output by this step serves as one of the independent conditions for triggering priority boost in step S5.

[0061] Step S4, Multi-dimensional Evaluation Steps:

[0062] This step acquires multiple quality parameters of the link and calculates the current link's health score based on these parameters. This step is used to comprehensively evaluate link quality from multiple dimensions, avoiding the one-sidedness of judging by a single indicator.

[0063] Step S4 obtains the link quality parameters from step S1; the health score output in this step serves as the core basis for the hierarchical decision in step S5.

[0064] Step S5, Hierarchical Decision-Making and Execution Steps:

[0065] This step performs tiered decision-making based on priority pre-boost signals, health scores, and fault determination thresholds: Priority is increased when a pre-boost signal is triggered; different levels of priority boosting are implemented when the health score falls within different ranges; priority rollback is implemented when the health score remains within a healthy range for a preset number of periods; the response magnitude is escalated or link protection switching is triggered when the health score remains within the first preset range for a preset number of periods; link protection switching is triggered when the health score falls within the second preset range for a preset number of periods; and link protection switching is triggered when the health score meets fault conditions, the number of consecutive packet losses reaches a preset threshold, or the latency exceeds a fault determination threshold. This step is used to achieve differentiated and precise responses, avoiding overreaction or underreaction caused by a single response mechanism.

[0066] In the hardware BFD link detection method based on trend prediction and multi-dimensional evaluation formed by the above steps, step S1, as the data foundation layer, continuously provides raw data to steps S2, S3, and S4; step S2 provides dynamic threshold calculation results (based on warning thresholds) to step S3 and fault judgment thresholds to step S5; steps S3 and S4 are executed in parallel, respectively outputting pre-boost signals and health scores to step S5; step S5 comprehensively receives all input signals and performs the final hierarchical decision and response.

[0067] Based on an understanding of the overall function and logical coordination of the above steps, the following section will further illustrate the specific implementation plans for each step from a technical implementation perspective.

[0068] As a specific example of an implementable method, step S1 in this method can be implemented using the following specific scheme:

[0069] First, see Figure 1 This illustrates the structural principle of the BFD processing engine used in step 1 of this method. Combined with... Figure 1 This BFD processing engine consists of seven functional units composed of hardware logic: a sequence number generation unit 111, a message sending and receiving unit 112, a message parsing unit 113, a sequence number verification unit 114, a timestamp recording unit 115, a delay calculation unit 116, and a status maintenance unit 117.

[0070] Based on this, each functional unit is configured to perform hardware processing operations in the following manner:

[0071] (1) Sequence number generation operation: The sequence number generation unit generates a unique incrementing sequence number for each BFD message to be sent based on a hardware counter. Each time a BFD message needs to be sent, the current counter value is read as the sequence number of the message, and after the sequence number is written into the header field of the BFD message, the counter automatically increments.

[0072] (2) Message transmission and reception operations: The message transmission and reception unit directly connects to the network physical port of the switching chip through a hardware interface to perform message transmission and reception. In the transmission direction, the BFD message data to be sent is read from the chip's internal buffer via direct memory access and sent to the network physical port; in the reception direction, BFD messages are received from the network physical port and the message data is written to the chip's internal buffer via direct memory access. The entire transmission and reception process does not require the central processing unit to participate in each packet.

[0073] (3) Message parsing operation: The message parsing unit performs message parsing through a hardware state machine and multi-stage pipelined logic circuits. Upon receiving a BFD message, the message data is read from the buffer, and the header fields of the BFD message are parsed in real time through a multi-stage pipeline to extract the values ​​of the sequence number field and the timestamp field. During the parsing process, message validity is checked simultaneously, and messages that do not conform to the specifications are directly discarded at the hardware level.

[0074] (4) Sequence Number Verification Operation: The sequence number verification unit performs sequence number verification through a hardware comparator. Internally, it maintains an expected sequence number register, obtains the sequence number of the currently received message from the message parsing operation, and compares the sequence number with the value in the expected sequence number register in real time. If they match, the messages are considered continuous, and the expected sequence number register is updated; if the sequence numbers are not continuous, a packet loss event is triggered, and the continuous packet loss count is recorded.

[0075] (5) Timestamp recording operation: The timestamp recording unit performs timestamp recording through a high-precision hardware clock and a dedicated register group. In the transmitting direction, the hardware automatically captures the value of the current hardware clock as the transmitting timestamp when the message leaves the chip port; in the receiving direction, the hardware automatically captures the value of the current hardware clock as the receiving timestamp when the message parsing operation identifies the BFD message header.

[0076] (6) Delay Calculation Operation: The delay calculation unit performs the delay calculation through a hardware subtractor logic. The receive and send timestamps of the same BFD message are obtained from the timestamp recording operation, and the difference between the two is calculated using the hardware subtractor to obtain the one-way delay value of the message. In a network environment using the IEEE 1588v2 precision time protocol for clock synchronization, the clock deviation between the transmitting and receiving ends can be controlled within the sub-microsecond level. In this case, the delay value obtained by direct subtraction has sufficient measurement accuracy. In environments without precision time protocol synchronization conditions, this delay value is mainly used for relative comparison of dynamic thresholds. The clock deviation, as a system constant, cancels out each other during the calculation of the mean and standard deviation of the sliding window, and does not affect the fault determination results based on statistical characteristics.

[0077] (7) State maintenance operation: The state maintenance unit performs BFD session state maintenance through a hardware state machine. Internally, it maintains the state of the current BFD session (including Down, Init, Up, etc.), obtains the state field from the received message from the message parsing operation, obtains the link continuity state from the sequence number verification operation, and combines the locally maintained current session state to determine and execute state transitions through hardware parallel logic.

[0078] Furthermore, in this step, when performing hardware-based processing of the entire BFD protocol process through the BFD processing engine, a unique sequence number is assigned to each transmitted message through sequence number generation; physical transmission and reception of messages are completed through message transmission and reception operations; sequence numbers and timestamps are extracted from received messages through message parsing operations; message continuity and packet loss are determined based on sequence numbers through sequence number verification operations; accurate transmission and reception times are provided through timestamp recording operations; delay values ​​are calculated based on timestamps through delay calculation operations; and the BFD session state machine is maintained by integrating the above information through state maintenance operations. All these operations are completed at the hardware level, forming a complete hardware processing flow for BFD messages.

[0079] As a specific example of an implementable method, step S2 in this method can be implemented in the following way:

[0080] Figure 3 The flowchart of the dynamic threshold calculation step in the method of the present invention is shown. See also Figure 3 In step S2 of the method of the present invention, a dynamic threshold calculation operation is performed in the switching chip. The specific implementation of this step includes the following sub-steps:

[0081] Step S2-1: Initialize the sliding window. Set the window capacity N and maintain a latency sample queue using a first-in-first-out (FIFO) strategy.

[0082] Step S2-2: Obtain the delay value D_new for each BFD message from the delay calculation operation in step S1. Whenever a new delay value is calculated, input the value into the sliding window.

[0083] Step S2-3: Determine if the sliding window is full. If not, add D_new directly to the window; if full, remove the oldest delay value D_old from the window and then add D_new to the window.

[0084] Step S2-4: Calculate the mean delay μ and standard deviation σ of the delay samples within the window using the Welford algorithm in real time. The specific recursive formula is as follows:

[0085] μ_window = μ_window-1 + (D_new - D_old) / N;

[0086] M_window = M_window-1 + (D_new - μ_window-1)·(D_new - μ_window);

[0087] ;

[0088] Where μ_window is the mean window delay after the update, μ_window-1 is the mean window delay before the update, D_new is the delay value of the newly arrived BFD message, D_old is the old delay value of the window that was removed (D_old is 0 when the sliding window is not full), M_window is the cumulative squared difference of the window after the update, M_window-1 is the cumulative squared difference of the window before the update, and σ_window is the standard deviation of the window delay after the update.

[0089] The aforementioned recursive calculation scheme allows this algorithm to complete the recursive calculation by maintaining only two state variables: the mean μ and the cumulative squared difference M. It eliminates the need to store all historical sample data, resulting in a constant memory footprint of O(1). This makes it particularly suitable for hardware implementation, requiring only a small number of registers for real-time statistics. Compared to existing schemes that recalculate based on all historical data, the recursive algorithm of this invention significantly reduces hardware overhead and computational latency, enabling real-time threshold updates upon the arrival of each BFD message.

[0090] Step S2-5: Based on the calculated μ_window and σ_window, calculate the fault determination threshold θ = μ_window ± K·σ_window, where K is a configurable parameter. Store the calculated threshold in a hardware register and update it in real time. This fault determination threshold is updated with the arrival of each BFD message frame, accurately reflecting the real-time status of the current link.

[0091] As a specific example of an implementable method, step S3 in this method can be implemented in the following way:

[0092] Figure 4 This illustrates the collaborative decision-making principle of the trend prediction step and the multi-dimensional evaluation step in the method of this invention. See also Figure 4 In the method of this invention, step S3 performs a trend prediction operation in the switching chip, achieving early intervention by monitoring the changing trend of the latency values ​​of multiple consecutive BFD messages. The trend prediction step and the multi-dimensional evaluation step are executed in parallel, and both output pre-boost signals and health scores to the hierarchical decision-making step, respectively.

[0093] As further explanation, the specific implementation of this step includes the following sub-steps:

[0094] Step S3-1: Obtain the delay value sequence D_1, D_2, ..., D_M of M consecutive BFD messages from the delay calculation operation in step S1, where M is the preset trend analysis window size (preferably ranging from 10 to 30).

[0095] Step S3-2: Calculate the first-order difference of the delay value sequence, that is, calculate the difference Δ_i = D_i - D_{i-1} (i=2,3,...,M) between two adjacent delay values. The first-order difference reflects the direction and magnitude of the delay value change between adjacent messages.

[0096] Step S3-3: Determine a monotonically increasing trend. When P consecutive first-order differences are all positive (P is a preset parameter, preferably ranging from 5 to 10), the delay value is determined to have a monotonically increasing trend. This determination method can effectively filter out normal fluctuations in delay in the network, triggering the prediction mechanism only when the delay continues to deteriorate, thus avoiding false triggering caused by instantaneous fluctuations.

[0097] Step S3-4: Perform trend prediction. Based on the determination of a monotonically increasing trend, calculate the average of the most recent P first-order differences as the trend slope. This slope is used to quantify the rate of latency deterioration within consecutive detection periods; a larger slope indicates a faster decline in link quality. Calculate the predicted latency value D_predict using the following formula. This predicted value is used to assess the potential latency value after T detection periods under the current deterioration trend:

[0098] slope = (1 / P)·Σ_{j=M-P+1}^{M} (D_j - D_{j-1});

[0099] D_predict = D_M + slope × T;

[0100] Where T is the preset prediction period (preferably ranging from 3 to 5 detection periods).

[0101] Step S3-5: Compare the predicted value D_predict with the warning threshold. If D_predict exceeds the warning threshold, a priority pre-boost signal is triggered. This warning threshold can be set to μ+1 / 2Kσ.

[0102] Compared to existing technologies that only trigger a response after the link quality deteriorates to a preset threshold, which is a "reactive" mechanism, the trend prediction step in this invention, by monitoring and predicting the trend of latency changes, triggers a pre-boost signal before the link quality deteriorates to a fault threshold, thus achieving "predictive" early intervention.

[0103] As a specific example of an implementable method, step S4 in this method can be implemented in the following way:

[0104] See here. Figure 4 This also illustrates the principle of the multi-dimensional evaluation step in this invention. Combined with... Figure 4 In step S4 of the method of this invention, a multi-dimensional evaluation operation is performed in the switching chip to obtain multiple quality parameters of the link from step S1, including but not limited to latency parameters, jitter parameters, and packet loss rate parameters. After normalizing each parameter, this step calculates the link health score using a weighted summation model.

[0105] The specific implementation of this step includes the following sub-steps:

[0106] Step S4-1: Obtain the link's latency parameters, jitter parameters, and packet loss rate parameters from step S1. The latency parameters are obtained from the latency calculation operation; the jitter parameters are obtained by calculating the absolute value of the difference between adjacent latency values; and the packet loss rate is obtained from the sequence number verification operation (by statistically analyzing the ratio of consecutive packet loss events to the total number of packets).

[0107] Step S4-2: Normalize the above three parameters, mapping the latency, jitter, and packet loss rate to the [0,1] interval respectively, to obtain the normalized latency value D_norm, the normalized jitter value J_norm, and the normalized packet loss rate L_norm. The reference maximum value used during normalization is preset through the configuration register and configured by the network administrator based on the service level agreement requirements or historical statistical data.

[0108] Step S4-3: Construct a link health assessment model and calculate the health score using the following formula:

[0109] H = α·D_norm + β·J_norm + γ·L_norm;

[0110] α, β, and γ are configurable weighting coefficients, and α + β + γ = 1. The default values ​​for α, β, and γ can be set to 0.5, 0.3, and 0.2, respectively. These weighting coefficients can be adjusted via configuration registers for different application scenarios.

[0111] Step S4-4: Calculate the health score H of the current link based on the values ​​of D_norm, J_norm, and L_norm. The smaller the H value, the better the link quality.

[0112] Compared to existing technologies that typically rely on a single metric to judge link quality, resulting in a one-sided assessment, this multi-dimensional evaluation method integrates latency, jitter, and packet loss rate into a weighted fusion evaluation, which can more comprehensively and accurately reflect the true quality of the link.

[0113] In a preferred embodiment of the present invention, the multi-dimensional evaluation step S4 of this method further includes a self-optimization mechanism that dynamically adjusts the weight coefficients α, β, and γ based on the historical response performance of the link. Specifically, the multi-dimensional evaluation step S4 records the latency improvement ΔD = D_before - D_after within a preset time period after each hierarchical decision, where D_before is the average latency value before triggering the hierarchical decision, and D_after is the average latency value within a preset time period (e.g., 10 detection cycles) after triggering the hierarchical decision.

[0114] Furthermore, an improvement quantity assessment counter is set in the multi-dimensional evaluation step. When the latency improvement quantity ΔD is lower than the preset threshold ΔD_th, the improvement quantity assessment counter increments. When the latency improvement quantity of multiple consecutive decisions (e.g., 5 consecutive decisions) is lower than the preset threshold, the multi-dimensional evaluation step automatically increases the health score threshold that triggers the corresponding level response (that is, Th1, Th2, and Th3 are simultaneously increased by a preset amount). The self-optimization mechanism configured accordingly enables the weight coefficients to be adaptively optimized according to the actual network environment and business needs, further improving the accuracy of the evaluation model.

[0115] As a specific example of an implementable method, step S5 in this method can be implemented in the following way:

[0116] Figure 5 The decision logic for the hierarchical decision-making and execution steps in this invention is illustrated. See also... Figure 5 In the method of this invention, step S5 performs hierarchical decision-making and execution operations in the switching chip. The specific implementation of this step includes the following sub-steps:

[0117] Step S5-1: Obtain decision input. Obtain the priority pre-boost signal from step S3; obtain the health score H from step S4; obtain the fault judgment threshold from step S2; obtain the packet loss detection result and the current latency value D_current from step S1. D_current is the latest output of the current one-way latency value of the link by the latency calculation unit, that is, the current sampled value of the real-time link quality detection.

[0118] Step S5-2: Determine if priority pre-boosting is triggered. If a priority pre-boosting signal is triggered, perform a priority boosting operation, raising the differential service code point field of the BFD message by the first increment.

[0119] Step S5-3: Perform health level interval determination and graded response. This step specifically includes the following sub-steps:

[0120] Step S5-3A: preset three thresholds: a first threshold Th1, a second threshold Th2, and a third threshold Th3, which satisfy Th1 < Th2 < Th3; acquire the current health score H.

[0121] Step S5-3B: determine whether to perform priority fallback. The hierarchical decision and execution step maintains a health cycle counter, which is configured to record the number of detection cycles in which the health score H continuously stays in the health interval (H > Th3). When the health score H > Th3, the health cycle counter is incremented by 1; when the health score H ≤ Th3, the health cycle counter is cleared. When the health cycle counter reaches a preset fallback threshold (e.g., 3 consecutive detection cycles), the hierarchical decision and execution step rolls back the differentiated services code point field of the BFD packet to the initial default value, and clears the amplitude accumulator.

[0122] Step S5-3C: determine whether H is in a first preset interval (Th2 < H ≤ Th3). If H is in the first preset interval:

[0123] trigger a first-level response, increase the priority of BFD packets by a first amplitude, and record the increase amplitude as the first amplitude;

[0124] the hierarchical decision and execution step maintains a continuous congestion counter, which is configured to record the number of detection cycles in which the health score H continuously stays in the first preset interval, and increment the counter;

[0125] when the continuous congestion counter reaches a first duration threshold (e.g., 10 detection cycles), increase the amplitude of the first-level response to a third amplitude, wherein the third amplitude is greater than the second amplitude;

[0126] when the continuous congestion counter reaches a second duration threshold (e.g., another 10 detection cycles, that is, a cumulative total of 20 detection cycles), it is determined that a fundamental fault exists on the current link, and a third-level response is directly triggered.

[0127] Step S5-3D: determine whether H is in a second preset interval (Th1 < H ≤ Th2). If H is in the second preset interval:

[0128] trigger a second-level response, increase the priority of BFD packets by a second amplitude (the second amplitude is greater than the first amplitude), and record the increase amplitude as the second amplitude;

[0129] the hierarchical decision and execution step increments the continuous congestion counter;

[0130] when the continuous congestion counter reaches a third duration threshold (e.g., 10 detection cycles), directly trigger the third-level response without waiting for an intermediate process.

[0131] Step S5-3E: Determine whether H is within the third preset interval (H ≤ Th1). If H is within the third preset interval, directly trigger the third-level response.

[0132] Step S5-3F: Perform amplitude accumulation and priority boosting (if backoff is not triggered). An amplitude accumulator is set up to accumulate the pre-boost amplitude recorded in step S5-2 and the graded response amplitude recorded in step S5-3 to obtain the total boost amplitude. Based on the total boost amplitude, the priority boosting operation for BFD message transmission is uniformly executed. When neither the pre-boost signal nor the first or second level response is triggered, the value of the amplitude accumulator is zero, and priority boosting is not performed. The execution relationship of each level of response is cumulative—when both the pre-boost signal and any level of graded response are triggered simultaneously, the value of the amplitude accumulator is the sum of the pre-boost amplitude and the graded response amplitude.

[0133] Step S5-4: Determine whether to trigger a Level 3 response. The conditions for triggering a Level 3 response include any of the following: (a) the health score H is in the third preset range; (b) the number of consecutive packet losses reaches a preset threshold (e.g., 3 consecutive packet losses); (c) the current latency value exceeds the fault determination threshold; (d) the Level 3 response is triggered due to a lack of improvement over a long period of time, as described in Step S5-3C or S5-3D.

[0134] Step S5-5: Execute the third-level response. When the third-level response is triggered, the control plane is notified via a hardware interrupt signal. The control plane then switches the service traffic from the current link to the backup link, records the fault event information (including fault time, fault type, latency value, packet loss rate, etc.), and generates alarm information.

[0135] As can be seen from the above, unlike the binary decision-making mechanism that typically uses a single threshold to trigger a single response in existing technologies, this hierarchical decision-making and execution step constructs a multi-level progressive decision-making system of "pre-boost → Level 1 → Level 2 → Level 3". It also achieves the superposition execution of responses at each level through an amplitude accumulator. Furthermore, it implements a priority fallback mechanism and a long-term no-improvement judgment mechanism through a health cycle counter and a congestion persistence counter, thereby distinguishing between temporary congestion and fundamental link failures, making the decision-making logic more complete and intelligent.

[0136] In response to the aforementioned hardware BFD link detection method based on trend prediction and multi-dimensional evaluation, this invention further provides a hardware BFD link detection system scheme based on trend prediction and multi-dimensional evaluation capable of implementing this detection method.

[0137] See Figure 2The diagram illustrates the overall architecture of the hardware BFD link detection system based on trend prediction and multi-dimensional evaluation in this invention. Based on the diagram, the hardware BFD link detection system 100 based on trend prediction and multi-dimensional evaluation provided by this invention mainly comprises five functional modules: a BFD processing engine 110, a dynamic threshold calculation module 120, a trend prediction module 130, a multi-dimensional evaluation module 140, and a hierarchical decision-making and execution module 150.

[0138] In its implementation, the BFD processing engine 110 in this system is integrated into the switching chip. This module is configured to perform BFD message transmission and reception processing and state machine maintenance in hardware, without requiring the central processing unit to participate in each packet.

[0139] The BFD processing engine 110 implements full hardware processing of the BFD protocol, eliminating software processing latency.

[0140] Furthermore, the BFD processing engine 110 constitutes the data source layer of the entire system, continuously outputting raw data such as the delay value, sequence number, and timestamp of the BFD message to the dynamic threshold calculation module 120, the trend prediction module 130, and the multi-dimensional evaluation module 140.

[0141] The dynamic threshold calculation module 120 in this system is integrated into the switching chip and interacts with the BFD processing engine 110. This module is configured to maintain the transmission delay samples of the most recent N BFD messages in real time based on a sliding window, calculate the delay statistical feature value in real time based on the transmission delay sample, and update the fault judgment threshold in real time based on the delay statistical feature value.

[0142] The dynamic threshold calculation module 120 specifically employs a recursive algorithm to achieve real-time statistics with O(1) space complexity, and the threshold is updated with each frame of the message. This module constitutes the system's judgment benchmark layer, obtains the latency value from the BFD processing engine 110, and outputs the fault judgment threshold to the hierarchical decision and execution module 150.

[0143] The trend prediction module 130 in this system is integrated into the switching chip and interacts with the dynamic threshold calculation module 120. This module is configured to monitor the changing trend of the transmission delay values ​​of multiple consecutive BFD messages, and trigger a priority pre-boost signal when the delay value predicted based on the changing trend meets a preset condition.

[0144] This module implements "predictive" early intervention and is used in the prediction layer of the system. It obtains the time delay value sequence from the BFD processing engine 110 and outputs the pre-boost signal to the hierarchical decision and execution module 150.

[0145] The multi-dimensional evaluation module 140 in this system is integrated into the switching chip and interacts with the BFD processing engine 110 and the dynamic threshold calculation module 120. This module is configured to acquire multiple quality parameters of the link and calculate the current link's health score based on these parameters.

[0146] Unlike existing technologies that rely on a single indicator, this module performs a weighted fusion evaluation across multiple dimensions to form the system's evaluation layer. It obtains quality parameters from the BFD processing engine 110 and outputs a health score to the hierarchical decision-making and execution module 150.

[0147] The hierarchical decision-making and execution module 150 in this system is integrated into the switching chip and interacts with the trend prediction module 130, the multi-dimensional evaluation module 140, and the dynamic threshold calculation module 120. This module is configured to perform hierarchical decisions and trigger corresponding execution operations based on the pre-boost signal, health score, and fault determination threshold.

[0148] This module constructs a multi-level progressive decision-making system, as well as a priority fallback mechanism and a long-term no-improvement judgment mechanism, to achieve differentiated and precise responses. It can constitute the decision-making and execution layer of the system, comprehensively receive all input signals, and execute the final hierarchical decision and response.

[0149] In this hardware BFD link detection system based on trend prediction and multi-dimensional evaluation, the BFD processing engine 110 provides raw data to the dynamic threshold calculation module 120, trend prediction module 130, and multi-dimensional evaluation module 140 as a data source. The dynamic threshold calculation module 120 provides early warning thresholds to the trend prediction module 130 and fault judgment thresholds to the hierarchical decision-making and execution module 150. The trend prediction module 130 and the multi-dimensional evaluation module 140 process data in parallel and output pre-boost signals and health scores to the hierarchical decision-making and execution module 150, respectively. The hierarchical decision-making and execution module 150 integrates all inputs and executes hierarchical decisions.

[0150] Based on an understanding of the overall functions and logical relationships of the various modules and units of the above system, the specific configuration schemes of each component will be explained from a technical implementation perspective below.

[0151] As a specific example of an implementation method, the configuration of the BFD processing engine 110 in this system is the same as that of the BFD processing engine in the aforementioned method step S1 (see [link]). Figure 1 (This will not be repeated here.)

[0152] In this engine implementation, all BFD protocol processing logic is implemented using hardware state machines and combinational logic, eliminating the waiting delay of software instruction execution; timestamps are automatically captured by hardware at the moment of message entry and exit, eliminating the jitter of software interrupt handling; message transmission and reception interact directly with the on-chip cache through direct memory access, eliminating the overhead of packet-by-packet processing by the central processing unit.

[0153] As a specific example of an implementation method, the dynamic threshold calculation module 120 in this system specifically includes a sliding window buffer, a mean and standard deviation recursive calculator, and a threshold register.

[0154] The sliding window buffer is configured to store the most recent N delay samples and is maintained in a first-in, first-out manner.

[0155] The mean and standard deviation recursive calculator is configured to be based on the Welford algorithm.

[0156] The threshold register is configured to store the calculated fault determination threshold.

[0157] As further explanation, all components in this dynamic threshold calculation module 120 are implemented using hardware logic. The specific implementation scheme is the same as that of step S2 in the aforementioned method, and will not be repeated here.

[0158] Unlike existing technologies that typically recalculate statistical values ​​based on all historical data, resulting in a time complexity of O(N) and a linear increase in computational overhead as the window size increases, this dynamic threshold calculation module 120 employs the Welford recursive algorithm, requiring only a constant number of multiplication and addition operations to complete the update, maintaining a constant time complexity of O(1). This difference enables the dynamic threshold calculation of this invention to be completed in real time upon the arrival of each message.

[0159] As a specific description of an implementation method, the trend prediction module 130 in this system specifically includes: a time delay value buffer, a difference calculator, trend determination logic, a prediction calculator, and a comparator.

[0160] The delay value buffer is configured to store M consecutive delay values.

[0161] The difference calculator is configured to calculate first-order differences;

[0162] The trend determination logic is configured to determine monotonically increasing trends.

[0163] The prediction calculator is configured to calculate the prediction delay value according to the formula D_predict = D_M + slope × T;

[0164] The comparator is configured to compare the predicted value with the warning threshold.

[0165] As a further explanation, the specific implementation scheme of the corresponding logic of each component in this trend prediction module 130 is the same as the implementation scheme of the aforementioned method step S3, and will not be repeated here.

[0166] Compared to existing link detection technologies that rely solely on the current state and are reactive, this trend prediction module 130 achieves proactive intervention by monitoring and predicting the changing trends of latency values.

[0167] As a specific description of an implementation method, the multi-dimensional evaluation module 140 in this system includes: a parameter acquisition interface, a normalization processor, a weight register, and a health calculator.

[0168] The parameter acquisition interface is configured to obtain latency, jitter, and packet loss rate from the BFD processing engine.

[0169] The normalization processor is configured to map each parameter to the [0,1] interval based on the reference maximum value in the configuration register;

[0170] The weight register is configured to store the configuration values ​​of α, β, and γ;

[0171] The health calculator is configured to perform weighted summation operations.

[0172] As further explanation, the specific implementation schemes of the corresponding logics of each component in this multi-dimensional evaluation module 140 are the same as the implementation schemes of the aforementioned method step S4, and will not be repeated here.

[0173] Unlike existing technologies that typically assess link quality based on a single dimension, this multi-dimensional assessment module 140, by constructing a multi-dimensional weighted fusion assessment model, can more comprehensively and accurately reflect link quality.

[0174] As a specific description of an implementation method, the hierarchical decision-making and execution module 150 in this system includes: a decision input interface, an interval comparator, a priority adjustment executor, an interrupt trigger, a health cycle counter, and a congestion persistence counter.

[0175] The decision input interface is configured to acquire input signals such as pre-boost signal, health score, current latency value, and packet loss detection results.

[0176] The interval comparator is configured to determine the preset interval in which the health score falls;

[0177] The priority adjustment executor is configured to perform modifications to differential service codepoint values ​​and queue assignments.

[0178] The interrupt trigger is configured to trigger a hardware interrupt signal;

[0179] Set the health cycle counter to record the number of consecutive cycles in which the health score is within the healthy range;

[0180] The congestion persistence counter is set to record the number of consecutive periods in which the health score is within the first or second preset range.

[0181] As further explanation, the specific implementation schemes of the corresponding logics of each component in this hierarchical decision and execution module 150 are the same as the implementation schemes of the aforementioned method step S5, and will not be repeated here.

[0182] Unlike existing technologies that typically employ a binary decision-making approach of "normal / fault," this hierarchical decision-making and execution module 150 constructs a multi-level progressive decision-making system that includes pre-promotion, first level, second level, and third level. Furthermore, it can utilize a counter mechanism to implement priority rollback and long-term no-improvement judgment, making the decision-making process more intelligent.

[0183] The hardware BFD link detection system based on trend prediction and multi-dimensional evaluation, formed by the above scheme, is further configured to execute the following operational logic:

[0184] (1) When the system is initialized, the central processing unit configures the sliding window capacity, weight coefficient, hierarchical threshold, configurable parameter K, etc., and sends the BFD session information to the BFD processing engine 110.

[0185] (2) After the session is established, the steady-state detection phase begins. The BFD processing engine 110 runs independently to complete the sending, receiving, parsing, verification, timestamp recording, delay calculation and state machine maintenance of BFD messages.

[0186] (3) The dynamic threshold calculation module 120 continuously obtains the delay value from the BFD processing engine 110, updates the sliding window, recursively calculates μ and σ, updates the fault judgment threshold and stores it in the hardware register.

[0187] (4) The trend prediction module 130 continuously obtains the time delay value sequence from the BFD processing engine 110, performs trend analysis and prediction, and triggers the priority pre-boost signal when necessary.

[0188] (5) The multi-dimensional evaluation module 140 continuously obtains latency, jitter and packet loss rate data from the BFD processing engine 110 and calculates the health score H.

[0189] (6) The hierarchical decision and execution module 150 continuously monitors the pre-boost signal, health score H, current delay value and continuous packet loss events, executes the corresponding response operation according to the hierarchical decision logic, and maintains the health cycle counter and congestion persistence counter to realize priority rollback and long-term no improvement judgment.

[0190] The following specific application example further illustrates the application and implementation process of the present invention and the technical effects that can be obtained.

[0191] This section uses the CTC7148 switching chip platform from Shengke as an example to illustrate the application and implementation process of this invention in detail.

[0192] (I) System Composition and Deployment

[0193] In this example, the deployment is based on the CTC7148 switching chip platform. The CTC7148 (DUET2) is a high-performance Ethernet switching chip for 10GbE / 25GbE applications, integrating an OAM engine (supporting SAT, data LM, and other O&M functions), a FlowTracing engine (supporting hardware buffer and latency monitoring), and a high-precision hardware clock. This chip has the hardware foundation to implement hardware BFD acceleration—the hardware state machine, high-precision clock, direct memory access controller, and other resources can all be used for hardware-based processing of BFD packets.

[0194] The BFD processing engine 110 is implemented by extending the hardware acceleration capabilities of the CTC7148 chip. The serial number generation unit 111 is implemented based on the chip's built-in 32-bit hardware counter. The message transceiver unit 112 interacts with the chip's on-chip cache through the chip's direct memory access controller. The message parsing unit 113 is implemented using the chip's programmable hardware state machine and three-stage pipelined logic circuitry. The serial number verification unit 114 is implemented using the chip's hardware comparator array. The timestamp recording unit 115 is implemented based on the chip's built-in high-precision hardware clock and dedicated register set. The delay calculation unit 116 is implemented using the chip's hardware subtractor. The state maintenance unit 117 is implemented using the chip's hardware state machine.

[0195] The dynamic threshold calculation module 120, trend prediction module 130, multi-dimensional evaluation module 140, and hierarchical decision-making and execution module 150 are all deployed in hardware logic within the CTC7148 switching chip, and the modules interact with each other through the chip's internal high-speed data bus. After completing the BFD session parameter configuration during the initialization phase, the central processing unit no longer participates in message processing during the steady-state detection process.

[0196] (II) Method and Flow

[0197] Step 1: Hardware processing of BFD messages;

[0198] After the BFD session is established, the steady-state detection phase begins. The sequence number generation unit 111 of the sending end BFD processing engine 110 assigns a unique, incrementing sequence number sq=n to the BFD message to be sent. The message transceiver unit 112 sends the BFD message to the network physical port via direct memory access. The timestamp recording unit 115 automatically captures the current hardware clock value T_send as the sending timestamp at the moment the message leaves the chip port.

[0199] After receiving the BFD message, the message transceiver unit 112 writes the message into the chip's buffer via direct memory access. The message parsing unit 113 parses the BFD message in real time through a three-stage pipeline, extracting the sequence number sq=n and the timestamp information it carries. The timestamp recording unit 115 automatically captures the current hardware clock value T_receive as the receive timestamp at the moment the message parsing unit 113 identifies the BFD message header. The delay calculation unit 116 calculates D = T_receive - T_send using a hardware subtractor to obtain the one-way delay value of the message.

[0200] The sequence number verification unit 114 compares the received message sequence number sq=n with the value in the expected sequence number register, determines that the messages are continuous, and updates the expected sequence number.

[0201] Step 2: Real-time calculation of dynamic threshold;

[0202] The delay value D is fed into the sliding window buffer of the dynamic threshold calculation module 120. Assuming the window capacity N=100 and the current window is full, the oldest delay value D_old is removed and the new delay value D_new is added.

[0203] The dynamic threshold calculation module 120 performs real-time recursive calculations based on the Welford algorithm.

[0204] μ_window = μ_window-1 + (D_new - D_old) / N

[0205] M_window = M_window-1 + (D_new - μ_window-1)·(D_new - μ_window)

[0206] ;

[0207] Once the dynamic threshold θ = μ_window + 3·σ_window (K=3) is calculated, it is immediately stored in the dynamic threshold register.

[0208] Step 3: Trend Forecasting;

[0209] The trend prediction module 130 obtains the latency value sequence (M=15) of the most recent 15 BFD messages from the BFD processing engine 110 and calculates the first-order difference. Assuming that the first-order differences are all positive for 8 consecutive times (P=8), it is determined that the latency value shows a monotonically increasing trend.

[0210] The trend prediction module 130 calculates the trend slope and prediction delay value. The warning threshold is set to μ+1.5σ (i.e., μ+1 / 2Kσ, K=3). If the prediction delay value exceeds the warning threshold, the trend prediction module 130 triggers a priority pre-boost signal.

[0211] Step 4: Multi-dimensional evaluation;

[0212] The multi-dimensional evaluation module 140 obtains the current link latency value D=2.8ms, jitter value J=0.6ms, and packet loss rate L=0.05% from the BFD processing engine 110.

[0213] Normalization: Based on the maximum reference values ​​in the configuration register (maximum latency reference value 5ms, maximum jitter reference value 2ms, maximum packet loss rate reference value 1%), calculate D_norm=2.8 / 5=0.56, J_norm=0.6 / 2=0.30, L_norm=0.05 / 1=0.05.

[0214] The weighting coefficients are set to default values ​​of α=0.5, β=0.3, and γ=0.2. The health score is then calculated as follows:

[0215] H = 0.5×0.56 + 0.3×0.30 + 0.2×0.05 = 0.38

[0216] Step 5: Hierarchical decision-making and execution;

[0217] The hierarchical decision and execution module 150 obtains the decision input: the pre-boost signal has been triggered, H=0.38, D_current=2.8ms, θ=μ+3σ.

[0218] Preset grading thresholds: Th1=0.2, Th2=0.4, Th3=0.7.

[0219] Judgment process:

[0220] (1) The pre-lift signal has been triggered. Record the lift range to be recorded.

[0221] (2) H=0.38 is within Th1 < H ≤ Th2 (0.2 < 0.38 ≤ 0.4), which is the first preset interval, triggering the first level response.

[0222] (3) Determine whether D_current=2.8ms exceeds θ, and determine whether the continuous packet loss count has reached the preset threshold. If neither is triggered, then the third-level response is not triggered.

[0223] Final execution result: The differential service code point field of the BFD message is upgraded to a preset level, and a corresponding high-priority processing queue is allocated to the BFD message inside the switching chip.

[0224] This example achieves the following technical effects through the synergistic effect of the aforementioned hardware-based BFD processing engine, real-time incremental dynamic threshold using a sliding window, trend prediction, and multi-dimensional evaluation-based hierarchical decision-making:

[0225] First, the entire steady-state detection process of BFD messages does not require the central processing unit to participate in each packet, eliminating uncertainties in the software processing path and achieving high-precision timestamps and millisecond-level detection response.

[0226] Second, the dynamic threshold is updated in real time with each BFD message frame, which can accurately reflect the real-time status changes of the link and avoid misjudgments caused by the fixed threshold mechanism.

[0227] Third, the trend prediction module triggers a pre-boost signal before the link quality deteriorates to the fault threshold, enabling early intervention and effectively avoiding business interruptions caused by delayed response.

[0228] Fourth, the multi-dimensional health assessment model integrates multiple dimensions such as latency, jitter, and packet loss rate, enabling accurate hierarchical assessment and differentiated response of link status, avoiding the one-sidedness of judging by a single indicator.

[0229] Fifth, the priority fallback mechanism automatically releases high-priority resources after the link recovers to health, avoiding long-term occupation; the long-term no-improvement judgment mechanism can distinguish between temporary congestion and fundamental link failure, gradually escalating the response strength when there is continuous congestion, and finally triggering link switching, thereby improving the system's robustness in dealing with complex network conditions.

[0230] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely illustrative of the principles of the invention. Various changes and modifications can be made to the invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of the present invention as claimed. The scope of protection of this invention is defined by the appended claims and their equivalents.

Claims

1. A hardware BFD link detection method based on trend prediction and multi-dimensional evaluation, characterized in that, The detection method includes: Hardware processing steps: A BFD processing engine is integrated into the switching chip. The BFD processing engine performs the sending and receiving of BFD messages and the maintenance of the state machine in hardware. The sending and receiving of BFD messages and the maintenance of the state machine do not require the central processing unit to participate in each packet. Dynamic threshold calculation steps: Based on a sliding window, maintain the transmission delay samples of the most recent N BFD messages in real time, calculate the delay statistical feature value in real time according to the transmission delay samples, and update the fault judgment threshold in real time according to the delay statistical feature value. Trend prediction step: Monitor the changing trend of transmission delay values ​​of multiple consecutive BFD messages. When the predicted delay value based on the changing trend meets the preset conditions, trigger the priority pre-boost signal. Multi-dimensional evaluation steps: Obtain multiple quality parameters of the link, and calculate the health score of the current link based on the multiple quality parameters; Hierarchical decision-making and execution steps: Based on the priority pre-boost signal, the health score, and the fault determination threshold, perform hierarchical decision-making: When the priority pre-boost signal is triggered, the transmission priority of the BFD message is increased; When the health score falls within different preset ranges, the corresponding priority is increased; when the health score remains within a healthy range for a preset number of periods, priority is rolled back; when the health score remains within the first preset range for a preset number of periods, the response amplitude is increased or link protection switching is triggered; when the health score falls within the second preset range for a preset number of periods, link protection switching is triggered. When the health score meets the preset fault conditions, the number of consecutive packet losses reaches the preset threshold, or the transmission delay value exceeds the fault determination threshold, link protection switching is triggered.

2. The hardware BFD link detection method based on trend prediction and multi-dimensional evaluation according to claim 1, characterized in that, In the hardware processing step, the BFD processing engine performs the following hardware processing operations: The sequence number generation unit generates a sequence number for each BFD message to be sent based on a hardware counter, and writes the sequence number into the header of the BFD message. The message transceiver unit interacts with the on-chip cache via direct memory access, sending BFD messages with the sequence number and receiving BFD messages sent by the peer. The received BFD messages are parsed in real time by the message parsing unit, and the sequence number and timestamp information in the BFD messages are extracted. The sequence number verification unit compares the extracted received message sequence number with the expected sequence number to determine message continuity and detect continuous packet loss. The timestamps for sending and receiving each BFD message are recorded using a timestamp recording unit. The delay calculation unit calculates the one-way delay value of each BFD message based on the sending timestamp and the receiving timestamp; The state of the BFD session is maintained through the state maintenance unit.

3. The hardware BFD link detection method based on trend prediction and multi-dimensional evaluation according to claim 1, characterized in that, In the dynamic threshold calculation step, the delay statistical feature value is calculated in real time based on the Welford algorithm. The delay statistical feature value includes the delay mean μ and the delay standard deviation σ.

4. The hardware BFD link detection method based on trend prediction and multi-dimensional evaluation according to claim 1, characterized in that, In the dynamic threshold calculation step, the fault determination threshold is μ±Kσ, where μ is the mean delay, σ is the standard deviation of the delay, and K is a configurable parameter.

5. The hardware BFD link detection method based on trend prediction and multi-dimensional evaluation according to claim 1, characterized in that, The multiple quality parameters include latency parameters, jitter parameters, and packet loss rate parameters; the health score is calculated using a normalized weighted summation model.

6. The hardware BFD link detection method based on trend prediction and multi-dimensional evaluation according to claim 1, characterized in that, In the trend prediction step, the preset condition is: the transmission delay value shows a monotonically increasing trend and the delay value predicted based on the monotonically increasing trend exceeds the warning threshold within a preset period.

7. The hardware BFD link detection method based on trend prediction and multi-dimensional evaluation according to claim 1, characterized in that, In the hierarchical decision-making and execution steps, the link protection switching is executed by notifying the control plane through a hardware interrupt.

8. The hardware BFD link detection method based on trend prediction and multi-dimensional evaluation according to claim 1, characterized in that, In the hierarchical decision-making and execution steps, increasing the sending priority of BFD messages includes modifying the differential service code point field value of the BFD message.

9. A hardware BFD link detection system based on trend prediction and multi-dimensional evaluation, characterized in that, The detection system includes: The BFD processing engine is integrated into the switching chip. The BFD processing engine is used to perform the sending and receiving of BFD messages and the maintenance of the state machine in hardware. The sending and receiving of BFD messages and the maintenance of the state machine do not require the central processing unit to participate in each packet. The dynamic threshold calculation module is integrated into the switching chip and interacts with the BFD processing engine. The dynamic threshold calculation module is used to maintain the transmission delay samples of the most recent N BFD messages in real time based on the sliding window, calculate the delay statistical feature value in real time based on the transmission delay sample, and update the fault judgment threshold in real time based on the delay statistical feature value. The trend prediction module is integrated into the switching chip and interacts with the dynamic threshold calculation module. The trend prediction module is used to monitor the changing trend of the transmission delay value of multiple consecutive BFD messages. When the delay value predicted based on the changing trend meets the preset conditions, a priority pre-boost signal is triggered. A multi-dimensional evaluation module is integrated into the switching chip and interacts with the BFD processing engine and the dynamic threshold calculation module. The multi-dimensional evaluation module is used to obtain multiple quality parameters of the link and calculate the health score of the current link based on the multiple quality parameters. The hierarchical decision-making and execution module, integrated into the switching chip and interacting with the trend prediction module, the multi-dimensional evaluation module, and the dynamic threshold calculation module, performs hierarchical decisions based on the priority pre-boost signal, the health score, and the fault determination threshold: When the priority pre-boost signal is triggered, the sending priority of BFD packets is increased; when the health score is in different preset intervals, the corresponding level of priority boost is executed; when the health score remains in the healthy interval for a preset number of periods, priority rollback is executed; when the health score remains in the first preset interval for a preset number of periods, the response amplitude is upgraded or link protection switching is triggered; when the health score is in the second preset interval for a preset number of periods, link protection switching is triggered; when the health score meets preset fault conditions, the number of consecutive packet losses reaches a preset threshold, or the transmission delay value exceeds the fault determination threshold, link protection switching is triggered.

10. The hardware BFD link detection system based on trend prediction and multi-dimensional evaluation according to claim 9, characterized in that, The BFD processing engine includes: A sequence number generation unit generates a sequence number for each BFD message to be sent based on a hardware counter, and writes the sequence number into the header of the BFD message. The message transceiver unit interacts with the on-chip cache via direct memory access, sends BFD messages with the sequence number, and receives BFD messages sent by the peer. The message parsing unit parses the received BFD messages in real time and extracts the sequence number and timestamp information from the BFD messages. The sequence number verification unit compares the extracted received message sequence number with the expected sequence number to determine message continuity and detect continuous packet loss. A timestamp recording unit records the sending timestamp and receiving timestamp of each BFD message; A delay calculation unit calculates the one-way delay value of each BFD message based on the sending timestamp and the receiving timestamp; A state maintenance unit maintains the BFD session state.

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