Delay-based adaptive routing

Abstract

This invention relates to delay-based adaptive routing, and specifically describes a system and method for adaptive routing in network communications. The system includes circuitry for: determining the delay of each of a plurality of queues, wherein the delay of a given queue is determined based on the depth of that queue and the rate of traffic leaving that queue; selecting one of the plurality of queues for forwarding data packets, based at least in part on the determined delay of each queue; and forwarding the data packets to the selected queue.

Description

Technical Field

[0001] This disclosure relates generally to network communications, and more specifically to systems and methods for adaptive routing in network communications. Background Technology

[0002] Communication protocols can be provided for certain network communications, such as Ethernet, to implement communication standards. In one example, such network communications could support artificial intelligence (AI) training workloads that require large east-west network bandwidth. Adaptive routing can be provided in network communications to maximize network utilization by load balancing traffic based on local switch states such as queue length and port utilization. Furthermore, AI training can include performance highly sensitive to changes in network conditions, including congestion, latency, and frame drops. Failed links in the network can lead to bandwidth reduction and potential congestion, especially when AI-related aspects of network communications are operating at high utilization. Adaptive routing allows for rebalancing decisions that may be based on local state and may not allow upstream switches or routers to divert traffic from downstream devices suffering from events that reduce bandwidth capacity, such as link failures or congestion. Attached Figure Description

[0003] This disclosure is described in conjunction with accompanying drawings, which are not necessarily drawn to scale: Figure 1 The illustration depicts a system undergoing an embodiment of adaptive routing in network communication; Figure 2 The illustration depicts a topology associated with a system for adaptive routing in network communications, according to at least one embodiment; Figure 3 The illustrations depict various aspects of a system for adaptive routing in network communication according to at least one embodiment; Figure 4 The illustration shows a system capable of executing at least one embodiment; Figure 5 The illustration shows a system capable of executing at least one embodiment; Figure 6 The illustration shows a process flow in a system for weighted routing according to at least one embodiment; Figure 7 The illustration shows a process flow in a system for configuring a pipeline engine according to at least one embodiment; Figure 8 A block diagram of an example system according to at least one embodiment is illustrated; Figure 9 An example data center according to at least one embodiment is shown; Figure 10 A processing system according to at least one embodiment is shown; Figure 11 A computer system according to at least one embodiment is shown; Figure 12 A system according to at least one embodiment is shown; Figure 13 An example integrated circuit according to at least one embodiment is shown; Figure 14 A computing system according to at least one embodiment is shown; Figure 15 An APU according to at least one embodiment is shown; Figure 16 A CPU according to at least one embodiment is shown; Figure 17 An example accelerator integration slice according to at least one embodiment is shown; Figure 18A and Figure 18B An example graphics processor according to at least one embodiment is shown; Figure 19A A graphics core according to at least one embodiment is shown; Figure 19B A GPGPU according to at least one embodiment is shown; Figure 20A A parallel processor according to at least one embodiment is shown; Figure 20B A processing cluster according to at least one embodiment is shown; Figure 20C A graphics multiprocessor according to at least one embodiment is shown; Figure 21 A graphics processor according to at least one embodiment is shown; Figure 22 A processor according to at least one embodiment is shown; Figure 23 A processor according to at least one embodiment is shown; Figure 24 A graphics processor core according to at least one embodiment is shown; Figure 25 A PPU according to at least one embodiment is shown; Figure 26 A GPC according to at least one embodiment is shown; Figure 27 A streaming multiprocessor according to at least one embodiment is illustrated; Figure 28 A software stack of a programming platform according to at least one embodiment is shown; Figure 29 The illustration shows an embodiment according to at least one of the embodiments. Figure 28 The CUDA implementation of the software stack; Figure 30 The illustration shows an embodiment according to at least one of the embodiments. Figure 28 The ROCm implementation of the software stack; Figure 31 The illustration shows an embodiment according to at least one of the embodiments. Figure 28 The OpenCL implementation of the software stack; Figure 32 Software supported by a programming platform according to at least one embodiment is shown; Figure 33 The illustration shows an embodiment of at least one of the following: Figures 28-31 Compiled code executed on the programming platform; Figure 34 The illustration shows an embodiment of at least one of the following: Figures 28-31 More detailed compiled code executed on the programming platform; Figure 35 This illustrates the transformation of source code before compilation, according to at least one embodiment; Figure 36A A system configured to compile and execute CUDA source code using different types of processing units, according to at least one embodiment, is shown; Figure 36B The diagram illustrates a configuration, according to at least one embodiment, to compile and execute using a CPU and a CUDA-enabled GPU. Figure 36A The system of CUDA source code; Figure 36C The diagram illustrates a configuration, according to at least one embodiment, to compile and execute using a CPU and a GPU with CUDA disabled. Figure 36A The system of CUDA source code; Figure 37 The diagram illustrates a method according to at least one embodiment. Figure 36C Example kernels converted by the CUDA to HIP conversion tool; Figure 38 A more detailed description is provided according to at least one embodiment. Figure 36C GPUs without CUDA enabled; and Figure 39 This illustrates how threads of an example CUDA grid, according to at least one embodiment, are mapped to... Figure 38 Different computing units; and Figure 40 This paper illustrates how to migrate existing CUDA code to data-parallel C++ code according to at least one embodiment. Detailed Implementation

[0004] The following description provides only examples and is not intended to limit the scope, applicability, or configuration of the claims. Rather, it is intended to provide those skilled in the art with enabling descriptions for implementing the described embodiments. It should be understood that various changes may be made to the function and arrangement of the elements without departing from the spirit and scope of the appended claims.

[0005] It should be understood that, based on the following description and for computational efficiency reasons, the components of the system can be placed at any suitable location within the distributed network of components without affecting the operation of the system.

[0006] Furthermore, it should be understood that the various links connecting the elements can be wired, traced, or wireless links, or any suitable combination thereof, or one or more other suitable known or later-developed elements capable of supplying data to and / or transmitting data from the connected elements. For example, the transmission medium used as a link can be any suitable carrier for electrical signals, including coaxial cables, copper wires and optical fibers, electrical traces on printed circuit boards (PCBs), etc.

[0007] As used in this article, the phrases “at least one,” “one or more,” “or,” and “and / or” are open expressions that function as both conjunctions and adversative conjunctions in action. For example, each of the expressions “at least one of A, B, and C,” “at least one of A, B, or C,” “one or more of A, B, and C,” “one or more of A, B, or C,” “A, B, and / or C,” and “A, B, or C” means A alone, B alone, C alone, A and B together, A and C together, B and C together, or A, B, and C together.

[0008] As used herein, the term "automatic" and its variations refer to any suitable process or operation performed without material human input. However, a process or operation may be automatic if input is received prior to its execution, even if the execution of the process or operation uses material or non-material human input. Human input is considered material if it influences how a process or operation is performed. It is agreed that human input used to perform a process or operation should not be considered "material."

[0009] The terms “determine,” “calculate,” “operate,” and their variations, as used herein, are used interchangeably and include any appropriate type of method, process, operation, or technique.

[0010] Various aspects of this disclosure are described herein with reference to the accompanying drawings, which are schematic illustrations of idealized configurations.

[0011] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It should also be understood that terms such as those defined in common dictionaries shall be interpreted as having the same meaning as they have in the context of the relevant technology and this disclosure.

[0012] Unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the” used herein include the plural forms as well. It should also be understood that the terms “comprising,” “including,” and / or “containing,” when used in this specification, specify the presence of the stated feature, integer, step, operation, element, and / or component, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. The term “and / or” includes any one and all combinations of one or more of the related listed items.

[0013] Figure 1 The illustration depicts a system 100 capable of withstanding an adaptive routing solution involving a distributed engine, as detailed herein. System 100 and the method for using such system 100 enable devices to distribute traffic adaptively. This minimizes the performance impact of link failures in the fabric or network, such as a three-tier Clos topology network.

[0014] The network 100 described herein includes at least one system or circuit, which may be an execution unit of a processor within leaf switches 106, 114. Leaf switches 106, 114 may be associated with corresponding racks or Ethernet groupings 2 102, 1 110 of local or remote hosts or other endpoints 1-N 104, 1-N 112, such as... Figure 1 As illustrated, network 100 may further include at least a spine switch or gateway 108 as part of one or more interconnecting devices 120 for providing Ethernet communication 116 among multiple leaf switches 106, 114. Thus, each Ethernet packet 2 102, 1 110 of hosts or other endpoints 1-N 104, 1-N 112 can communicate within the packet using the leaf switch, and can communicate across packets using the spine switch or gateway 108.

[0015] In at least one embodiment, a system for adaptive routing in network communications includes at least one switch (such as a leaf switch) or another device that determines which traffic queue to forward a given data packet to, based at least in part on the latency of one or more flow queues within each traffic queue. For example, the device may be configured to calculate the latency based on queue depth and the average amount of data leaving each queue. Next, a grade may be assigned based on the latency. This grade can be used to select the port or traffic queue for routing the data packet. In some implementations, the device may receive data indicating a decrease in the amount of data in the corresponding queue and calculate the rate of traffic leaving that corresponding queue based on the received data.

[0016] In at least one embodiment, the device for providing adaptive routing includes one or more circuits for: determining the latency of each of a plurality of queues, wherein the latency of a given queue is determined based on the depth of the given queue and the rate of traffic leaving the given queue; selecting one of the plurality of queues for forwarding data packets, based at least in part on the determined latency of each queue; and forwarding the data packets to the selected queue.

[0017] In some implementations, the circuitry is further configured to receive data indicating a decrease in the amount of data in the corresponding queue, and to calculate the rate of traffic leaving the corresponding queue using the data indicating the decrease. In some implementations, the circuitry is further configured to calculate the rate of traffic leaving the corresponding queue by dividing the decrease in the amount of data by a time window. In some implementations, the circuitry is further configured to calculate the rate of traffic leaving the corresponding queue by normalizing the decrease in the amount of data based on a time window. In some implementations, the circuitry is further configured to determine the delay of the corresponding queue by right-shifting the depth of the corresponding queue by the logarithm of the rate of traffic leaving the corresponding queue to base 2. In some implementations, each of the multiple queues is associated with an egress port. In some implementations, the queues of the multiple queues are flow queues, and one or more circuits are further configured to select a flow queue based on the determined delay of each queue. In some implementations, the circuitry is further configured to assign a level to each of the multiple queues based on the determined delay, and to use the level to select a queue. In some implementations, the level is used by adaptive routing circuitry to select the queue.

[0018] In at least one embodiment, a dedicated integrated controller (ASIC) is configured to: determine the latency of each of a plurality of queues, wherein the latency of a given queue is determined based on the depth of the given queue and the rate of traffic leaving the given queue; select a queue from the plurality of queues for forwarding data packets, at least in part based on the determined latency of each queue; and forward the data packets to the selected queue. In some implementations, the ASIC is further configured to receive data indicating a reduction in the amount of data in the given queue, and to calculate the rate of traffic leaving the given queue using the data indicating the reduction. In some implementations, the ASIC is further configured to calculate the rate of traffic leaving the given queue by dividing the reduction in the amount of data by a time window. In some implementations, the ASIC is further configured to calculate the rate of traffic leaving the given queue by normalizing the reduction in the amount of data based on a time window. In some implementations, the ASIC is further configured to determine the latency of the given queue by right-shifting the depth of the given queue by the logarithm of the rate of traffic leaving the given queue to base 2. In some implementations, each of the plurality of queues is associated with an egress port. In some implementations, the queues among the multiple queues are flow queues, and the ASIC is further used to select a flow queue based on the determined latency of each queue. In some implementations, the ASIC is further used to assign a level to each of the multiple queues based on the determined latency, and use that level to select a queue. In some implementations, this level is used by adaptive routing circuitry to select that one queue.

[0019] In at least one embodiment, a method includes: determining the latency of each of a plurality of queues, wherein the latency of a respective queue is determined based on the depth of the respective queue and the rate of traffic leaving the respective queue; selecting a queue from the plurality of queues for forwarding a data packet, at least in part based on the determined latency of each queue; and forwarding the data packet to the selected queue. In some implementations, the method further includes: receiving data indicating a reduction in the amount of data in the respective queue; and using the data indicating the reduction to calculate the rate of traffic leaving the respective queue. In some implementations, the method further includes: calculating the rate of traffic leaving the respective queue by dividing the reduction in the amount of data by a time window. In some implementations, the method further includes: calculating the rate of traffic leaving the respective queue by normalizing the reduction in the amount of data based on a time window. In some implementations, the method further includes: determining the latency of the respective queue by right-shifting the depth of the respective queue by the base-2 logarithm of the rate of traffic leaving the respective queue. In some implementations, each of the plurality of queues is associated with an egress port. In some implementations, the queues among the multiple queues are flow queues, and the method further includes selecting a flow queue based on the determined delay of each queue. In some implementations, the method further includes assigning a level to each of the multiple queues based on the determined delay, and using that level to select a queue. In some implementations, the level is used by an adaptive routing circuit to select that one queue.

[0020] Figure 2 The illustration depicts a topology associated with a system for adaptive routing in Ethernet communications, according to at least one embodiment. In the illustrated topology, there are two super spine switches 206 and four spine switches 203, connected to them by four leaf switches 114. Each arrow connecting the spine switches 203, super spine switches 206, and leaf switches 114 may represent multiple links. As an example, each of the spine switches 1, 2, 3, and 4 203 may be connected to each super spine switch 206 via sixteen paths. Due to any number of factors, one or more paths between the spine switches 1, 2, 3, and 4 203 and the super spine switches 1 and 2 206 may become inactive, such as due to congestion or other network problems.

[0021] A path that is operating as expected can be considered active. As an example of a scenario where an adaptive routing system as described herein can be utilized, consider the arrow connecting spine switch 1 203 to super spine switch 1 206 as representing four links. If one of the four links between spine switch 1 203 and super spine switch 1 206 fails, then destinations accessible through super spine switch 1 206 should receive 3 / 4 of the total throughput capacity.

[0022] In network clusters, unbalanced topology can be caused by various factors, such as cable detachment, uneven traffic distribution, or inherent structural asymmetry. These imbalances often lead to congestion and poor network performance, especially in large-scale clusters. Traditional routing algorithms struggle to manage traffic effectively in such scenarios because they typically don't consider potential bottlenecks along the path. Current solutions for adaptive routing often require costly hardware upgrades or significant modifications to existing infrastructure. A more efficient and cost-effective approach to adaptive routing is needed, particularly one that can leverage existing hardware and is compatible with previous generations of products.

[0023] like Figure 3 As illustrated herein, the computing device 303 mentioned can be a node, computing system, switch, router, network interface controller (NIC), network endpoint, network device, or any device including several ports 306a-d and capable of transmitting data. The ports 306a-d of the computing device 303 can be used to interconnect with other devices 303 (such as nodes, computing systems, network endpoints, and network devices) to form a network. Device 303 can act as a central node in the network or can be any node in the network. Device 303 can be cabled in topologies including, for example, spine switches, top-of-rack (TOR) switches, tail-of-row switches, and / or leaf switches. The network of device 303 can include one or more spine switches and / or one or more leaf switches, and can be connected to other devices 303. As a non-limiting example, the network can be configured to include a multi-layer switch topology, which can include one or more devices 303 connecting one or more network endpoints. Other non-limiting examples of network topologies that can be utilized in a network include dragonfly networks, two-level fat-tree networks, three-level networks, etc. This device 303's network can provide use cases for a wide range of settings, from data centers and cloud computing infrastructure to artificial intelligence systems.

[0024] Device 303 is capable of receiving data (e.g., data packets), processing data, and forwarding the data to appropriate destinations within the network, such as other devices 303 and / or network endpoints. In some implementations, device 303 may be included in a chassis, platform, or rack, which may contain one or more devices 303 and one or more power supply devices and / or other components.

[0025] In some implementations, device 303 may include one or more ports 306a-c connected to one or more ports 306 of other devices 303 and / or other network endpoints. Although Figure 3 Device 303 is illustrated as including four ports 306a-d, but it should be understood that device 303 may include more or fewer ports than depicted. Processes such as applications executed by network endpoints may include transmitting data via device 303 to other network endpoints on the network. Data may flow across the network using one or more protocols such as Transmission Control Protocol (TCP), User Datagram Protocol (UDP), or Internet Protocol (IP). Each device 303, upon receiving data from a network endpoint or another device 303, may examine the data to identify its destination and route it across the network. Routing within device 303 may be implemented using a combination of switching hardware 309 and one or more other circuits.

[0026] Ports 306a-d of device 303 facilitate the transmission, delivery, and transfer of data packets or de-packetized data through device 303. Such ports 306a-d can be used as interface points for connecting network cables, thereby connecting device 303 to other devices 303 and / or other nodes.

[0027] Each port 306a-d is capable of receiving incoming data packets from other devices and / or transmitting outgoing data packets to other devices. In some implementations, ports 306a-d may be configured to operate as dedicated ingress or egress ports 306, or may be configured to operate in a dual capacity, capable of performing both ingress and egress functions. For example, egress port 306 may be dedicated to sending data from device 303, while ingress port 306 may be used solely to receive incoming data into device 303.

[0028] The switching hardware 309 of device 303 is capable of handling received data packets by determining the port 306 from which data packets will be sent and forwarding the data packets from the determined port 306. Each port 306 of device 303 may be associated with one or more queues 321a-d. When a data packet or data of any format is to be sent from port 306, the data packet may be stored in the queue 321 associated with port 306 until port 306 is ready and / or available for sending the data packet.

[0029] Switching hardware 309 may include several queues 321a-d for supporting data packet streams entering and exiting ports 306a-d respectively. In some embodiments, queues 321a-d may correspond to buffers 312, etc., that can be used to temporarily store or collect data packets or portions thereof when received at ports 306a-d and / or for transmission through ports 306a-d.

[0030] To support the functionality of the switching hardware 309, one or more circuits may be configured to control various aspects of the switching hardware 309 to implement packet-related adaptive routing. For example, one or more circuits may be configured to operate as an adaptive routing (AR) engine 327. These circuits may include one or more processors or microprocessors, and in some implementations may include a CPU, ASIC, NIC, and / or other processing circuitry systems capable of handling the computational, decision-making, and management functions required for the operation of the computing device 303.

[0031] The AR Engine 327 can be configured to dynamically adjust packet forwarding decisions based on real-time network conditions. In some implementations, the AR Engine 327 can continuously monitor congestion levels, link utilization, latency, and / or other metrics used to optimize traffic flow. The AR Engine 327 can receive input from multiple sources, including network telemetry data, link state information, flow statistics, congestion feedback mechanisms, and routing policies configured by the network administrator. These inputs enable the AR Engine 327 to analyze queue depth, packet loss rate, Explicit Congestion Notification (ECN) flags, Priority Flow Control (PFC) pause frames, historical link utilization trends, and / or other indicators. Based on such real-time indicators, the AR Engine 327 can determine how traffic should be routed to avoid congestion, how traffic should be distributed more evenly across available links, or how traffic should be prioritized according to defined QoS policies.

[0032] AR engine 327 can process incoming telemetry and network status information and update the forwarding table, equal cost multipath (ECMP) balancing configuration, and / or traffic shaping mechanism of device 303 to reflect optimized routing decisions. If congestion is detected, AR engine 327 can modify ECMP functions, adjust flow assignment, or insert packet tags to guide traffic through lower utilization paths. In some implementations, AR engine 327 can interact with circuitry such as packet pruning to perform functions such as selectively reducing packet size, removing redundant fields in headers, or truncating payloads.

[0033] The queue information system 324 may be a circuit or group of circuits responsible for storing, managing, and analyzing queue information data, which will be used by the AR engine 327 and / or other circuitry to control packet scheduling, congestion control, traffic prioritization, and / or other functions. The queue information system 324 may monitor queue depth, buffer occupancy, packet arrival rate, packet loss rate, and traffic category distribution to provide information related to network conditions. The queue information system 324 may be implemented within an ASIC or other components and may interface directly with the AR engine 327 and / or the central database system 330.

[0034] The queue information system 324 can also send queue depth information to the central database system 330 for use by the AR engine 327 and / or other components of device 303 to perform AR, network monitoring, analysis, and / or congestion prediction. Such data can be transmitted in the form of pop signals (decreasing amounts) per flow queue (TQ) and per flow queue (FQ) or per {TQ, FQ} and / or queue depth signals, where TQ and FQ represent different levels of traffic aggregation and flow-specific queue structures. Pop signals, as described herein, can indicate the rate at which packets are dequeued, allowing the AR engine 327 to track queue emptying rates over time. Queue depth signals can provide periodic snapshots of queue occupancy, enabling the AR engine 327 to determine the level of traffic congestion within queues 321a-d of device 303. AI-driven network optimizers, SDN controllers, or centralized telemetry platforms can utilize this information for real-time adjustments, such as reallocating bandwidth, rerouting traffic, or modifying buffer management policies.

[0035] As described herein, a TQ can represent an aggregated queue that stores packets based on traffic categories such as Quality of Service (QoS) or other types of priority levels. An FQ, as described herein, can be a queue that stores packets from a specific flow. A flow, as described herein, can be a stream of packets identified by one or more of the following identifiers: source IP, destination IP, source port, destination port, protocol type, and / or other identifiers. FQs can operate within a TQ, and a TQ can contain multiple FQs.

[0036] The circuitry of device 303 can be configured to handle the management and control functions of device 303, such as managing routing groups, creating tables, configuring ports, and otherwise managing the operation of device 303. The circuitry can execute software and / or firmware to configure and manage device 303, such as an operating system and management tools.

[0037] For example, such circuitry in device 303 may include processor 315. Processor 315 of device 303 may include one or more processing circuitry (such as a graphics processing unit (GPU), central processing unit (CPU), data processing unit (DPU), ASIC, field-programmable gate array (FPGA), or one or more other circuitry capable of performing computations) and memory and storage resources for running software applications, handling data processing, and performing specific tasks as needed. In some implementations, device 303 may also, or alternatively, include hardware such as a GPU for handling intensive tasks for machine learning, artificial intelligence (AI) workloads, or other complex processes.

[0038] The switching hardware 309 of device 303 and / or one or more other circuits may utilize information stored in memory 318 to support routing decisions. As described herein, the memory 318 of device 303 may include one or more memory elements capable of storing configuration settings, routing groups, application data, operating system data, and other data. Such memory elements may include, for example, random access memory (RAM), dynamic RAM (DRAM), flash memory, non-volatile RAM (NVRAM), ternary content-addressable memory (TCAM), static RAM (SRAM), and / or other formats of memory elements. The memory elements of memory 318 may also include one or more registers, such as general-purpose registers, special-purpose registers, data registers, and other types of registers that can be used to store and retrieve information relating to queue fill levels, packet QoS values, and other information.

[0039] As described in further detail herein, the memory 318 of device 303 may store information related to the performance of device 303. As an example, memory 318 may store information such as data related to the round-trip time of data packets received and transmitted by device 303, congestion of device 303, congestion of one or more ports 306a-d of device 303, calculation of congestion per queue 321a-d of device 303, packet loss of device 303, calculation of error rate of device 303, bandwidth utilization of device 303, throughput of device 303, temperature of device 303, power metric of device 303, and / or other information.

[0040] Information stored in memory 318 of device 303 can be used in relation to responding to probe packets (as described in more detail below) by appending data to probe packets received by device 303, such that probe packets can be transmitted from device 303 and received by another device 303, which can be enabled to access the information to determine or analyze the performance of device 303.

[0041] The memory 318 of device 303 can also be used to store data in the form of a database and / or registers. For example, memory 318 may include registers that can be used to store sampled QoS values, as described below. Memory 318 may hold an egress queue mapping database that can be used to map probe packets received by computing device 303 to priority egress queues. Memory 318 may also hold an egress queue fill level database that can be used to store sampled values ​​of the fill levels of the egress queues of computing device 303.

[0042] like Figure 4 The illustrated queue information system 324 of the device (such as an ASIC) described herein can output a pop signal 406 on a per TQ and / or per FQ basis, and output a queue depth signal 409 on a per TQ and / or per FQ basis.

[0043] As described in this article, a TQ can be associated with a specific egress port. For example, each egress port of a switch can be associated with a TQ. Data packets destined for transmission via a specific egress port can be stored in the TQ to await transmission.

[0044] As described in this article, an FQ can be associated with a specific TQ. For example, each TQ of a switch can be associated with one or more FQs. FQs can be used to provide QoS or other priority levels for routed packets. Packets of different flows that are to be sent via the same egress port can be stored in different FQs within a single TQ associated with that egress port.

[0045] Pop signal 406 may correspond to a packet exit event from one or more FQs. Pop signal 406 may be an indicator generated when a packet physically exits the exit queue. Pop signal 406 may be generated by queue information system 324 as described above, which may be one or more circuits within an ASIC. Queue information system 324 may be configured to initiate a pop signal after determining that a packet has been successfully delivered from an FQ and / or TQ, and the pop signal may be a digital signal indicating packet departure, for example, transmitted via a control line or bus.

[0046] For example, each pop signal 406 may include a signal such as a logic high ("1") pulse. In some implementations, pop signal 406 may further identify the FQ and / or TQ associated with pop signal 406. For example, pop signal 406 may indicate that a packet has left a specific FQ within a specific TQ.

[0047] The queue depth signal 409 (also referred to herein as the occupancy level signal) indicates the current occupancy or fill level of each individual queue within the device's memory. The queue depth signal 409 can be generated individually and explicitly for each FQ and / or TQ. The queue depth signal 409 can originate from a queue information system 324 that continuously monitors each FQ and / or TQ. In some implementations, the queue information system 324 can maintain an occupancy counter. For example, the corresponding occupancy counter can increment for each enqueue operation triggered by the arrival of a packet and its storage in a given FQ and / or TQ, and decrement for each dequeue operation that corresponds to the generation of the pop signal 406 described above.

[0048] The queue depth signal 409 can be digitally represented as a value in the device's memory or register. In some implementations, the queue depth signal 409 can be a packet count (e.g., indicating the number of packets currently queued) or a byte count (e.g., indicating the number of bits or bytes currently queued). The queue depth signal 409 can be continuously or periodically available to the central database system 327. For example, the central database system 327 can store the current queue depth of one or more TQs and / or FQs.

[0049] As described above, the central database system 327 can receive the pop signal 406 and the queue depth signal 409, and can store the pop signal 406 and / or the queue depth signal 409 in their original format, or can use the pop signal 406 and the queue depth signal 409 to update the memory within the central database system 327.

[0050] The central database system 327 can be configured to calculate the pop rate 415 on a per TQ and / or per FQ basis. For a given FQ, the pop rate 415 can be calculated by the central database system 327 based on the cumulative count of pop signals 406 associated with that FQ and a predetermined time window. The database system 327 can maintain a counter associated with each FQ, which can increment each time a pop signal 406 of the FQ is received.

[0051] At the end of each predetermined time window, the central database system 327 can divide the current cumulative pop signal count from the counter by the duration of the time window to generate a pop rate 415. Depending on the implementation, the resulting pop rate 415 can be expressed numerically as packets per second, or bytes or bits per second.

[0052] In some implementations, to simplify division, the operating circuitry can be configured to perform a shift or otherwise normalize the accumulated pop signal count to a time window. For example, the accumulated pop signal count can be shifted right by one time window.

[0053] The central database system 327 can be further configured to output a delay 418 on a per TQ and / or per FQ basis. The delay 418 can indicate the amount of delay or time experienced by packets in each FQ and / or TQ. The delay 418 can be calculated by the central database system 327 based on the queue depth signal 409 and the pop rate 415. To determine the delay 418 on a per TQ and / or per FQ basis, the central database system 327 can perform an arithmetic division of the queue depth of the FQ by the pop rate 415 of that FQ. In various implementations, the central database system 327 can perform the delay determination at predetermined intervals or continuously. As described above, the resulting delay 418 determination can be output as a signal to the AR engine 330.

[0054] In some implementations, a circuit can be used to calculate the delay, configured to right-shift the FQ occupancy rate or queue depth to the logarithm (log2) of the pop rate. The right shift as described herein can be performed using one or more multiplexers and / or combined shift logic. In some implementations, the delay can also be determined to be zero if the pop rate is zero.

[0055] AR engine 330 can be configured to receive and / or read packet data 424 and output port decision 427 on a per-packet basis. As described below, port decision 427 can indicate the TQ and / or specific FQ to which the packet associated with packet data 424 should be forwarded. Port decision 427 can be made by AR engine 330 based on delay 418 from central database system 327, and can be via the following... Figure 7The method 700 and based on the following text regarding Figure 6 It is made based on the aforementioned port level.

[0056] As described herein, packet data 424 may include data associated with a packet to be transmitted by the device. Packet data 424 may include the entire packet, a packet header, or one or more specific fields of the packet header. AR engine 330 can use packet data 424 to identify the destination of the packet associated with packet data 424. Based on the destination of the packet, AR engine 330 is able to identify one or more TQs or egress ports from which the packet may be routed to its destination. Port decision 427 may indicate the TQ and / or egress port to which the packet associated with packet data 424 should be forwarded.

[0057] As described herein, the AR engine 330 can be configured to determine which TQ to forward a specific data packet to based on the latency of each TQ. Based on this latency, the AR engine can assign a rank to each TQ and / or FQ, and can send data packets to the TQ and / or FQ with the optimal rank.

[0058] like Figure 5 As illustrated, comparator 503 can be used to map a delay 506 based on FQ and / or TQ to a specific threshold to generate an AR level 509. The process of assigning an AR level 509 based on a comparison of the delay and the threshold can be described below. Figure 6 As stated herein, while AR Level 509 is described as relating to latency determination, it should be understood that additional or alternative factors, such as buffer occupancy, queue utilization, and configuration settings, may be considered.

[0059] To assign a grade to an FQ, the FQ's delay can be compared to one or more thresholds. For example, if the delay is less than a first threshold, the initial grade can be determined to be zero. If the delay is greater than or equal to the first threshold and less than a second threshold, the initial grade can be determined to be 1. If the delay is greater than or equal to the second threshold and less than a third threshold, the initial grade can be determined to be 2, and so on. It should be understood that the specific grade numbers used in this document are provided for illustrative purposes only and should not be considered as limiting in any way.

[0060] Figure 6 The illustration shows an embodiment according to at least one of the embodiments. Figure 1-5The system contains a process flow or method 600 for adaptive routing. Method 600 begins at 603 and ends at 612. Method 600 can be executed using a switch or other computing device. In some implementations, method 600 may begin in response to the receipt of a data packet, or it may be an ongoing process repeated throughout the duration of the operation of the device executing method 600. In some implementations, method 600 may be executed in parallel, such as for different ingress ports, different flows, etc. Method 600 may include: using a queuing information system, a central database system, and / or an adaptive routing engine that performs adaptive routing to provide port decisions for data packets.

[0061] Using method 600, levels can be assigned to ports, TQs, and / or FQs. These levels can be used to route packets in such a way that an efficient communication link between the source and destination can be established between a first device (such as a computing device's NIC, leaf switch, spine switch, or super spine switch) and a remote device (such as a leaf switch, spine switch, or super spine switch). Alternatively or additionally, levels can be used to select the port of the device performing method 600 for transmitting specific packets. Although Figure 2 A specific network topology is shown, but it should be understood that the systems and methods described herein can be used for other topologies.

[0062] In some implementations, as a result of method 600, data packets can be transmitted over the network on egress ports in a desired distribution manner. For example, method 600 can be used to assign levels to several FQ, TQ, and / or egress ports, and the AR engine can use the assigned levels to achieve specific distributions in response to network events such as the creation of new paths, link failures, etc. In some implementations, method 600 can be combined with the following... Figure 7 The described method 700 is executed to select a path for network communication between the device and the destination. For example, method 600 can be executed by a device in the network to assign levels to FQ, TQ, and / or ports, and method 700 can be executed by a device to use these levels to route packets, resulting in efficient distribution of traffic throughout the network.

[0063] like Figure 6As illustrated, method 600 may include receiving a pop signal and a queue depth or occupancy signal at 603. The pop signal and queue depth may be associated with a specific FQ within a specific TQ, which is associated with a specific port. As described above, the pop signal may be an indication that one or more packets have left the FQ. For example, the pop signal may indicate the amount of data reduction in the corresponding FQ. The queue depth or occupancy signal may be the current amount of data or the current number of packets in the corresponding FQ. Alternatively, the queue depth signal may be data that the device performing the method can use to calculate, determine, or estimate the amount of data or the current number of packets in the FQ.

[0064] Next, at 606, the device can calculate the pop rate based on the pop signal and a time window. This pop rate can be the rate of traffic leaving the corresponding FQ. As described above, the pop rate can be calculated using the pop signal and a time window. The pop rate, or the rate of traffic leaving the corresponding FQ, can be calculated by dividing the decrease in the pop signal or data volume by the time window. In some implementations, the rate of traffic leaving the corresponding queue can be calculated by normalizing the decrease in data volume based on the time window or by right-shifting the decrease in data volume by the time window.

[0065] After calculating the pop-out rate, at point 609, the device can determine the latency based on the queue depth signal and the pop-out rate. As described above, the latency of a given queue can be determined based on the depth of that queue and the rate at which traffic leaves that queue. The latency of a given queue can be determined by right-shifting the depth of that queue by the logarithm of the rate at which traffic leaves that queue. In some implementations, method 600 may include determining the latency of each of a plurality of queues. For example, method 600 may be executed in parallel for multiple FQs, TQs, streams, egress ports, or other packets.

[0066] Finally, at 612, based on a comparison of the delay with one or more thresholds, the delay can be used to assign a level to the queue associated with that delay. As described above, the AR engine can be configured to compare the delay with one or more thresholds to map the delay to a level. The level to which the delay is mapped can be assigned to the queue associated with that delay, and this level can be used, for example, via the following discussion... Figure 7 The method described in 700 is used to select a queue.

[0067] Figure 7 The illustration shows an embodiment according to at least one of the embodiments. Figure 1-5The system contains a process flow or method 700 for adaptive routing. Method 700 begins at 703 and ends at 712. Method 700 can be executed using a switch or other computing device. In some implementations, method 700 may begin in response to the receipt of a data packet, or it may be an ongoing process repeated throughout the entire operating duration of the device executing method 700. In some implementations, method 700 may be executed in parallel, for example, for different ingress ports, different flows, or other methods. Method 700 may include using a queuing information system, a central database system, and / or an adaptive routing engine that performs adaptive routing to provide port decisions for data packets.

[0068] Using method 700, a port, TQ, and / or FQ can be selected for a data packet, and the data packet can be forwarded to that port, TQ, and / or FQ in such a way that the path between the device performing method 700 (such as a computing device's NIC, leaf switch, spine switch, or super spine switch) and a remote device (such as a leaf switch, spine switch, or super spine switch) enables an efficient communication link between source and destination. Although Figure 2 A specific network topology is shown, but it should be understood that the systems and methods described herein can be used with other topologies.

[0069] In some implementations, as a result of method 700, data packets can be transmitted over the network at the egress port in the desired distribution manner. For example, method 700 can be executed by the AR engine to achieve specific distributions due to network events such as the creation of a new path, link failure, etc. In some implementations, method 700 can be combined with the above-mentioned... Figure 6 The described method 600 is executed to select a path for network communication between the device and the destination. For example, method 600 can be executed by a device in the network to assign levels to FQ, TQ, and / or ports, and method 700 can be executed by a device to use these levels to route packets, resulting in efficient distribution of traffic throughout the network.

[0070] like Figure 7 As illustrated, method 700 may include receiving data packets at 703. As described above, the device may be a switch, router, or another device that receives and forwards data packets over a network. The device may include a dedicated ingress port or a port capable of sending and receiving data. Data packets may be received from one or more interconnected devices in the form of packaged data streams. When a data packet first arrives at a device, the device may process the data packet using switching hardware circuitry such as an ASIC, as described above.

[0071] At point 706, the device can also determine the latency of one or more exit queues. Exit queues can be, for example, FQ and / or TQ. Determining the queue latency can be done as described above regarding... Figure 6 However, it should be understood that in some implementations, the queue delay can be determined in other ways. This disclosure should not be construed as limiting oneself to any particular delay system used to determine the queue delay.

[0072] Next, at 709, a queue can be selected based on the delay of each determined queue. This queue can be selected from a group of queues, where each queue in the group is a potential option for routing packets received at 703. For example, the device's AR engine or other circuitry can be configured to determine the destination of the packets and, based on that destination, determine a group of queues from which packets can be forwarded. As described above, each queue can be associated with an egress port. By selecting a queue, the device can effectively select the port from which packets are transmitted. Furthermore, while the systems and methods of this disclosure are described herein with respect to queue selection, it should be understood that the same or similar systems and methods can be used to select the port from which packets are routed.

[0073] The selection of queues can be based at least in part on the determined latency of each queue. For example, as described above, the queue latency can be used to assign a rank to the queue. Each queue in the queue group from which packets are forwarded can be assigned a rank, and the AR engine or other circuitry can be configured to select a queue to route packets based at least in part on that rank or otherwise at least in part on the latency of each queue. In some implementations, each FQ can be assigned a rank, and the AR engine can route packets to a specific TQ based on the rank of each FQ or the determined latency of each FQ.

[0074] Finally, at 712, the packet can be forwarded to the selected queue. For example, the packet can be placed in the selected queue, which can be a TQ or an FQ within a TQ. When the packet reaches the head of the selected queue, it can be removed from the queue, thereby initiating the pop signal-related event as described above. Finally, after dequeueing, the packet can be transmitted to the network medium via the egress port associated with the selected queue.

[0075] Figure 8 A block diagram of an example system 800 according to at least one embodiment is illustrated. In at least one embodiment, system 800 may include one or more CPUs 810 connected to one or more multi-GPU communication systems (e.g., multi-GPU communication system 802) via one or more signal conductors 812. Figure 8In the illustrated embodiment, one or more CPUs 810 include CPUs 810A and 810B, respectively connected to the multi-GPU communication system 802 via signal conductors 812A and 812B. Figure 8 In the multi-GPU communication system 802, GPUs 808 are interconnected via at least one switch 806 and at least one signal conductor 804. In the illustrated embodiment, one or more switches 806 include switches 806A-806D, GPUs 808 include GPUs 808A-808P, and one or more signal conductors 804 include signal conductors 804A-804E.

[0076] As a non-limiting example, signal conductor 804 can link GPU 808 to one or more switches 806, and signal conductors 812A and 812B can link at least one of the switches 806 to one or more CPUs 810. Figure 8 As illustrated, CPUs 810A and 810B can be connected to switches 806A and 806C respectively via signal conductors 812A and 812B. In at least one embodiment, one or more of the CPUs 810 can be implemented as follows: Figure 16 The CPU 1600 and GPU 808 shown in the illustration can be implemented as one or more GPUs. Figure 14 The illustration shows one or more parallel processors 1412.

[0077] The multi-GPU communication system 802 can be implemented as a mesh network, which can have a local area network topology in which infrastructure nodes or devices can be directly, dynamically, and non-hierarchically connected to other nodes and can cooperate with each other to efficiently route data. Examples of infrastructure devices may include bridges, one or more switches 806, and / or other types of infrastructure devices. The multi-GPU communication system 802 may be referred to as a GPU-to-GPU system. By way of non-limiting example, the multi-GPU communication system 802 can be implemented as a GPU-to-GPU link system (e.g., an NVLINK® GPU-to-GPU interconnect system), in which one or more switches 806 may include one or more GPU-to-GPU switches (e.g., one or more NVSWITCH™ switches).

[0078] Switch 806A is connected to GPUs 808A-808D via signal conductor 804A, switch 806B is connected to GPUs 808E-808H via signal conductor 804B, switch 806C is connected to GPUs 808I-808L via signal conductor 804C, and switch 806D is connected to GPUs 808M-808P via signal conductor 804D. Switches 806A-806D are interconnected via signal conductor 804E. During the duration of the dedicated connection, each of the one or more switches 806 can act as a connection between two endpoints within a router and / or system 800. In at least one embodiment, one or more switches of the one or more switches 806 can be implemented using a node-on-node switch architecture (e.g., one or more NVSWITCH™ switches) that connects processing units (e.g., one or more GPUs, one or more CPUs, and / or one or more other types of processors). System 800 can be used as part of another system (such as a data center) that includes hardware, network, software and / or libraries, and executes applications that perform inference, for example, by executing artificial intelligence (“AI”) or machine learning models.

[0079] The systems and methods described herein can be used, but are not limited to, non-autonomous vehicles, semi-autonomous vehicles (e.g., in one or more adaptive driver assistance systems (ADAS)), manned and unmanned robots or robotic platforms, warehouse vehicles, off-road vehicles, vehicles coupled to one or more trailers, aircraft, boats, shuttles, emergency response vehicles, motorcycles, electric or motorized bicycles, aircraft, engineering vehicles, underwater vehicles, drones, and / or other types of vehicles. The systems and methods described herein can be used in augmented reality, virtual reality, mixed reality, robotics, security and supervision, autonomous or semi-autonomous machine applications, and / or any other technological space where one or more signal conductors may have at least two distinct states consuming different amounts of power.

[0080] The systems and methods described herein can be used, but are not limited to, non-autonomous vehicles, semi-autonomous vehicles (e.g., in one or more adaptive driver assistance systems (ADAS)), manned and unmanned robots or robotic platforms, warehouse vehicles, off-road vehicles, vehicles coupled to one or more trailers, aircraft, boats, shuttles, emergency response vehicles, motorcycles, electric or motorized bicycles, aircraft, engineering vehicles, underwater vehicles, drones, and / or other types of vehicles. Furthermore, the systems and methods described herein can be used for a variety of purposes, by way of example but not limited to, machine control, machine motion, machine driving, synthetic data generation, model training, perception, augmented reality, virtual reality, mixed reality, robotics, safety and supervision, simulation and digital twins, autonomous or semi-autonomous machine applications, deep learning, environmental simulation, object or actor simulation and / or digital twins, data center processing, conversational AI, optical transport simulation (e.g., ray tracing, path tracing, etc.), collaborative content creation for 3D assets, cloud computing, web hosting services or web hosting platforms, and / or any other suitable applications.

[0081] The disclosed embodiments can comprise a variety of different systems, such as automotive systems (e.g., control systems for autonomous or semi-autonomous machines, perception systems for autonomous or semi-autonomous machines), systems implemented using robots, aviation systems, medical systems, boating systems, smart area monitoring systems, systems for performing deep learning operations, systems for performing simulation operations, systems for performing digital twin operations, systems implemented using edge devices, systems containing one or more virtual machines (VMs), systems for performing synthetic data generation operations, systems implemented at least partially in a data center, systems for performing conversational AI operations, systems for performing optical transmission simulations, systems for performing collaborative content creation for 3D assets, systems implemented at least partially using cloud computing resources, systems for implementing web hosting services (e.g., runtime for program optimization) or web hosting platforms (e.g., integrated development environments including program optimization as a service) (as an application programming interface (“API”) between two or more separate applications or systems), and other types of systems.

[0082] Data Center Figure 9 An example data center 900 according to at least one embodiment is shown. In at least one embodiment, the data center 900 includes, but is not limited to, a data center infrastructure layer 910, a framework layer 920, a software layer 930, and an application layer 940.

[0083] In at least one embodiment, such as Figure 9As shown, the data center infrastructure layer 910 may include a resource coordinator 912, grouped computing resources 914, and node computing resources (“nodes CR”) 916(1)-916(N), where “N” represents any complete positive integer. In at least one embodiment, nodes CR 916(1)-916(N) may include, but are not limited to, any number of central processing units (“CPUs”) or other processors (including accelerators, field-programmable gate arrays (“FPGAs”), data processing units (“DPUs”) in network devices, graphics processors, etc.), memory devices (e.g., dynamic read-only memory), storage devices (e.g., solid-state drives or disk drives), network input / output (“NW I / O”) devices, network switches, virtual machines (“VMs”), power modules, and cooling modules, etc. In at least one embodiment, one or more of nodes CR 916(1)-916(N) may be servers having one or more of the aforementioned computing resources.

[0084] In at least one embodiment, the grouped computing resources 914 may include individual groups (not shown) of node CRs housed in one or more racks, or a plurality of racks (also not shown) housed in data centers in various geographic locations. The individual groups of node CRs within the grouped computing resources 914 may include computing, networking, memory, or storage resources that can be configured or allocated to support groups of one or more workloads. In at least one embodiment, several node CRs, including CPUs or processors, may be grouped within one or more racks to provide computing resources to support one or more workloads. In at least one embodiment, one or more racks may also include any number of power modules, cooling modules, and network switches, in any combination.

[0085] In at least one embodiment, resource coordinator 912 may be configured or otherwise control one or more nodes CR 916(1)-916(N) and / or grouped computing resources 914. In at least one embodiment, resource coordinator 912 may include a Software Design Infrastructure (“SDI”) management entity for data center 900. In at least one embodiment, resource coordinator 912 may include hardware, software, or some combination thereof.

[0086] In at least one embodiment, such as Figure 9As shown, the framework layer 920 includes, but is not limited to, a job scheduler 932, a configuration manager 934, a resource manager 936, and a distributed file system 938. In at least one embodiment, the framework layer 920 may include a framework of software 952 supporting the software layer 930 and / or one or more applications 942 of the application layer 940. In at least one embodiment, the software 952 or application 942 may respectively include web-based service software or applications, such as services or applications provided by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, the framework layer 920 may be, but is not limited to, a free and open-source software web application framework, such as Apache Spark™ (hereinafter referred to as "Spark") which can leverage the distributed file system 938 for large-scale data processing (e.g., "big data"). In at least one embodiment, the job scheduler 932 may include a Spark driver to facilitate the scheduling of workloads supported by the various layers of the data center 900. In at least one embodiment, the configuration manager 934 may be able to configure different layers, such as the software layer 930 and the framework layer 920 including Spark and the distributed file system 938 for supporting large-scale data processing. In at least one embodiment, resource manager 936 is capable of managing cluster or group computing resources mapped to or allocated to support distributed file system 938 and job scheduler 932. In at least one embodiment, cluster or group computing resources may include group computing resources 914 on data center infrastructure layer 910. In at least one embodiment, resource manager 936 may coordinate with resource coordinator 912 to manage these mapped or allocated computing resources.

[0087] In at least one embodiment, the software 952 included in the software layer 930 may include software used by at least a portion of the nodes CR 916(1)-916(N), the grouped computing resources 914, and / or the distributed file system 938 of the framework layer 920. One or more types of software may include, but are not limited to, Internet web page search software, email virus scanning software, database software, and streaming video content software.

[0088] In at least one embodiment, one or more applications 942 included in the application layer 940 may include one or more types of applications used by at least a portion of nodes CR 916(1)-916(N), grouped computing resources 914, and / or the distributed file system 938 of the framework layer 920. One or more types of applications may include, but are not limited to, CUDA applications.

[0089] In at least one embodiment, any of the configuration manager 934, resource manager 936, and resource coordinator 912 can implement any number and type of self-modification actions based on any amount and type of data acquired in any technically feasible manner. In at least one embodiment, self-modification actions can mitigate potentially poor configuration decisions by data center operators of data center 900 and can prevent underutilization and / or poor performance of the data center.

[0090] In at least one embodiment, the data center 900 can be used to implement, for example, a combination of Figures 1-8 The description refers to one or more systems and / or processes of the like.

[0091] Computer-based systems The following figures present, but are not limited to, example computer-based systems that can be used to implement at least one embodiment.

[0092] Figure 10 A processing system 1000 according to at least one embodiment is illustrated. In at least one embodiment, the system 1000 includes one or more processors 1002 and one or more graphics processors 1008, and may be a single-processor desktop system, a multi-processor workstation system, or a server system having a large number of processors 1002 or processor cores 1007. In at least one embodiment, the processing system 1000 is a processing platform incorporated within a system-on-a-chip (SoC) integrated circuit for use in mobile, handheld, or embedded devices.

[0093] In at least one embodiment, the processing system 1000 may include or be integrated into a server-based gaming platform, including a game console, mobile game console, handheld game console, or online game console, which are game and media consoles. In at least one embodiment, the processing system 1000 is a mobile phone, smartphone, tablet computing device, or mobile internet device. In at least one embodiment, the processing system 1000 may also include components coupled to or integrated into a wearable device, such as a smartwatch, smart glasses, augmented reality, or virtual reality device. In at least one embodiment, the processing system 1000 is a television or set-top box device having one or more processors 1002 and a graphical interface generated by one or more graphics processors 1008.

[0094] In at least one embodiment, each of the one or more processors 1002 includes one or more processor cores 1007 to process instructions that, when executed, perform operations against the system and user software. In at least one embodiment, each of the one or more processor cores 1007 is configured to process a specific instruction set 1009. In at least one embodiment, the instruction set 1009 may facilitate Complex Instruction Set Computing (CISC), Reduced Instruction Set Computing (RISC), or computation via Very Long Instruction Word (VLIW). In at least one embodiment, the plurality of processor cores 1007 may each process a different instruction set 1009, which may include instructions that facilitate the emulation of other instruction sets. In at least one embodiment, the processor cores 1007 may also include other processing devices, such as digital signal processors (DSPs).

[0095] In at least one embodiment, processor 1002 includes cache memory 1004. In at least one embodiment, processor 1002 may have a single internal cache or multiple levels of internal caches. In at least one embodiment, the cache memory is shared among various components of processor 1002. In at least one embodiment, processor 1002 also uses an external cache (e.g., a Level 3 (L3) cache or a last-level cache (LLC)) (not shown), which can be shared among processor cores 1007 using known cache coherence techniques. In at least one embodiment, processor 1002 further includes a register file 1006, which may include different types of registers (e.g., integer registers, floating-point registers, status registers, and instruction pointer registers) for storing different types of data. In at least one embodiment, register file 1006 may include general-purpose registers or other registers.

[0096] In at least one embodiment, one or more processors 1002 are coupled to one or more interface buses 1010 to transmit communication signals, such as address, data, or control signals, between the processor 1002 and other components in the system 1000. In at least one embodiment, the interface bus 1010 may be a processor bus, such as a version of the Direct Media Interface (DMI) bus. In at least one embodiment, the interface bus 1010 is not limited to the DMI bus and may include one or more peripheral component interconnect buses (e.g., PCI, PCI Express), memory buses, or other types of interface buses. In at least one embodiment, the processor 1002 includes an integrated memory controller 1016 and a platform controller hub 1030. In at least one embodiment, the memory controller 1016 facilitates communication between storage devices and other components of the processing system 1000, while the platform controller hub (PCH) 1030 provides connectivity to input / output (I / O) devices via a local I / O bus.

[0097] In at least one embodiment, storage device 1020 may be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase-change memory device, or a device with suitable performance for use as processor memory. In at least one embodiment, storage device 1020 may be used as system memory of processing system 1000 to store data 1022 and instructions 1021 for use when one or more processors 1002 execute applications or processes. In at least one embodiment, memory controller 1016 is also coupled to an optional external graphics processor 1012, which may communicate with one or more graphics processors 1008 of processor 1002 to perform graph and media operations. In at least one embodiment, display device 1011 may be connected to processor 1002. In at least one embodiment, display device 1011 may include one or more internal display devices, such as those in mobile electronic devices or portable computer devices, or external display devices connected via a display interface (e.g., DisplayPort). In at least one embodiment, the display device 1011 may include a head-mounted display (HMD), such as a stereoscopic display device for virtual reality (VR) or augmented reality (AR) applications.

[0098] In at least one embodiment, the platform controller hub 1030 enables peripheral devices to connect to the storage device 1020 and the processor 1002 via a high-speed I / O bus. In at least one embodiment, the I / O peripheral devices include, but are not limited to, an audio controller 1046, a network controller 1034, a firmware interface 1028, a wireless transceiver 1026, a touch sensor 1025, and a data storage device 1024 (e.g., a hard disk drive, flash memory, etc.). In at least one embodiment, the data storage device 1024 may be connected via a memory interface (e.g., SATA) or via a peripheral bus, such as a peripheral component interconnect bus (e.g., PCI, PCIe). In at least one embodiment, the touch sensor 1025 may include a touchscreen sensor, a pressure sensor, or a fingerprint sensor. In at least one embodiment, the wireless transceiver 1026 may be a Wi-Fi transceiver, a Bluetooth transceiver, or a mobile network transceiver, such as a 3G, 4G, or LTE transceiver. In at least one embodiment, the firmware interface 1028 enables communication with the system firmware and may be, for example, a Unified Extensible Firmware Interface (UEFI). In at least one embodiment, network controller 1034 may enable network connectivity to a wired network. In at least one embodiment, a high-performance network controller (not shown) is coupled to interface bus 1010. In at least one embodiment, audio controller 1046 is a multi-channel high-definition audio controller. In at least one embodiment, processing system 1000 includes an optional legacy I / O controller 1040 for coupling legacy (e.g., Personal System 2 (PS / 2)) devices to processing system 1000. In at least one embodiment, platform controller hub 1030 may also be connected to one or more Universal Serial Bus (USB) controllers 1042 that connect input devices, such as a keyboard and mouse combination 1043, a camera 1044, or other USB input devices.

[0099] In at least one embodiment, instances of the memory controller 1016 and platform controller hub 1030 may be integrated into a discrete external graphics processor, such as external graphics processor 1012. In at least one embodiment, the platform controller hub 1030 and / or the memory controller 1016 may be external to one or more processors 1002. For example, in at least one embodiment, the processing system 1000 may include an external memory controller 1016 and a platform controller hub 1030, which may be configured as a memory controller hub and a peripheral controller hub in a system chipset communicating with the processor 1002.

[0100] In at least one embodiment, the processing system 1000 can be used to implement, for example, a combination. Figures 1-8 The description refers to one or more systems and / or processes of the like.

[0101] Figure 11 A computer system 1100 according to at least one embodiment is illustrated. In at least one embodiment, the computer system 1100 may be a system having interconnected devices and components, a System-on-a-Chip (SoC), or some combination thereof. In at least one embodiment, the computer system 1100 is formed by a processor 1102, which may include execution units for executing instructions. In at least one embodiment, the computer system 1100 may include, but is not limited to, components such as the processor 1102, which employs execution units including logic to execute algorithms for process data. In at least one embodiment, the computer system 1100 may include a processor, such as the PENTIUM® processor family, Xeon™, Itanium®, XScale™ and / or StrongARM™, Intel® Core™ or Intel® Nervana™ microprocessors available from Intel Corporation of Santa Clara, California, although other systems (including PCs, engineering workstations, set-top boxes, etc.) may also be used. In at least one embodiment, computer system 1100 may execute a version of the Windows operating system available from Microsoft Corporation of Redmond, Wash., although other operating systems (such as UNIX and Linux), embedded software, and / or graphical user interfaces may also be used.

[0102] In at least one embodiment, the computer system 1100 can be used in other devices, such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol (IP) devices, digital cameras, personal digital assistants (“PDAs”), and handheld PCs. In at least one embodiment, the embedded application may include a microcontroller, a digital signal processor (“DSP”), a system-on-a-chip (SoC), a network computer (“Net PC”), a set-top box, a network hub, a wide area network (“WAN”) switch, or any other system capable of executing one or more instructions according to at least one embodiment.

[0103] In at least one embodiment, computer system 1100 may include, but is not limited to, processor 1102, which may include, but is not limited to, one or more execution units 1108 configured to execute Computing Unified Device Architecture (“CUDA”) programs (CUDA® is developed by NVIDIA Corporation in Santa Clara, California). In at least one embodiment, a CUDA program is at least a portion of a software application written in the CUDA programming language. In at least one embodiment, computer system 1100 is a single-processor desktop or server system. In at least one embodiment, computer system 1100 may be a multiprocessor system. In at least one embodiment, processor 1102 may include, but is not limited to, a CISC microprocessor, a RISC microprocessor, a VLIW microprocessor, a processor implementing instruction set combinations, or any other processor device, such as a digital signal processor. In at least one embodiment, processor 1102 may be coupled to a processor bus 1110, which can transmit data signals between processor 1102 and other components in computer system 1100.

[0104] In at least one embodiment, processor 1102 may include, but is not limited to, a Level 1 (“L1”) internal cache memory (“cache”) 1104. In at least one embodiment, processor 1102 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, the cache memory may reside external to processor 1102. In at least one embodiment, processor 1102 may include a combination of internal and external caches. In at least one embodiment, register file 1106 may store different types of data in various registers, including but not limited to integer registers, floating-point registers, status registers, and instruction pointer registers.

[0105] In at least one embodiment, an execution unit 1108, including but not limited to logic for performing integer and floating-point operations, is also located within the processor 1102. The processor 1102 may also include a microcode (“ucode”) read-only memory (“ROM”) for storing microcode of certain macro instructions. In at least one embodiment, the execution unit 1108 may include logic for processing a packaged instruction set 1109. In at least one embodiment, by including the packaged instruction set 1109 in the instruction set of the general-purpose processor 1102, along with the associated circuitry for executing the instructions, packaged data in the general-purpose processor 1102 can be used to perform operations used by numerous multimedia applications. In at least one embodiment, many multimedia applications can be executed more quickly and efficiently by using the full width of the processor’s data bus to perform operations on the packaged data, which may eliminate the need to transfer smaller data units on the processor’s data bus to perform one or more operations on a data element at a time.

[0106] In at least one embodiment, the execution unit 1108 may also be used in a microcontroller, embedded processor, graphics device, DSP, and other types of logic circuitry. In at least one embodiment, the computer system 1100 may include, but is not limited to, the memory 1120. In at least one embodiment, the memory 1120 may be implemented as a DRAM device, an SRAM device, a flash memory device, or other storage device. The memory 1120 may store instructions 1119 and / or data 1121 represented by data signals that can be executed by the processor 1102.

[0107] In at least one embodiment, the system logic chip may be coupled to processor bus 1110 and memory 1120. In at least one embodiment, the system logic chip may include, but is not limited to, a memory controller hub (“MCH”) 1116, and processor 1102 may communicate with MCH 1116 via processor bus 1110. In at least one embodiment, MCH 1116 may provide a high-bandwidth memory path 1118 to memory 1120 for instruction and data storage, as well as for storage of graphics commands, data, and textures. In at least one embodiment, MCH 1116 may initiate data signals between processor 1102, memory 1120, and other components in computer system 1100, and bridge data signals between processor bus 1110, memory 1120, and system I / O 1122. In at least one embodiment, the system logic chip may provide a graphics port for coupling to a graphics controller. In at least one embodiment, MCH 1116 can be coupled to memory 1120 via high-bandwidth memory path 1118, and graphics / video card 1112 can be coupled to MCH 1116 via Accelerated Graphics Port (“AGP”) interconnect 1114.

[0108] In at least one embodiment, computer system 1100 may use system I / O 1122 as a proprietary hub interface bus to couple MCH 1116 to I / O controller hub (“ICH”) 1130. In at least one embodiment, ICH 1130 may provide direct connectivity to certain I / O devices via a local I / O bus. In at least one embodiment, the local I / O bus may include, but is not limited to, a high-speed I / O bus for connecting peripheral devices to memory 1120, chipset, and processor 1102. Examples may include, but are not limited to, an audio controller 1129, a firmware hub (“Flash BIOS”) 1128, a wireless transceiver 1126, data storage 1124, a conventional I / O controller 1123 and keyboard interface including user input 1125, a serial expansion port 1127 (e.g., USB), and a network controller 1134. Data storage 1124 may include a hard disk drive, floppy disk drive, CD-ROM device, flash memory device, or other mass storage device.

[0109] In at least one embodiment, Figure 11 A system comprising interconnected hardware devices or "chips" is shown. In at least one embodiment, Figure 11 An example SoC can be shown. In at least one embodiment, Figure 11The devices shown can be interconnected with proprietary interconnects, standardized interconnects (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of system 1100 are interconnected using a compute fast link (CXL) interconnect.

[0110] In at least one embodiment, the computer system 1100 can be used to implement, for example, a combination Figures 1-8 The description refers to one or more systems and / or processes of the like.

[0111] Figure 12 A system 1200 according to at least one embodiment is illustrated. In at least one embodiment, system 1200 is an electronic device utilizing processor 1210. In at least one embodiment, system 1200 may be, for example, but not limited to, a laptop computer, tower server, rack server, blade server, edge device communicatively coupled to one or more local or cloud service providers, laptop computer, desktop computer, tablet computer, mobile device, telephone, embedded computer, or any other suitable electronic device.

[0112] In at least one embodiment, system 1200 may include, but is not limited to, processor 1210 communicatively coupled to any suitable number or type of components, peripherals, modules, or devices. In at least one embodiment, processor 1210 uses a bus or interface coupling, such as an I2C bus, a system management bus (“SMBus”), a low pin count (LPC) bus, a serial peripheral interface (“SPI”), a high-definition audio (“HDA”) bus, a serial advanced technology accessory (“SATA”) bus, a USB (versions 1, 2, and 3) bus, or a universal asynchronous receiver / transmitter (“UART”) bus. In at least one embodiment, Figure 12 A system is illustrated, comprising interconnected hardware devices or "chips". In at least one embodiment, Figure 12 An example SoC can be shown. In at least one embodiment, Figure 12 The device shown can be interconnected with proprietary interconnects, standardized interconnects (e.g., PCIe), or some combination thereof. In at least one embodiment, Figure 12 One or more components are interconnected using Computational Fast Link (CXL) interconnects.

[0113] In at least one embodiment, Figure 12This may include a display 1224, a touchscreen 1225, a touchpad 1230, a near-field communication unit (“NFC”) 1245, a sensor hub 1240, a thermal sensor 1246, a fast chipset (“EC”) 1235, a trusted platform module (“TPM”) 1238, a BIOS / firmware / flash memory (“BIOS, FW Flash”) 1222, a DSP 1260, a solid-state drive (“SSD”) or hard disk drive (“HDD”) 1220, a wireless local area network unit (“WLAN”) 1250, a Bluetooth unit 1252, a wireless wide area network unit (“WWAN”) 1256, a global positioning system (GPS) 1255, a camera (“USB 3.0 camera”) 1254 (e.g., a USB 3.0 camera), or a low-power double data rate (“LPDDR”) memory unit (“LPDDR3”) 1215 implemented in, for example, the LPDDR3 standard. These components may each be implemented in any suitable manner.

[0114] In at least one embodiment, other components may be communicatively coupled to processor 1210 via the components discussed above. In at least one embodiment, accelerometer 1241, ambient light sensor (“ALS”) 1242, compass 1243, and gyroscope 1244 may be communicatively coupled to sensor hub 1240. In at least one embodiment, thermal sensor 1239, fan 1237, keyboard 1236, and touchpad 1230 may be communicatively coupled to EC 1235. In at least one embodiment, speaker 1263, earphone 1264, and microphone (“mic”) 1265 may be communicatively coupled to audio unit (“audio codec and Class D amplifier”) 1262, which in turn may be communicatively coupled to DSP 1260. In at least one embodiment, audio unit 1262 may include, for example, but not limited to, audio encoder / decoder (“codec”) and Class D amplifier. In at least one embodiment, SIM card (“SIM”) 1257 may be communicatively coupled to WWAN unit 1256. In at least one embodiment, components such as WLAN unit 1250, Bluetooth unit 1252, and WWAN unit 1256 can be implemented as next-generation form factor (NGFF).

[0115] In at least one embodiment, system 1200 can be used to implement, for example, a combination. Figures 1-8 The description refers to one or more systems and / or processes of the like.

[0116] Figure 13An example integrated circuit 1300 according to at least one embodiment is illustrated. In at least one embodiment, the example integrated circuit 1300 is a SoC (System-on-a-Chip) that can be fabricated using one or more IP cores. In at least one embodiment, the integrated circuit 1300 includes one or more application processors 1305 (e.g., CPU, DPU), at least one graphics processor 1310, and may additionally include an image processor 1315 and / or a video processor 1320, any of which may be a modular IP core. In at least one embodiment, the integrated circuit 1300 includes peripheral or bus logic including a USB controller 1325, a UART controller 1330, an SPI / SDIO controller 1335, and an I2S / I2C controller 1340. In at least one embodiment, the integrated circuit 1300 may include a display device 1345 coupled to one or more of a High Definition Multimedia Interface (HDMI) controller 1350 and a Mobile Industrial Processor Interface (MIPI) display interface 1355. In at least one embodiment, storage may be provided by a flash memory subsystem 1360, including flash memory and a flash memory controller. In at least one embodiment, a memory interface may be provided via memory controller 1365 for accessing SDRAM or SRAM memory devices. In at least one embodiment, some integrated circuits also include an embedded security engine 1370.

[0117] In at least one embodiment, the integrated circuit 1300 can be used to implement, for example, a combination of Figures 1-8 The description refers to one or more systems and / or processes of the like.

[0118] Figure 14 A computing system 1400 according to at least one embodiment is illustrated. In at least one embodiment, the computing system 1400 includes a processing subsystem 1401 having one or more processors 1402 and a system memory 1404 communicating via an interconnect path that may include a memory hub 1405. In at least one embodiment, the memory hub 1405 may be a separate component within a chipset assembly or may be integrated within one or more processors 1402. In at least one embodiment, the memory hub 1405 is coupled to an I / O subsystem 1411 via a communication link 1406. In at least one embodiment, the I / O subsystem 1411 includes an I / O hub 1407 that enables the computing system 1400 to receive input from one or more input devices 1408. In at least one embodiment, the I / O hub 1407 may enable a display controller, which is included in one or more processors 1402, for providing output to one or more display devices 1410A. In at least one embodiment, one or more display devices 1410A coupled to the I / O hub 1407 may include local, internal, or embedded display devices.

[0119] In at least one embodiment, the processing subsystem 1401 includes one or more parallel processors 1412 coupled to the memory hub 1405 via a bus or other communication link 1413. In at least one embodiment, the communication link 1413 may be one of many standards-based communication link technologies or protocols, such as, but not limited to, PCIe, or may be a vendor-specific communication interface or communication architecture. In at least one embodiment, the one or more parallel processors 1412 form a computationally concentrated parallel or vector processing system that may include a large number of processing cores and / or processing clusters, such as a multi-core integrated (MIC) processor. In at least one embodiment, the one or more parallel processors 1412 form a graphics processing subsystem capable of outputting pixels to one or more display devices 1410A coupled via an I / O hub 1407. In at least one embodiment, the one or more parallel processors 1412 may also include a display controller and a display interface (not shown) to enable direct connection to one or more display devices 1410B.

[0120] In at least one embodiment, system storage unit 1414 may be connected to I / O hub 1407 to provide a storage mechanism for computing system 1400. In at least one embodiment, I / O switch 1416 may be used to provide an interface mechanism to enable connectivity between I / O hub 1407 and other components, such as network adapter 1418 and / or wireless network adapter 1419 that may be integrated into the platform, and various other devices that may be added via one or more additional devices 1420. In at least one embodiment, network adapter 1418 may be an Ethernet adapter or another wired network adapter. In at least one embodiment, wireless network adapter 1419 may include one or more Wi-Fi, Bluetooth, NFC, or other network devices comprising one or more radios.

[0121] In at least one embodiment, the computing system 1400 may include other components not explicitly shown, including USB or other port connections, optical storage drives, video capture devices, etc., and may also be connected to the I / O hub 1407. In at least one embodiment, for Figure 14 The communication paths that interconnect the various components can be implemented using any suitable protocol, such as PCI (Peripheral Component Interconnect) based protocols (e.g., PCIe), or other bus or point-to-point communication interfaces and / or protocols (e.g., NVLink™ high-speed interconnect or interconnect protocols).

[0122] In at least one embodiment, one or more parallel processors 1412 include circuitry optimized for graphics and video processing (including, for example, video output circuitry) and constitute a graphics processing unit (GPU). In at least one embodiment, one or more parallel processors 1412 include circuitry optimized for general-purpose processing. In at least one embodiment, components of the computing system 1400 may be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, one or more parallel processors 1412, memory hub 1405, processor 1402, and I / O hub 1407 may be integrated into a system-on-a-chip (SoC) integrated circuit. In at least one embodiment, components of the computing system 1400 may be integrated into a single package to form a system-in-package (SIP) configuration. In at least one embodiment, at least a portion of the components of the computing system 1400 may be integrated into a multi-chip module (MCM) that can interconnect with other MCMs to a modular computing system. In at least one embodiment, the I / O subsystem 1411 and display device 1410B are omitted from the computing system 1400.

[0123] In at least one embodiment, the computing system 1400 can be used to implement, for example, a combination of... Figures 1-8 The description refers to one or more systems and / or processes of the like.

[0124] Processing system The following figures illustrate, but are not limited to, example processing systems that can be used to implement at least one embodiment.

[0125] Figure 15 An accelerated processing unit (“APU”) 1500 according to at least one embodiment is illustrated. In at least one embodiment, the APU 1500 was developed by AMD Inc. of Santa Clara, California. In at least one embodiment, the APU 1500 can be configured to execute applications, such as CUDA programs. In at least one embodiment, the APU 1500 includes, but is not limited to, a core complex 1510, a graphics complex 1540, an architecture 1560, an I / O interface 1570, a memory controller 1580, a display controller 1592, and a multimedia engine 1594. In at least one embodiment, the APU 1500 can be, but is not limited to, any combination of any number of core complexes 1510, any number of graphics complexes 1540, any number of display controllers 1592, and any number of multimedia engines 1594. For illustrative purposes, multiple instances of similar objects are indicated herein by reference numerals, wherein the reference numerals identify the object, and the numbers in parentheses identify the desired instances.

[0126] In at least one embodiment, the core complex 1510 is a CPU, the graphics complex 1540 is a GPU, and the APU 1500 is a processing unit that is not limited to 1510 and 1540 integrated onto a single chip. In at least one embodiment, some tasks may be assigned to the core complex 1510, while other tasks may be assigned to the graphics complex 1540. In at least one embodiment, the core complex 1510 is configured to execute main control software associated with the APU 1500, such as an operating system. In at least one embodiment, the core complex 1510 is the main processor of the APU 1500, which controls and coordinates the operation of other processors. In at least one embodiment, the core complex 1510 issues commands to control the operation of the graphics complex 1540. In at least one embodiment, the core complex 1510 may be configured to execute host executable code derived from CUDA source code, and the graphics complex 1540 may be configured to execute device executable code derived from CUDA source code.

[0127] In at least one embodiment, the core complex 1510 includes, but is not limited to, cores 1520(1)-1520(4) and L3 cache 1530. In at least one embodiment, the core complex 1510 may include, but is not limited to, any combination of any number of cores 1520 and any number and type of cache. In at least one embodiment, the cores 1520 are configured to execute instructions of a specific instruction set architecture (“ISA”). In at least one embodiment, each core 1520 is a CPU core.

[0128] In at least one embodiment, each core 1520 includes, but is not limited to, a fetch / decode unit 1522, an integer execution engine 1524, a floating-point execution engine 1526, and an L2 cache 1528. In at least one embodiment, the fetch / decode unit 1522 fetches instructions, decodes these instructions, generates micro-operations, and dispatches individual micro-instructions to the integer execution engine 1524 and the floating-point execution engine 1526. In at least one embodiment, the fetch / decode unit 1522 may simultaneously dispatch one micro-instruction to the integer execution engine 1524 and another micro-instruction to the floating-point execution engine 1526. In at least one embodiment, the integer execution engine 1524 performs operations not limited to integer and memory operations. In at least one embodiment, the floating-point engine 1526 performs operations not limited to floating-point and vector operations. In at least one embodiment, the fetch-decode unit 1522 dispatches micro-instructions to a single execution engine, which replaces both the integer execution engine 1524 and the floating-point execution engine 1526.

[0129] In at least one embodiment, each core 1520(i) can access the L2 cache 1528(i) included in core 1520(i), where i is an integer representing a specific instance of core 1520. In at least one embodiment, each core 1520 included in core complex 1510(j) is connected to other cores 1520 included in core complex 1510(j) via an L3 cache 1530(j) included in core complex 1510(j), where j is an integer representing a specific instance of core complex 1510. In at least one embodiment, a core 1520 included in core complex 1510(j) can access all L3 caches 1530(j) included in core complex 1510(j), where j is an integer representing a specific instance of core complex 1510. In at least one embodiment, the L3 cache 1530 may include, but is not limited to, any number of slices.

[0130] In at least one embodiment, the graphics complex 1540 may be configured to perform computational operations in a highly parallel manner. In at least one embodiment, the graphics complex 1540 is configured to perform graphics pipeline operations, such as drawing commands, pixel operations, geometric calculations, and other operations associated with rendering an image to a display. In at least one embodiment, the graphics complex 1540 is configured to perform graphics-independent operations. In at least one embodiment, the graphics complex 1540 is configured to perform both graphics-related and graphics-independent operations.

[0131] In at least one embodiment, the graphics complex 1540 includes, but is not limited to, any number of computing units 1550 and an L2 cache 1542. In at least one embodiment, the computing units 1550 share the L2 cache 1542. In at least one embodiment, the L2 cache 1542 is partitioned. In at least one embodiment, the graphics complex 1540 includes, but is not limited to, any number of computing units 1550 and any number (including zero) and type of cache. In at least one embodiment, the graphics complex 1540 includes, but is not limited to, any number of dedicated graphics hardware.

[0132] In at least one embodiment, each computing unit 1550 includes, but is not limited to, any number of SIMD units 1552 and shared memory 1554. In at least one embodiment, each SIMD unit 1552 implements a SIMD architecture and is configured to execute operations in parallel. In at least one embodiment, each computing unit 1550 may execute any number of thread blocks, but each thread block executes on a single computing unit 1550. In at least one embodiment, a thread block includes, but is not limited to, any number of execution threads. In at least one embodiment, a workgroup is a thread block. In at least one embodiment, each SIMD unit 1552 executes a different warp. In at least one embodiment, a warp is a group of threads (e.g., 16 threads), where each thread in the warp belongs to a single thread block and is configured to process different datasets based on a single instruction set. In at least one embodiment, prediction can be used to disable one or more threads in a warp. In at least one embodiment, a channel is a thread. In at least one embodiment, a work item is a thread. In at least one embodiment, a wavefront is a warp. In at least one embodiment, different wavefronts in a thread block can be synchronized together and communicate via shared memory 1554.

[0133] In at least one embodiment, structure 1560 is a system interconnect that facilitates data and control transfers across core complex 1510, graphics complex 1540, I / O interface 1570, memory controller 1580, display controller 1592, and multimedia engine 1594. In at least one embodiment, in addition to or instead of structure 1560, APU 1500 may also include, but is not limited to, any number and type of system interconnects that facilitate data and control transfers across any number and type of components that may be directly or indirectly linked, either internally or externally to APU 1500. In at least one embodiment, I / O interface 1570 represents any number and type of I / O interface (e.g., PCI, PCI-Extended (“PCI-X”), PCIe, Gigabit Ethernet (“GBE”), USB, etc.). In at least one embodiment, various types of peripheral devices are coupled to I / O interface 1570. In at least one embodiment, the peripheral device coupled to the I / O interface 1570 may include, but is not limited to, a keyboard, mouse, printer, scanner, joystick or other types of game controllers, media recording devices, external storage devices, network interface cards, etc.

[0134] In at least one embodiment, the display controller AMD92 displays images on one or more display devices (e.g., liquid crystal display (LCD) devices). In at least one embodiment, the multimedia engine 1594 includes, but is not limited to, any number and type of multimedia-related circuitry, such as video decoders, video encoders, image signal processors, etc. In at least one embodiment, the memory controller 1580 facilitates data transfer between the APU 1500 and the unified system memory 1590. In at least one embodiment, the core complex 1510 and the graphics complex 1540 share the unified system memory 1590.

[0135] In at least one embodiment, the APU 1500 implements a memory subsystem, including but not limited to any number and type of memory controllers 1580 and memory devices (e.g., shared memory 1554) that can be dedicated to a single component or shared among multiple components. In at least one embodiment, the APU 1500 implements a cache subsystem, including but not limited to one or more cache memories (e.g., L2 cache 1628, L3 cache 1530, and L2 cache 1542), each cache memory being component-private or shared among any number of components (e.g., core 1520, core complex 1510, SIMD unit 1552, compute unit 1550, and graphics complex 1540).

[0136] In at least one embodiment, the APU 1500 can be used to implement, for example, a combination of Figures 1-8 The description refers to one or more systems and / or processes of the like.

[0137] Figure 16 A CPU 1600 according to at least one embodiment is illustrated. In at least one embodiment, the CPU 1600 was developed by AMD Inc. of Santa Clara, California. In at least one embodiment, the CPU 1600 can be configured to execute an application. In at least one embodiment, the CPU 1600 is configured to execute host control software, such as an operating system. In at least one embodiment, the CPU 1600 issues commands to control the operation of an external GPU (not shown). In at least one embodiment, the CPU 1600 can be configured to execute host executable code derived from CUDA source code, and the external GPU can be configured to execute device executable code derived from such CUDA source code. In at least one embodiment, the CPU 1600 includes, but is not limited to, any number of core complexes 1610, architectures 1660, I / O interfaces 1670, and memory controllers 1680.

[0138] In at least one embodiment, the core complex 1610 includes, but is not limited to, cores 1620(1)-1620(4) and L3 cache 1630. In at least one embodiment, the core complex 1610 may include, but is not limited to, any combination of any number of cores 1620 and any number and type of cache. In at least one embodiment, the cores 1620 are configured to execute instructions of a specific ISA. In at least one embodiment, each core 1620 is a CPU core.

[0139] In at least one embodiment, each core 1620 includes, but is not limited to, a fetch / decode unit 1622, an integer execution engine 1624, a floating-point execution engine 1626, and an L2 cache 1628. In at least one embodiment, the fetch / decode unit 1622 fetches instructions, decodes these instructions, generates micro-operations, and dispatches individual micro-instructions to the integer execution engine 1624 and the floating-point execution engine 1626. In at least one embodiment, the fetch / decode unit 1622 may simultaneously dispatch one micro-instruction to the integer execution engine 1624 and another micro-instruction to the floating-point execution engine 1626. In at least one embodiment, the integer execution engine 1624 performs operations not limited to integer and memory operations. In at least one embodiment, the floating-point engine 1626 performs operations not limited to floating-point and vector operations. In at least one embodiment, the fetch-decode unit 1622 dispatches micro-instructions to a single execution engine, which replaces both the integer execution engine 1624 and the floating-point execution engine 1626.

[0140] In at least one embodiment, each core 1620(i) can access the L2 cache 1628(i) included in core 1620(i), where i is an integer representing a specific instance of core 1620. In at least one embodiment, each core 1620 included in core complex 1610(j) is connected to other cores 1620 in core complex 1610(j) via an L3 cache 1630(j) included in core complex 1610(j), where j is an integer representing a specific instance of core complex 1610. In at least one embodiment, a core 1620 included in core complex 1610(j) can access all L3 caches 1630(j) included in core complex 1610(j), where j is an integer representing a specific instance of core complex 1610. In at least one embodiment, the L3 cache 1630 may include, but is not limited to, any number of slices.

[0141] In at least one embodiment, structure 1660 is a system interconnect that facilitates data and control transfers across core complexes 1610(1)-1610(N) (where N is a positive integer), I / O interface 1670, and memory controller 1680. In at least one embodiment, in addition to or instead of structure 1660, CPU 1600 may also include, but is not limited to, any number and type of system interconnects that facilitate data and control transfers across any number and type of components that may be directly or indirectly linked, either inside or outside CPU 1600. In at least one embodiment, I / O interface 1670 represents any number and type of I / O interfaces (e.g., PCI, PCI-X, PCIe, GBE, USB, etc.). In at least one embodiment, various types of peripheral devices are coupled to I / O interface 1670. In at least one embodiment, peripheral devices coupled to I / O interface 1670 may include, but are not limited to, displays, keyboards, mice, printers, scanners, joysticks or other types of game controllers, media recording devices, external storage devices, network interface cards, etc.

[0142] In at least one embodiment, memory controller 1680 facilitates data transfer between CPU 1600 and system memory 1690. In at least one embodiment, core complex 1610 and graphics complex 1640 share system memory 1690. In at least one embodiment, CPU 1600 implements a memory subsystem, which includes, but is not limited to, any number and type of memory controllers 1680 and memory devices that may be dedicated to a component or shared among multiple components. In at least one embodiment, CPU 1600 implements a cache subsystem, which includes, but is not limited to, one or more cache memories (e.g., L2 cache 1628 and L3 cache 1630), each cache memory may be component-private or shared among any number of components (e.g., core 1620 and core complex 1610).

[0143] In at least one embodiment, CPU 1600 can be used to implement, for example, a combination of Figures 1-8 The description refers to one or more systems and / or processes of the like.

[0144] Figure 17An example accelerator integration slice 1790 according to at least one embodiment is illustrated. As used herein, a "slice" includes a designated portion of the processing resources of an accelerator integrated circuit. In at least one embodiment, the accelerator integrated circuit provides cache management, memory access, environment management, and interrupt management services for multiple graphics processing engines among multiple graphics acceleration modules. Each graphics processing engine may comprise a separate GPU. Optionally, the graphics processing engine may include different types of graphics processing engines within the GPU, such as graphics execution units, media processing engines (e.g., video encoders / decoders), samplers, and blit engines. In at least one embodiment, a graphics acceleration module may be a GPU having multiple graphics processing engines. In at least one embodiment, the graphics processing engines may be individual GPUs integrated on a general-purpose package, line card, or chip.

[0145] The application's effective address space 1782 within system memory 1714 stores process element 1783. In one embodiment, process element 1783 is stored in response to a GPU call 1781 from an application 1780 executing on processor 1707. Process element 1783 contains the processing state of the corresponding application 1780. A job descriptor (WD) 1784 contained in process element 1783 may be a single job requested by the application or may contain pointers to job queues. In at least one embodiment, WD 1784 is a pointer to a job request queue in the application's effective address space 1782.

[0146] The graphics acceleration module 1746 and / or the various graphics processing engines may be shared by all or some processes in the system. In at least one embodiment, infrastructure may be included for establishing a processing state and sending the WD 1784 to the graphics acceleration module 1746 to begin operation in a virtualized environment.

[0147] In at least one embodiment, a dedicated process programming model is used for implementation. In this model, a single process owns the graphics acceleration module 1746 or an individual graphics processing engine. Since the graphics acceleration module 1746 is owned by a single process, the hypervisor initializes the accelerator integrated circuit for the owned partition, and the operating system initializes the accelerator integrated circuit for the owned partition when the graphics acceleration module 1746 is allocated.

[0148] During operation, the WD fetch unit 1791 in the accelerator integrated slice 1790 fetches the next WD 1784, which includes instructions for the work to be performed by one or more graphics processing engines of the graphics acceleration module 1746. Data from the WD 1784 can be stored in register 1745 and used by the memory management unit (MMU) 1739, interrupt management circuitry 1747, and / or environment management circuitry 1748, as shown. For example, one embodiment of the MMU 1739 includes segment / page roaming circuitry for accessing segment / page tables 1786 within the OS virtual address space 1785. The interrupt management circuitry 1747 can handle interrupt events (INT) 1792 received from the graphics acceleration module 1746. When performing graph operations, the effective address 1793 generated by the graphics processing engine is translated into an actual address by the MMU 1739.

[0149] In one embodiment, the same register set 1745 is copied for each graphics processing engine and / or graphics acceleration module 1746 and can be initialized by the hypervisor or operating system. Each of these copied registers can be included in the accelerator integration slice 1790. Table 1 shows example registers that can be initialized by the hypervisor.

[0150] Table 1 – Registers for Supervisor Initialization Table 2 shows exemplary registers that can be initialized by the operating system.

[0151] Table 2 – Operating System Initialization Registers In one embodiment, each WD 1784 is specific to a particular graphics acceleration module 1746 and / or a particular graphics processing engine. It contains all the information required for the graphics processing engine to perform its work or to do so, or it may be a pointer to a memory location where the application has established a command queue for the work to be done.

[0152] In at least one embodiment, the accelerator integration slice 1790 can be used to achieve, for example, a combination Figures 1-8 The description refers to one or more systems and / or processes of the like.

[0153] Figures 18A-18B An example graphics processor according to at least one embodiment of this document is illustrated. In at least one embodiment, any example graphics processor may be manufactured using one or more IP cores. In addition to the illustrations, other logic and circuitry may be included in at least one embodiment, including additional graphics processor / cores, peripheral interface controllers, or general-purpose processor cores. In at least one embodiment, the example graphics processor is used within a System-on-a-Chip (SoC).

[0154] Figure 18A An example graphics processor 1810 of a SoC integrated circuit according to at least one embodiment is shown, which can be manufactured using one or more IP cores. Figure 18B An additional example graphics processor 1840 of a SoC integrated circuit according to at least one embodiment is shown, which can be manufactured using one or more IP cores. In at least one embodiment, Figure 18A The graphics processor 1810 is a low-power graphics processor core. In at least one embodiment, Figure 18B The graphics processor 1840 is a higher-performance graphics processor core. In at least one embodiment, each graphics processor 1810, 1840 may be... Figure 13 A variant of the 1310 graphics processor.

[0155] In at least one embodiment, the graphics processor 1810 includes a vertex processor 1805 and one or more fragment processors 1815A-1815N (e.g., 1815A, 1815B, 1815C, 1815D to 1815N-1 and 1815N). In at least one embodiment, the graphics processor 1810 can execute different shader programs via separate logic, such that the vertex processor 1805 is optimized to perform operations for the vertex shader program, while one or more fragment processors 1815A-1815N perform fragment (e.g., pixel) shading operations for fragments or pixels or shader programs. In at least one embodiment, the vertex processor 1805 performs the vertex processing stage of the 3D graphics pipeline and generates primitive and vertex data. In at least one embodiment, the fragment processors 1815A-1815N use the primitive and vertex data generated by the vertex processor 1805 to generate framebuffers for display on a display device. In at least one embodiment, the fragment processors 1815A-1815N are optimized to execute fragment shader programs as provided in the OpenGL API, which can be used to perform operations similar to those of pixel shader programs provided in the Direct 3D API.

[0156] In at least one embodiment, the graphics processor 1810 additionally includes one or more MMUs 1820A-1820B, caches 1825A-1825B, and circuit interconnects 1830A-1830B. In at least one embodiment, one or more MMUs 1820A-1820B provide a virtual-to-physical address mapping for the graphics processor 1810, including for the vertex processor 1805 and / or fragment processors 1815A-1815N, which can reference vertex or image / texture data stored in memory, in addition to vertex or image / texture data stored in one or more caches 1825A-1825B. In at least one embodiment, one or more MMUs 1820A-1820B can be synchronized with other MMUs within the system, including with... Figure 13 One or more application processors 1305, graphics processors 1315, and / or video processors 1320 are associated with one or more MMUs, enabling each processor 1305-1320 to participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnects 1830A-1830B enable the graphics processor 1810 to connect to other IP cores within the SoC via the SoC's internal bus or via a direct connection.

[0157] In at least one embodiment, the graphics processor 1840 includes Figure 18A The graphics processor 1810 includes one or more MMUs 1820A-1820B, caches 1825A-1825B, and circuit interconnects 1830A-1830B. In at least one embodiment, the graphics processor 1840 includes one or more shader cores 1855A-1855N (e.g., 1855A, 1855B, 1855C, 1855D, 1855E, 1855F, to 1855N-1 and 1855N) that provide a unified shader core architecture, wherein a single core or type of core can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, the number of shader cores may vary. In at least one embodiment, the graphics processor 1840 includes an inter-core task manager 1845 that acts as a thread dispatcher to assign execution threads to one or more shader cores 1855A-1855N and a tile unit 1858 to accelerate tile-based rendering operations, wherein rendering operations of a scene are subdivided in image space, for example, to take advantage of local spatial consistency within the scene or to optimize the use of internal caches.

[0158] In at least one embodiment, Figures 18A-18B One or more systems described in the text are used to achieve, for example, combination Figures 1-8 The description refers to one or more systems and / or processes of the like.

[0159] Figure 19A A graphics core 1900 according to at least one embodiment is shown. In at least one embodiment, the graphics core 1900 may include... Figure 13 The graphics processor 1310 is located within it. In at least one embodiment, the graphics core 1900 may be... Figure 18B The graphics core 1900 uses a unified shader core 1855A-1855N. In at least one embodiment, the graphics core 1900 includes a shared instruction cache 1902, texture units 1918, and cache / shared memory 1920, which are common to execution resources within the graphics core 1900. In at least one embodiment, the graphics core 1900 may include multiple slices 1901A-1901N or partitions of each core, and the graphics processor may include multiple instances of the graphics core 1900. Slices 1901A-1901N may include supporting logic including local instruction caches 1904A-1904N, thread schedulers 1906A-1906N, thread dispatchers 1908A-1908N, and a set of registers 1910A-1910N. In at least one embodiment, slices 1901A-1901N may include a set of additional functional units (AFU) 1912A-1912N, floating-point units (FPU) 1914A-1914N, integer arithmetic logic units (ALU) 1916A-1916N, address calculation units (ACU) 1913A-1913N, double-precision floating-point units (DPFPU) 1915A-1915N, and matrix processing units (MPU) 1917A-1917N.

[0160] In one embodiment, the FPU 1914A-1914N can perform single-precision (32-bit) and half-precision (16-bit) floating-point operations, while the DPFPU 1915A-1915N can perform double-precision (64-bit) floating-point operations. In at least one embodiment, the ALU 1916A-1916N can perform variable-precision integer operations with 8-bit, 16-bit, and 32-bit precision, and can be configured for mixed-precision operations. In at least one embodiment, the MPU 1917A-1917N can also be configured for mixed-precision matrix operations, including half-precision floating-point operations and 8-bit integer operations. In at least one embodiment, the MPU 1917A-1917N can perform various matrix operations to accelerate CUDA programs, including enabling support for accelerated General Matrix-to-Matrix Multiplication (GEMM). In at least one embodiment, the AFU 1912A-1912N can perform additional logical operations not supported by floating-point or integer units, including trigonometric operations (e.g., Sine, Cosine, etc.).

[0161] Figure 19B A general-purpose graphics processing unit (GPGPU) 1930 is illustrated in at least one embodiment. In at least one embodiment, the GPGPU 1930 is highly parallel and suitable for deployment on a multi-chip module. In at least one embodiment, the GPGPU 1930 can be configured to enable highly parallel computational operations to be performed by a GPU array. In at least one embodiment, the GPGPU 1930 can be directly linked to other instances of the GPGPU 1930 to create a multi-GPU cluster to improve execution time for CUDA programs. In at least one embodiment, the GPGPU 1930 includes a host interface 1932 for connection to a host processor. In at least one embodiment, the host interface 1932 is a PCIe interface. In at least one embodiment, the host interface 1932 can be a vendor-specific communication interface or communication structure. In at least one embodiment, the GPGPU 1930 receives commands from the host processor and uses a global scheduler 1934 to assign execution threads associated with those commands to a set of computational clusters 1936A-1936H. In at least one embodiment, computing clusters 1936A-1936H share cache memory 1938. In at least one embodiment, cache memory 1938 can be used as an advanced cache of cache memory within computing clusters 1936A-1936H.

[0162] In at least one embodiment, the GPGPU 1930 includes memory 1944A-1944B coupled to the computing cluster 1936A-1936H via a set of memory controllers 1942A-1942B. In at least one embodiment, memory 1944A-1944B may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory.

[0163] In at least one embodiment, computing clusters 1936A-1936H each include a set of graphics cores, such as Figure 19A The graphics core 1900 may include various types of integer and floating-point logic units, capable of performing computational operations at various precisions, including computations suitable for CUDA programs. For example, in at least one embodiment, at least a subset of the floating-point units in each computing cluster 1936A-1936H may be configured to perform 16-bit or 32-bit floating-point operations, while different subsets of the floating-point units may be configured to perform 64-bit floating-point operations.

[0164] In at least one embodiment, multiple instances of GPGPU 1930 can be configured to operate as a computing cluster. Computing clusters 1936A-1936H can implement any technically feasible communication technology for synchronization and data exchange. In at least one embodiment, the multiple instances of GPGPU 1930 communicate via host interface 1932. In at least one embodiment, GPGPU 1930 includes an I / O hub 1939 that couples GPGPU 1930 to GPU link 1940, enabling direct connection to other instances of GPGPU 1930. In at least one embodiment, GPU link 1940 is coupled to a dedicated GPU-to-GPU bridge, enabling communication and synchronization among the multiple instances of GPGPU 1930. In at least one embodiment, GPU link 1940 is coupled to a high-speed interconnect for sending and receiving data to and from other GPGPUs or parallel processors. In at least one embodiment, the multiple instances of GPGPU 1930 reside in a separate data processing system and communicate via a network device accessible via host interface 1932. In at least one embodiment, the GPU link 1940 may be configured to connect to a host processor, supplementing or replacing the host interface 1932. In at least one embodiment, the GPGPU 1930 may be configured to execute CUDA programs.

[0165] In at least one embodiment, Figures 19A-19BThe described system is used to detect and / or predict (e.g., within a multi-GPU system) signals conducted by signal conductors, using various algorithms, formulas, and / or processes (e.g., combining...). Figure 1-8 Those described herein) transition signal conductors between active and inactive states, and / or otherwise perform the operations described herein. In at least one embodiment, the GPU 808 (see...) Figure 8 One or more of these can be implemented using a general-purpose graphics processing unit 1930. In at least one embodiment, Figures 19A-19B The one or more systems described herein are used to implement one or more systems and / or processes, such as in combination. Figures 1-8 Those described.

[0166] Figure 20A A parallel processor 2000 according to at least one embodiment is shown. In at least one embodiment, various components of the parallel processor 2000 may be implemented using one or more integrated circuit devices, such as programmable processors, application-specific integrated circuits (ASICs), or FPGAs.

[0167] In at least one embodiment, the parallel processor 2000 includes a parallel processing unit 2002. In at least one embodiment, the parallel processing unit 2002 includes an I / O unit 2004 that enables communication with other devices, including other instances of the parallel processing unit 2002. In at least one embodiment, the I / O unit 2004 can be directly connected to other devices. In at least one embodiment, the I / O unit 2004 is connected to other devices using a hub or switch interface (e.g., a memory hub 2005). In at least one embodiment, the connection between the memory hub 2005 and the I / O unit 2004 forms a communication link. In at least one embodiment, the I / O unit 2004 is connected to a host interface 2006 and a memory crossbar switch 2016, wherein the host interface 2006 receives commands for performing processing operations, and the memory crossbar switch 2016 receives commands for performing memory operations.

[0168] In at least one embodiment, when host interface 2006 receives a command buffer via I / O unit 2004, host interface 2006 can direct work operations to execute those commands to front end 2008. In at least one embodiment, front end 2008 is coupled to scheduler 2010, which is configured to assign commands or other work items to processing array 2012. In at least one embodiment, scheduler 2010 ensures that processing array 2012 is correctly configured and in an active state before assigning tasks to processing array 2012. In at least one embodiment, scheduler 2010 is implemented via firmware logic executed on a microcontroller. In at least one embodiment, the microcontroller-implemented scheduler 2010 can be configured to perform complex scheduling and work assignment operations at both coarse and fine granular levels, thereby enabling fast preemption and environment switching of threads executing on processing array 2012. In at least one embodiment, host software can demonstrate workloads scheduled on processing array 2012 via one of multiple graphics processing doorbells. In at least one embodiment, the workload can then be automatically distributed on the processing array 2012 by the scheduler 2010 logic within the microcontroller, which includes the scheduler 2010.

[0169] In at least one embodiment, the processing array 2012 may include up to "N" processing clusters (e.g., clusters 2014A, 2014B to 2014N). In at least one embodiment, each cluster 2014A-2014N of the processing array 2012 may execute a large number of concurrent threads. In at least one embodiment, the scheduler 2010 may use various scheduling and / or work allocation algorithms to allocate work to the clusters 2014A-2014N of the processing array 2012, which may vary depending on the workload generated by each type of program or computation. In at least one embodiment, scheduling may be handled dynamically by the scheduler 2010, or may be partially assisted by compiler logic during the compilation of program logic configured to be executed by the processing array 2012. In at least one embodiment, different clusters 2014A-2014N of the processing array 2012 may be assigned to process different types of programs or to perform different types of computations.

[0170] In at least one embodiment, the processing array 2012 may be configured to perform various types of parallel processing operations. In at least one embodiment, the processing array 2012 is configured to perform general-purpose parallel computing operations. For example, in at least one embodiment, the processing array 2012 may include logic for performing processing tasks, including filtering video and / or audio data, performing modeling operations, including physical operations, and performing data transformations.

[0171] In at least one embodiment, the processing array 2012 is configured to perform parallel graphics processing operations. In at least one embodiment, the processing array 2012 may include additional logic to support the execution of such graphics processing operations, including but not limited to texture sampling logic for performing texture operations, as well as tessellation logic and other vertex processing logic. In at least one embodiment, the processing array 2012 may be configured to execute shader programs related to graphics processing, such as, but not limited to, vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. In at least one embodiment, the parallel processing unit 2002 may transfer data from system memory via I / O unit 2004 for processing. In at least one embodiment, during processing, the transferred data may be stored in on-chip memory (e.g., parallel processor memory 2022) and then written back to system memory.

[0172] In at least one embodiment, when the parallel processing unit 2002 is used to perform graph processing, the scheduler 2010 may be configured to divide the processing workload into tasks of approximately equal size to better distribute graphics processing operations among the multiple clusters 2014A-2014N of the processing array 2012. In at least one embodiment, portions of the processing array 2012 may be configured to perform different types of processing. For example, in at least one embodiment, a first portion may be configured to perform vertex shading and topology generation, a second portion may be configured to perform tessellation and geometry shading, and a third portion may be configured to perform pixel shading or other screen-space operations to generate a rendered image for display. In at least one embodiment, intermediate data generated by one or more of the clusters 2014A-2014N may be stored in a buffer to allow intermediate data to be transferred between the clusters 2014A-2014N for further processing.

[0173] In at least one embodiment, the processing array 2012 may receive processing tasks to be executed via a scheduler 2010, which receives commands defining the processing tasks from a front end 2008. In at least one embodiment, the processing task may include an index of data to be processed, such as surface (patch) data, raw data, vertex data, and / or pixel data, as well as state parameters and commands defining how the data is processed (e.g., what program to execute). In at least one embodiment, the scheduler 2010 may be configured to acquire an index corresponding to a task, or may receive an index from the front end 2008. In at least one embodiment, the front end 2008 may be configured to ensure that the processing array 2012 is configured to be active before initiating the workload specified by an incoming command buffer (e.g., a batch buffer, push buffer, etc.).

[0174] In at least one embodiment, each of one or more instances of the parallel processing unit 2002 may be coupled to the parallel processor memory 2022. In at least one embodiment, the parallel processor memory 2022 may be accessed via a memory crossbar switch 2016, which may receive memory requests from the processing array 2012 and the I / O unit 2004. In at least one embodiment, the memory crossbar switch 2016 may access the parallel processor memory 2022 via a memory interface 2018. In at least one embodiment, the memory interface 2018 may include a plurality of partition units (e.g., partition units 2020A, 2020B to 2020N), each of which may be coupled to a portion (e.g., a memory cell) of the parallel processor memory 2022. In at least one embodiment, the plurality of partition units 2020A-2020N are configured to be equal to the number of memory units, such that the first partition unit 2020A has a corresponding first memory unit 2024A, the second partition unit 2020B has a corresponding memory unit 2024B, and the Nth partition unit 2020N has a corresponding Nth memory unit 2024N. In at least one embodiment, the number of partition units 2020A-2020N may not be equal to the number of memory devices.

[0175] In at least one embodiment, memory cells 2024A-2024N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In at least one embodiment, memory cells 2024A-2024N may also include 3D stacked memory, including but not limited to high bandwidth memory (HBM). In at least one embodiment, rendering targets such as frame buffers or texture maps may be stored across memory cells 2024A-2024N, allowing partitioning cells 2020A-2020N to write portions of each rendering target in parallel, to efficiently utilize the available bandwidth of the parallel processor memory 2022. In at least one embodiment, local instances of the parallel processor memory 2022 may be excluded to facilitate a unified memory design that combines system memory with local cache memory.

[0176] In at least one embodiment, any of the clusters 2014A-2014N of the processing array 2012 can process data to be written to any memory cell 2024A-2024N within the parallel processor memory 2022. In at least one embodiment, the memory crossbar switch 2016 can be configured to transfer the output of each cluster 2014A-2014N to any partition cell 2020A-2020N or another cluster 2014A-2014N, and the clusters 2014A-2014N can perform further processing operations on the output. In at least one embodiment, each cluster 2014A-2014N can communicate with the memory interface 2018 via the memory crossbar switch 2016 to read from or write to various external storage devices. In at least one embodiment, the memory crossbar switch 2016 has a connection to a memory interface 2018 for communication with I / O unit 2004, and a connection to a local instance of parallel processor memory 2022, thereby enabling processing units within different processing clusters 2014A-2014N to communicate with system memory or other memory not local to parallel processing unit 2002. In at least one embodiment, the memory crossbar switch 2016 may use virtual channels to separate traffic flows between clusters 2014A-2014N and partition units 2020A-2020N.

[0177] In at least one embodiment, multiple instances of the parallel processing unit 2002 may be provided on a single insert card, or multiple insert cards may be interconnected. In at least one embodiment, different instances of the parallel processing unit 2002 may be configured to interoperate, even if the different instances have different numbers of processing cores, different numbers of local parallel processor memories, and / or other configuration differences. For example, in at least one embodiment, some instances of the parallel processing unit 2002 may include higher-precision floating-point units relative to other instances. In at least one embodiment, a system combining one or more instances of the parallel processing unit 2002 or the parallel processor 2000 may be implemented in various configurations and form factors, including but not limited to desktop, laptop, or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[0178] In at least one embodiment, Figure 20A One or more systems described in the text are used to achieve, for example, combination Figures 1-8 The description refers to one or more systems and / or processes of the like.

[0179] Figure 20B A processing cluster 2094 according to at least one embodiment is illustrated. In at least one embodiment, the processing cluster 2094 is included within a parallel processing unit. In at least one embodiment, the processing cluster 2094 is... Figure 20A An example of one of the processing clusters 2014A-2014N. In at least one embodiment, the processing cluster 2094 can be configured to execute a number of threads in parallel, wherein the term "thread" refers to an instance of a specific program executing on a particular set of input data. In at least one embodiment, a Single Instruction Multiple Data (SIMD) instruction issuing technique is used to support the parallel execution of a large number of threads without providing multiple independent instruction units. In at least one embodiment, a Single Instruction Multiple Threading (SIMT) technique is used to support the parallel execution of a large number of generally synchronous threads, which uses a common instruction unit configured to issue instructions to a set of processing engines within each processing cluster 2094.

[0180] In at least one embodiment, the operation of the processing cluster 2094 can be controlled by a pipeline manager 2032 that assigns processing tasks to the SIMT parallel processors. In at least one embodiment, the pipeline manager 2032... Figure 20A The scheduler 2010 receives instructions and manages the execution of these instructions via the graphics multiprocessor 2034 and / or texture unit 2036. In at least one embodiment, the graphics multiprocessor 2034 is an example instance of a SIMT parallel processor. However, in at least one embodiment, the processing cluster 2094 may include various types of SIMT parallel processors with different architectures. In at least one embodiment, the processing cluster 2094 may include one or more instances of the graphics multiprocessor 2034. In at least one embodiment, the graphics multiprocessor 2034 can process data, and the data crossover switch 2040 can be used to distribute the processed data to one of several possible destinations, including other shader units. In at least one embodiment, the pipeline manager 2032 can facilitate the distribution of processed data by specifying the destination of the processed data to be distributed via the data crossover switch 2040.

[0181] In at least one embodiment, each graphics multiprocessor 2034 within the processing cluster 2094 may include the same set of functional execution logic (e.g., arithmetic logic units, load-memory units (LSUs), etc.). In at least one embodiment, the functional execution logic may be configured in a pipelined manner, wherein new instructions may be issued before previous instructions complete. In at least one embodiment, the functional execution logic supports a variety of operations, including integer and floating-point arithmetic, comparison operations, Boolean operations, shift operations, and computation of various algebraic functions. In at least one embodiment, the same functional unit hardware may be used to perform different operations, and any combination of functional units may exist.

[0182] In at least one embodiment, instructions transmitted to the processing cluster 2094 constitute threads. In at least one embodiment, a group of threads executed across a set of parallel processing engines is a thread group. In at least one embodiment, the thread group executes programs on different input data. In at least one embodiment, each thread within the thread group may be assigned to a different processing engine within the graphics multiprocessor 2034. In at least one embodiment, the thread group may include fewer threads than the number of processing engines within the graphics multiprocessor 2034. In at least one embodiment, when the number of threads included in the thread group is less than the number of processing engines, one or more processing engines may be idle during a loop that is processing the thread group. In at least one embodiment, the thread group may also include more threads than the number of processing engines within the graphics multiprocessor 2034. In at least one embodiment, when the thread group includes more threads than the number of processing engines within the graphics multiprocessor 2034, processing can be performed in consecutive clock cycles. In at least one embodiment, multiple thread groups can be executed simultaneously on the graphics multiprocessor 2034.

[0183] In at least one embodiment, the graphics multiprocessor 2034 includes an internal cache memory for performing load and store operations. In at least one embodiment, the graphics multiprocessor 2034 may forgo the internal cache and use a cache memory within the processing cluster 2094 (e.g., L1 cache 2048). In at least one embodiment, each graphics multiprocessor 2034 may also access partition units (e.g., Figure 20A The L2 cache is located within partition units 2020A-2020N, ​​which are shared among all processing clusters 2094 and can be used to transfer data between threads. In at least one embodiment, the graphics multiprocessor 2034 can also access off-chip global memory, which may include one or more of local parallel processor memory and / or system memory. In at least one embodiment, any memory outside of the parallel processing unit 2002 can be used as global memory. In at least one embodiment, the processing cluster 2094 includes multiple instances of the graphics multiprocessor 2034, which can share common instructions and data that can be stored in the L1 cache 2048.

[0184] In at least one embodiment, each processing cluster 2094 may include an MMU 2045 configured to map virtual addresses to physical addresses. In at least one embodiment, one or more instances of the MMU 2045 may reside in Figure 20AWithin the memory interface 2018. In at least one embodiment, the MMU 2045 includes a set of page table entries (PTEs) for mapping virtual addresses to physical addresses of tiles (more on tiles) and optionally to cache line indices. In at least one embodiment, the MMU 2045 may include an address translation back buffer (TLB) or a cache that may reside within the graphics multiprocessor 2034, L1 cache 2048, or processing cluster 2094. In at least one embodiment, physical addresses are processed to allocate surface data access locality for efficient request interleaving between partition units. In at least one embodiment, cache line indices may be used to determine whether a request for a cache line is a hit or a miss.

[0185] In at least one embodiment, the processing cluster 2094 can be configured such that each graphics multiprocessor 2034 is coupled to a texture unit 2036 to perform texture mapping operations, which may involve determining texture sample locations, reading texture data, and filtering texture data. In at least one embodiment, texture data is read as needed from an internal texture L1 cache (not shown) or from an L1 cache within the graphics multiprocessor 2034, and texture data is also retrieved from an L2 cache, local parallel processor memory, or system memory. In at least one embodiment, each graphics multiprocessor 2034 outputs a processed task to a data crossbar switch 2040 to provide the processed task to another processing cluster 2094 for further processing or to store the processed task in an L2 cache, local parallel processor memory, or system memory via a memory crossbar switch 2016. In at least one embodiment, a pre-raster operation unit (preROP) 2042 is configured to receive data from the graphics multiprocessor 2034 and direct the data to a ROP unit, which may be associated with a partitioning unit (e.g., [missing information]). Figure 20A The PreROP2042 unit is located together with the partition units 2020A-2020N. In at least one embodiment, the PreROP2042 unit can perform optimizations for color blending, organize pixel color data, and perform address translation.

[0186] Figure 20C A graphics multiprocessor 2096 according to at least one embodiment is illustrated. In at least one embodiment, the graphics multiprocessor 2096 is Figure 20BThe graphics multiprocessor 2034 is included. In at least one embodiment, the graphics multiprocessor 2096 is coupled to the pipeline manager 2032 of the processing cluster 2094. In at least one embodiment, the graphics multiprocessor 2096 has an execution pipeline including, but not limited to, an instruction cache 2052, an instruction unit 2054, an address mapping unit 2056, a register file 2058, one or more GPGPU cores 2062, and one or more LSUs 2066. The GPGPU cores 2062 and LSUs 2066 are coupled to cache memory 2072 and shared memory 2070 via memory and cache interconnect 2068.

[0187] In at least one embodiment, instruction cache 2052 receives a stream of instructions to be executed from pipeline manager 2032. In at least one embodiment, instructions are cached in instruction cache 2052 and dispatched to instruction unit 2054 for execution. In one embodiment, instruction unit 2054 may dispatch instructions as thread groups (e.g., thread bundles), assigning each thread of the thread group to a different execution unit within GPGPU core 2062. In at least one embodiment, instructions can access any local, shared, or global address space by specifying an address within a unified address space. In at least one embodiment, address mapping unit 2056 may be used to translate addresses in the unified address space into different memory addresses that can be accessed by LSU 2066.

[0188] In at least one embodiment, register file 2058 provides a set of registers for functional units of graphics multiprocessor 2096. In at least one embodiment, register file 2058 provides temporary storage for operands of data paths connected to functional units of graphics multiprocessor 2096 (e.g., GPGPU core 2062, LSU 2066). In at least one embodiment, register file 2058 is partitioned among each functional unit, such that a dedicated portion of register file 2058 is allocated to each functional unit. In at least one embodiment, register file 2058 is partitioned among different thread groups being executed by graphics multiprocessor 2096.

[0189] In at least one embodiment, each of the GPGPU cores 2062 may include an FPU and / or an ALU for executing instructions of the graph multiprocessor 2096. The GPGPU cores 2062 may be architecturally similar or may differ in architecture. In at least one embodiment, a first portion of the GPGPU core 2062 includes a single-precision FPU and an integer ALU, while a second portion of the GPGPU core includes a double-precision FPU. In at least one embodiment, the FPU may implement the IEEE 754-2008 standard for floating-point arithmetic or enable variable-precision floating-point arithmetic. In at least one embodiment, the graphics multiprocessor 2096 may additionally include one or more fixed-function or special-function units to perform specific functions, such as copying rectangles or pixel blending operations. In at least one embodiment, one or more of the GPGPU cores 2062 may also include fixed-function or special-function logic.

[0190] In at least one embodiment, the GPGPU core 2062 includes SIMD logic capable of executing a single instruction on multiple sets of data. In at least one embodiment, the GPGPU core 2062 can physically execute SIMD4, SIMD8, and SIMD9 instructions, and logically execute SIMD1, SIMD2, and SIMD32 instructions. In at least one embodiment, the SIMD instructions for the GPGPU core can be generated by a shader compiler at compile time, or automatically generated when executing a program written and compiled for a Single Program Multiple Data (SPMD) or SIMT architecture. In at least one embodiment, multiple threads of a program configured for a SIMT execution model can be executed using a single SIMD instruction. For example, in at least one embodiment, eight SIMD threads performing the same or similar operations can be executed in parallel using a single SIMD8 logic unit.

[0191] In at least one embodiment, the memory and cache interconnect 2068 is an interconnect network connecting each functional unit of the graphics multiprocessor 2096 to the register file 2058 and the shared memory 2070. In at least one embodiment, the memory and cache interconnect 2068 is a cross-switch interconnect that allows the LSU 2066 to perform load and store operations between the shared memory 2070 and the register file 2058. In at least one embodiment, the register file 2058 can operate at the same frequency as the GPGPU core 2062, resulting in very low latency for data transfer between the GPGPU core 2062 and the register file 2058. In at least one embodiment, the shared memory 2070 can be used to enable communication between threads executing on functional units within the graphics multiprocessor 2096. In at least one embodiment, the cache memory 2072 can be used, for example, as a data cache to cache texture data communicated between functional units and texture units 2036. In at least one embodiment, the shared memory 2070 can also be used as a program-managed cache. In at least one embodiment, in addition to the automatically cached data stored in cache memory 2072, the thread executing on GPGPU core 2062 can also programmatically store data in shared memory.

[0192] In at least one embodiment, a parallel processor or GPGPU, as described herein, is communicatively coupled to the host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. In at least one embodiment, the GPU may be communicatively coupled to the host processor / core via a bus or other interconnect (e.g., high-speed interconnects such as PCIe or NVLink). In at least one embodiment, the GPU may be integrated with the core on the same package or chip and communicatively coupled to the core via an internal processor bus / interconnect (i.e., within the package or chip). In at least one embodiment, regardless of how the GPU is connected, the processor core may assign work to the GPU in the form of a sequence of commands / instructions contained in the WD. In at least one embodiment, the GPU then uses dedicated circuitry / logic to efficiently process these commands / instructions.

[0193] In at least one embodiment, Figures 20A-20C The described system is used to detect and / or predict (e.g., within a multi-GPU system) signals conducted by signal conductors, using various algorithms, formulas, and / or processes (e.g., combining...). Figure 1-8 Those described herein) transition signal conductors between active and inactive states, and / or otherwise perform the operations described herein. In at least one embodiment, Figures 20A-20CThe one or more systems described herein are used to implement one or more systems and / or processes, such as in combination. Figures 1-8 Those described.

[0194] Figure 21 A graphics processor 2100 according to at least one embodiment is illustrated. In at least one embodiment, the graphics processor 2100 includes a ring interconnect 2102, a pipeline front end 2104, a media engine 2137, and graphics cores 2180A-2180N. In at least one embodiment, the ring interconnect 2102 couples the graphics processor 2100 to other processing units, including other graphics processors or one or more general-purpose processor cores. In at least one embodiment, the graphics processor 2100 is one of many processors integrated within a multi-core processing system.

[0195] In at least one embodiment, the graphics processor 2100 receives multiple batches of commands via a ring interconnect 2102. In at least one embodiment, the input commands are interpreted by a command stream converter 2103 in a pipeline front-end 2104. In at least one embodiment, the graphics processor 2100 includes scalable execution logic to perform 3D geometry processing and media processing via graphics cores 2180A-2180N. In at least one embodiment, for 3D geometry processing commands, the command stream converter 2103 provides commands to the geometry pipeline 2136. In at least one embodiment, for at least some media processing commands, the command stream converter 2103 provides commands to a video front-end 2134, which is coupled to a media engine 2137. In at least one embodiment, the media engine 2137 includes a video quality engine (VQE) 2130 for video and image post-processing, and a multi-format encoding / decoding (MFX) engine 2133 for providing hardware-accelerated media data encoding and decoding. In at least one embodiment, the geometry pipeline 2136 and the media engine 2137 each generate an execution thread for the thread execution resources provided by at least one graphics core 2180A.

[0196] In at least one embodiment, the graphics processor 2100 includes scalable thread execution resources characterized by modular graphics cores 2180A-2180N (sometimes referred to as core slices), each modular core having multiple sub-cores 2150A-2150N, 2160A-2160N (sometimes referred to as core sub-slices). In at least one embodiment, the graphics processor 2100 may have any number of graphics cores 2180A to 2180N. In at least one embodiment, the graphics processor 2100 includes a graphics core 2180A having at least a first sub-core 2150A and a second sub-core 2160A. In at least one embodiment, the graphics processor 2100 is a low-power processor having a single sub-core (e.g., 2150A). In at least one embodiment, the graphics processor 2100 includes multiple graphics cores 2180A-2180N, each graphics core including a set of first sub-cores 2150A-2150N and a set of second sub-cores 2160A-2160N. In at least one embodiment, each of the first sub-cores 2150A-2150N includes at least a first set of execution units (EUs) 2152A-2152N and media / texture samplers 2154A-2154N. In at least one embodiment, each of the second sub-cores 2160A-2160N includes at least a second set of execution units 2162A-2162N and samplers 2164A-2164N. In at least one embodiment, each sub-core 2150A-2150N, 2160A-2160N shares a set of shared resources 2170A-2170N. In at least one embodiment, the shared resources include shared cache memory and pixel operation logic.

[0197] In at least one embodiment, Figure 21 One or more systems described in the text are used to achieve, for example, combination Figures 1-8 The description refers to one or more systems and / or processes of the like.

[0198] Figure 22A processor 2200 is illustrated according to at least one embodiment. In at least one embodiment, the processor 2200 may include, but is not limited to, logic circuitry for executing instructions. In at least one embodiment, the processor 2200 can execute instructions, including x86 instructions, ARM instructions, special-purpose instructions for ASICs, etc. In at least one embodiment, the processor 2210 may include registers for storing packaged data, such as the 64-bit wide MMX™ registers in an Intel microprocessor enabled by MMX technology in Santa Clara, California. In at least one embodiment, the MMX registers available in integer and floating-point forms can operate with packaged data elements accompanied by SIMD and Streaming SIMD Extensions (“SSE”) instructions. In at least one embodiment, a 128-bit wide XMM register associated with SSE2, SSE3, SSE4, AVX, or later (generally referred to as “SSEx”) technologies can hold such packaged data operands. In at least one embodiment, the processor 2210 can execute instructions to accelerate CUAD programs.

[0199] In at least one embodiment, processor 2200 includes an ordered front end (“front end”) 2201 to fetch instructions to be executed and prepare instructions for later use in the processor pipeline. In at least one embodiment, front end 2201 may include several units. In at least one embodiment, instruction prefetcher 2226 fetches instructions from memory and provides the instructions to instruction decoder 2228, which in turn decodes or interprets the instructions. For example, in at least one embodiment, instruction decoder 2228 decodes the received instructions into one or more operations, so-called “micro-instructions” or “micro-operations” (also referred to as “micro-operations” or “micro-instructions”), for execution. In at least one embodiment, instruction decoder 2228 parses the instructions into opcodes and corresponding data and control fields, which can be used by the microarchitecture to perform operations. In at least one embodiment, trace cache 2230 may assemble the decoded micro-instructions into a program-ordered sequence or trace in micro-instruction queue 2234 for execution. In at least one embodiment, when trace cache 2230 encounters complex instructions, microcode ROM 2232 provides the micro-instructions required to complete the operation.

[0200] In at least one embodiment, some instructions may be converted into a single micro-operation, while others require several micro-operations to complete the entire operation. In at least one embodiment, if more than four micro-instructions are required to complete an instruction, the instruction decoder 2228 may access the microcode ROM 2232 to execute the instruction. In at least one embodiment, an instruction may be decoded into a small number of micro-instructions for processing at the instruction decoder 2228. In at least one embodiment, if multiple micro-instructions are required to complete an operation, the instructions may be stored in the microcode ROM 2232. In at least one embodiment, the trace cache 2230 references an entry point programmable logic array (“PLA”) to determine the correct micro-instruction pointer for reading a microcode sequence from the microcode ROM 2232 to complete one or more instructions, according to at least one embodiment. In at least one embodiment, after the microcode ROM 2232 has completed the micro-operation ordering of the instructions, the machine front end 2201 may resume fetching micro-operations from the trace cache 2230.

[0201] In at least one embodiment, the out-of-order execution engine (“out-of-order engine”) 2203 can prepare instructions for execution. In at least one embodiment, the out-of-order execution logic has multiple buffers to smooth and reorder the instruction flow to optimize performance as instructions descend the pipeline and are scheduled for execution. The out-of-order execution engine 2203 includes, but is not limited to, an allocator / register renamer 2240, a memory microinstruction queue 2242, an integer / floating-point microinstruction queue 2244, a memory scheduler 2246, a fast scheduler 2202, a slow / general-purpose floating-point scheduler (“slow / general-purpose FP scheduler”) 2204, and a simple floating-point scheduler (“simple FP scheduler”) 2206. In at least one embodiment, the fast scheduler 2202, the slow / general-purpose floating-point scheduler 2204, and the simple floating-point scheduler 2206 are also collectively referred to as “microinstruction schedulers 2202, 2204, 2206”. The allocator / register renamer 2240 allocates the machine buffers and resources required for the sequential execution of each microinstruction. In at least one embodiment, allocator / register renaming unit 2240 renames logical registers to entries in a register file. In at least one embodiment, allocator / register renaming unit 2240 also assigns entries for each microinstruction in one of two microinstruction queues, memory microinstruction queue 2242 for memory operations and integer / floating-point microinstruction queue 2244 for non-memory operations, preceding memory scheduler 2246 and microinstruction schedulers 2202, 2204, 2206. In at least one embodiment, microinstruction schedulers 2202, 2204, 2206 determine when they are ready to execute a microinstruction based on the readiness of their dependent input register operand sources and the availability of the execution resource microinstructions that need to be completed. In at least one embodiment, fast scheduler 2202 of at least one embodiment can schedule on each half of the master clock cycle, while slow / general-purpose floating-point scheduler 2204 and simple floating-point scheduler 2206 can schedule once per master processor clock cycle. In at least one embodiment, microinstruction schedulers 2202, 2204, and 2206 arbitrate the scheduling port to schedule microinstructions for execution.

[0202] In at least one embodiment, execution block 2211 includes, but is not limited to, integer register file / tribute network 2208, floating-point register file / tribute network (“FP register file / tribute network”) 2210, address generation units (“AGU”) 2212 and 2214, fast arithmetic logic units (“fast ALU”) 2216 and 2218, slow ALU 2220, floating-point ALU (“FP”) 2222, and floating-point movement unit (“FP movement”) 2224. In at least one embodiment, integer register file / tribute network 2208 and floating-point register file / bypass network 2210 are also referred to herein as “register files 2208, 2210”. In at least one embodiment, AGUS 2212 and 2214, fast ALU 2216 and 2218, slow ALU 2220, floating-point ALU 2222, and floating-point movement unit 2224 are also referred to herein as "execution units 2212, 2214, 2216, 2218, 2220, 2222, and 2224". In at least one embodiment, the execution block may include, but is not limited to, any number (including zero) and type of register files, branch networks, address generation units, and execution units (in any combination).

[0203] In at least one embodiment, register files 2208, 2210 may be arranged between microinstruction schedulers 2202, 2204, 2206 and execution units 2212, 2214, 2216, 2218, 2220, 2222, and 2224. In at least one embodiment, integer register file / tribute network 2208 performs integer operations. In at least one embodiment, floating-point register file / tribute network 2210 performs floating-point operations. In at least one embodiment, each of register files 2208, 2210 may include, but is not limited to, a tribute network that can bypass or forward recently completed results not yet written to the register file to a new dependent object. In at least one embodiment, register files 2208, 2210 may communicate data with each other. In at least one embodiment, integer register file / tribute network 2208 may include, but is not limited to, two separate register files, one register file for low-order 32-bit data and a second register file for high-order 32-bit data. In at least one embodiment, the floating-point register file / branch network 2210 may include, but is not limited to, entries with a width of 128 bits, since floating-point instructions typically have operands with a width of 64 to 128 bits.

[0204] In at least one embodiment, execution units 2212, 2214, 2216, 2218, 2220, 2222, and 2224 can execute instructions. In at least one embodiment, register files 2208 and 2210 store integer and floating-point data operation values ​​that the microinstructions need to execute. In at least one embodiment, processor 2200 may include, but is not limited to, any number of execution units 2212, 2214, 2216, 2218, 2220, 2222, and 2224, and combinations thereof. In at least one embodiment, floating-point ALU 2222 and floating-point move unit 2224 can perform floating-point, MMX, SIMD, AVX, and SSE or other operations, including specialized machine learning instructions. In at least one embodiment, floating-point ALU 2222 may include, but is not limited to, a 64-bit multiplication-64-bit floating-point divider to perform division, square root, and remainder micro-operations. In at least one embodiment, floating-point hardware can be used to process instructions involving floating-point values. In at least one embodiment, ALU operations can be passed to fast ALUs 2216 and 2218. In at least one embodiment, fast ALUs 2216 and 2218 can perform fast operations with an effective delay of half a clock cycle. In at least one embodiment, most complex integer operations are routed to slow ALU 2220, because slow ALU 2220 can include, but is not limited to, integer execution hardware for long-latency type operations, such as multipliers, shifters, flag logic, and branching. In at least one embodiment, memory load / store operations can be performed by ALUs 2212 and 2214. In at least one embodiment, fast ALU 2216, fast ALU 2218, and slow ALU 2220 can perform integer operations on 64-bit data operands. In at least one embodiment, fast ALU 2216, fast ALU 2218, and slow ALU 2220 can be implemented to support various data bit sizes including 16, 32, 128, 256, etc. In at least one embodiment, the floating-point ALU 2222 and the floating-point movement unit 2224 can be implemented to support a range of operands with various bit widths. In at least one embodiment, the floating-point ALU 2222 and the floating-point movement unit 2224 can operate on 128-bit wide packaged data operands in conjunction with SIMD and multimedia instructions.

[0205] In at least one embodiment, microinstruction schedulers 2202, 2204, and 2206 schedule dependent operations before the parent load completes execution. In at least one embodiment, since microinstructions can be speculatively scheduled and executed within processor 2200, processor 2200 may also include logic for handling memory misses. In at least one embodiment, if a data load miss occurs in the data cache, there may be a dependent operation running in the pipeline that temporarily deprives the scheduler of the correct data. In at least one embodiment, a replay mechanism tracks and re-executes instructions that use incorrect data. In at least one embodiment, it may be necessary to replay dependent operations and may allow independent operations to be completed. In at least one embodiment, the scheduler and replay mechanism of at least one embodiment of the processor may also be designed to capture instruction sequences for text string comparison operations.

[0206] In at least one embodiment, the term "register" may refer to an onboard processor storage location that can be used as part of an instruction that identifies an operand. In at least one embodiment, a register may be one that can be used from outside the processor (from a programmer's perspective). In at least one embodiment, a register may not be limited to a particular type of circuitry. Rather, in at least one embodiment, a register may store data, provide data, and perform the functions described herein. In at least one embodiment, the registers described herein may be implemented using a variety of different techniques via circuitry within the processor, such as dedicated physical registers, dynamically allocated physical registers renamed using register renaming, a combination of dedicated and dynamically allocated physical registers, etc. In at least one embodiment, an integer register stores 32-bit integer data. The register file of at least one embodiment also includes eight multimedia SIMD registers for encapsulating data.

[0207] In at least one embodiment, Figure 22 One or more systems described in the text are used to achieve, for example, combination Figures 1-8 The description refers to one or more systems and / or processes of the like.

[0208] Figure 23A processor 2300 according to at least one embodiment is illustrated. In at least one embodiment, the processor 2300 includes, but is not limited to, one or more processor cores (cores) 2302A-2302N, an integrated memory controller 2314, and an integrated graphics processor 2308. In at least one embodiment, the processor 2300 may include additional cores up to and including additional processor cores 2302N, indicated by dashed boxes. In at least one embodiment, each processor core 2302A-2302N includes one or more internal cache units 2304A-2304N. In at least one embodiment, each processor core may also access one or more units 2306 of a shared cache.

[0209] In at least one embodiment, internal cache units 2304A-2304N and shared cache unit 2306 represent a cache memory hierarchy within processor 2300. In at least one embodiment, cache memory units 2304A-2304N may include at least one level of instruction and data within each processor core, and one or more levels of cache in a shared intermediate cache, such as L2, L3, L4, or other levels of cache, wherein the highest level of cache is classified as LLC before external memory. In at least one embodiment, cache coherence logic maintains coherence between the various cache units 2306 and 2304A-2304N.

[0210] In at least one embodiment, the processor 2300 may further include a set of one or more bus controller units 2316 and a system agent core 2310. In at least one embodiment, the one or more bus controller units 2316 manage a set of peripheral buses, such as one or more PCI or PCI Express buses. In at least one embodiment, the system agent core 2310 provides management functions for various processor components. In at least one embodiment, the system agent core 2310 includes one or more integrated memory controllers 2314 to manage access to various external memory devices (not shown).

[0211] In at least one embodiment, one or more processor cores 2302A-2302N include support for concurrent multithreading. In at least one embodiment, system agent core 2310 includes components for coordinating and operating processor cores 2302A-2302N during multithreaded processing. In at least one embodiment, system agent core 2310 may additionally include a power control unit (PCU) including logic and components for regulating one or more power states of processor cores 2302A-2302N and graphics processor 2308.

[0212] In at least one embodiment, processor 2300 further includes graphics processor 2308 to perform graphics processing operations. In at least one embodiment, graphics processor 2308 is coupled to a shared cache unit 2306 and a system proxy core 2310 including one or more integrated memory controllers 2314. In at least one embodiment, system proxy core 2310 further includes a display controller 2311 for driving graphics processor output to one or more coupled displays. In at least one embodiment, display controller 2311 may also be a separate module coupled to graphics processor 2308 via at least one interconnect, or it may be integrated within graphics processor 2308.

[0213] In at least one embodiment, the ring-based interconnect unit 2312 is used to couple internal components of the processor 2300. In at least one embodiment, alternative interconnect units, such as point-to-point interconnects, switched interconnects, or other technologies, may be used. In at least one embodiment, the graphics processor 2308 is coupled to the ring interconnect 2312 via I / O link 2313.

[0214] In at least one embodiment, I / O link 2313 represents at least one of a variety of I / O interconnects, including packaged I / O interconnects that facilitate communication between various processor components and high-performance embedded memory module 2318 (e.g., eDRAM module). In at least one embodiment, each of processor cores 2302A-2302N and graphics processor 2308 uses embedded memory module 2318 as a shared LLC.

[0215] In at least one embodiment, processor cores 2302A-2302N are homogeneous cores executing a common instruction set architecture. In at least one embodiment, processor cores 2302A-2302N are heterogeneous in terms of the instruction set architecture (ISA), with one or more processor cores 2302A-2302N executing a common instruction set, while one or more other processor cores 2302A-2302N execute a common instruction set or a subset of a different instruction set. In at least one embodiment, processor cores 2302A-2302N are heterogeneous in terms of microarchitecture, with one or more cores having relatively high power consumption coupled to one or more power cores having lower power consumption. In at least one embodiment, processor 2300 can be implemented on one or more chips or implemented as a SoC integrated circuit.

[0216] In at least one embodiment, Figure 23 One or more systems described in the text are used to achieve, for example, combination Figures 1-8 The description refers to one or more systems and / or processes of the like.

[0217] Figure 24A graphics processor core 2400 according to at least one embodiment described is illustrated. In at least one embodiment, the graphics processor core 2400 is included within a graphics core array. In at least one embodiment, the graphics processor core 2400 (sometimes referred to as a core slice) may be one or more graphics cores within a modular graphics processor. In at least one embodiment, the graphics processor core 2400 is an example of a graphics core slice, and the graphics processor described herein may include multiple graphics core slices based on target power and performance envelopes. In at least one embodiment, each graphics core 2400 may include a fixed-function block 2430, also referred to as a sub-slice, coupled to a plurality of sub-cores 2401A-2401F, which includes modular blocks of general-purpose and fixed-function logic.

[0218] In at least one embodiment, the fixed-function block 2430 includes a geometry / fixed-function pipeline 2436, which, for example, may be shared by all sub-cores of the graphics processor 2400 in a lower-performance and / or lower-power graphics processor implementation. In at least one embodiment, the geometry / fixed-function pipeline 2436 includes a 3D fixed-function pipeline, a video front-end unit, a thread generator and a thread dispatcher, and a unified return buffer manager that manages a unified return buffer.

[0219] In at least one embodiment, fixed function block 2430 further includes a graphics SoC interface 2437, a graphics microcontroller 2438, and a media pipeline 2439. The graphics SoC interface 2437 provides an interface between the graphics core 2400 and other processor cores in the SoC integrated circuit system. In at least one embodiment, the graphics microcontroller 2438 is a programmable subprocessor configurable to manage various functions of the graphics processor 2400, including thread dispatch, scheduling, and preemption. In at least one embodiment, the media pipeline 2439 includes logic that facilitates decoding, encoding, preprocessing, and / or post-processing of multimedia data, including image and video data. In at least one embodiment, the media pipeline 2439 implements media operations via requests for computation or sampling logic within subcores 2401-2401F.

[0220] In at least one embodiment, the SoC interface 2437 enables the graphics core 2400 to communicate with a general-purpose application processor core (e.g., a CPU) and / or other components within the SoC, including memory hierarchy elements such as shared LLC memory, system RAM, and / or embedded on-chip or packaged DRAM. In at least one embodiment, the SoC interface 2437 also enables communication with fixed-function devices within the SoC (e.g., a camera imaging pipeline) and enables the use and / or implementation of global memory atoms that can be shared between the graphics core 2400 and the CPU within the SoC. In at least one embodiment, the SoC interface 2437 also implements power management control for the graphics core 2400 and enables interfacing between the clock domain of the graphics core 2400 and other clock domains within the SoC. In at least one embodiment, the SoC interface 2437 enables the receipt of command buffers from a command stream converter and a global thread dispatcher, configured to provide commands and instructions to each of one or more graphics cores within the graphics processor. In at least one embodiment, when a media operation is to be performed, commands and instructions can be dispatched to the media pipeline 2439, or when a graph processing operation is to be performed, they can be assigned to the geometry and fixed function pipelines (e.g., geometry and fixed function pipelines 2436 and 2414).

[0221] In at least one embodiment, the graphics microcontroller 2438 can be configured to perform various scheduling and management tasks on the graphics core 2400. In at least one embodiment, the graphics microcontroller 2438 can perform graph and / or computation workload scheduling on various graphics parallel engines within the execution unit (EU) arrays 2402A-2402F, 2404A-2404F in subcores 2401A-2401F. In at least one embodiment, host software executing on the CPU core of the SoC including the graphics core 2400 can submit a workload of one of a plurality of graphics processor doorbells, which invokes scheduling operations on the appropriate graphics engine. In at least one embodiment, the scheduling operation includes determining which workload should be run next, submitting the workload to a command stream converter, preempting existing workloads running on the engine, monitoring the progress of the workload, and notifying the host software when the workload is completed. In at least one embodiment, the graphics microcontroller 2438 may also facilitate a low-power or idle state of the graphics core 2400, thereby providing the graphics core 2400 with the ability to save and restore registers across low-power state transitions within the graphics core 2400, independent of the operating system and / or the graphics driver software on the system.

[0222] In at least one embodiment, the graphics core 2400 may have more or fewer subcores than the illustrated subcores 2401A-2401F, up to N modular subcores. For each group of N subcores, in at least one embodiment, the graphics core 2400 may further include shared functional logic 2410, shared and / or cache memory 2412, geometry / fixed-function pipeline 2414, and additional fixed-function logic 2416 to accelerate various graphics and computational processing operations. In at least one embodiment, the shared functional logic 2410 may include logic units (e.g., samplers, mathematical and / or inter-thread communication logic) that can be shared by each of the N subcores within the graphics core 2400. The shared and / or cache memory 2412 may be an LLC of the N subcores 2401A-2401F within the graphics core 2400, and may also be used as shared memory accessible by multiple subcores. In at least one embodiment, a geometry / fixed function pipeline 2414 may be included to replace the geometry / fixed function pipeline 2436 within the fixed function block 2430, and may include the same or similar logic units.

[0223] In at least one embodiment, the graphics core 2400 includes additional fixed-function logic 2416, which may include various fixed-function acceleration logics for use by the graphics core 2400. In at least one embodiment, the additional fixed-function logic 2416 includes additional geometry pipelines for use in position-only shading. In position-only shading, there are at least two geometry pipelines, and in the full geometry pipeline and culling pipeline within the geometry / fixed-function pipelines 2416, 2436, it is an additional geometry pipeline that can be included in the additional fixed-function logic 2416. In at least one embodiment, the culling pipeline is a trimmed version of the full geometry pipeline. In at least one embodiment, the full pipeline and the culling pipeline can execute different instances of the application, each with a separate environment. In at least one embodiment, position-only shading can hide long culling runs of discarded triangles, thereby allowing shading to be completed earlier in some cases. For example, in at least one embodiment, the culling pipeline logic in the additional fixed-function logic 2416 can execute the position shader in parallel with the main application and typically generates critical results faster than the full pipeline because the culling pipeline acquires and occludes the positional attributes of vertices without performing rasterization and rendering pixels to the framebuffer. In at least one embodiment, the culling pipeline can use the generated critical results to compute visibility information for all triangles, regardless of whether those triangles were culled. In at least one embodiment, the full pipeline (which may be referred to as the replay pipeline in this case) can consume visibility information to skip culled triangles and only occlude the visible triangles that are ultimately passed to the rasterization stage.

[0224] In at least one embodiment, the additional fixed-function logic 2416 may also include general target processing acceleration logic, such as fixed-function matrix multiplication logic, for implementing a decelerated CUAD program.

[0225] In at least one embodiment, each graphics subcore 2401A-2401F includes a set of execution resources that can be used to perform graph, media, and computational operations in response to requests from the graphics pipeline, media pipeline, or shader program. In at least one embodiment, the graphics subcore 2401A-2401F includes multiple EU arrays 2402A-2402F, 2404A-2404F, thread dispatch and inter-thread communication (TD / IC) logic 2403A-2403F, 3D (e.g., texture) samplers 2405A-2405F, media samplers 2406A-2406F, shader processors 2407A-2407F, and shared local memory (SLM) 2408A-2408F. Each of the EU arrays 2402A-2402F and 2404A-2404F contains multiple execution units, which are GUGPUs capable of servicing graphics, media, or computational operations, performing floating-point and integer / fixed-point logic operations, including graphics, media, or computational shader programs. In at least one embodiment, the TD / IC logic 2403A-2403F performs local thread dispatch and thread control operations for the execution units within the subcore and facilitates communication between threads executing on the execution units of the subcore. In at least one embodiment, the 3D samplers 2405A-2405F can read data associated with textures or other 3D graphics into memory. In at least one embodiment, the 3D samplers can read texture data differently based on the sampling state and texture format configured and associated with a given texture. In at least one embodiment, the media samplers 2406A-2406F can perform similar read operations based on the type and format associated with the media data. In at least one embodiment, each graphics subcore 2401A-2401F may alternatively include a unified 3D and media sampler. In at least one embodiment, threads executing on execution units within each subcore 2401A-2401F may utilize shared local memory 2408A-2408F within each subcore, enabling threads executing within a thread group to utilize a common pool of on-chip memory for execution.

[0226] In at least one embodiment, Figure 24 One or more systems described in the text are used to achieve, for example, combination Figures 1-8 The description refers to one or more systems and / or processes of the like.

[0227] Figure 25A parallel processing unit (“PPU”) 2500 according to at least one embodiment is illustrated. In at least one embodiment, the PPU 2500 is configured with machine-readable code that, if executed by the PPU 2500, causes the PPU 2500 to perform some or all of the processes and techniques described herein. In at least one embodiment, the PPU 2500 is a multi-threaded processor implemented on one or more integrated circuit devices and utilizes multi-threading as a latency-hiding technique designed to process computer-readable instructions (also known as machine-readable instructions or simple instructions) that are executed in parallel on multiple threads. In at least one embodiment, a thread refers to an execution thread and is an instance of a set of instructions configured to be executed by the PPU 2500. In at least one embodiment, the PPU 2500 is a graphics processing unit (“GPU”) configured to implement a graphics rendering pipeline for processing three-dimensional (“3D”) graphics data to generate two-dimensional (“2D”) image data for display on a display device, such as an LCD device. In at least one embodiment, the PPU 2500 is used to perform computations, such as linear algebra operations and machine learning operations. Figure 25 An example parallel processor is shown for illustrative purposes only and should be interpreted as a non-limiting example of a processor architecture implemented in at least one embodiment.

[0228] In at least one embodiment, one or more PPUs 2500 are configured to accelerate high-performance computing (“HPC”), data center, and machine learning applications. In at least one embodiment, one or more PPUs 2500 are configured to accelerate CUDA programs. In at least one embodiment, the PPU 2500 includes, but is not limited to, I / O unit 2506, front-end unit 2510, scheduler unit 2512, job allocation unit 2514, hub 2516, crossbar (“Xbar”) 2520, one or more general-purpose processing clusters (“GPCs”) 2518, and one or more partitioning units (“memory partitioning units”) 2522. In at least one embodiment, the PPU 2500 is connected to a host processor or other PPU 2500 via one or more high-speed GPU interconnects (“GPU interconnects”) 2508. In at least one embodiment, the PPU 2500 is connected to a host processor or other peripheral device via a system bus or interconnect 2502. In one embodiment, the PPU 2500 is connected to local memory including one or more memory devices (“memory”) 2504. In at least one embodiment, the memory device 2504 includes, but is not limited to, one or more dynamic random access memory (“DRAM”) devices. In at least one embodiment, the one or more DRAM devices are configured and / or configurable as a high bandwidth memory (“HBM”) subsystem, and multiple DRAM dies are stacked within each device.

[0229] In at least one embodiment, the high-speed GPU interconnect 2508 may refer to a wire-based multi-channel communication link used by the system for scaling, and includes one or more PPUs 2500s (“CPUs”) coupled with one or more CPUs, supporting cache coherency between the PPUs 2500s and the CPUs, as well as CPU master control. In at least one embodiment, the high-speed GPU interconnect 2508 transmits data and / or commands to other units of the PPU 2500, such as one or more copy engines, video encoders, video decoders, power management units, and / or other components, via a hub 2516. Figure 25 Other components that may not be explicitly shown.

[0230] In at least one embodiment, the I / O unit 2506 is configured to access the host processor via the system bus 2502. Figure 25(Not shown) Sending and receiving communications (e.g., commands, data). In at least one embodiment, I / O unit 2506 communicates directly with the host processor via system bus 2502 or via one or more intermediate devices (e.g., memory bridges). In at least one embodiment, I / O unit 2506 may communicate with one or more other processors (e.g., one or more PPUs 2500) via system bus 2502. In at least one embodiment, I / O unit 2506 implements a PCIe interface for communication via the PCIe bus. In at least one embodiment, I / O unit 2506 implements an interface for communication with external devices.

[0231] In at least one embodiment, I / O unit 2506 decodes packets received via system bus 2502. In at least one embodiment, at least some packets represent commands configured to cause PPU 2500 to perform various operations. In at least one embodiment, I / O unit 2506 sends the decoded commands to various other units of PPU 2500 as specified by the commands. In at least one embodiment, the commands are sent to front-end unit 2510 and / or to hub 2516 or other units of PPU 2500, such as one or more copy engines, video encoders, video decoders, power management units, etc. Figure 25 (Not explicitly shown). In at least one embodiment, I / O unit 2506 is configured to route communication between various logical units of PPU 2500.

[0232] In at least one embodiment, a program executed by the host processor encodes a command stream in a buffer that provides a workload to the PPU 2500 for processing. In at least one embodiment, the workload includes instructions and data to be processed by those instructions. In at least one embodiment, the buffer is a region in memory accessible (e.g., read / write) by both the host processor and the PPU 2500—the host interface unit can be configured to access a buffer in system memory connected to the system bus 2502 via memory requests transmitted through the system bus 2502 via the I / O unit 2506. In at least one embodiment, the host processor writes a command stream to the buffer and then sends a pointer indicating the start of the command stream to the PPU 2500, causing the front-end unit 2510 to receive pointers to one or more command streams and manage one or more command streams, read commands from the command streams, and forward the commands to the respective units of the PPU 2500.

[0233] In at least one embodiment, front-end unit 2510 is coupled to scheduler unit 2512, which configures various GPCs 2518 to process tasks defined by one or more command streams. In at least one embodiment, scheduler unit 2512 is configured to track status information related to the various tasks managed by scheduler unit 2512, wherein the status information may indicate which GPC 2518 a task is assigned to, whether the task is active or inactive, the priority associated with the task, etc. In at least one embodiment, scheduler unit 2512 manages multiple tasks executed on one or more GPCs 2518.

[0234] In at least one embodiment, scheduler unit 2512 is coupled to job allocation unit 2514, which is configured to dispatch tasks for execution on GPC 2518. In at least one embodiment, job allocation unit 2514 tracks multiple scheduled tasks received from scheduler unit 2512 and manages a pool of pending tasks and an active task pool for each GPC 2518. In at least one embodiment, the pool of pending tasks includes multiple time slots (e.g., 32 time slots) containing tasks assigned to a particular GPC 2518 for processing; the active task pool may include multiple time slots (e.g., 4 time slots) for tasks actively processed by GPC 2518, such that as one of the GPCs 2518 completes its execution, that task is evicted from the active task pool of the GPC 2518, and one of other tasks is selected from the pool of pending tasks and scheduled for execution on the GPC 2518. In at least one embodiment, if an active task is idle on GPC 2518, for example while waiting for data dependency resolution, the active task is evicted from GPC 2518 and returned to the task pool, while another task in the task pool is selected and scheduled to be executed on GPC 2518.

[0235] In at least one embodiment, the work allocation unit 2514 communicates with one or more GPCs 2518 via XBar 2520. In at least one embodiment, XBar 2520 is an interconnect network that couples a plurality of units of PPU 2500 to other units of PPU 2500, and can be configured to couple the work allocation unit 2514 to a specific GPC 2518. In at least one embodiment, other units of one or more PPUs 2500 can also be connected to XBar 2520 via hub 2516.

[0236] In at least one embodiment, tasks are managed by scheduler unit 2512 and assigned to one of GPCs 2518 by job allocation unit 2514. GPCs 2518 are configured to process tasks and produce results. In at least one embodiment, results may be consumed by other tasks in GPCs 2518, routed to different GPCs 2518 via XBar 2520, or stored in memory 2504. In at least one embodiment, results may be written to memory 2504 via partitioning unit 2522, which implements a memory interface for writing data to or reading data from memory 2504. In at least one embodiment, results may be transferred to another PPU 2500 or CPU via high-speed GPU interconnect 2508. In at least one embodiment, a PPU 2500 includes, but is not limited to, U partitioning units 2522, which is equal to the number of separate and distinct memory devices 2504 coupled to the PPU 2500.

[0237] In at least one embodiment, the host processor executes a driver core that implements an application programming interface (API) that enables one or more applications executing on the host processor to schedule operations for execution on the PPU 2500. In one embodiment, multiple computing applications are executed concurrently by the PPU 2500, and the PPU 2500 provides isolation, Quality of Service (“QoS”), and independent address spaces for the multiple computing applications. In at least one embodiment, application-generating instructions (e.g., in the form of API calls) cause the driver core to generate one or more tasks for execution by the PPU 2500, and the driver core outputs the tasks to one or more streams processed by the PPU 2500. In at least one embodiment, each task includes one or more associated thread groups, which may be referred to as a warp. In at least one embodiment, a warp includes multiple associated threads (e.g., 32 threads) that can be executed in parallel. In at least one embodiment, a cooperating thread may refer to multiple threads, including instructions for performing tasks and exchanging data via shared memory.

[0238] In at least one embodiment, Figure 25 One or more systems described in the text are used to achieve, for example, combination Figures 1-8 The description refers to one or more systems and / or processes of the like.

[0239] Figure 26 A GPC2600 according to at least one embodiment is shown. In at least one embodiment, the GPC 2600 is Figure 25The GPC 2518. In at least one embodiment, each GPC 2600 includes, but is not limited to, a plurality of hardware units for processing tasks, and each GPC 2600 includes, but is not limited to, a pipeline manager 2602, a pre-raster operation unit (“PROP”) 2604, a raster engine 2608, a work assignment crossbar switch (“WDX”) 2616, a memory management unit (“MMU”) 2618, one or more data processing clusters (“DPC”) 2606, and any suitable combination of components.

[0240] In at least one embodiment, the operation of GPC 2600 is controlled by pipeline manager 2602. In at least one embodiment, pipeline manager 2602 manages the configuration of one or more DPCs 2606 to handle tasks assigned to GPC 2600. In at least one embodiment, pipeline manager 2602 configures at least one of one or more DPCs 2606 to implement at least a portion of the graphics rendering pipeline. In at least one embodiment, DPC 2606 is configured to execute vertex shader programs on programmable streaming multiprocessor (“SM”) 2614. In at least one embodiment, pipeline manager 2602 is configured to route packets received from the work allocation unit to appropriate logic units within GPC 2600, and in at least one embodiment, some packets may be routed to fixed-function hardware units in PROP 2604 and / or raster engine 2608, while other packets may be routed to DPC 2606 for processing by raw engine 2612 or SM 2614. In at least one embodiment, pipeline manager 2602 configures at least one of DPCs 2606 to implement a neural network model and / or computation pipeline. In at least one embodiment, pipeline manager 2602 configures at least one of DPCs 2606 to execute at least a portion of a CUDA program.

[0241] In at least one embodiment, PROP unit 2604 is configured to route data generated by raster engine 2608 and DPC 2606 to raster operation (“ROP”) units in partitioned units, such as those described above. Figure 25Memory partitioning unit 2522, etc., are described in more detail. In at least one embodiment, PROP unit 2604 is configured to perform optimizations for color blending, organize pixel data, perform address translation, etc. In at least one embodiment, raster engine 2608 includes, but is not limited to, multiple fixed-function hardware units configured to perform various raster operations, and in at least one embodiment, raster engine 2608 includes, but is not limited to, a setup engine, a coarse raster engine, a culling engine, a clipping engine, a fine raster engine, a tile aggregation engine, and any suitable combination thereof. In at least one embodiment, the setup engine receives the transformed vertices and generates plane equations associated with the geometric primitives defined by the vertices; the plane equations are transmitted to the coarse raster engine to generate coverage information of basic primitives (e.g., x, y coverage masks of tiles); the output of the coarse raster engine is transmitted to the culling engine, in which fragments associated with primitives that fail the z-test are culled, and transmitted to the clipping engine, in which fragments located outside the view frustum are clipped. In at least one embodiment, the cropped and culled fragments are passed to a fine raster engine to generate properties of the pixel fragments based on a planar equation generated by the settings engine. In at least one embodiment, the output of the raster engine 2608 includes fragments that will be processed by any suitable entity (e.g., by a fragment shader implemented within the DPC 2606).

[0242] In at least one embodiment, each DPC 2606 included in the GPC 2600 includes, but is not limited to, an M-pipeline controller (“MPC”) 2610; a primitive engine 2612; one or more SMs 2614; and any suitable combination thereof. In at least one embodiment, the MPC 2610 controls the operation of the DPC 2606, routing packets received from the pipeline manager 2602 to the appropriate units within the DPC 2606. In at least one embodiment, packets associated with vertices are routed to the primitive engine 2612, which is configured to retrieve vertex attributes associated with vertices from memory; conversely, packets associated with shader programs may be sent to the SM 2614.

[0243] In at least one embodiment, the SM 2614 includes, but is not limited to, a programmable streaming processor configured to process tasks represented by multiple threads. In at least one embodiment, the SM 2614 is multithreaded and configured to execute multiple threads (e.g., 32 threads) from a specific thread group concurrently, and implements a Single Instruction, Multiple Data (“SIMD”) architecture, wherein each thread in a group of threads (e.g., a thread bundle) is configured to process a different dataset based on the same instruction set. In at least one embodiment, all threads in the thread group execute the same instructions. In at least one embodiment, the SM 2614 implements a Single Instruction, Multiple Thread (“SIMT”) architecture, wherein each thread in a group of threads is configured to process a different dataset based on the same instruction set, but wherein individual threads in the thread group are allowed to diverge during execution. In at least one embodiment, a program counter, call stack, and execution state are maintained for each thread bundle, thereby achieving concurrency between the thread bundle and serial execution within the thread bundle when threads in the thread bundle diverge. In another embodiment, a program counter, call stack, and execution state are maintained for each individual thread, thereby ensuring equal concurrency among all threads within and between thread bundles. In at least one embodiment, an execution state is maintained for each individual thread, and threads executing the same instructions can be converged and executed in parallel to improve efficiency. The following is in conjunction with... Figure 27 At least one embodiment of SM 2614 is described in more detail.

[0244] In at least one embodiment, the MMU 2618 is integrated with the GPC 2600 and memory partitioning unit (e.g., Figure 25 The MMU 2618 provides an interface between partition units 2522 and provides virtual address to physical address translation, memory protection, and memory request arbitration. In at least one embodiment, the MMU 2618 provides one or more translation back buffers (“TLBs”) for performing virtual address to physical address translation in memory.

[0245] In at least one embodiment, Figure 26 One or more systems described in the text are used to achieve, for example, combination Figures 1-8 The description refers to one or more systems and / or processes of the like.

[0246] Figure 27 A streaming multiprocessor (“SM”) 2700 according to at least one embodiment is illustrated. In at least one embodiment, the SM 2700 is Figure 26The SM 2700 includes, but is not limited to, instruction cache 2702; one or more scheduler units 2704; register file 2708; one or more processing cores (“cores”) 2710; one or more special function units (“SFUs”) 2712; one or more load / store units (“LSUs”) 2714; interconnect network 2716; shared memory / Level 1 (“L1”) cache 2718; and any suitable combination thereof. In at least one embodiment, the work allocation unit schedules tasks to execute on a general-purpose processing cluster (“GPC”) of parallel processing units (“PPUs”), and each task is assigned to a specific data processing cluster (“DPC”) within the GPC, and if the task is associated with a shader program, the task is assigned to one of the SMs 2700. In at least one embodiment, the scheduler unit 2704 receives tasks from the work allocation unit and manages instruction scheduling for one or more thread blocks assigned to the SM 2700. In at least one embodiment, scheduler unit 2704 schedules thread blocks to execute as thread bundles of parallel threads, wherein each thread block is assigned at least one thread bundle. In at least one embodiment, each thread bundle executes a thread. In at least one embodiment, scheduler unit 2704 manages multiple different thread blocks, assigns thread bundles to different thread blocks, and then dispatches instructions from multiple different cooperative groups to various functional units (e.g., processing core 2710, SFU 2712, and LSU 2714) in each clock cycle.

[0247] In at least one embodiment, a "cooperative group" can refer to a programming model used to organize groups of communicating threads, allowing developers to express the granularity at which threads are communicating, thereby enabling richer and more efficient parallel decompositions. In at least one embodiment, the cooperative startup API supports synchronization between blocks of threads to execute parallel algorithms. In at least one embodiment, the API of a conventional programming model provides a single, simple construct for synchronizing cooperative threads: a barrier (e.g., the `syncthreads()` function) across all threads in a block of threads. However, in at least one embodiment, programmers can define thread groups at a granularity smaller than that of a thread block and synchronize within the defined group to achieve higher performance, design flexibility, and software reuse in the form of a set of group-wide functional interfaces. In at least one embodiment, cooperative groups enable programmers to explicitly define thread groups at the sub-block and multi-block granularity and perform set operations, such as synchronizing threads within the cooperative group. In at least one embodiment, the sub-block granularity is as small as that of a single thread. In at least one embodiment, the programming model supports clean composition across software boundaries, allowing library and utility functions to be safely synchronized in their native environment without having to make assumptions about convergence. In at least one embodiment, the cooperative group primitives enable new patterns of cooperative parallelism, including but not limited to producer-consumer parallelism, opportunistic parallelism, and global synchronization across the entire thread block mesh.

[0248] In at least one embodiment, dispatch unit 2706 is configured to send instructions to one or more functional units, and scheduler unit 2704 includes, but is not limited to, two dispatch units 2706 that enable two different instructions from the same thread bundle to be dispatched in each clock cycle. In at least one embodiment, each scheduler unit 2704 includes a single dispatch unit 2706 or additional dispatch units 2706.

[0249] In at least one embodiment, each SM 2700 includes, but is not limited to, a register file 2708 that provides a set of registers for functional units of the SM 2700. In at least one embodiment, the register file 2708 is partitioned between each functional unit, thereby allocating a dedicated portion of the register file 2708 for each functional unit. In at least one embodiment, the register file 2708 is partitioned between different thread bundles executed by the SM 2700, and the register file 2708 provides temporary storage for operands connected to data paths of functional units. In at least one embodiment, each SM 2700 includes, but is not limited to, a plurality of L processing cores 2710. In at least one embodiment, the SM 2700 includes, but is not limited to, a large number (e.g., 128 or more) of different processing cores 2710. In at least one embodiment, each processing core 2710 includes, but is not limited to, a fully pipelined, single-precision, double-precision, and / or mixed-precision processing unit, which includes, but is not limited to, a floating-point arithmetic logic unit and an integer arithmetic logic unit. In at least one embodiment, the floating-point arithmetic logic unit implements the IEEE 754-2008 standard for floating-point arithmetic. In at least one embodiment, the processing core 2710 includes, but is not limited to, 64 single-precision (32-bit) floating-point cores, 64 integer cores, 32 double-precision (64-bit) floating-point cores and 8 tensor cores.

[0250] In at least one embodiment, the tensor core is configured to perform matrix operations. In at least one embodiment, one or more tensor cores are included in the processing core 2710. In at least one embodiment, the tensor core is configured to perform deep learning matrix arithmetic, such as convolution operations for neural network training and inference. In at least one embodiment, each tensor core operates on a 4×4 matrix and performs matrix multiplication and accumulation operations D = A×B + C, where A, B, C, and D are 4×4 matrices.

[0251] In at least one embodiment, matrix multiplication inputs A and B are 16-bit floating-point matrices, and accumulation matrices C and D are either 16-bit or 32-bit floating-point matrices. In at least one embodiment, the Tensor Core performs 32-bit floating-point accumulation on the 16-bit floating-point input data. In at least one embodiment, the 16-bit floating-point multiplication uses 64 operations to obtain a full-precision product, which is then accumulated with other intermediate multiplications using 32-bit floating-point addition to perform a 4x4x4 matrix multiplication. In at least one embodiment, the Tensor Core is used to perform matrix operations on larger two-dimensional or higher-dimensional matrices composed of these smaller components. In at least one embodiment, an API (such as the CUDA-C++ API) exposes specialized matrix loading, matrix multiplication and accumulation, and matrix storage operations to efficiently utilize the Tensor Core from CUDA-C++ programs. In at least one embodiment, at the CUDA level, the thread bundle level interface assumes a 16×16 matrix spanning all 32 thread bundle threads.

[0252] In at least one embodiment, each SM 2700 includes, but is not limited to, M SFUs 2712 that perform special functions (e.g., attribute evaluation, inverse square root, etc.). In at least one embodiment, the SFUs 2712 include, but are not limited to, tree traversal units configured to traverse hierarchical tree data structures. In at least one embodiment, the SFUs 2712 include, but are not limited to, texture units configured to perform texture map filtering operations. In at least one embodiment, the texture unit is configured to load texture maps (e.g., a 2D array of texture pixels) from memory and sample the texture maps to produce sampled texture values ​​for use by a shader program executed by the SM 2700. In at least one embodiment, the texture maps are stored in shared memory / L1 cache 2718. In at least one embodiment, the texture unit uses mip-maps (e.g., texture maps with different levels of detail) to implement texture operations (such as filtering operations). In at least one embodiment, each SM 2700 includes, but is not limited to, two texture units.

[0253] In at least one embodiment, each SM 2700 includes, but is not limited to, N LSUs 2714 that implement load and store operations between the shared memory / L1 cache 2718 and the register file 2708. In at least one embodiment, each SM 2700 includes, but is not limited to, an interconnect network 2716 that connects each functional unit to the register file 2708, and the LSUs 2714 that connect to both the register file 2708 and the shared memory / L1 cache 2718. In at least one embodiment, the interconnect network 2716 is a crossbar switch that can be configured to connect any functional unit to any register in the register file 2708 and to connect the LSUs 2714 to memory locations in both the register file 2708 and the shared memory / L1 cache 2718.

[0254] In at least one embodiment, the shared memory / L1 cache 2718 is an array of on-chip memory that, in at least one embodiment, allows data storage and communication between the SM 2700 and the primitive engine, as well as between threads within the SM 2700. In at least one embodiment, the shared memory / L1 cache 2718 includes, but is not limited to, a storage capacity of 128KB and is located on the path from the SM 2700 to the partition unit. In at least one embodiment, the shared memory / L1 cache 2718 is used for cache reads and writes. In at least one embodiment, one or more of the shared memory / L1 cache 2718, the L2 cache, and the memory are backup storage.

[0255] In at least one embodiment, combining data caching and shared memory functionality into a single memory block provides improved performance for both types of memory access. In at least one embodiment, the capacity is used by programs that do not use shared memory or is used as a cache; for example, if shared memory is configured to use half its capacity, texture and load / store operations can use the remaining capacity. According to at least one embodiment, integration within the shared memory / L1 cache 2718 enables the shared memory / L1 cache 2718 to be used as a high-throughput pipeline for streaming data, while providing high-bandwidth and low-latency access to frequently reused data. In at least one embodiment, a simpler configuration can be used compared to graphics processing when configured for general-purpose parallel computing. In at least one embodiment, a simpler programming model is created by bypassing a fixed-function GPU. In at least one embodiment, in a general-purpose parallel computing configuration, the work allocation unit directly allocates and distributes blocks of threads to the DPC. In at least one embodiment, threads within a block execute the same program, using unique thread IDs in computation to ensure each thread produces unique results, using an SM 2700 to execute the program and perform computations, using a shared memory / L1 cache 2718 for communication between threads, and using an LSU 2714 to read and write global memory via the shared memory / L1 cache 2718 and memory partitioning units. In at least one embodiment, when configured for general-purpose parallel computing, the SM 2700 writes commands to the scheduler unit 2704 that can be used to start new work on the DPC.

[0256] In at least one embodiment, the PPU is included in or coupled to a desktop computer, laptop computer, tablet computer, server, supercomputer, smartphone (e.g., wireless, handheld device), PDA, digital camera, vehicle, head-mounted display, handheld electronic device, etc. In at least one embodiment, the PPU is implemented on a single semiconductor substrate. In at least one embodiment, the PPU is included in a system-on-chip (“SoC”) along with one or more other devices (e.g., additional PPUs, memory, RISC CPU, MMU, digital-to-analog converter (“DAC”), etc.).

[0257] In at least one embodiment, the PPU may be included on a graphics card that includes one or more storage devices. The graphics card may be configured to connect to a PCIe slot on a desktop computer motherboard. In at least one embodiment, the PPU may be an integrated GPU (“iGPU”) included in the motherboard's chipset.

[0258] In at least one embodiment, Figure 27 One or more systems described in the text are used to achieve, for example, combination Figures 1-8The description refers to one or more systems and / or processes of the like.

[0259] Software architecture for general-purpose computing The following figures illustrate, but are not limited to, exemplary software constructions for implementing at least one embodiment.

[0260] Figure 28 A software stack of a programming platform according to at least one embodiment is illustrated. In at least one embodiment, the programming platform is a platform for accelerating computational tasks by utilizing hardware on a computing system. In at least one embodiment, software developers can access the programming platform through libraries, compiler instructions, and / or extensions to programming languages. In at least one embodiment, the programming platform may be, but is not limited to, CUDA, Radeon Open Computing Platform (“ROCm”), OpenCL (OpenCL™ developed by Khronosgroup), SYCL, or Intel One API.

[0261] In at least one embodiment, the software stack 2800 of the programming platform provides an execution environment for the application 2801. In at least one embodiment, the application 2801 may include any computer software capable of being launched on the software stack 2800. In at least one embodiment, the application 2801 may include, but is not limited to, artificial intelligence (“AI”) / machine learning (“ML”) applications, high-performance computing (“HPC”) applications, virtual desktop infrastructure (“VDI”), or data center workloads.

[0262] In at least one embodiment, application 2801 and software stack 2800 run on hardware 2807. In at least one embodiment, hardware 2807 may include one or more GPUs, CPUs, FPGAs, AI engines, and / or other types of computing devices supporting a programming platform. In at least one embodiment, such as using CUDA, software stack 2800 may be vendor-specific and compatible only with devices from a specific vendor. In at least one embodiment, such as using OpenCL, software stack 2800 may be used with devices from different vendors. In at least one embodiment, hardware 2807 includes a host connected to one or more devices that can be accessed via application programming interface (API) calls to perform computational tasks. In at least one embodiment, compared to the host within hardware 2807, which may include, but is not limited to, a CPU (but may also include computing devices) and its memory, devices within hardware 2807 may include, but are not limited to, GPUs, FPGAs, AI engines, or other computing devices (but may also include CPUs) and their memory.

[0263] In at least one embodiment, the software stack 2800 of the programming platform includes, but is not limited to, multiple libraries 2803, a runtime 2805, and a device kernel driver 2806. In at least one embodiment, each library 2803 may include data and programming code that can be used by a computer program and utilized during software development. In at least one embodiment, library 2803 may include, but is not limited to, pre-written code and subroutines, classes, values, type specifications, configuration data, documentation, help data, and / or message templates. In at least one embodiment, library 2803 includes functions optimized for execution on one or more types of devices. In at least one embodiment, library 2803 may include, but is not limited to, functions for performing mathematical, deep learning, and / or other types of operations on the device. In at least one embodiment, library 2803 is associated with a corresponding API 2802, which may include one or more APIs that expose functions implemented in library 2803.

[0264] In at least one embodiment, application 2801 is written as source code, which is compiled into executable code, as follows: Figure 33-35 This will be discussed in more detail. In at least one embodiment, the executable code of application 2801 may run at least partially on an execution environment provided by software stack 2800. In at least one embodiment, during the execution of application 2801, code that needs to run on the device (compared to the host) may be obtained. In this case, in at least one embodiment, runtime 2805 may be invoked to load and start the necessary code on the device. In at least one embodiment, runtime 2805 may include any technically feasible runtime system capable of supporting the execution of application 2801.

[0265] In at least one embodiment, runtime 2805 is implemented as one or more runtime libraries associated with a corresponding API (shown as API 2804). In at least one embodiment, one or more such runtime libraries may include, but are not limited to, functions for memory management, execution control, device management, error handling, and / or synchronization, etc. In at least one embodiment, memory management functions may include, but are not limited to, functions for allocating, dealing with, and copying device memory, and for transferring data between host memory and device memory. In at least one embodiment, execution control functions may include, but are not limited to, functions for launching functions on the device (sometimes referred to as "kernels" when the function is a global function that can be called from the host), and functions for setting attribute values ​​in buffers maintained by the runtime library for a given function to be executed on the device.

[0266] In at least one embodiment, the runtime library and the corresponding API 2804 can be implemented in any technically feasible manner. In at least one embodiment, one (or any number of) APIs may expose a low-level set of functions for fine-grained control of the device, while another (or any number of) APIs may expose such a higher-level set of functions. In at least one embodiment, a high-level runtime API can be built on top of the low-level APIs. In at least one embodiment, one or more runtime APIs may be language-specific APIs layered on top of language-independent runtime APIs.

[0267] In at least one embodiment, device kernel driver 2806 is configured to facilitate communication with the underlying device. In at least one embodiment, device kernel driver 2806 may provide APIs such as API 2804 and / or low-level functions upon which other software depends. In at least one embodiment, device kernel driver 2806 may be configured to compile intermediate representation (“IR”) code into binary code at runtime. In at least one embodiment, for CUDA, device kernel driver 2806 may compile non-hardware-specific parallel thread execution (“PTX”) IR code into binary code (cached compiled binary code) for a specific target device (sometimes referred to as “final” code) at runtime. In at least one embodiment, doing so allows the final code to run on the target device, which may not exist when the source code was initially compiled into PTX code. Alternatively, in at least one embodiment, device source code may be compiled into binary code offline, without requiring device kernel driver 2806 to compile IR code at runtime.

[0268] In at least one embodiment, Figure 28 One or more systems described in the text are used to achieve, for example, combination Figures 1-8 The description refers to one or more systems and / or processes of the like.

[0269] Figure 29 The illustration shows an embodiment according to at least one of the embodiments. Figure 28 The software stack 2800 is a CUDA implementation. In at least one embodiment, the CUDA software stack 2900 on which an application 2901 can be launched includes a CUDA library 2903, a CUDA runtime 2905, a CUDA driver 2907, and a device kernel driver 2908. In at least one embodiment, the CUDA software stack 2900 executes on hardware 2909, which may include a CUDA-enabled GPU developed by NVIDIA Corporation of Santa Clara, California.

[0270] In at least one embodiment, application 2901, CUDA runtime 2905, and device kernel driver 2908 can respectively perform functions similar to those of application 2801, runtime 2805, and device kernel driver 2806, in combination with the above. Figure 28 The CUDA driver 2907 is described in at least one embodiment. In at least one embodiment, the CUDA driver API 2907 includes a library (libcuda.so) implementing the CUDA driver API 2906. In at least one embodiment, similar to the CUDA runtime API 2904 implemented by the CUDA runtime library (cudart), the CUDA driver API 2906 may expose, but is not limited to, functions for memory management, execution control, device management, error handling, synchronization, and / or graphics interoperability. In at least one embodiment, the CUDA driver API 2906 differs from the CUDA runtime API 2904 in that the CUDA runtime API 2904 simplifies device code management by providing implicit initialization, context (similar to processes) management, and module (similar to dynamically loaded libraries) management. In contrast to the high-level CUDA runtime API 2904, in at least one embodiment, the CUDA driver API 2906 is a low-level API that provides finer-grained control over the device, particularly regarding context and module loading. In at least one embodiment, the CUDA driver API 2906 may expose functions for context management that are not exposed by the CUDA runtime API 2904. In at least one embodiment, the CUDA driver API 2906 is also language-independent and supports, in addition to the CUDA runtime API 2904, OpenCL, for example. Furthermore, in at least one embodiment, development libraries, including the CUDA runtime 2905, can be considered separate from the driver components, including the user-mode CUDA driver 2907 and the kernel-mode device driver 2908 (sometimes also referred to as the "display" driver).

[0271] In at least one embodiment, CUDA library 2903 may include, but is not limited to, mathematical libraries, deep learning libraries, parallel algorithm libraries, and / or signal / image / video processing libraries, which parallel computing applications (e.g., application 2901) may utilize. In at least one embodiment, CUDA library 2903 may include mathematical libraries, such as the cuBLAS library, which is an implementation of basic linear algebra subroutines (“BLAS”) for performing linear algebra operations; the cuFFT library for computing the Fast Fourier Transform (“FFT”); and the cuRAND library for generating random numbers, etc. In at least one embodiment, CUDA library 2903 may include deep learning libraries, such as the cuDNN library for primitives of deep neural networks and the TensorRT platform for high-performance deep learning inference, etc.

[0272] In at least one embodiment, Figure 29 One or more systems described in the text are used to achieve, for example, combination Figures 1-8 The description refers to one or more systems and / or processes of the like.

[0273] Figure 30 The illustration shows an embodiment according to at least one of the embodiments. Figure 28 The software stack 2800 is a ROCm implementation. In at least one embodiment, the ROCm software stack 3000 on which the application 3001 can be launched includes a language runtime 3003, a system runtime 3005, a thunk 3007, and a ROCm kernel driver 3008. In at least one embodiment, the ROCm software stack 3000 executes on hardware 3009, which may include a ROCm-enabled GPU developed by AMD Inc. of Santa Clara, California.

[0274] In at least one embodiment, application 3001 can perform actions in conjunction with the above. Figure 28 The discussed application 2801 has similar functionality. Additionally, in at least one embodiment, the language runtime 3003 and system runtime 3005 can perform functions combined with the above. Figure 28 The runtime 2805 discussed has similar functionality. In at least one embodiment, the language runtime 3003 and the system runtime 3005 differ in that the system runtime 3005 is a language-independent runtime that implements the ROCr system runtime API 3004 and utilizes the Heterogeneous System Architecture (“HSA”) runtime API. In at least one embodiment, the HSA runtime API is a thin-user mode API that exposes interfaces for access and interaction with the AMD GPU, including functions for memory management, execution control of the kernel dispatched by the architecture, error handling, system and agent information, and runtime initialization and shutdown, etc. In at least one embodiment, compared to the system runtime 3005, the language runtime 3003 is an implementation of a language-specific runtime API 3002 layered on top of the ROCr system runtime API 3004. In at least one embodiment, the language runtime API may include, but is not limited to, the Portable Heterogeneous Computing Interface (“HIP”) language runtime API, the Heterogeneous Computing Compiler (“HCC”) language runtime API, or the OpenCL API, etc. In particular, the HIP language is an extension of the C++ programming language with a functionally similar version having CUDA mechanisms, and in at least one embodiment, the HIP language runtime API includes features combined with the above. Figure 29 The discussion focuses on functions similar to CUDA runtime API 2904, such as those used for memory management, execution control, device management, error handling, and synchronization.

[0275] In at least one embodiment, the thunk (ROCt) 3007 is an interface 3006 that can be used to interact with the underlying ROCm driver 3008. In at least one embodiment, the ROCm driver 3008 is a ROCk driver, which is a combination of an AMD GPU driver and an HSA core driver (AMDKFD). In at least one embodiment, the AMD GPU driver is a device core driver for GPUs developed by AMD, which performs the above-described combination. Figure 28 The device kernel driver 2806 discussed has similar functionality. In at least one embodiment, the HSA kernel driver is a driver that allows different types of processors to share system resources more efficiently via hardware features.

[0276] In at least one embodiment, various libraries (not shown) may be included in the ROCm software stack 3000 above the language runtime 3003, and provide integration with the above. Figure 29 The discussed CUDA library 2903 has similar functionality. In at least one embodiment, various libraries may include, but are not limited to, mathematical, deep learning, and / or other libraries, such as the hipBLAS library which implements functions similar to CUDA cuBLAS, the rocFFT library which is similar to CUDA cuFFT for computing FFT, etc.

[0277] In at least one embodiment, Figure 30 The system described herein is used to detect and / or predict (e.g., within a multi-GPU system) signals conducted by signal conductors, and employs various algorithms, formulas, and / or processes (e.g., combining...) Figure 1-8 Those described herein) transition signal conductors between active and inactive states, and / or otherwise perform the operations described herein. In at least one embodiment, Figure 30 The one or more systems described herein are used to implement one or more systems and / or processes, such as in combination. Figures 1-8 Those described.

[0278] Figure 31 The illustration shows an embodiment according to at least one of the embodiments. Figure 28 The software stack 2800 is an OpenCL implementation. In at least one embodiment, the OpenCL software stack 3100 on which the application 3101 can be launched includes an OpenCL framework 3110, an OpenCL runtime 3106, and a driver 3107. In at least one embodiment, the OpenCL software stack 3100 executes on non-vendor-specific hardware 2909. In at least one embodiment, because devices developed by different vendors support OpenCL, specific OpenCL drivers may be required for interoperability with hardware from such vendors.

[0279] In at least one embodiment, the application 3101, the OpenCL runtime 3106, the device kernel driver 3107, and the hardware 3108 can respectively execute the above-described combination. Figure 28 The application 2801, runtime 2805, device kernel driver 2806, and hardware 2807 discussed have similar functionality. In at least one embodiment, application 3101 also includes an OpenCL kernel 3102 with code that will be executed on the device.

[0280] In at least one embodiment, OpenCL defines a "platform" that allows a host to control devices connected to that host. In at least one embodiment, the OpenCL framework provides a platform-level API and a runtime API, shown as Platform API 3103 and Runtime API 3105. In at least one embodiment, Runtime API 3105 uses a context to manage the execution of the kernel on the device. In at least one embodiment, each identified device can be associated with a respective context, which Runtime API 3105 can use to manage the device's command queue, program objects and kernel objects, shared memory objects, etc. In at least one embodiment, Platform API 3103 discloses functions that allow the device context to select and initialize devices, submit work to devices via command queues, and enable data transfers to and from devices, etc. Additionally, in at least one embodiment, the OpenCL framework provides various built-in functions (not shown), including mathematical functions, relational functions, and image processing functions, etc.

[0281] In at least one embodiment, compiler 3104 is also included in the OpenCL framework 3110. In at least one embodiment, the source code may be compiled offline before the application is executed or compiled online during the execution of the application. In contrast to CUDA and ROCm, the OpenCL application in at least one embodiment may be compiled online by compiler 3104, which is included to represent any number of compilers that can be used to compile source code and / or IR code (e.g., Standard Portable Intermediate Representation (“SPIR-V”) code) into binary code. Alternatively, in at least one embodiment, the OpenCL application may be compiled offline before execution of such an application.

[0282] In at least one embodiment, Figure 31 The system described herein is used to detect and / or predict (e.g., within a multi-GPU system) signals conducted by signal conductors, and employs various algorithms, formulas, and / or processes (e.g., combining...) Figure 1-8Those described herein) transition signal conductors between active and inactive states, and / or otherwise perform the operations described herein. In at least one embodiment, Figure 31 The one or more systems described herein are used to implement one or more systems and / or processes, such as in combination. Figures 1-8 Those described.

[0283] Figure 32 Software supported by a programming platform according to at least one embodiment is illustrated. In at least one embodiment, the programming platform 3204 is configured to support various programming models 3203, middleware and / or libraries 3202, and frameworks 3201 that the application 3200 may depend on. In at least one embodiment, the application 3200 may be an AI / ML application implemented using, for example, a deep learning framework (e.g., MXNet, PyTorch, or TensorFlow), which may depend on libraries such as cuDNN, the NVIDIA Collective Communications Library (“NCCL”), and / or the NVIDIA Developer Data Loading Library (“DALI”) CUDA library to provide accelerated computation on the underlying hardware.

[0284] In at least one embodiment, the programming platform 3204 can be a combination of the above-described components. Figure 29 , Figure 30 and Figure 31 One of the described CUDA, ROCm, or OpenCL platforms. In at least one embodiment, the programming platform 3204 supports multiple programming models 3203, which are abstractions of the underlying computing system that allow for the expression of algorithms and data structures. In at least one embodiment, the programming model 3203 may expose features of the underlying hardware to improve performance. In at least one embodiment, the programming model 3203 may include, but is not limited to, CUDA, HIP, OpenCL, C++ Accelerated Massive Parallelism (“C++ AMP”), Open Multiprocessing (“OpenMP”), Open Accelerator (“OpenACC”), and / or Vulcan Compute.

[0285] In at least one embodiment, the library and / or middleware 3202 provides an abstract implementation of the programming model 3204. In at least one embodiment, such a library includes data and programming code that can be used by a computer program and utilized during software development. In at least one embodiment, in addition to those available from the programming platform 3204, such middleware also includes software that provides services to applications. In at least one embodiment, the library and / or middleware 3202 may include, but is not limited to, cuBLAS, cuFFT, cuRAND, and other CUDA libraries, or rocBLAS, rocFFT, rocRAND, and other ROCm libraries. Additionally, in at least one embodiment, the library and / or middleware 3202 may include NCCL and ROCm Communication Collection Library (“RCCL”) libraries, which provide communication routines for GPUs, MIOpen libraries for deep learning acceleration, and / or intrinsic libraries for linear algebra, matrix and vector operations, geometric transformations, numerical solvers, and related algorithms.

[0286] In at least one embodiment, the application framework 3201 depends on libraries and / or middleware 3202. In at least one embodiment, each application framework 3201 is a software framework for implementing a standard structure of application software. Returning to the AI / ML example discussed above, in at least one embodiment, AI / ML applications can be implemented using frameworks such as Caffe, Caffe2, TensorFlow, Keras, PyTorch, or the MxNet deep learning framework.

[0287] In at least one embodiment, Figure 32 The system described herein is used to detect and / or predict (e.g., within a multi-GPU system) signals conducted by signal conductors, and employs various algorithms, formulas, and / or processes (e.g., combining...) Figure 1-8 Those described herein) transition signal conductors between active and inactive states, and / or otherwise perform the operations described herein. In at least one embodiment, Figure 32 The one or more systems described herein are used to implement one or more systems and / or processes, such as in combination. Figures 1-8 Those described.

[0288] Figure 33 Compilation code according to at least one embodiment is shown to be used in Figure 28-31The application is executed on one of the programming platforms. In at least one embodiment, compiler 3301 receives source code 3300, which includes both host code and device code. In at least one embodiment, compiler 3301 is configured to convert source code 3300 into host executable code 3302 for execution on a host and device executable code 3303 for execution on a device. In at least one embodiment, source code 3300 may be compiled offline before executing the application or compiled online during application execution.

[0289] In at least one embodiment, source code 3300 may include code in any programming language supported by compiler 3301, such as C++, C, Fortran, etc. In at least one embodiment, source code 3300 may be included in a single-source file, which has a mixture of host code and device code, and indicates the location of the device code therein. In at least one embodiment, the single-source file may be a .cu file including CUDA code or a .hip.cpp file including HIP code. Alternatively, in at least one embodiment, source code 3300 may include multiple source code files instead of a single source file, in which the host code and device code are separate.

[0290] In at least one embodiment, compiler 3301 is configured to compile source code 3300 into host executable code 3302 for execution on a host and device executable code 3303 for execution on a device. In at least one embodiment, compiler 3301 performs operations including resolving source code 3300 into an abstract system tree (AST), performing optimizations, and generating executable code. In at least one embodiment where source code 3300 comprises a single source file, compiler 3301 may separate device code and host code within this single source file, compile the device code and host code into device executable code 3303 and host executable code 3302 respectively, and link the device executable code 3303 and host executable code 3302 together in a single file, as described below. Figure 34 To be discussed in more detail.

[0291] In at least one embodiment, the host executable code 3302 and the device executable code 3303 can be in any suitable format, such as binary code and / or IR code. In the case of CUDA, in at least one embodiment, the host executable code 3302 may include native object code, while the device executable code 3303 may include code in a PTX intermediate representation. In at least one embodiment, in the case of ROCm, both the host executable code 3302 and the device executable code 3303 can include target binary code.

[0292] In at least one embodiment, Figure 33 The system described herein is used to detect and / or predict (e.g., within a multi-GPU system) signals conducted by signal conductors, and employs various algorithms, formulas, and / or processes (e.g., combining...) Figure 1-8 Those described herein) transition signal conductors between active and inactive states, and / or otherwise perform the operations described herein. In at least one embodiment, Figure 33 The one or more systems described herein are used to implement one or more systems and / or processes, such as in combination. Figures 1-8 Those described.

[0293] Figure 34 It is compiled code according to at least one embodiment to be used in Figure 28-31 A more detailed illustration is provided on one of the programming platforms. In at least one embodiment, compiler 3401 is configured to receive source code 3400, compile source code 3400, and output executable file 3410. In at least one embodiment, source code 3400 is a single source file, such as a .cu file, a .hip.cpp file, or a file of other formats, which includes both host code and device code. In at least one embodiment, compiler 3401 may be, but is not limited to, an NVIDIA CUDA compiler (“NVCC”) for compiling CUDA code in .cu files, or an HCC compiler for compiling HIP code in .hip.cpp files.

[0294] In at least one embodiment, compiler 3401 includes compiler front-end 3402, host compiler 3405, device compiler 3406, and linker 3409. In at least one embodiment, compiler front-end 3402 is configured to separate device code 3404 from host code 3403 in source code 3400. In at least one embodiment, device code 3404 is compiled by device compiler 3406 into device executable code 3408, which, as described, may include binary code or IR code. In at least one embodiment, host code 3403 is compiled separately by host compiler 3405 into host executable code 3407. In at least one embodiment, for NVCC, host compiler 3405 may be, but is not limited to, a general-purpose C / C++ compiler that outputs native object code, while device compiler 3406 may be, but is not limited to, a low-level virtual machine (“LLVM”) based compiler that forks the LLVM compiler infrastructure and outputs PTX code or binary code. In at least one embodiment, for HCC, both the host compiler 3405 and the device compiler 3406 can be, but are not limited to, LLVM-based compilers that output target binary code.

[0295] In at least one embodiment, after compiling source code 3400 into host executable code 3407 and device executable code 3408, linker 3409 links the host and device executable codes 3407 and 3408 together in executable file 3410. In at least one embodiment, the native object code of the host and PTX or the binary code of the device can be linked together in an executable and linkable format (“ELF”) file, which is a container format for storing object code.

[0296] In at least one embodiment, Figure 34 The system described herein is used to detect and / or predict (e.g., within a multi-GPU system) signals conducted by signal conductors, and employs various algorithms, formulas, and / or processes (e.g., combining...) Figure 1-8 Those described herein) transition signal conductors between active and inactive states, and / or otherwise perform the operations described herein. In at least one embodiment, Figure 34 The one or more systems described herein are used to implement one or more systems and / or processes, such as in combination. Figures 1-8 Those described.

[0297] Figure 35 The illustration shows the transformation of source code prior to compilation, according to at least one embodiment. In at least one embodiment, source code 3500 is passed via a transformation tool 3501, which transforms source code 3500 into transformed source code 3502. In at least one embodiment, a compiler 3503 is used to compile the transformed source code 3502 into host executable code 3504 and device executable code 3405, a process similar to that of compiler 3301 compiling source code 3300 into host executable code 3302 and device executable code 3303, as described above. Figure 33 The subject of discussion.

[0298] In at least one embodiment, the transformation performed by the transformation tool 3501 is used to port source code 3500 to perform in an environment different from where it was originally intended to run. In at least one embodiment, the transformation tool 3501 may include, but is not limited to, a HIP converter for “hipify” CUDA code intended for a CUDA platform into HIP code that can be compiled and executed on the ROCm platform. In at least one embodiment, the transformation of source code 3500 may include: parsing source code 3500 and converting calls to APIs provided by one programming model (e.g., CUDA) into corresponding calls to APIs provided by another programming model (e.g., HIP), as combined below. Figure 36A and Figure 37This will be discussed in more detail. Returning to the example of porting CUDA code, in at least one embodiment, calls to the CUDA runtime API, CUDA driver API, and / or CUDA libraries can be translated into corresponding HIP API calls. In at least one embodiment, the automatic translation performed by the translation tool 3501 may sometimes be incomplete, requiring additional manual intervention to fully port the source code 3500.

[0299] In at least one embodiment, Figure 35 The system described herein is used to detect and / or predict (e.g., within a multi-GPU system) signals conducted by signal conductors, and employs various algorithms, formulas, and / or processes (e.g., combining...) Figure 1-8 Those described herein) transition signal conductors between active and inactive states, and / or otherwise perform the operations described herein. In at least one embodiment, Figure 35 The one or more systems described herein are used to implement one or more systems and / or processes, such as in combination. Figures 1-8 Those described.

[0300] Configure GPUs for general-purpose computing The following figures illustrate, but are not limited to, exemplary architectures for compiling and executing computational source code according to at least one embodiment.

[0301] Figure 36A A system 36A00 is shown, configured to compile and execute CUDA source code 3610 using different types of processing units according to at least one embodiment. In at least one embodiment, system 36A00 includes, but is not limited to, CUDA source code 3610, CUDA compiler 3650, host executable code 3670(1), host executable code 3670(2), CUDA device executable code 3684, CPU 3690, CUDA-enabled GPU 3694, GPU 3692, CUDA to HIP conversion tool 3620, HIP source code 3630, HIP compiler driver 3640, HCC 3660, and HCC device executable code 3682.

[0302] In at least one embodiment, CUDA source code 3610 is a collection of human-readable code in the CUDA programming language. In at least one embodiment, CUDA code is human-readable code in the CUDA programming language. In at least one embodiment, the CUDA programming language is an extension of the C++ programming language, which includes, but is not limited to, defining device code and mechanisms for distinguishing between device code and host code. In at least one embodiment, device code is source code that can be executed in parallel on a device after compilation. In at least one embodiment, the device may be a processor optimized for parallel instruction processing, such as a CUDA-enabled GPU 3690, GPU 36192, or another GPGPU. In at least one embodiment, host code is source code that can be executed on a host after compilation. In at least one embodiment, the host is a processor optimized for sequential instruction processing, such as CPU 3690.

[0303] In at least one embodiment, CUDA source code 3610 includes, but is not limited to, any number (including zero) of global functions 3612, any number (including zero) of device functions 3614, any number (including zero) of host functions 3616, and any number (including zero) of host / device functions 3618. In at least one embodiment, the global functions 3612, device functions 3614, host functions 3616, and host / device functions 3618 can be mixed in CUDA source code 3610. In at least one embodiment, each global function 3612 is executable on a device and is callable from a host. Therefore, in at least one embodiment, one or more of the global functions 3612 can serve as entry points for a device. In at least one embodiment, each global function 3612 is a kernel. In at least one embodiment, and in a technique called dynamic parallelism, one or more global functions 3612 define a kernel that is executable on a device and is callable from such a device. In at least one embodiment, the kernel is executed in parallel N times (where N is any positive integer) by N different threads on the device during execution.

[0304] In at least one embodiment, each device function 3614 is executed on a device and can only be called from such a device. In at least one embodiment, each host function 3616 is executed on a host and can only be called from such a host. In at least one embodiment, each host / device function 3616 defines both a host version of a function that is executable on a host and can only be called from such a host, and a device version of a function that is executable on a device and can only be called from such a device.

[0305] In at least one embodiment, CUDA source code 3610 may also include, but is not limited to, any number of calls to any number of functions defined by CUDA runtime API 3602. In at least one embodiment, CUDA runtime API 3602 may include, but is not limited to, any number of functions executed on the host for allocating and dealing device memory, transferring data between host memory and device memory, managing a system with multiple devices, etc. In at least one embodiment, CUDA source code 3610 may also include, but is not limited to, any number of calls to any number of functions specified in any number of other CUDA APIs. In at least one embodiment, a CUDA API may be any API designed to be used by CUDA code. In at least one embodiment, a CUDA API includes, but is not limited to, CUDA runtime API 3602, CUDA driver APIs, APIs for any number of CUDA libraries, etc. In at least one embodiment, and relative to CUDA runtime API 3602, the CUDA driver API is a lower-level API but can provide finer-grained control over devices. In at least one embodiment, examples of CUDA libraries include, but are not limited to, cuBLAS, cuFFT, cURAND, cuDNN, etc.

[0306] In at least one embodiment, CUDA compiler 3650 compiles input CUDA code (e.g., CUDA source code 3610) to generate host executable code 3670(1) and CUDA device executable code 3684. In at least one embodiment, CUDA compiler 3650 is an NVCC. In at least one embodiment, host executable code 3670(1) is a compiled version of host code included in input source code executable on CPU 3690. In at least one embodiment, CPU 3690 can be any processor optimized for sequential instruction processing.

[0307] In at least one embodiment, CUDA device executable code 3684 is a compiled version of device code included in input source code executable on a CUDA-enabled GPU 3694. In at least one embodiment, CUDA device executable code 3684 includes, but is not limited to, binary code. In at least one embodiment, CUDA device executable code 3684 includes, but is not limited to, IR code, such as PTX code, which is further compiled at runtime by a device driver into binary code for a specific target device (e.g., a CUDA-enabled GPU 3694). In at least one embodiment, the CUDA-enabled GPU 3694 can be any processor optimized for parallel instruction processing and supporting CUDA. In at least one embodiment, the CUDA-enabled GPU 3694 was developed by NVIDIA Corporation of Santa Clara, California.

[0308] In at least one embodiment, the CUDA-to-HIP conversion tool 3620 is configured to convert CUDA source code 3610 into functionally similar HIP source code 3630. In at least one embodiment, the HIP source code 3630 is a collection of human-readable code in a HIP programming language. In at least one embodiment, the HIP code is human-readable code in a HIP programming language. In at least one embodiment, the HIP programming language is an extension of the C++ programming language, including but not limited to a functionally similar version of the CUDA mechanism, used to define device code and distinguish between device code and host code. In at least one embodiment, the HIP programming language may include a subset of the functionality of the CUDA programming language. In at least one embodiment, for example, the HIP programming language includes, but is not limited to, a mechanism for defining global functions 3612; however, such a HIP programming language may lack support for dynamic parallelism, therefore, the global function 3612 defined in the HIP code can only be called from the host.

[0309] In at least one embodiment, the HIP source code 3630 includes, but is not limited to, any number (including zero) of global functions 3612, any number (including zero) of device functions 3614, any number (including zero) of host functions 3616, and any number (including zero) of host / device functions 3618. In at least one embodiment, the HIP source code 3630 may also include any number of calls to any number of functions specified in the HIP runtime API 3632. In one embodiment, the HIP runtime API 3632 includes, but is not limited to, functionally similar versions of a subset of functions included in the CUDA runtime API 3602. In at least one embodiment, the HIP source code 3630 may also include any number of calls to any number of functions specified in any number of other HIP APIs. In at least one embodiment, the HIP API may be any API designed for use by HIP code and / or ROCm. In at least one embodiment, the HIP API includes, but is not limited to, the HIP runtime API 3632, the HIP driver API, APIs for any number of HIP libraries, APIs for any number of ROCm libraries, etc.

[0310] In at least one embodiment, the CUDA-to-HIP conversion tool 3620 converts each kernel call in CUDA code from CUDA syntax to HIP syntax, and converts any number of other CUDA calls in the CUDA code into any number of other functionally similar HIP calls. In at least one embodiment, a CUDA call is a call to a function specified in the CUDA API, and a HIP call is a call to a function specified in the HIP API. In at least one embodiment, the CUDA-to-HIP conversion tool 3620 converts any number of calls to functions specified in the CUDA runtime API 3602 into any number of calls to functions specified in the HIP runtime API 3632.

[0311] In at least one embodiment, the CUDA to HIP conversion tool 3620 is a tool called hipify-perl that performs a text-based conversion process. In at least one embodiment, the CUDA to HIP conversion tool 3620 is a tool called hipify-clang that, compared to hipify-perl, performs a more complex and robust conversion process involving parsing the CUDA code using clang (a compiler front-end) and then converting the resulting symbols. In at least one embodiment, in addition to the modifications performed by the CUDA to HIP conversion tool 3620, correctly converting the CUDA code into HIP code may require further modifications (e.g., manual editing).

[0312] In at least one embodiment, the HIP compiler driver 3640 is the front end that determines the target device 3646 and then configures a compiler compatible with the target device 3646 to compile the HIP source code 3630. In at least one embodiment, the target device 3646 is a processor optimized for parallel instruction processing. In at least one embodiment, the HIP compiler driver 3640 can determine the target device 3646 in any technically feasible manner.

[0313] In at least one embodiment, if the target device 3646 is CUDA-compatible (e.g., a CUDA-enabled GPU 3694), the HIP compiler driver 3640 generates HIP / NVCC compilation commands 3642. In at least one embodiment and in conjunction with... Figure 36B In more detail, the HIP / NVCC compilation command 3642 configures the CUDA compiler 3650 to compile the HIP source code 3630 using, but not limited to, a HIP-to-CUDA translation header and a CUDA runtime library. In at least one embodiment and in response to the HIP / NVCC compilation command 3642, the CUDA compiler 3650 generates host executable code 3670(1) and CUDA device executable code 3684.

[0314] In at least one embodiment, if the target device 3646 is incompatible with CUDA, the HIP compiler driver 3640 generates HIP / HCC compilation commands 3644. In at least one embodiment and as in conjunction with... Figure 36C In more detail, HIP / HCC compilation command 3644 configures HCC 3660 to compile HIP source code 3630 using the HCC header and HIP / HCC runtime library. In at least one embodiment and in response to HIP / HCC compilation command 3644, HCC 3660 generates host executable code 3670 (2) and HCC device executable code 3682. In at least one embodiment, HCC device executable code 3682 is a compiled version of device code executable on GPU 3692 contained in HIP source code 3630. In at least one embodiment, GPU 3692 may be any processor optimized for parallel instruction processing, incompatible with CUDA, and compatible with HCC. In at least one embodiment, GPU 3692 was developed by AMD Inc. of Santa Clara, California. In at least one embodiment, GPU 3692 is a GPU 3692 without CUDA enabled.

[0315] For illustrative purposes only, Figure 36AThe document describes three different processes that, in at least one embodiment, can be implemented to compile CUDA source code 3610 for execution on CPU 3690 and various devices. In at least one embodiment, a direct CUDA process compiles CUDA source code 3610 for execution on CPU 3690 and a CUDA-enabled GPU 3694 without converting CUDA source code 3610 to HIP source code 3630. In at least one embodiment, an indirect CUDA process converts CUDA source code 3610 to HIP source code 3630 and then compiles the HIP source code 3630 for execution on CPU 3690 and a CUDA-enabled GPU 3694. In at least one embodiment, a CUDA / HCC process converts CUDA source code 3610 to HIP source code 3630 and then compiles the HIP source code 3630 for execution on CPU 3690 and GPU 3692.

[0316] The direct CUDA flow, which can be implemented in at least one embodiment, can be depicted by dashed lines and a series of bubble comments A1-A3. In at least one embodiment, and as indicated by bubble comment A1, CUDA compiler 3650 receives CUDA source code 3610 and CUDA compilation command 3648 that configures CUDA compiler 3650 to compile CUDA source code 3610. In at least one embodiment, the CUDA source code 3610 used in the direct CUDA flow is written in a CUDA programming language based on a programming language other than C++ (e.g., C, Fortran, Python, Java, etc.). In at least one embodiment, and in response to CUDA compilation command 3648, CUDA compiler 3650 generates host executable code 3670(1) and CUDA device executable code 3684 (indicated by bubble comment A2). In at least one embodiment, and as indicated by bubble comment A3, host executable code 3670(1) and CUDA device executable code 3684 can be executed on CPU 3690 and CUDA-enabled GPU 3694, respectively. In at least one embodiment, the CUDA device executable code 3684 includes, but is not limited to, binary code. In at least one embodiment, the CUDA device executable code 3684 includes, but is not limited to, PTX code, and is further compiled at runtime into binary code for a specific target device.

[0317] The indirect CUDA process, which can be implemented in at least one embodiment, can be described by dashed lines and a series of bubble comments B1-B6. In at least one embodiment, and as shown in bubble comment B1, CUDA-to-HIP conversion tool 3620 receives CUDA source code 3610. In at least one embodiment, and as shown in bubble comment B2, CUDA-to-HIP conversion tool 3620 converts CUDA source code 3610 into HIP source code 3630. In at least one embodiment, and as shown in bubble comment B3, HIP compiler driver 3640 receives HIP source code 3630 and determines whether the target device 3646 has CUDA enabled.

[0318] In at least one embodiment and as shown in bubble note B4, the HIP compiler driver 3640 generates HIP / NVCC compilation commands 3642 and sends both the HIP / NVCC compilation commands 3642 and the HIP source code 3630 to the CUDA compiler 3650. In at least one embodiment and as shown in combination Figure 36B In more detail, HIP / NVCC compilation command 3642 configures CUDA compiler 3650 to compile HIP source code 3630 using, but not limited to, a HIP-to-CUDA translation header and a CUDA runtime library. In at least one embodiment and in response to HIP / NVCC compilation command 3642, CUDA compiler 3650 generates host executable code 3670(1) and CUDA device executable code 3684 (indicated by bubble comment B5). In at least one embodiment and as shown by bubble comment B6, host executable code 3670(1) and CUDA device executable code 3684 can be executed on CPU 3690 and CUDA-enabled GPU 3694, respectively. In at least one embodiment, CUDA device executable code 3684 includes, but is not limited to, binary code. In at least one embodiment, CUDA device executable code 3684 includes, but is not limited to, PTX code, and is further compiled at runtime into binary code for a specific target device.

[0319] The CUDA / HCC process, which can be implemented in at least one embodiment, can be described by solid lines and a series of bubble comments C1-C6. In at least one embodiment, and as shown in bubble comment C1, the CUDA to HIP conversion tool 3620 receives CUDA source code 3610. In at least one embodiment, and as shown in bubble comment C2, the CUDA to HIP conversion tool 3620 converts the CUDA source code 3610 into HIP source code 3630. In at least one embodiment, and as shown in bubble comment C3, the HIP compiler driver 3640 receives the HIP source code 3630 and determines that the target device 3646 does not have CUDA enabled.

[0320] In at least one embodiment, the HIP compiler driver 3640 generates HIP / HCC compilation commands 3644 and sends both the HIP / HCC compilation commands 3664 and the HIP source code 3630 to the HCC 3660 (indicated by bubble comment C4). In at least one embodiment and as in combination Figure 36C In more detail, HIP / HCC compilation command 3664 configures HCC 3660 to compile HIP source code 3630 using, but not limited to, the HCC header and HIP / HCC runtime library. In at least one embodiment and in response to HIP / HCC compilation command 3644, HCC 3660 generates host executable code 3670(2) and HCC device executable code 3682 (indicated by bubble comment C5). In at least one embodiment and as shown by bubble comment C6, host executable code 3670(2) and HCC device executable code 3682 can be executed on CPU 3690 and GPU 3692, respectively.

[0321] In at least one embodiment, after converting CUDA source code 3610 to HIP source code 3630, the HIP compiler driver 3640 can then be used to generate executable code for a CUDA-enabled GPU 3694 or GPU 3692 without re-executing CUDA to the HIP conversion tool 3620. In at least one embodiment, the CUDA to HIP conversion tool 3620 converts CUDA source code 3610 to HIP source code 3630 and then stores it in memory. In at least one embodiment, the HIP compiler driver 3640 then configures HCC 3660 to generate host executable code 3670 (2) and HCC device executable code 3682 based on the HIP source code 3630. In at least one embodiment, the HIP compiler driver 3640 then configures CUDA compiler 3650 to generate host executable code 3670 (1) and CUDA device executable code 3684 based on the stored HIP source code 3630.

[0322] Figure 36B The diagram illustrates a configuration, according to at least one embodiment, to compile and execute using a CPU 3690 and a CUDA-enabled GPU 3694. Figure 36A The system 3604 includes, but is not limited to, CUDA source code 3610, CUDA to HIP conversion tool 3620, HIP source code 3630, HIP compiler driver 3640, CUDA compiler 3650, host executable code 3670 (1), CUDA device executable code 3684, CPU 3690, and CUDA-enabled GPU 3694.

[0323] In at least one embodiment and as previously mentioned herein Figure 36A As described, the CUDA source code 3610 includes, but is not limited to, any number (including zero) of global functions 3612, any number (including zero) of device functions 3614, any number (including zero) of host functions 3616, and any number (including zero) of host / device functions 3618. In at least one embodiment, the CUDA source code 3610 also includes, but is not limited to, any number of calls to any number of functions specified in any number of CUDA APIs.

[0324] In at least one embodiment, the CUDA to HIP conversion tool 3620 converts CUDA source code 3610 into HIP source code 3630. In at least one embodiment, the CUDA to HIP conversion tool 3620 converts each kernel call in the CUDA source code 3610 from CUDA syntax to HIP syntax, and converts any number of other CUDA calls in the CUDA source code 3610 into any number of other functionally similar HIP calls.

[0325] In at least one embodiment, the HIP compiler driver 3640 determines that the target device 3646 is CUDA enabled and generates HIP / NVCC compilation commands 3642. In at least one embodiment, the HIP compiler driver 3640 then configures the CUDA compiler 3650 via the HIP / NVCC compilation commands 3642 to compile the HIP source code 3630. In at least one embodiment, as part of configuring the CUDA compiler 3650, the HIP compiler driver 3640 provides access to a HIP-to-CUDA translation header 3652. In at least one embodiment, the HIP-to-CUDA translation header 3652 translates an arbitrary number of mechanisms (e.g., functions) specified in an arbitrary number of HIP APIs into an arbitrary number of mechanisms specified in an arbitrary number of CUDA APIs. In at least one embodiment, the CUDA compiler 3650 uses the HIP-to-CUDA translation header 3652 in conjunction with a CUDA runtime library 3654 corresponding to the CUDA runtime API 3602 to generate host executable code 3670(1) and CUDA device executable code 3684. In at least one embodiment, host executable code 3670(1) and CUDA device executable code 3684 can then be executed on CPU 3690 and CUDA-enabled GPU 3694, respectively. In at least one embodiment, CUDA device executable code 3684 includes, but is not limited to, binary code. In at least one embodiment, CUDA device executable code 3684 includes, but is not limited to, PTX code, and is further compiled at runtime into binary code for a specific target device.

[0326] Figure 36C A system 3606 according to at least one embodiment is shown, the system 3606 being configured to compile and execute using a CPU 3690 and a GPU 3692 with CUDA disabled. Figure 36A The CUDA source code 3610. In at least one embodiment, the system 3606 includes, but is not limited to, the CUDA source code 3610, the CUDA to HIP conversion tool 3620, the HIP source code 3630, the HIP compiler driver 3640, the HCC 3660, the host executable code 3670 (2), the HCC device executable code 3682, the CPU 3690, and the GPU 3692.

[0327] In at least one embodiment, and as previously mentioned herein Figure 36AAs described, the CUDA source code 3610 includes, but is not limited to, any number (including zero) of global functions 3612, any number (including zero) of device functions 3614, any number (including zero) of host functions 3616, and any number (including zero) of host / device functions 3618. In at least one embodiment, the CUDA source code 3610 also includes, but is not limited to, any number of calls to any number of functions specified in any number of CUDA APIs.

[0328] In at least one embodiment, the CUDA to HIP conversion tool 3620 converts CUDA source code 3610 into HIP source code 3630. In at least one embodiment, the CUDA to HIP conversion tool 3620 converts each kernel call in the CUDA source code 3610 from CUDA syntax to HIP syntax, and converts any number of other CUDA calls in the source code 3610 into any number of other functionally similar HIP calls.

[0329] In at least one embodiment, the HIP compiler driver 3640 then determines that the target device 3646 is not CUDA enabled and generates a HIP / HCC compilation command 3644. In at least one embodiment, the HIP compiler driver 3640 then configures the HCC 3660 to execute the HIP / HCC compilation command 3644, thereby compiling the HIP source code 3630. In at least one embodiment, the HIP / HCC compilation command 3644 configures the HCC 3660 to use, but not limited to, the HIP / HCC runtime library 3658 and the HCC header 3656 to generate host executable code 3670(2) and HCC device executable code 3682. In at least one embodiment, the HIP / HCC runtime library 3658 corresponds to the HIP runtime API 3632. In at least one embodiment, the HCC header 3656 includes, but is not limited to, any number and type of interoperability mechanisms for HIP and HCC. In at least one embodiment, host executable code 3670 (2) and HCC device executable code 3682 can be executed on CPU 3690 and GPU 3692, respectively.

[0330] In at least one embodiment, Figures 36A-36C One or more systems described in the text are used to achieve, for example, combination Figures 1-8 The description refers to one or more systems and / or processes of the like.

[0331] Figure 37 The diagram illustrates a method according to at least one embodiment. Figure 36CAn exemplary kernel is converted by the CUDA to HIP conversion tool 3620. In at least one embodiment, the CUDA source code 3610 divides the overall problem that a given kernel is designed to solve into relatively coarse subproblems that can be solved independently using thread blocks. In at least one embodiment, each thread block includes, but is not limited to, any number of threads. In at least one embodiment, each subproblem is divided into relatively small pieces that can be solved in parallel by threads within the thread block. In at least one embodiment, threads within a thread block can cooperate by sharing data through shared memory and by coordinating memory accesses through synchronized execution.

[0332] In at least one embodiment, CUDA source code 3610 organizes thread blocks associated with a given kernel into a one-dimensional, two-dimensional, or three-dimensional grid of thread blocks. In at least one embodiment, each thread block includes, but is not limited to, any number of threads, and the grid includes, but is not limited to, any number of thread blocks.

[0333] In at least one embodiment, the kernel is using " global The specifier declares functions in the device code. In at least one embodiment, CUDA kernel startup syntax 3710 is used to specify the size of the mesh for executing the kernel for a given kernel call and the associated flow. In at least one embodiment, CUDA kernel startup syntax 3710 is specified as "KernelName <<<GridSize,BlockSize,SharedMemorySize,Stream > >> (KernelArguments);". In at least one embodiment, the execution configuration syntax is a "<<< ... >>>" construct, which is inserted between the kernel name ("KernelName") and the bracketed list of kernel parameters ("KernelArguments"). In at least one embodiment, the CUDA kernel startup syntax 3710 includes, but is not limited to, the CUDA startup function syntax instead of the execution configuration syntax.

[0334] In at least one embodiment, "GridSize" is of type dim3 and specifies the size and dimensions of the grid. In at least one embodiment, type dim3 is a CUDA-defined structure, which includes, but is not limited to, unsigned integers x, y, and z. In at least one embodiment, if z is not specified, z defaults to 1. In at least one embodiment, if y is not specified, y defaults to 1. In at least one embodiment, the number of thread blocks in the grid is equal to the product of GridSize.x, GridSize.y, and GridSize.z. In at least one embodiment, "BlockSize" is of type dim3 and specifies the size and dimensions of each thread block. In at least one embodiment, the number of threads per thread block is equal to the product of BlockSize.x, BlockSize.y, and BlockSize.z. In at least one embodiment, each thread executing the kernel has a unique thread ID, which can be accessed within the kernel via a built-in variable (e.g., "threadIdx").

[0335] In at least one embodiment, regarding CUDA kernel startup syntax 3710, "SharedMemorySize" is an optional parameter that specifies the number of bytes dynamically allocated for each thread block in shared memory for a given kernel call, excluding statically allocated memory. In at least one embodiment and regarding CUDA kernel startup syntax 3710, SharedMemorySize defaults to zero. In at least one embodiment and regarding CUDA kernel startup syntax 3710, "stream" is an optional parameter that specifies an associated stream and defaults to zero to specify a default stream. In at least one embodiment, a stream is a sequence of commands executed sequentially (which may be issued by different host threads). In at least one embodiment, different streams may execute commands out of order or simultaneously relative to each other.

[0336] In at least one embodiment, CUDA source code 3610 includes, but is not limited to, kernel definitions and a main function for the exemplary kernel "MatAdd". In at least one embodiment, the main function is host code executed on the host and includes, but is not limited to, kernel calls that cause the kernel MatAdd to execute on the device. In at least one embodiment, as shown, the kernel MatAdd adds two matrices A and B of size N x N, where N is a positive integer, and stores the result in matrix C. In at least one embodiment, the main function defines the threadsPerBlock variable as 16 x 16 and the numBlocks variable as N / 16 x N / 16. In at least one embodiment, the main function then specifies the kernel call "MatAdd<<<numBlocks,threadsPerBlock> >> (A, B, C);”. In at least one embodiment, and in accordance with CUDA kernel startup syntax 3710, a grid of thread blocks of size N / 16 × N / 16 is used to execute the kernel MatAdd, where each thread block is 16 × 16. In at least one embodiment, each thread block comprises 256 threads, creating a grid with enough blocks to allow one thread per matrix element, and each thread in the grid executes the kernel MatAdd to perform a pairwise addition.

[0337] In at least one embodiment, while converting CUDA source code 3610 to HIP source code 3630, the CUDA-to-HIP conversion tool 3620 converts each kernel call in the CUDA source code 3610 from CUDA kernel startup syntax 3710 to HIP kernel startup syntax 3720, and converts any number of other CUDA calls in the source code 3610 into any number of other functionally similar HIP calls. In at least one embodiment, the HIP kernel startup syntax 3720 is specified as “hipLaunchKernelGGL(KernelName,GridSize, BlockSize, SharedMemorySize, Stream,KernelArguments);”. In at least one embodiment, each of KernelName, GridSize, BlockSize, ShareMemorySize, Stream, and KernelArguments has the same meaning in the HIP kernel startup syntax 3720 as it does in the CUDA kernel startup syntax 3710 (as previously described herein). In at least one embodiment, the parameters SharedMemorySize and Stream are required in HIP kernel startup syntax 3720, but optional in CUDA kernel startup syntax 3710.

[0338] In at least one embodiment, in addition to the kernel call that causes the kernel MatAdd to execute on the device, Figure 37 The part of HIP source code 3630 described in the text is related to... Figure 37 The portion is identical to that depicted in CUDA source code 3610. In at least one embodiment, the kernel MatAdd is defined in HIP source code 3630, having the same "..." as the kernel MatAdd defined in CUDA source code 3610. global "Declaration specifier. In at least one embodiment, the kernel call in HIP source code 3630 is "hipLaunchKernelGGL(MatAdd, numBlocks, threadsPerBlock, 0, 0, A, B, C);", while the corresponding kernel call in CUDA source code 3610 is "MatAdd <<<numBlocks,threadsPerBlock> >> (A, B, C);”.

[0339] In at least one embodiment, Figure 37 The system described herein is used to detect and / or predict (e.g., within a multi-GPU system) signals conducted by signal conductors, and employs various algorithms, formulas, and / or processes (e.g., combining...) Figure 1-8 Those described herein) transition signal conductors between active and inactive states, and / or otherwise perform the operations described herein. In at least one embodiment, Figure 37 The one or more systems described herein are used to implement one or more systems and / or processes, such as in combination. Figures 1-8 Those described.

[0340] Figure 38 A more detailed description is provided according to at least one embodiment. Figure 36C The GPU 3692 is a CUDA-unenabled GPU. In at least one embodiment, the GPU 3692 was developed by AMD Inc. of Santa Clara City. In at least one embodiment, the GPU 3692 can be configured to perform computational operations in a highly parallel manner. In at least one embodiment, the GPU 3692 is configured to perform graphics pipeline operations, such as drawing commands, pixel operations, geometric calculations, and other operations associated with rendering images to a display. In at least one embodiment, the GPU 3692 is configured to perform graphics-independent operations. In at least one embodiment, the GPU 3692 is configured to perform both graphics-related and graphics-independent operations. In at least one embodiment, the GPU 3692 can be configured to execute device code included in HIP source code 3630.

[0341] In at least one embodiment, the GPU 3692 includes, but is not limited to, any number of programmable processing units 3820, an command processor 3810, an L2 cache 3822, a memory controller 3870, a DMA engine 3880 (1), a system memory controller 3882, a DMA engine 3880 (2), and a GPU controller 3884. In at least one embodiment, each programmable processing unit 3820 includes, but is not limited to, a workload manager 3830 and any number of compute units 3840. In at least one embodiment, the command processor 3810 reads commands from one or more command queues (not shown) and distributes the commands to the workload manager 3830. In at least one embodiment, for each programmable processing unit 3820, the associated workload manager 3830 distributes work to the compute units 3840 included in the programmable processing unit 3820. In at least one embodiment, each compute unit 3840 can execute any number of thread blocks, but each thread block executes on a single compute unit 3840. In at least one embodiment, the workgroup is a thread block.

[0342] In at least one embodiment, each computing unit 3840 includes, but is not limited to, any number of SIMD units 3850 and shared memory 3860. In at least one embodiment, each SIMD unit 3850 implements a SIMD architecture and is configured to perform operations in parallel. In at least one embodiment, each SIMD unit 3850 includes, but is not limited to, a vector ALU 3852 and a vector register file 3854. In at least one embodiment, each SIMD unit 3850 executes a different thread bundle. In at least one embodiment, a thread bundle is a group of threads (e.g., 16 threads), where each thread in the thread bundle belongs to a single thread block and is configured to process different datasets based on a single instruction set. In at least one embodiment, prediction can be used to disable one or more threads in a thread bundle. In at least one embodiment, a channel is a thread. In at least one embodiment, a work item is a thread. In at least one embodiment, a wavefront is a thread bundle. In at least one embodiment, different wavefronts in a thread block can be synchronized together and communicate via shared memory 3860.

[0343] In at least one embodiment, the programmable processing unit 3820 is referred to as a "shading engine". In at least one embodiment, in addition to the computing unit 3840, each programmable processing unit 3820 also includes, but is not limited to, any number of dedicated graphics hardware. In at least one embodiment, each programmable processing unit 3820 includes, but is not limited to, any number (including zero) of geometry processors, any number (including zero) of rasterizers, any number (including zero) of rendering backends, a workload manager 3830, and any number of computing units 3840.

[0344] In at least one embodiment, compute units 3840 share an L2 cache 3822. In at least one embodiment, the L2 cache 3822 is partitioned. In at least one embodiment, all compute units 3840 in the GPU 3692 have access to the GPU memory 3890. In at least one embodiment, a memory controller 3870 and a system memory controller 3882 facilitate data transfer between the GPU 3692 and the host, and a DMA engine 3880 (1) enables asynchronous memory transfers between the GPU 3692 and the host. In at least one embodiment, a memory controller 3870 and a GPU controller 3884 facilitate data transfers between the GPU 3692 and other GPUs 3692, and a DMA engine 3880 (2) enables asynchronous memory transfers between the GPU 3692 and other GPUs 3692.

[0345] In at least one embodiment, GPU 3692 includes, but is not limited to, any number and type of system interconnects that facilitate data and control transfers between any number and type of directly or indirectly linked components, either internally or externally to GPU 3692. In at least one embodiment, GPU 3692 includes, but is not limited to, any number and type of I / O interfaces (e.g., PCIe) coupled to any number and type of peripheral devices. In at least one embodiment, GPU 3692 may include, but is not limited to, any number (including zero) of display engines and any number (including zero) of multimedia engines. In at least one embodiment, GPU 3692 implements a memory subsystem that includes, but is not limited to, any number and type of memory controllers (e.g., memory controller 3870 and system memory controller 3882) and memory devices dedicated to a component or shared among multiple components (e.g., shared memory 3860). In at least one embodiment, GPU3692 implements a cache subsystem that includes, but is not limited to, one or more cache memories (e.g., L2 cache 3822), each cache memory being either private or shared among any number of components (e.g., SIMD unit 3850, compute unit 3840, and programmable processing unit 3820).

[0346] In at least one embodiment, Figure 38 The system described herein is used to detect and / or predict (e.g., within a multi-GPU system) signals conducted by signal conductors, and employs various algorithms, formulas, and / or processes (e.g., combining...) Figure 1-8 Those described herein) transition signal conductors between active and inactive states, and / or otherwise perform the operations described herein. In at least one embodiment, Figure 38 The one or more systems described herein are used to implement one or more systems and / or processes, such as in combination. Figures 1-8 Those described.

[0347] Figure 39 This illustrates how threads of an exemplary CUDA grid 3920, according to at least one embodiment, are mapped to... Figure 38 Different computational units 3840. In at least one embodiment, and for illustrative purposes only, grid 3920 has a GridSize of BX multiplied by BY multiplied by 1 and a BlockSize of TX multiplied by TY multiplied by 1. Therefore, in at least one embodiment, grid 3920 includes, but is not limited to, (BX * BY) thread blocks 3930, each thread block 3930 including, but not limited to, (TX * TY) threads 3940. Threads 3940 in Figure 39 It is depicted as a curved arrow.

[0348] In at least one embodiment, grid 3920 is mapped to programmable processing unit 3820(1), which includes, but is not limited to, computing units 3840(1)-3840(C). In at least one embodiment, and as shown, (BJ * BY) thread block 3930 is mapped to computing unit 3840(1), and the remaining thread blocks 3930 are mapped to computing unit 3840(2). In at least one embodiment, each thread block 3930 may include, but is not limited to, any number of thread bundles, and each thread bundle is mapped to... Figure 38 Different SIMD units 3850.

[0349] In at least one embodiment, the thread bundles in a given thread block 3930 can be synchronized together and communicate via shared memory 3860 included in the associated computing unit 3840. For example, and in at least one embodiment, the thread bundles in thread block 3930 (BJ, 1) can be synchronized together and communicate via shared memory 3860 (1). For example, and in at least one embodiment, the thread bundles in thread block 3930 (BJ + 1, 1) can be synchronized together and communicate via shared memory 3860 (2).

[0350] In at least one embodiment, Figure 39 The system described herein is used to detect and / or predict (e.g., within a multi-GPU system) signals conducted by signal conductors, and employs various algorithms, formulas, and / or processes (e.g., combining...) Figure 1-8 Those described herein) transition signal conductors between active and inactive states, and / or otherwise perform the operations described herein. In at least one embodiment, Figure 39The one or more systems described herein are used to implement one or more systems and / or processes, such as in combination. Figures 1-8 Those described.

[0351] Figure 40 This document illustrates how to migrate existing CUDA code to data-parallel C++ code according to at least one embodiment. Data-parallel C++ (DPC++) can refer to an open, standards-based alternative to a single-architecture proprietary language that allows developers to reuse code across hardware targets (CPUs and accelerators, such as GPUs and FPGAs) and also perform custom tweaks for specific accelerators. DPC++ uses similar and / or the same C and C++ constructs as ISO C++, which developers may be familiar with. DPC++ incorporates the Khronos Group's standard SYCL to support data parallelism and heterogeneous programming. SYCL stands for Cross-Platform Abstraction Layer, built on the underlying concepts, portability, and efficiency of OpenCL, enabling code for heterogeneous processors to be written in a "single-source" style using standard C++. SYCL enables single-source development, where C++ template functions can contain both host code and device code to build complex algorithms accelerated using OpenCL, and then reuse them throughout the source code for different types of data.

[0352] In at least one embodiment, a DPC++ compiler is used to compile DPC++ source code that can be deployed across various hardware targets. In at least one embodiment, the DPC++ compiler is used to generate DPC++ applications that can be deployed across various hardware targets, and DPC++ compatibility tools are used to migrate CUDA applications to multi-platform programs in DPC++. In at least one embodiment, the DPC++ basic toolkit includes: a DPC++ compiler for deploying applications across various hardware targets; DPC++ libraries for improving productivity and performance on CPUs, GPUs, and FPGAs; DPC++ compatibility tools for migrating CUDA applications to multi-platform applications; and any suitable combination thereof.

[0353] In at least one embodiment, the DPC++ programming model simplifies one or more aspects related to programming CPUs and accelerators by using modern C++ features to express parallelism with a programming language called Data Parallel C++. The DPC++ programming language can be used for code reuse against hosts (e.g., CPUs) and accelerators (e.g., GPUs or FPGAs) using a single-source language, and clearly communicates execution and memory dependencies. Mappings within the DPC++ code can be used to translate applications to run on the hardware or set of hardware devices that best accelerate workloads. Even on platforms without available accelerators, the host can be used to simplify the development and debugging of device code.

[0354] In at least one embodiment, CUDA source code 4000 is provided as input to the DPC++ compatibility tool 4002 to generate human-readable DPC++ 4004. In at least one embodiment, the human-readable DPC++ 4004 includes inline comments generated by the DPC++ compatibility tool 4002, which guide developers on how and / or where to modify the DPC++ code to complete the coding and tune it to the desired performance 4006, thereby generating DPC++ source code 4008.

[0355] In at least one embodiment, CUDA source code 4000 is or includes a collection of human-readable source code in the CUDA programming language. In at least one embodiment, CUDA source code 4000 is human-readable source code using the CUDA programming language. In at least one embodiment, the CUDA programming language is an extension of the C++ programming language, including but not limited to mechanisms for defining device code and distinguishing between device code and host code. In at least one embodiment, device code is source code that, after compilation, can be executed on a device (e.g., a GPU or FPGA) and may include one or more parallelizable workflows that can be executed on one or more processor cores of the device. In at least one embodiment, the device may be a processor optimized for parallel instruction processing, such as a CUDA-enabled GPU, GPU, or another GPGPU. In at least one embodiment, host code is source code that, after compilation, can be executed on a host machine. In at least one embodiment, some or all of the host code and device code can be executed in parallel across CPU and GPU / FPGA. In at least one embodiment, the host is a processor optimized for sequential instruction processing, such as a CPU. Figure 40 The CUDA source code 4000 described is consistent with what is discussed elsewhere in this document.

[0356] In at least one embodiment, DPC++ compatibility tool 4002 refers to an executable tool, program, application, or any other suitable type of tool for facilitating the migration of CUDA source code 4000 to DPC++ source code 4008. In at least one embodiment, DPC++ compatibility tool 4002 is a command-line based code migration tool that can be used as part of the DPC++ toolkit for porting existing CUDA sources to DPC++. In at least one embodiment, DPC++ compatibility tool 4002 converts some or all of the source code of a CUDA application from CUDA to DPC++ and generates a result file, at least partially written in DPC++, referred to as human-readable DPC++ 4004. In at least one embodiment, human-readable DPC++ 4004 includes comments generated by DPC++ compatibility tool 4002 to indicate where user intervention may be required. In at least one embodiment, user intervention is necessary when CUDA source code 4000 calls a CUDA API that does not have a DPC++ API; other examples requiring user intervention will be discussed in more detail later.

[0357] In at least one embodiment, the workflow for migrating CUDA source code 4000 (e.g., an application or a portion thereof) includes creating one or more build database files; migrating CUDA to DPC++ using DPC++ compatibility tool 4002; completing the migration and verifying its correctness to generate DPC++ source code 4008; and compiling DPC++ source code 4008 using the DPC++ compiler to generate a DPC++ application. In at least one embodiment, the compatibility tool provides a utility that intercepts commands used during Makefile execution and stores them in the build database files. In at least one embodiment, the files are stored in JSON format. In at least one embodiment, intercepted build commands translate Makefile commands into DPC compatibility commands.

[0358] In at least one embodiment, intercept-build is a utility script that intercepts the build process to capture build options, macro definitions, and include paths, and writes this data to a build database file. In at least one embodiment, the build database file is a JSON file. In at least one embodiment, the DPC++ compatibility tool 4002 parses the build database and applies options when migrating input sources. In at least one embodiment, the use of intercept-build is optional but strongly recommended for Make or CMake-based environments. In at least one embodiment, the migration database includes commands, directories, and files: commands may include necessary build flags; directories may include paths to header files; and files may include paths to CUDA files.

[0359] In at least one embodiment, the DPC++ compatibility tool 4002 migrates CUDA code (e.g., applications) written in CUDA to DPC++ by generating DPC++ as much as possible. In at least one embodiment, the DPC++ compatibility tool 4002 is available as part of a toolkit. In at least one embodiment, the DPC++ toolkit includes an intercept-build tool. In at least one embodiment, the intercept-build tool creates a build database that captures build commands to migrate CUDA files. In at least one embodiment, the DPC++ compatibility tool 4002 uses the build database generated by the intercept-build tool to migrate CUDA code to DPC++. In at least one embodiment, non-CUDA C++ code and files are migrated as is. In at least one embodiment, the DPC++ compatibility tool 4002 generates a human-readable DPC++ 4004, which may be DPC++ code, such as that generated by the DPC++ compatibility tool 4002, that cannot be compiled by the DPC++ compiler and requires additional pipelines to verify incorrectly migrated code portions, and may involve manual intervention, such as intervention by a developer. In at least one embodiment, the DPC++ compatibility tool 4002 provides hints or tools embedded in the code to help developers manually migrate additional code that cannot be migrated automatically. In at least one embodiment, the migration is a one-time activity for a source file, project, or application.

[0360] In at least one embodiment, the DPC++ compatibility tool 40002 is capable of successfully migrating all portions of CUDA code to DPC++, and can simply include optional steps for manually verifying and tuning the performance of the generated DPC++ source code. In at least one embodiment, the DPC++ compatibility tool 4002 directly generates DPC++ source code 4008 that is compiled by the DPC++ compiler, without requiring or utilizing manual intervention to modify the DPC++ code generated by the DPC++ compatibility tool 4002. In at least one embodiment, the DPC++ compatibility tool generates compilable DPC++ code that developers can selectively tune based on performance, readability, maintainability, and various other considerations, or any combination thereof.

[0361] In at least one embodiment, one or more CUDA source files are migrated to DPC++ source files, at least in part, using DPC++ compatibility tool 4002. In at least one embodiment, the CUDA source code includes one or more header files, which may include CUDA header files. In at least one embodiment, the CUDA source files include text that can be printed.<cuda.h> header files and<stdio.h> Header file. In at least one embodiment, a portion of the CUDA source file for the vector addition kernel may be written as or related to: #include<cuda.h> #include<stdio.h> #define VECTOR_SIZE 256 [] global__ void VectorAddKernel(float* A, float* B, float* C) { A[threadIdx.x] = threadIdx.x + 1.0f; B[threadIdx.x] = threadIdx.x + 1.0f; C[threadIdx.x] = A[threadIdx.x] + B[threadIdx.x]; } int main() { float *d_A, *d_B, *d_C; cudaMalloc(&d_A, VECTOR_SIZE*sizeof(float)); cudaMalloc(&d_B, VECTOR_SIZE*sizeof(float)); cudaMalloc(&d_C, VECTOR_SIZE*sizeof(float)); VectorAddKernel<<<1, VECTOR_SIZE>>>(d_A, d_B, d_C); float Result[VECTOR_SIZE] = {}; cudaMemcpy(Result, d_C, VECTOR_SIZE*sizeof(float),cudaMemcpyDeviceToHost); cudaFree(d_A); cudaFree(d_B); cudaFree(d_C); for (int i=0; i <VECTOR_SIZE; i++ { if (i % 16 == 0) { printf("\n"); } printf("%f ", Result[i]); } return 0; } In at least one embodiment, and in conjunction with the CUDA source files presented above, the DPC++ compatibility tool 4002 parses the CUDA source code and replaces the header files with appropriate DPC++ and SYCL header files. In at least one embodiment, the DPC++ header files include helper declarations. In CUDA, there is a concept of thread IDs; correspondingly, in DPC++ or SYCL, there is a local identifier for each element.

[0362] In at least one embodiment, and in relation to the CUDA source file presented above, there are two vectors A and B, which are initialized and the result of vector addition is placed into vector C as part of VectorAddKernel(). In at least one embodiment, as part of migrating CUDA code to DPC++ code, the DPC++ compatibility tool 4002 converts the CUDA thread ID used to index worker elements to the SYCL standard addressing of the worker elements via the local ID. In at least one embodiment, the DPC++ code generated by the DPC++ compatibility tool 4002 can be optimized—for example, by reducing the dimension of nd_item, thereby increasing memory and / or processor utilization.

[0363] In at least one embodiment, and in conjunction with the CUDA source files presented above, memory allocation is migrated. In at least one embodiment, relying on SYCL concepts such as platform, device, context, and queue, cudaMalloc() is migrated to a unified shared memory SYCL call malloc_device() to which the device and context are passed. In at least one embodiment, the SYCL platform may have multiple devices (e.g., host and GPU devices); a device may have multiple queues to which jobs can be submitted; each device may have a context; and a context may have multiple devices and manage shared memory objects.

[0364] In at least one embodiment, and in conjunction with the CUDA source files presented above, the `main()` function invokes or calls `VectorAddKernel()` to add two vectors A and B and store the result in vector C. In at least one embodiment, the CUDA code calling `VectorAddKernel()` is replaced by DPC++ code to submit the kernel to the command queue for execution. In at least one embodiment, the command group handler `cgh` passes the data submitted to the queue, synchronization, and computation, and `parallel_for` is called for multiple global elements and multiple work items in the workgroup that invoke `VectorAddKernel()`.

[0365] In at least one embodiment, and in conjunction with the CUDA source files presented above, CUDA calls to copy device memory and then free memory for vectors A, B, and C are migrated to corresponding DPC++ calls. In at least one embodiment, C++ code (e.g., standard ISO C++ code for printing vectors of floating-point variables) is migrated as is without modification by the DPC++ compatibility tool 4002. In at least one embodiment, the DPC++ compatibility tool 4002 modifies the CUDA API used for memory setup and / or host calls to execute the kernel on an accelerated device. In at least one embodiment, and in conjunction with the CUDA source files presented above, the corresponding human-readable DPC++4004 (e.g., compilable) is written as or related to: #include<CL / sycl.hpp> #include<dpct / dpct.hpp> #define VECTOR_SIZE 256 void VectorAddKernel(float* A, float* B, float* C, sycl::nd_item <3> item_ct1) { A[item_ct1.get_local_id(2)] = item_ct1.get_local_id(2) + 1.0f; B[item_ct1.get_local_id(2)] = item_ct1.get_local_id(2) + 1.0f; C[item_ct1.get_local_id(2)] = A[item_ct1.get_local_id(2)] + B[item_ct1.get_local_id(2)]; } int main() { float *d_A, *d_B, *d_C; d_A = (float *)sycl::malloc_device(VECTOR_SIZE * sizeof(float), dpct::get_current_device(), dpct::get_default_context()); d_B = (float *)sycl::malloc_device(VECTOR_SIZE * sizeof(float), dpct::get_current_device(), dpct::get_default_context()); d_C = (float *)sycl::malloc_device(VECTOR_SIZE * sizeof(float), dpct::get_current_device(), dpct::get_default_context()); dpct::get_default_queue_wait().submit([&](sycl::handler &cgh) { cgh.parallel_for( sycl::nd_range<3>(sycl::range<3>(1, 1, 1) * sycl::range<3>(1, 1, VECTOR_SIZE) * sycl::range<3>(1, 1, VECTOR_SIZE)), [=](sycl::nd_items<3> item_ct1) { VectorAddKernel(d_A, d_B, d_C, item_ct1); }); }); float Result[VECTOR_SIZE] = {}; dpct::get_default_queue_wait() .memcpy(Result, d_C, VECTOR_SIZE * sizeof(float)) .wait(); sycl::free(d_A, dpct::get_default_context()); sycl::free(d_B, dpct::get_default_context()); sycl::free(d_C, dpct::get_default_context()); for (int i=0; i<VECTOR_SIZE; i++ { if (i % 16 == 0) { printf("\n"); } printf("%f ", Result[i]); } return 0; } In at least one embodiment, human-readable DPC++ 4004 refers to the output generated by the DPC++ compatibility tool 4002 and can be optimized in one or another. In at least one embodiment, the human-readable DPC++ 4004 generated by the DPC++ compatibility tool 4002 can be manually edited by developers after migration to make it more maintainable, performant, or for other considerations. In at least one embodiment, the DPC++ code generated by the DPC++ compatibility tool 40002 (e.g., publicly available DPC++) can be optimized by removing duplicate calls to get_current_device() and / or get_default_context() for each malloc_device() call. In at least one embodiment, the DPC++ code generated above uses a 3D nd_range, which can be refactored to use only a single dimension, thereby reducing memory usage. In at least one embodiment, developers can manually edit the DPC++ code generated by the DPC++ compatibility tool 4002 to replace the use of unified shared memory with accessors. In at least one embodiment, the DPC++ compatibility tool 4002 has the option to change how it migrates CUDA code to DPC++ code. In at least one embodiment, the DPC++ compatibility tool 4002 is verbose because it uses a generic template to migrate CUDA code to DPC++ code, which is suitable for a wide range of situations.

[0366] In at least one embodiment, the CUDA to DPC++ migration workflow includes the following steps: preparing the migration using an intercept-build script; performing the migration of the CUDA project to DPC++ using the DPC++ compatibility tool 4002; reviewing and editing the source files of the migration to ensure their integrity and correctness; and compiling the final DPC++ code to generate the DPC++ application. In at least one embodiment, manual review of the DPC++ source code may be required in one or more scenarios, including but not limited to: the migrated API not returning error codes (CUDA code can return error codes that can subsequently be used by the application, but SYCL uses exceptions to report errors, therefore error codes are not used to expose errors); DPC++ does not support CUDA compute capability-related logic; statements cannot be deleted. In at least one embodiment, scenarios requiring manual intervention in the DPC++ code may include, but are not limited to: replacing error code logic with (*,0) code or commenting it out; equivalent DPC++ APIs being unavailable; CUDA compute capability-related logic; hardware-related APIs (clock()); APIs lacking unsupported features; performing time measurement logic; handling built-in vector type conflicts; migrating the cuBLAS API; and more.

[0367] In at least one embodiment, Figure 40 The system described herein is used to detect and / or predict (e.g., within a multi-GPU system) signals conducted by signal conductors, and employs various algorithms, formulas, and / or processes (e.g., combining...) Figure 1-8 Those described herein) transition signal conductors between acti...

Claims

1. An apparatus comprising one or more circuits, said one or more circuits being used to: Determine the delay for each of a plurality of queues, wherein the delay for a given queue is determined based on the depth of the given queue and the rate of flow leaving the given queue; A queue is selected from the plurality of queues for forwarding data packets, based at least in part on the determined delay of each queue. as well as The data packet is forwarded to the selected queue.

2. The device of claim 1, wherein the circuitry is further configured to: Receive data indicating the amount of data reduction in the corresponding queue; and The rate at which the flow leaves the corresponding queue is calculated using the data indicating the reduction amount.

3. The device of claim 2, wherein the circuitry is further configured to: calculate the rate of the flow leaving the corresponding queue by dividing the amount of data reduction by a time window.

4. The device of claim 2, wherein the circuitry is further configured to: calculate the rate of the flow leaving the corresponding queue by normalizing the amount of data reduction based on a time window.

5. The device of claim 2, wherein the circuitry is further configured to: determine the delay of the corresponding queue by right-shifting the depth of the corresponding queue to the logarithm of the rate of the flow leaving the corresponding queue to base 2.

6. The device of claim 1, wherein each of the plurality of queues is associated with an exit port.

7. The device of claim 1, wherein the queues in the plurality of queues are flow queues, and the one or more circuits are further configured to select a flow queue based on the determined delay of each queue.

8. The apparatus of claim 1, wherein the circuitry is further configured to: assign a level to each of the plurality of queues based on a determined delay, and use the level to select one of the queues.

9. The device of claim 8, wherein the level is selected by an adaptive routing circuit for the selection of the queue.

10. A dedicated integrated controller ASIC for: Determine the delay for each of a plurality of queues, wherein the delay for a given queue is determined based on the depth of the given queue and the rate of flow leaving the given queue; A queue is selected from the plurality of queues for forwarding data packets, based at least in part on the determined delay of each queue. as well as The data packet is forwarded to the selected queue.

11. The ASIC of claim 10, further configured to: Receive data indicating the amount of data reduction in the corresponding queue; and The rate at which the flow leaves the corresponding queue is calculated using the data indicating the reduction amount.

12. The ASIC of claim 11, further configured to: calculate the rate of the flow leaving the corresponding queue by dividing the amount of data reduction by a time window.

13. The ASIC of claim 11, further configured to: calculate the rate of the flow leaving the corresponding queue by normalizing the reduction in the amount of data based on a time window.

14. The ASIC of claim 11, further configured to: determine the delay of the corresponding queue by right-shifting the depth of the corresponding queue to the logarithm of the rate of the flow leaving the corresponding queue to base 2.

15. The ASIC of claim 10, wherein each of the plurality of queues is associated with an exit port.

16. The ASIC of claim 10, wherein the queues among the plurality of queues are flow queues, and the ASIC is further configured to select a flow queue based on the determined delay of each queue.

17. The ASIC of claim 10, further configured to: assign a level to each of the plurality of queues based on a determined delay, and use the level to select one of the queues.

18. The ASIC of claim 17, wherein the level is used by an adaptive routing circuit to select the queue.

19. A method comprising: Determine the delay for each of a plurality of queues, wherein the delay for a given queue is determined based on the depth of the given queue and the rate of flow leaving the given queue; A queue is selected from the plurality of queues for forwarding data packets, based at least in part on the determined delay of each queue. as well as The data packet is forwarded to the selected queue.

20. The method of claim 19, further comprising: Receive data indicating the amount of data reduction in the corresponding queue; as well as The rate at which the flow leaves the corresponding queue is calculated using the data indicating the reduction amount.

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