Address access method, device and equipment for on-chip interconnect request queue

Abstract

The application relates to the field of on-chip interconnection technology and discloses an address access method, device and equipment of an on-chip interconnection request queue. The address access method of the on-chip interconnection request queue provided by the application comprises the following steps: receiving first request information, and detecting whether there is an access conflict between the first request information and second request information in a first request entry queue; when the access conflict exists, an association relationship between the first request information and the second request information is established; a first request entry corresponding to the first request is set to a suspended state and added to a second request entry queue; and in response to the completion of processing of the second request entry, the suspended state of the first request entry is cleared to process the first request information. Through the association relationship between the requests and the suspended state management, the blocked request is directly located and woken up, the wake-up delay is reduced, the system concurrency capability is improved, and a request storm is avoided.

Description

Technical Field

[0001] This application relates to the field of on-chip interconnect technology, and specifically to an address access method, apparatus and device for an on-chip interconnect request queue. Background Technology

[0002] In related technologies, on-chip interconnect request queues typically employ entry blocking or return retry mechanisms when handling address conflicts. This prevents even non-conflicting requests from entering the system, reducing concurrency. In high-concurrency scenarios, repeated resending of requests can create request storms, increasing external traffic pressure. After the blocking source request completes, the entire request queue needs to be scanned to find the blocked request, resulting in complex wake-up logic, high latency, and high power consumption. It is also difficult to directly locate the blocked request, posing risks of processing delays and logical deadlocks. Summary of the Invention

[0003] This application provides a method, apparatus, and device for accessing the address of an on-chip interconnect request queue. It reduces wake-up latency, improves system concurrency, and avoids request storms.

[0004] In a first aspect, this application provides an address access method for an on-chip interconnect request queue. The method includes: receiving first request information and detecting whether there is an access conflict between the first request information and second request information in a first request entry queue, wherein the second request information is any request information corresponding to the first request entry queue, and the request entry is used to carry the corresponding request information; when there is an access conflict, establishing an association between the first request information and the second request information; setting the first request entry corresponding to the first request to a suspended state and adding it to the second request entry queue; wherein the first request entry queue is used to represent a request entry queue without access conflicts, and the second request entry queue is used to represent a request entry queue with access conflicts; in response to the completion of processing of the second request entry, clearing the suspended state of the first request entry and adding the first request entry to the first request entry queue.

[0005] The above technical solution avoids the problems of reduced system concurrency and surges in external traffic caused by traditional ingress blocking or invalid retries. Simultaneously, by establishing precise correlations, the complexity and high latency of full queue scanning are eliminated, enabling efficient and accurate wake-up of conflicting requests and providing a foundation for handling multi-level blocking relationships.

[0006] In one optional implementation, establishing the association between the first request information and the second request information includes: writing a request entry identifier corresponding to the first request entry into the second request entry corresponding to the second request.

[0007] According to the above technical solution, the first request entry that needs to be woken up can be directly located based on the pre-written request entry identifier, thus completely eliminating the reliance on scanning the entire queue. This simplifies the complexity of the wake-up logic and reduces the timing overhead and power consumption caused by scanning the entire queue.

[0008] In one optional implementation, a request entry identifier corresponding to the first request entry is written into the second request entry corresponding to the second request, including: allocating a first request entry to the first request information; setting attribute information corresponding to the first request information in the first request entry, wherein the attribute information includes a request entry identifier, request address information, security domain identifier, suspended state bit, executable flag bit, and wake-up association information; setting the suspended state bit and clearing the executable flag bit in the first request entry; and writing the request entry identifier into the wake-up association information in the second request entry.

[0009] Based on the above technical solution, this application provides underlying data support for achieving accurate blocking dependency records by refining the attribute configuration and state management mechanism of request entries. This solves the problems of wake-up delay and complex logical processing caused by the lack of accurate associated records in existing technologies, significantly improving wake-up efficiency and system response speed, and laying a solid foundation for handling multi-level blocking relationships.

[0010] In one optional implementation, in response to the completion of processing of the second request entry, the suspended state of the first request entry is cleared, including: reading the wake-up association information of the second request entry to determine the request entry identifier corresponding to the first request entry; locating the address of the first request entry corresponding to the request entry identifier based on the request entry identifier; setting the executable flag bit in the first request entry and clearing the suspended state bit.

[0011] Based on the above technical solution, the technical problem of how to quickly locate and resume suspended requests after processing preceding blocked requests is effectively solved. This achieves rapid wake-up of blocked requests, effectively resolving the high latency issue caused by the scanning mechanism, improving the overall processing efficiency and concurrency of the on-chip interconnect system, and thus optimizing system performance.

[0012] In an optional implementation, the method further includes: receiving third request information; detecting the comparison flag status of each request information in the request entry queue, wherein the comparison flag status is used to characterize whether the request entry corresponding to the request information has undergone access conflict comparison, and when access conflict comparison has been performed and an access conflict exists, the comparison flag status changes from an on state to a off state, and the request entry queue includes a first request entry queue and a second request entry queue; filtering out fourth request information with the comparison flag status in the on state and performing access conflict detection with the third request information; when an access conflict exists, obtaining the wake-up association information of the fourth request entry corresponding to the fourth request information; establishing an association relationship between the third request information and the fourth request information; setting the third request entry corresponding to the third request information to a suspended state and adding it to the second request entry queue; and in response to the completion of processing of the fourth request entry, clearing the suspended state of the third request entry and adding the third request entry to the first request entry queue.

[0013] Based on the above technical solution, precise tracking and management of the chained blocking relationships in the request queue are achieved. This avoids repeated scanning of the entire queue, effectively solves the processing latency problem caused by multi-level blocking through chained wake-up logic, reduces the probability of logical deadlock, and significantly improves the processing efficiency and system stability of the on-chip interconnect request queue in complex conflict scenarios.

[0014] In one optional implementation, detecting whether there is an access conflict between the first request information and the second request information in the first request entry queue includes: determining the first request entry and the second request entry corresponding to the first request information and the second request information respectively; comparing the attribute information in the first request entry and the second request entry; and determining that there is an access conflict between the first request information and the second request information when the request address information and the security domain identifier in the attribute information are the same.

[0015] Based on the above technical solution, this application can achieve refined judgment of on-chip interconnection request access conflicts. This reduces the false positive and false negative rates, avoiding reduced system concurrency and resource waste caused by false positives, and also avoiding the risk of data inconsistency caused by false negatives.

[0016] In an alternative implementation, the method further includes setting the first request entry to an executable state and adding it to the first request entry queue when there is no access conflict.

[0017] Based on the above technical solution, the admission and execution paths for normal requests are clearly defined, ensuring that the system can efficiently and smoothly schedule non-conflicting requests while handling conflicting requests. This effectively improves the overall throughput efficiency of the on-chip interconnect request queue and optimizes the utilization of system resources.

[0018] In one optional implementation, the response to the completion of processing of the second request entry includes at least one of the following: the completion of processing of the second request entry and execution of an entry exit event; the triggering of a cache replacement operation for the second request entry; the completion of a cache consistency maintenance interaction process for the second request entry; and the completion of a preset stage for data or response delivery for the second request entry.

[0019] Based on the above technical solution, this application provides detailed definitions for various specific scenarios in which the processing of the second request entry is completed, thereby providing a precise triggering time for waking up the first request entry. This allows the suspended first request entry to be woken up as soon as the conflict is truly resolved, thereby significantly reducing the waiting time of the request, improving the overall throughput and response speed of the on-chip interconnect system, and avoiding system instability or performance degradation that may result from inaccurate wake-up.

[0020] Secondly, this application provides an address access device for an on-chip interconnect request queue. The device includes: a receiving module, configured to receive first request information and detect whether there is an access conflict between the first request information and second request information in a first request entry queue, wherein the second request information is any request information corresponding to the first request entry queue; an association module, configured to establish an association relationship between the first request information and the second request information when an access conflict exists; an adding module, configured to set the first request entry corresponding to the first request to a suspended state and add it to the second request entry queue; wherein the first request entry queue is used to represent a queue of request entries without access conflicts, and the second request entry queue is used to represent a queue of request entries with access conflicts; and a setting module, configured to clear the suspended state of the first request entry and add the first request entry to the first request entry queue in response to the completion of processing of the second request entry.

[0021] Thirdly, this application provides an electronic device, including: a memory and a processor, which are communicatively connected to each other. The memory stores computer instructions, and the processor executes the computer instructions to perform the on-chip interconnect request queue address access method of the first aspect or any corresponding embodiment described above.

[0022] Fourthly, this application provides a computer-readable storage medium storing computer instructions for causing a computer to execute the on-chip interconnect request queue address access method of the first aspect or any corresponding embodiment thereof.

[0023] Fifthly, this application provides a computer program product, including computer instructions for causing a computer to execute the on-chip interconnect request queue address access method of the first aspect or any corresponding embodiment thereof. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0025] Figure 1 This is a schematic flowchart of a first method for accessing the address of an on-chip interconnect request queue according to an embodiment of this application. Figure 2 This is a second flowchart illustrating the address access method for an on-chip interconnect request queue according to an embodiment of this application; Figure 3 This is a schematic diagram of a third method for accessing the address of an on-chip interconnect request queue according to an embodiment of this application. Figure 4 This is an example diagram of an address access method for an on-chip interconnect request queue according to an embodiment of this application; Figure 5 This is a structural block diagram of an address access device for an on-chip interconnect request queue according to an embodiment of this application; Figure 6 This is a schematic diagram of the hardware structure of an electronic device according to an embodiment of this application. Detailed Implementation

[0026] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0027] It is understood that before using the technical solutions disclosed in the various embodiments of this application, users should be informed of the types, scope of use, and usage scenarios of the personal information involved in this application in an appropriate manner in accordance with relevant laws and regulations, and user authorization should be obtained.

[0028] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0029] This application proposes an address access method for an on-chip interconnect request queue, such as... Figure 1 As shown, the method includes: Step S101: Receive first request information and detect whether there is an access conflict between the first request information and the second request information in the first request entry queue. The second request information is any request information corresponding to the first request entry queue, and the request entry is used to carry the corresponding request information.

[0030] Step S102: When an access conflict exists, establish an association between the first request information and the second request information.

[0031] Step S103: Set the first request entry corresponding to the first request to a suspended state and add it to the second request entry queue; wherein, the first request entry queue is used to represent the request entry queue without access conflict, and the second request entry queue is used to represent the request entry queue with access conflict.

[0032] In step S104, in response to the completion of processing of the second request entry, the pending state of the first request entry is cleared, and the first request entry is added to the first request entry queue.

[0033] For ease of understanding, the following explains some key terms in this embodiment: The on-chip interconnect request queue is used to store and manage various requests transmitted in the on-chip interconnect system. These requests may include memory access, peripheral access, etc., and their processing order and efficiency directly affect the overall system performance.

[0034] Request information refers to all the data and metadata contained in a specific request, such as the request address, data length, operation type (read / write), security domain identifier, priority, etc. Request information is the basis for the system's processing and judgment.

[0035] A request entry is the carrier of request information in a queue. It is usually a data structure used to store request information and its related status, identifiers, and other control information. Each request is assigned one request entry.

[0036] The first request entry queue represents the set of request entries that currently do not have access conflicts. Request entries in the queue are typically in an executable state, awaiting scheduling and processing.

[0037] The second request entry queue represents the set of request entries currently experiencing access conflicts. Request entries in this queue are typically suspended, waiting for their blocking source requests to complete processing.

[0038] Access conflict refers to a situation where two or more requests accessing the same resource, such as the same memory address, cannot be processed simultaneously due to operation type, such as read-write conflict, or security permissions.

[0039] A relationship is a logical connection established between conflicting request information when access conflicts exist. This connection is used to indicate which request was blocked by which request, so that the blocked request can be accurately woken up after the blocking source request completes.

[0040] A pending state refers to a request entry that does not yet meet the conditions for execution. Request entries in the pending state will not be selected for execution by the scheduler until their pending state is cleared.

[0041] Processing complete means that the request information carried by a request entry has completed all its scheduled operations, including data transmission, status update, resource release, etc., and no longer blocks other requests.

[0042] This application provides a method for accessing the address of an on-chip interconnect request queue, the specific implementation of which is as follows: First, a first request message is received, and it is checked whether there is an access conflict between this first request message and a second request message in the first request entry queue. Specifically, a request receiving module is configured to receive a request from the on-chip interconnect network and encapsulate the request as a first request message. Subsequently, a conflict detection unit is configured to compare the first request message with any existing second request message in the current first request entry queue. For example, the detection can be based on parameters such as the address range of the request, the operation type (e.g., read / write conflict), and security domain identifier. As another implementation, the detection can also use a hash table or lookup table to quickly determine whether there is a potential conflict.

[0043] Furthermore, when an access conflict is detected, an association is established between the first request information and the second request information. This association is intended to explicitly indicate that the first request information is blocked by the second request information. For example, this can be achieved by maintaining a mapping table internally, which records the correspondence between blocked requests and blocked requests. Alternatively, a pointer or reference to the blocked request entry can be set in the request entry corresponding to the second request information to establish a logical connection between the two.

[0044] Based on this, the first request entry corresponding to the first request is set to a suspended state and added to the second request entry queue. Specifically, when the first request information is detected to have an access conflict with the second request information and an association is established, the request entry corresponding to the first request information is marked as non-executable. For example, a status bit in the request entry can be set to indicate that it is in a suspended state. Subsequently, the first request entry in the suspended state is removed from or not added to the first request entry queue, but is instead added to the second request entry queue, which is specifically used to store conflicting requests. Request entries in the second request entry queue will wait for their blocking source request to be processed.

[0045] Finally, in response to the completion of processing the second request entry, the suspended state of the first request entry is cleared, allowing processing of the first request information. Specifically, when the request information carried by the second request entry is processed and exits the system, the system identifies the first request entry that was blocked by it based on previously established associations. For example, the identifier of the blocked first request entry can be obtained by querying a previously maintained mapping table. Once the first request entry is identified, its suspended state is cleared, making it executable. Thus, the first request entry can be re-added to the first request entry queue or directly selected by the scheduler for subsequent processing of the first request information it carries.

[0046] It is understood that the on-chip interconnect request queue address access method proposed in this application achieves fine-grained management of conflicting requests by introducing a suspension and wake-up mechanism based on association relationships. This method avoids the problems of reduced system concurrency and surges in external traffic caused by traditional entry blocking or invalid retries. At the same time, by establishing precise association relationships, it eliminates the complexity and high latency of full queue scanning, achieves efficient and accurate wake-up of conflicting requests, and provides a foundation for handling multi-level blocking relationships.

[0047] In some embodiments, this application further proposes an address access method for an on-chip interconnect request queue, such as... Figure 2 As shown, the method includes: Step S201: Receive the first request information and check whether there is an access conflict between the first request information and the second request information in the first request entry queue. See details. Figure 1 Step S101 in the embodiment will not be described again here.

[0048] Step S202: When an access conflict exists, establish an association between the first request information and the second request information. Specifically, this includes: Step S2021: Write the request entry identifier corresponding to the first request entry into the second request entry corresponding to the second request.

[0049] Specifically, the second request entry corresponding to the second request refers to the specific data structure or storage unit in the on-chip interconnect request queue that carries the second request information. The second request entry represents the request currently being processed or causing a conflict. It not only contains attribute information such as the address and security domain of the second request itself, but is also designed to record relevant information about the first request that conflicts with it and is suspended. Its implementation may include, but is not limited to: a specific storage unit in the request queue, allocated to the second request and containing multiple fields, one of which is specifically used to store associated information; or, a separate register group or memory region, associated with the second request through pointers or indexes, used to store the detailed status and associated information of the second request.

[0050] Writing the request entry identifier corresponding to the first request entry means storing a unique identifier representing the first request entry into the second request entry. The request entry identifier is information used to uniquely identify a request entry in the queue, such as an index value, an address pointer, or a unique label. By writing this identifier, after the second request is processed, the system can directly and quickly locate the first request entry that was blocked by it, thereby achieving precise wake-up. The implementation methods may include, but are not limited to: directly writing the physical index or logical address of the first request entry in the request queue into a reserved association information field within the second request entry; for example, if the request queue is an array, writing the index of the first request entry in the array; or assigning a globally unique ID to each request entry and writing the ID of the first request entry into the association field of the second request entry; or setting a pointer to the first request entry in the second request entry, which stores the starting address of the first request entry in memory.

[0051] Step S203: Set the first request entry corresponding to the first request to a pending state and add it to the second request entry queue. See details... Figure 1 Step S103 in the embodiment will not be described again here.

[0052] Step S204: In response to the completion of processing the second request entry, the pending state of the first request entry is cleared, and the first request entry is added to the first request entry queue. See details. Figure 1 Step S104 in the embodiment will not be described again here.

[0053] Understandably, through the above technical solution, when the system detects an access conflict between the first and second request information, it no longer simply suspends the first request entry. Instead, it establishes an explicit, point-to-point dependency by directly writing the request entry identifier corresponding to the first request entry into the second request entry corresponding to the second request. This allows the system to directly locate the first request entry that needs to be woken up based on the pre-written request entry identifier after the second request entry is processed, thus completely eliminating the dependence on scanning the entire queue. This simplifies the complexity of the wake-up logic and reduces the timing overhead and power consumption caused by scanning the entire queue.

[0054] In some embodiments, this application further proposes a specific implementation method for writing a request entry identifier corresponding to the first request entry into the second request entry corresponding to the second request, which includes the following steps: Step a1: Allocate a first request entry to the first request information. A first request entry is a storage unit or data structure used to carry the first request information. Allocating this entry means reserving and initializing a dedicated storage space in the system for newly arrived request information that needs processing. Specifically, this allocation process can be implemented by selecting an available entry from a free register set in the hardware or a unit in SRAM (Static Random Access Memory) and marking it as occupied; alternatively, it can be implemented by using a software-managed data structure, such as a linked list or array, to obtain a free request entry object from a preset request entry pool and bind it to the first request information.

[0055] Step a2: Set the attribute information corresponding to the first request information in the first request entry. The attribute information includes a request entry identifier, request address information, security domain identifier, suspended status bit, executable flag bit, and wake-up association information. The attribute information is a set of key metadata describing the first request entry and the first request information it carries. Its setting aims to comprehensively record the characteristics, status, and dependencies of the request with other requests, providing necessary data support for subsequent conflict detection, status management, and wake-up operations. The request entry identifier is a unique index number or hash value that identifies the first request entry. For example, it can be a fixed-width integer serving as the index of the entry in the request queue array, or a unique ID automatically generated by the hardware. The request address information indicates the memory address or resource address that the first request information needs to access. For example, it can directly store the physical or virtual address of the request, or store the start address and length of an address range. The security domain identifier is used to identify the security context or permission level to which the first request information belongs. For example, it can be a bit field representing different security levels, or an index pointing to a security policy table. The suspended status bit is a Boolean flag indicating whether the first request entry is suspended. For example, it can be a single-bit register where 1 indicates suspended and 0 indicates not suspended. The executable flag is a Boolean flag indicating whether the first request entry can be scheduled for execution. For example, it can be a single-bit register where 1 indicates executable and 0 indicates not executable. The wake-up association information stores information related to the first request entry used to wake up other blocked requests, or information indicating which request blocked the request. This could be, for example, a request entry identifier pointing to the second request entry blocking the first request entry, or a linked list head pointer pointing to all other request entries blocked by the first request entry.

[0056] Step a3 involves setting the pending status bit and clearing the executable flag bit in the first request entry. When an access conflict is detected, setting the pending status bit explicitly marks the request as "blocked," preventing it from being processed immediately. Simultaneously, clearing the executable flag bit prevents the request from being selected for execution by the scheduler at the scheduling level, thus ensuring proper conflict handling and avoiding data inconsistency or system errors. This operation can be performed by writing specific values ​​to the status register corresponding to the first request entry, for example, by directly modifying the corresponding bits in the register using bit manipulation instructions; or at the software level, by updating the corresponding Boolean variables or enumeration values ​​in the first request entry data structure, and then the hardware logic controls request scheduling based on the values ​​of these variables.

[0057] Step a4: Write the request entry identifier into the wake-up association information of the second request entry. By recording the unique identifier of the blocked request (first request entry) in the blocking source (second request entry), the system can directly locate and wake up the blocked request through this identifier after the blocking source has finished processing, without performing a global scan. This write operation can directly store the request entry identifier (e.g., its index number) of the first request entry into the reserved wake-up association information field in the second request entry data structure; or, if the wake-up association information supports storing multiple identifiers, the first request entry identifier can be added to the linked list or array maintained by the wake-up association information of the second request entry.

[0058] It is understood that, through the above technical solution, this application provides underlying data support for achieving accurate blocking dependency records by refining the attribute configuration and state management mechanism of request entries. This solves the problems of wake-up delay and complex logical processing caused by the lack of accurate associated records in existing technologies, significantly improving wake-up efficiency and system response speed, and laying a solid foundation for handling multi-level blocking relationships.

[0059] In some embodiments, this application further proposes an address access method for an on-chip interconnect request queue, such as... Figure 3 As shown, the method includes: Step S301: Receive the first request information and check whether there is an access conflict between the first request information and the second request information in the first request entry queue. See details... Figure 1 Step S101 in the embodiment will not be described again here.

[0060] Step S302: When an access conflict exists, establish an association between the first request information and the second request information. Specifically, this includes: Step S3021: Write the request entry identifier corresponding to the first request entry into the second request entry corresponding to the second request. See details. Figure 3 Step S2021 in the embodiment will not be repeated here.

[0061] Step S303: Set the first request entry corresponding to the first request to a pending state and add it to the second request entry queue. See details. Figure 1 Step S103 in the embodiment will not be described again here.

[0062] Step S304: In response to the completion of processing the second request entry, the pending state of the first request entry is cleared, and the first request entry is added to the first request entry queue. Specifically, this includes: Step S3041: Read the wake-up association information of the second request entry to determine the request entry identifier corresponding to the first request entry.

[0063] Step S3042: Based on the request entry identifier, locate the address of the first request entry corresponding to the request entry identifier.

[0064] Step S3043: Set the executable flag in the first request entry and clear the pending status bit.

[0065] Specifically, wake-up association information is one or a set of data fields stored in the second request entry. Its function is to directly record or point to the identifier of the first request entry that has an access conflict with the second request entry and is therefore suspended. When the second request entry is processed, the system accesses the storage unit corresponding to the second request entry and reads the preset wake-up association information field therein, thereby directly obtaining the request entry identifier corresponding to the suspended first request entry. For example, the wake-up association information can be a register field storing one or more request entry identifiers; or it can be a pointer to a linked list or array storing multiple request entry identifiers, through which all associated request entry identifiers can be retrieved. This direct read mechanism avoids scanning the entire request queue, significantly improving wake-up efficiency.

[0066] The request entry identifier is a unique identifier for the first request entry, serving to provide a fast and accurate index for locating the physical storage location of that request entry within the storage system. Specifically, the request entry identifier can be used as an index to query a pre-built mapping table, such as a hash table, lookup table, or content-addressable memory, which stores the correspondence between request entry identifiers and their specific addressing addresses in the queue storage structure. Furthermore, if request entries are organized in storage space according to a specific pattern, such as contiguous allocation, the request entry identifier can also be combined with a base address. Through simple arithmetic operations, such as adding the identifier to the base address and multiplying by the entry size, the addressing address of the first request entry can be directly calculated. In this way, the system can accurately locate the first request entry that needs to be woken up, ensuring the accuracy of subsequent operations.

[0067] The executable flag and suspended status bits are key status indicators in the first request entry, used to control its scheduling and execution flow in the on-chip interconnect system. Setting the executable flag indicates that the first request entry has been resumed from the suspended state and is marked as eligible for selection and execution by the scheduler. Clearing the suspended status bits explicitly indicates that the request is no longer waiting for a blocking source to complete. In implementation, this can be accomplished by writing to the status register or memory unit corresponding to the first request entry; for example, setting the bit corresponding to the executable flag to logic "1" and the bit corresponding to the suspended status bit to logic "0". In hardware design, specific control logic or a state machine can also trigger atomic update operations on these flag bits after receiving a wake-up signal and locating the first request entry, thereby ensuring the immediacy and consistency of state transitions.

[0068] It is understood that, through the above technical solution, this application provides an efficient and accurate request wake-up mechanism, effectively solving the technical problem of how to quickly locate and resume suspended requests after processing preceding blocked requests. It achieves rapid wake-up of blocked requests, effectively solving the high latency problem caused by the scanning mechanism, improving the overall processing efficiency and concurrency of the on-chip interconnect system, thereby optimizing system performance.

[0069] In some of the solutions mentioned above in this application, address conflicts are handled by establishing associations between requests. However, when dealing with multi-level blocking relationships, if a subsequent request conflicts with an already blocked request again, the existing solutions lack effective management of such chain-like dependencies, making it impossible to directly establish a multi-level blocking chain. This causes the wake-up of subsequent requests to rely on complex global scanning or multiple triggers, increasing processing latency and posing a risk of logical deadlock.

[0070] In response, this application further proposes an address access method for an on-chip interconnect request queue, which further includes: Step b1: Receive the third request information.

[0071] The on-chip interconnect continuously sends out various resource access requests. The receiving module continuously monitors the bus, cross switch interface and other channels, captures newly arrived third request information, assigns an independent third request entry to the third request information, completes the encapsulation of attribute information such as request address, security domain identifier, operation type, priority and other attributes, and sends it to the conflict detection preprocessing unit to wait for conflict comparison logic processing.

[0072] Step b2: Detect the comparison flag status of each request information in the request entry queue. The comparison flag status is used to indicate whether the request entry corresponding to the request information has been compared for access conflict. When an access conflict has been compared and an access conflict exists, the comparison flag status changes from the open state to the closed state. The request entry queue includes a first request entry queue and a second request entry queue.

[0073] The system traverses all active request entries globally, covering the first request entry queue storing executable requests and the second request entry queue storing suspended and blocked requests. It reads the comparison flag bit configured inside each request entry one by one. This flag bit is a hardware single-bit status register, which is set to the enabled state by default after power-on and after the entry is allocated, indicating that the entry has not yet completed a conflict comparison with a newly arrived request. If a request entry has previously completed a conflict detection with other requests and determined that there is an address access conflict, the hardware automatically latches the comparison flag bit of the entry to the disabled state, marking that the entry does not need to participate in the conflict comparison of this third request, thereby reducing the hardware comparator timing overhead caused by repeated comparisons and reducing dynamic power consumption.

[0074] Step b3: Filter out the fourth request information whose comparison flag is enabled and perform access conflict detection with the third request information.

[0075] All historical conflict entries with the comparison flags off are filtered out, and only the fourth request information corresponding to the fourth request entry with the flags on is extracted and sent to the dedicated address conflict comparison unit in parallel. The comparison unit simultaneously extracts the request address information and security domain identifier from the third and fourth request entries, and completes the equality judgment through parallel comparison logic, thereby narrowing the scope of conflict comparison, avoiding repeated traversal of invalid entries in the entire queue, and significantly shortening the pipeline latency of a single conflict detection.

[0076] Step b4: When an access conflict exists, obtain the wake-up association information of the fourth request entry corresponding to the fourth request information.

[0077] If the address information and security domain identifier match perfectly, it is determined that the third request and the fourth request have a resource access conflict. Then, the reserved wake-up association information storage field inside the fourth request entry is located, and all blocked request entry identifiers, entry addressing indexes, chain blocking list pointers and other dependent metadata recorded in the field are read. The blocking source dependency relationship of the current fourth request itself is traced, providing underlying data support for building a multi-level chain blocking link.

[0078] Step b5: Establish the association between the third request information and the fourth request information.

[0079] Step b6: Set the third request entry corresponding to the third request information to a pending state and add it to the second request entry queue.

[0080] Write the globally unique request entry identifier of the third request entry to the end of the wake-up association information linked list of the fourth request entry to build a point-to-point blocking dependency association; synchronously perform a state rewrite operation on the third request entry: clear the suspended state bit of the entry to 1 and the executable flag bit to 0, and prevent the scheduler from selecting the entry to participate in pipeline execution; then remove the third request entry with the updated state from the waiting scheduling path and store it in a second request entry queue that is specially stored for blocking suspended requests for management, without occupying the normal scheduling resources of the first request entry queue, and ensuring that conflict-free requests are continuously processed in parallel.

[0081] Step b7: In response to the completion of processing of the fourth request entry, the pending state of the third request entry is cleared, and the third request entry is added to the queue of the first request entries.

[0082] When the fourth request entry triggers any one of the following processing completion events: entry exit event, cache replacement, cache consistency interaction completion, or data response delivery completion, the wake-up control unit reads the third request entry identifier stored in the wake-up association information of the fourth request entry and directly indexes and addresses the storage location of the third request entry through the identifier; performs state reversal on the third request entry: clears the suspended state bit, sets the executable flag bit, and removes the blocking restriction; finally, the third request entry that has been restored to the executable state is migrated to the first request entry queue and handed over to the scheduling unit for normal scheduling into the on-chip interconnect processing pipeline.

[0083] This approach is understandable. By introducing a comparison flag, the system can quickly filter requests to be compared, avoiding duplicate conflict detection across the entire queue and reducing the timing pressure and power consumption of the hardware comparison circuit. Simultaneously, a multi-level chained blocking link is built based on the wake-up association information of the fourth request entry, enabling precise dependency binding of multi-layered nested conflicting requests. Once the upstream blocked request is processed, the system can directly locate and wake up the downstream suspended request without globally scanning the queue. This effectively solves the wake-up delay and logical deadlock risks caused by multi-level blocking in scenarios with multiple requests accessing the same address, further improving the throughput performance and operational stability of the on-chip interconnect request queue in high-concurrency, multi-conflict scenarios.

[0084] In some embodiments, this application further proposes a method for detecting whether there is an access conflict between the first request information and the second request information in the first request entry queue, the method comprising: Step c1: Determine the first request entry and the second request entry corresponding to the first request information and the second request information, respectively.

[0085] Step c2: Compare the attribute information in the first request entry and the second request entry.

[0086] Step c3: When the request address information and security domain identifier in the attribute information are the same, it is determined that there is an access conflict between the first request information and the second request information.

[0087] Specifically, when detecting whether there is an access conflict between the first request information and the second request information in the first request entry queue, it is first necessary to determine the first request entry and the second request entry corresponding to the first request information and the second request information, respectively. This aims to ensure that the comparison operation can be applied to the correct and complete request data structure. In one implementation, the system can maintain a mapping table from request information to request entries, such as a hash table or lookup table. When the first request information is received, its corresponding first request entry is quickly located by querying this mapping table. For the second request information in the first request entry queue, the system can traverse the queue and perform the same lookup operation for each second request information to obtain its corresponding second request entry.

[0088] Subsequently, the attribute information in the first and second request entries is compared. Attribute information is a set of data contained in a request entry that describes the characteristics of the request; its completeness and accuracy directly affect the effectiveness of conflict determination. In one embodiment, the system can be designed with a dedicated comparison logic unit that receives two request entries as input and compares their respective attribute fields one by one. For example, the request address information can be compared first, followed by the security domain identifier, or multiple key attributes can be compared simultaneously.

[0089] Ultimately, when the requested address information and security domain identifier in the attribute information are the same, an access conflict is determined between the first and second request information. This clarifies the precise definition of an access conflict. In hardware implementation, the requested address information and security domain identifier can be compared in parallel using combinational logic gates. For example, two independent comparators can be used to compare the address information and security domain identifier separately, and then the outputs of the two comparators can be connected through an AND gate. The AND gate only outputs a "conflict exists" signal when both comparators output "equal" signals.

[0090] It is understood that, through the above technical solution, this application can achieve refined judgment of on-chip interconnection request access conflicts. This reduces the false positive rate and false negative rate, avoids the reduction in system concurrency and resource waste caused by false positives, and also avoids the risk of data inconsistency caused by false negatives.

[0091] In some embodiments, this application proposes an address access method for an on-chip interconnect request queue, the method further comprising: Step d1: When there is no access conflict, set the first request entry to the executable state and add it to the first request entry queue.

[0092] Specifically, in an on-chip interconnect system, multiple requests may simultaneously access the same address resource, thus triggering an access conflict. The purpose of this conditional judgment is to distinguish between conflicting requests requiring special handling (such as suspension) and non-conflicting requests that can be executed immediately. For example, by comparing the request address information and security domain identifier corresponding to the first and second request information, if both are different, it is determined that there is no access conflict. If the resource is not locked and the arbitrator allows access, it is considered that there is no access conflict.

[0093] "Setting the first request entry to an executable state" means marking the request entry as an internal state indicating that it is ready to be selected and executed by the scheduler without waiting for other conditions. This ensures that the system can efficiently identify and process requests that can be executed immediately. For example, a dedicated "executable flag" can be set within the first request entry, and this flag is set when the request entry is determined to be executable.

[0094] "Adding to the first request entry queue" means adding the first request entry, which has been set to the executable state, to a queue used to store request entries without access conflicts. Adding the first request entry to this queue signifies that the request entry has passed conflict detection and has been deemed by the system to be eligible for normal scheduling and execution. For example, a first-in, first-out (FIFO) queue can be used; once a request entry is set to the executable state, its tail is inserted into the first request entry queue, and the scheduler retrieves the request from the head of the queue for processing. Considering that different requests may have different priorities, the first request entry queue can also be implemented as a priority queue. When adding a request entry, it is inserted into the appropriate position in the queue according to its priority, ensuring that high-priority requests are scheduled first.

[0095] It is understandable that the above technical solution clarifies the admission and execution paths of normal requests, ensuring that the system can efficiently and smoothly schedule non-conflicting requests while handling conflicting requests. This effectively improves the overall throughput efficiency of the on-chip interconnect request queue and optimizes the utilization of system resources.

[0096] In some embodiments, this application further proposes a response to the completion of processing of a second request entry, including at least one of the following: completion processing of the second request entry and execution of an entry exit event; triggering a cache replacement operation for the second request entry; the second request entry completing a cache consistency maintenance interaction process; and a preset stage for the second request entry completing data or response delivery.

[0097] Specifically, when the second request entry completes processing and executes an entry exit event, it means that the request represented by the second request entry has completed all its predetermined operations in the on-chip interconnect system, and the entry has been formally removed from the request queue or related processing unit, or its resources have been released. For example, in one implementation, after completing the data transmission, calculation, or status update of the request corresponding to the second request entry, the request processing unit sends a "complete" signal to the request queue management module. This signal carries a unique identifier for the second request entry. Upon receiving this signal, the request queue management module marks the entry as exitable and performs the corresponding resource release operation, such as reclaiming the storage space occupied by the entry, and triggers the wake-up of the associated first request entry in this exit event. In another implementation, an "exit stage" or "completion stage" is set at the end of the request processing pipeline. When the request data corresponding to the second request entry flows through this stage and successfully completes all operations, such as writing data to the target address and sending a response signal, the control logic of this stage automatically generates an entry exit event. This event not only cleans up the state of the entry in the pipeline, but also checks whether the entry is associated with any pending first-request entries. If so, it immediately triggers the wake-up of these pending entries.

[0098] When a second request entry triggers a cache replacement operation, it means that the request corresponding to the second request entry causes a data block in the system cache to be replaced out of the cache. This serves as the trigger condition for waking up suspended requests. For example, in one implementation, in the cache controller, when a cache line needs to be replaced due to data updates or prefetching caused by a write or read operation corresponding to the second request entry, the cache controller checks whether the cache line to be replaced has an address conflict with any suspended first request entries while performing the replacement operation. Once it is confirmed that the replacement operation has been completed and that the operation has resolved potential address conflicts, the associated first request entry is woken up.

[0099] When the second request entry completes the cache consistency maintenance interaction process, in a multi-core or multi-processor system, it means that the request corresponding to the second request entry involves shared data and has completed all necessary cache consistency protocol interactions, ensuring the data's consistent state across all relevant caches. This serves as the trigger condition for waking up the suspended request. For example, in one implementation, in the cache consistency controller, when the request corresponding to the second request entry, such as a write operation, needs to acquire exclusive or modify permissions for a shared cache line, a consistency protocol interaction is initiated. Once all relevant caches have responded and confirmed the state update, the consistency controller generates a "consistency maintenance complete" signal. This signal indicates that the data state of the shared address has stabilized, at which point the waking up of the first request entry suspended due to the address conflict can be triggered.

[0100] When the second request entry completes a preset stage of data or response delivery, it means that the request corresponding to the second request entry has reached a pre-defined critical stage during data transmission or response generation. At this point, it can be considered that its occupation of shared resources or its impact on address conflicts has been resolved, thereby triggering the waking of the suspended request. For example, in one implementation, for a write request, the preset stage could be that the data has been successfully written to the target memory or cache, and a write completion signal has been sent. For a read request, the preset stage could be that the requested data has been read from the memory or cache and has begun to be sent to the request source, or that the response header information has been sent. In the data path or response generation module, when it detects that the data or response stream has reached this preset critical point, a "stage completion" event is triggered, thereby waking up the associated first request entry.

[0101] It is understood that, through the above technical solution, this application has refined the definition of various specific scenarios in which the processing of the second request entry is completed, thereby providing a precise triggering time for waking up the first request entry, so that the suspended first request entry can be woken up as soon as the conflict is truly resolved, thereby significantly reducing the waiting time of the request, improving the overall throughput and response speed of the on-chip interconnect system, and avoiding system instability or performance degradation that may be caused by inaccurate wake-up.

[0102] In one example, such as Figure 4 As shown, the above technical solution will be explained in more detail through a more specific example: In an on-chip interconnect system, a request queue manager handles memory access requests from various initiators, such as multiple processor cores and direct memory access (DMA) controllers. This manager maintains two main queues: a first request entry queue for currently executable request entries without access conflicts; and a second request entry queue for request entries suspended due to access conflicts. Each request entry contains attribute information such as a request entry identifier, request address information, security domain identifier, suspended status bit, executable flag bit, and wake-up association information.

[0103] Receiving New Requests and Detecting Conflicts: Suppose the system receives a new first request, for example, a write request to address A. The request queue manager first allocates a first request entry for this first request. Then, the manager checks whether there is an access conflict between this first request and existing second request entries in the first request entry queue, such as a read request to address A. Specifically, the manager compares the attribute information in the first and second request entries. If their request address information and security domain identifier are identical, an access conflict is determined.

[0104] Establishing an association and suspending: When an access conflict is detected between the first request and the second request, the system will not immediately reject the first request or require it to retry. Instead, it will establish an association between the two. Specifically, in the wake-up association information field of the second request entry corresponding to the second request, the request entry identifier corresponding to the first request entry is written. At the same time, the suspended status bit in the first request entry is set, and its executable flag is cleared, indicating that the request cannot be executed temporarily. Subsequently, the first request entry is removed from the first request entry queue and added to the second request entry queue.

[0105] This avoids the problems of reduced system concurrency and surges in external traffic caused by entry blocking or return retry signals in existing technologies. Even if there is a conflict between the first request and the second request, the system allows the first request to enter the queue and establish a connection, instead of simply rejecting or forcing a retransmission, thereby improving the system's concurrent processing capabilities.

[0106] Wake-up upon completion of the second request: Assume that after a period of time, the second request entry completes its processing, for example, a data read operation completes and an entry exit event is executed. In response to the completion of the second request entry's processing, the system clears the suspended state of the first request entry. Specifically, the system reads the wake-up association information in the second request entry to determine the request entry identifier corresponding to the first request entry that was blocked by it. Based on this request entry identifier, the system can accurately locate the address of the first request entry. Subsequently, the executable flag in the first request entry is set, and its suspended state bit is cleared. At this point, the first request entry becomes executable and can be scheduled for processing.

[0107] This avoids the complexity, high latency, and high power consumption issues of existing technologies that require scanning the entire request queue to find blocked requests. The system eliminates the need for a global scan, significantly reducing the complexity of the wake-up logic, the length of the timing path, and power consumption, while also reducing wake-up latency.

[0108] Receiving a third request and detecting conflicts: Suppose that while the first request entry is still pending, the system receives a new third request, for example, a read request for address A. The manager checks whether this third request conflicts with requests in the request entry queue where the comparison flag is enabled. Suppose the detection result shows that the third request conflicts with the first request, for example, the request address information and security domain identifier are the same.

[0109] Establishing multi-level associations and suspending requests: When an access conflict exists, the system establishes an association between the third request information and the first request information, that is, it writes the request entry identifier corresponding to the third request entry into the wake-up association information of the first request entry. Subsequently, the third request entry corresponding to the third request is set to a suspended state and added to the second request entry queue.

[0110] This mechanism can accurately record and transmit multi-level dependencies. For example, the second request blocks the first request, and the first request blocks the third request. This solves the problem that existing technologies have difficulty in handling multi-level blocking relationships and avoids the risks of processing delays and logical deadlocks.

[0111] When the first request entry is processed, the system reads the wake-up association information from the first request entry to determine the request entry identifier corresponding to the third request entry that was blocked by it. Based on this identifier, the system locates the address of the third request entry and clears the suspended state of the third request entry, making it executable, thereby processing the third request information.

[0112] Handling of conflict-free requests: Assuming the system receives a new request and detects that it does not conflict with any other request in the first request queue, the system sets the corresponding request entry to an executable state and adds it directly to the first request queue, awaiting scheduling and execution.

[0113] It is understandable that this method effectively avoids the problems of entry point blocking, reduced high concurrency, and surges in external traffic in existing technologies by establishing precise inter-request relationships when access conflicts are detected and suspending conflicting requests and moving them to a dedicated queue. Simultaneously, by utilizing association information for direct location and wake-up, the complexity, latency, and power consumption of the wake-up logic are significantly reduced, and multi-level blocking relationships can be flexibly handled, thereby improving the overall processing efficiency of the on-chip interconnect request queue and system performance.

[0114] This embodiment also provides an address access device for an on-chip interconnect request queue, which is used to implement the above embodiments and preferred embodiments; details already described will not be repeated. As used below, the term "module" can be a combination of software and / or hardware that implements a predetermined function. Although the device described in the following embodiments is preferably implemented in software, hardware implementation, or a combination of software and hardware, is also possible and contemplated.

[0115] This embodiment provides an address access device for an on-chip interconnect request queue, such as... Figure 5 As shown, it includes: The receiving module 501 is used to receive first request information and detect whether there is an access conflict between the first request information and the second request information in the first request entry queue, wherein the second request information is any request information corresponding to the first request entry queue; The association module 502 is used to establish an association relationship between the first request information and the second request information when an access conflict exists; The addition module 503 is used to set the first request entry corresponding to the first request to a suspended state and add it to the second request entry queue; wherein, the first request entry queue is used to represent the request entry queue without access conflict, and the second request entry queue is used to represent the request entry queue with access conflict. The setting module 504 is used to clear the pending state of the first request entry and add the first request entry to the first request entry queue in response to the completion of the processing of the second request entry.

[0116] In some alternative implementations, the association module 502 includes: The first unit writes the request entry identifier corresponding to the first request entry into the second request entry corresponding to the second request.

[0117] The on-chip interconnect request queue address access device provided in this application embodiment can execute the on-chip interconnect request queue address access method provided in any embodiment of this application, and has the corresponding functional modules and beneficial effects for executing the method. Further functional descriptions of the above modules and units are the same as those in the corresponding embodiments described above, and will not be repeated here.

[0118] Figure 6 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application.

[0119] The following is a detailed reference. Figure 6 This diagram illustrates a suitable structural schematic for implementing the electronic device described in the embodiments of this application. The electronic device may include a processor (e.g., a central processing unit, graphics processor, etc.) 601, which can perform various appropriate actions and processes according to a program stored in read-only memory (ROM) 602 or a program loaded from memory 608 into random access memory (RAM) 603. The RAM 603 also stores various programs and data required for the operation of the electronic device. The processor 601, ROM 602, and RAM 603 are interconnected via a bus 604. An input / output (I / O) interface 605 is also connected to the bus 604.

[0120] Typically, the following devices can be connected to I / O interface 605: input devices 606 including, for example, touchscreens, touchpads, keyboards, mice, cameras, microphones, accelerometers, gyroscopes, etc.; output devices 607 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; memory devices 608 including, for example, magnetic tapes, hard disks, etc.; and communication devices 609. Communication device 609 allows electronic devices to communicate wirelessly or wiredly with other devices to exchange data. Although Figure 6 Electronic devices with various devices are shown, but it should be understood that it is not required to implement or have all of the devices shown, and more or fewer devices may be implemented or have instead.

[0121] Specifically, according to embodiments of this application, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments of this application include a computer program product comprising a computer program carried on a non-transitory computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via communication device 609, or installed from memory 608, or installed from ROM 602. When the computer program is executed by processor 601, it performs the functions defined in the address access method for the on-chip interconnect request queue of embodiments of this application.

[0122] Figure 6 The electronic device shown is merely an example and should not impose any limitation on the functionality and scope of use of the embodiments of this application.

[0123] This application also provides a computer-readable storage medium. The methods described in this application can be implemented in hardware or firmware, or implemented as recordable on a storage medium, or implemented as computer code downloaded over a network and originally stored on a remote storage medium or a non-transitory machine-readable storage medium and then stored on a local storage medium. Thus, the methods described herein can be processed by software stored on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. The storage medium can be a magnetic disk, optical disk, read-only memory, random access memory, flash memory, hard disk, or solid-state drive, etc.; further, the storage medium can also include combinations of the above types of memory. It is understood that computers, processors, microprocessor controllers, or programmable hardware include storage components capable of storing or receiving software or computer code. When the software or computer code is accessed and executed by the computer, processor, or hardware, the on-chip interconnect request queue address access method shown in the above embodiments is implemented.

[0124] A portion of this application can be applied as a computer program product, such as computer program instructions, which, when executed by a computer, can invoke or provide the methods and / or technical solutions according to this application through the operation of the computer. Those skilled in the art will understand that the forms in which computer program instructions exist in a computer-readable medium include, but are not limited to, source files, executable files, installation package files, etc. Correspondingly, the ways in which computer program instructions are executed by a computer include, but are not limited to: the computer directly executing the instructions, or the computer compiling the instructions and then executing the corresponding compiled program, or the computer reading and executing the instructions, or the computer reading and installing the instructions and then executing the corresponding installed program. Here, the computer-readable medium can be any available computer-readable storage medium or communication medium accessible to a computer.

[0125] Although embodiments of this application have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of this application, and all such modifications and variations fall within the scope defined by the appended claims.

Claims

1. A method for accessing the address of an on-chip interconnect request queue, characterized in that, The method includes: Receive first request information and detect whether there is an access conflict between the first request information and the second request information in the first request entry queue, wherein the second request information is any request information corresponding to the first request entry queue, and the request entry is used to carry the corresponding request information; When an access conflict exists, establish an association between the first request information and the second request information; Set the first request entry corresponding to the first request to a suspended state and add it to the second request entry queue; wherein, the first request entry queue is used to represent the request entry queue without access conflict, and the second request entry queue is used to represent the request entry queue with access conflict. In response to the completion of processing of the second request entry, the pending state of the first request entry is cleared, and the first request entry is added to the first request entry queue.

2. The method according to claim 1, characterized in that, Establishing the association between the first request information and the second request information includes: Write the request entry identifier corresponding to the first request entry into the second request entry corresponding to the second request.

3. The method according to claim 2, characterized in that, The step of writing the request entry identifier corresponding to the first request entry into the second request entry corresponding to the second request includes: Assign the first request entry to the first request information; In the first request entry, attribute information corresponding to the first request information is set, wherein the attribute information includes request entry identifier, request address information, security domain identifier, suspended status bit, executable flag bit, and wake-up association information; Set the suspended status bit in the first request entry and clear the executable flag bit; Write the request entry identifier into the wake-up association information in the second request entry.

4. The method according to claim 1, characterized in that, The step of clearing the pending state of the first request entry in response to the completion of processing the second request entry includes: Read the wake-up association information of the second request entry to determine the request entry identifier corresponding to the first request entry; Based on the request entry identifier, locate the address of the first request entry corresponding to the request entry identifier; Set the executable flag in the first request entry to the specified value and clear the pending status flag.

5. The method according to claim 1, characterized in that, The method further includes; Receive third-party request information; The comparison flag status of each request information in the request entry queue is detected. The comparison flag status is used to indicate whether the request entry corresponding to the request information has been compared for access conflict. When an access conflict has been compared and an access conflict exists, the comparison flag status changes from the open state to the closed state. The request entry queue includes the first request entry queue and the second request entry queue. The fourth request information with the comparison flag set to "on" is selected and access conflict detection is performed on it together with the third request information. When an access conflict exists, obtain the wake-up association information of the fourth request entry corresponding to the fourth request information; Establish the association between the third request information and the fourth request information; Set the third request entry corresponding to the third request information to a suspended state and add it to the second request entry queue; In response to the completion of processing of the fourth request entry, the pending state of the third request entry is cleared, and the third request entry is added to the first request entry queue.

6. The method according to claim 1, characterized in that, The step of detecting whether there is an access conflict between the first request information and the second request information in the first request entry queue includes: Determine the first request entry and the second request entry corresponding to the first request information and the second request information, respectively; Compare the attribute information in the first request entry and the second request entry; When the request address information and security domain identifier in the attribute information are the same, it is determined that there is an access conflict between the first request information and the second request information.

7. The method according to claim 1, characterized in that, The method further includes: When there is no access conflict, the first request entry is set to the executable state and added to the first request entry queue.

8. The method according to claim 1, characterized in that, The response to the completion of processing of the second request entry includes at least one of the following: The second request entry is completed and the entry exit event is executed; The second request entry triggers a cache replacement operation; The second request entry completes the cache consistency maintenance interaction process; The second request item completes the preset stage of data or response delivery.

9. An address access device for an on-chip interconnect request queue, characterized in that, The device includes: The receiving module is used to receive first request information and detect whether there is an access conflict between the first request information and second request information in the first request entry queue, wherein the second request information is any request information corresponding to the first request entry queue; The association module is used to establish an association between the first request information and the second request information when an access conflict exists; An adding module is used to set the first request entry corresponding to the first request to a suspended state and add it to the second request entry queue; wherein, the first request entry queue is used to represent the request entry queue without access conflict, and the second request entry queue is used to represent the request entry queue with access conflict. The setting module is used to clear the pending state of the first request entry and add the first request entry to the first request entry queue in response to the completion of processing of the second request entry.

10. An electronic device, characterized in that, include: A memory and a processor are communicatively connected, the memory storing computer instructions, and the processor executing the computer instructions to perform the address access method of the on-chip interconnect request queue as described in any one of claims 1 to 8.

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