Pse switch, power supply control method and pse mainboard

Abstract

This invention provides a PSE switch, a power supply control method, and a PSE motherboard, relating to the field of switch technology. The switch includes a PSE motherboard and a primary power supply. The PSE motherboard includes at least one PSE port and at least one positive power supply switch. The positive power supply terminal of the at least one PSE port is correspondingly connected to the at least one positive power supply switch, and each positive power supply switch is connected to the output terminal of the primary power supply. The on / off state of the positive power supply switch controls the output state of the corresponding PSE port's positive power supply terminal. The PSE motherboard is used to determine the device type connected to each PSE port based on detection signals. Based on the device type connected to each PSE port, the output state of the positive power supply terminal, and the output state of the negative power supply terminal, the power supply control result of each PSE port for the connected device is determined. This invention avoids on-site engineering problems caused by mutual power supply when PSE switches are cascaded and the problem of PSE port CE test exceeding the standard.

Description

Technical Field

[0001] This invention relates to the field of switch technology, and more particularly to a PSE switch, a power supply control method, and a PSE motherboard. Background Technology

[0002] A PSE (Power Sourcing Equipment) switch is a switch that provides both network communication and power to PDs (Power Devices). Current PSE switches typically integrate a primary power supply and a PSE motherboard. The primary power supply provides the first stage of power (PSE+ / GND) to the PSE motherboard. The PE (Protective Earthing) wire at the primary power input is usually connected to a metal chassis via metal screws. The PSE motherboard's reference ground is the primary power output ground, i.e., GND (Ground). However, the motherboard may also be secured to the metal chassis with metal screws, resulting in the PE wire and GND being at the same potential. Currently, when multiple PSE switches are cascaded, and the first PSE switch is powered on, adjacent PSE switches connected via network cables supply power to each other, causing problems in the engineering field.

[0003] In related technologies, a capacitor is typically used to bridge the PSE motherboard reference ground and the screw holes in the metal chassis within the PSE switch, creating unequal potentials between the PE line and GND. This disconnects the power supply circuit in the aforementioned field problem, preventing the first PSE switch from supplying power to other PSE switches and thus avoiding the field issue. However, in these PSE switches, primary power supply interference can couple to the output, causing the CE (Conduction Emission) test of the PSE port to exceed the limit. Therefore, how to simultaneously solve both the field problem and the issue of excessive CE (Conduction Emission) test results at the PSE port is a pressing technical challenge. Summary of the Invention

[0004] This invention provides a PSE switch, a power supply control method, and a PSE motherboard to solve the deficiencies in related technologies, such as engineering field problems and PSE port CE test exceeding standards.

[0005] This invention provides a PSE switch, including: a PSE motherboard and a primary power supply.

[0006] The PSE motherboard includes at least one PSE port and at least one positive power supply switch. The positive power supply terminal of the at least one PSE port is connected to the at least one positive power supply switch, and each positive power supply switch is connected to the output terminal of the primary power supply. The on / off state of the positive power supply switch is used to control the output state of the corresponding PSE port's positive power supply terminal.

[0007] The PSE motherboard is used to determine the type of device connected to each PSE port based on the detection signal; and to determine the power supply control result of each PSE port to the connected device based on the type of device connected to each PSE port, the output state of the positive power supply and the output state of the negative power supply.

[0008] According to the PSE switch provided by the present invention, the PSE motherboard determines the power supply control result of each PSE port to the connected device based on the device type connected to each PSE port, the output state of the positive power supply terminal, and the output state of the negative power supply terminal, including: For each of the PSE ports, if the device type connected to the PSE port is a powered device, and the output states corresponding to the positive and negative power supplies are both in the power supply state, then the power supply control result of the PSE port for the connected device is determined to be power supply.

[0009] According to the PSE switch provided by the present invention, the first terminal of the positive power supply switch is used to receive a first control signal, the first control signal being used to control the on / off state of the positive power supply switch; the second terminal of the positive power supply switch is connected to the output terminal of the primary power supply; the third terminal of the positive power supply switch is connected to the positive power supply terminal of the corresponding PSE port, the negative terminal of the diode, and the first terminal of the capacitor; the positive terminal of the diode is connected to the negative power supply terminal of the corresponding PSE port and the second terminal of the capacitor.

[0010] According to the PSE switch provided by the present invention, the PSE motherboard further includes a PSE control chip, which is used to control the output state of the negative power supply terminal of each PSE port.

[0011] According to the PSE switch provided by the present invention, the PSE control chip includes a microcontroller unit and a negative power supply switch, wherein: The microcontroller is connected to the first terminal of the negative power supply switch. The first terminal of the negative power supply switch is used to receive a second control signal sent by the microcontroller. The second control signal is used to control the on / off state of the negative power supply switch. The second terminal of the negative power supply switch is connected to the negative power supply terminal of the corresponding PSE port. The third terminal of the negative power supply switch is grounded.

[0012] According to the PSE switch provided by the present invention, when the positive power supply switch is disposed in the PSE control chip, the first end of the positive power supply switch is connected to the microcontroller unit, and the first end of the positive power supply switch is used to receive the first control signal sent by the microcontroller unit. When the positive power supply switch is located outside the PSE control chip, the first end of the positive power supply switch is connected to the processor in the PSE motherboard, and the first end of the positive power supply switch is used to receive the first control signal sent by the processor.

[0013] The present invention also provides a power supply control method applied to a PSE switch as described in any of the above claims, the method comprising the following steps.

[0014] Determine the output status of the positive and negative power supply terminals corresponding to each PSE port.

[0015] The type of device connected to each PSE port is determined based on the detection signal.

[0016] Based on the device type connected to each PSE port, the output status of the positive power supply terminal, and the output status of the negative power supply terminal, the power supply control result of each PSE port for the connected device is determined.

[0017] The present invention also provides a PSE motherboard, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the power supply control method as described above.

[0018] The present invention also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the power supply control method as described above.

[0019] The present invention also provides a computer program product, including a computer program that, when executed by a processor, implements the power supply control method as described above.

[0020] The PSE switch, power supply control method, and PSE motherboard provided by this invention include a positive power supply switch connected to each PSE port within the PSE motherboard. The on / off state of each positive power supply switch controls the output state of the positive power supply terminal of each PSE port. The PSE motherboard determines the device type connected to each PSE port based on detection signals, and further determines the power supply control result for each PSE port to the connected device based on the device type, the output state of the positive power supply terminal, and the output state of the negative power supply terminal. In this invention, by using the device type connected to the PSE port, the output state of the positive power supply terminal, and the output state of the negative power supply terminal, it determines whether the PSE protocol or PoE protocol is met, thereby providing power to connected devices that meet the PSE or PoE protocol. This avoids on-site engineering problems caused by mutual power supply when PSE switches are cascaded. Furthermore, by setting a positive power supply switch to control the output state of the positive power supply terminal of the PSE port, the PSE motherboard does not require separate grounding design, thus avoiding the problem of PSE port CE test exceeding the limit. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in this invention or related technologies, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is one of the schematic diagrams of PSE switch cascading provided by related technologies.

[0023] Figure 2 This is the second schematic diagram of PSE switch cascading provided by related technologies.

[0024] Figure 3 This is a schematic diagram of the CE test results for the PSE port provided by the relevant technology.

[0025] Figure 4 This is a schematic diagram of the structure of the PSE switch provided in an embodiment of the present invention.

[0026] Figure 5 This is a schematic diagram of the PoE protocol power supply process provided in an embodiment of the present invention.

[0027] Figure 6 This is a schematic diagram of the structure of the PSE motherboard provided in an embodiment of the present invention.

[0028] Figure 7 This is a schematic diagram of the PSE motherboard structure when the positive power supply switch is external, as provided in an embodiment of the present invention.

[0029] Figure 8This is a schematic diagram of PSE switch cascading provided in an embodiment of the present invention.

[0030] Figure 9 This is a schematic diagram of the CE test results of the PSE port provided in an embodiment of the present invention.

[0031] Figure 10 This is a flowchart illustrating the power supply control method provided in an embodiment of the present invention.

[0032] Figure 11 This is a schematic diagram of the structure of the PSE motherboard provided in an embodiment of the present invention.

[0033] Figure label: 100: PSE motherboard; 110: PSE port; 120: PSE control chip; 121: Microcontroller unit; 200: Primary power supply. Detailed Implementation

[0034] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0035] When multiple PSE (Power Sourcing Equipment) switches are cascaded, and the first PSE switch is powered on, adjacent PSE switches connected via network cables will supply power to each other, causing problems in the engineering field. Taking two cascaded PSE switches as an example... Figure 1 This is one of the schematic diagrams of PSE switch cascading provided by related technologies, such as... Figure 1 As shown, switch 1 and switch 2 are cascaded.

[0036] (1) Switch 1 is powered on, and switch 2 is not powered on. After switch 1 and switch 2 are connected by a network cable, the positive terminal PSE+ of the primary power output in switch 1 is connected to the PSE port of the PSE motherboard in switch 1. The network cable transmits PSE+ to the PSE motherboard in switch 2. Since both switches are connected to the PE end at the same time, there is a voltage difference between the PSE motherboard and the PE end of switch 2 equal to the primary power output voltage. That is, switch 1 supplies power to switch 2. If switch 2 is connected to an external PD (Power Device), there is a supply voltage of 44V to 57V between PSE+ and PSE- in switch 2, and switch 2 can supply power to the connected power device. If switch 2 is connected to a low-voltage power supply device, the high supply voltage in switch 2 may cause the interface connected to the low-voltage power supply device to fail due to overvoltage.

[0037] (2) When switch 1 is connected to switch 2 and all PSE ports of switch 2 are connected to powered devices, the power of switch 2 is the output power of the primary power supply in switch 1. At this time, the current in the network cable of the two cascaded switches is too large, which will burn out the network cable.

[0038] (3) When all PSE ports of both switches are connected to loads, the output power of the primary power supply in switch 1 is insufficient, causing all loads to lose power.

[0039] (4) When two switches are powered on simultaneously and all PSE ports of both switches are connected to loads, the primary power supplies of the two switches may have inconsistent output voltages. Since all subsequent loads are powered by the primary power supply with the higher output voltage, the primary power supply with the lower output voltage will be protected, and the corresponding switch load will lose power. Even if the primary power supplies of the two switches are not from the same supplier, the primary power supply with the lower output voltage may be damaged.

[0040] Figure 2 This is the second diagram illustrating the cascading of PSE switches provided by relevant technologies, such as... Figure 2 As shown, in the relevant technology, by adding a capacitor between the PSE motherboard reference ground and the screw holes of the metal chassis, a voltage difference exists between the PSE+ and GND terminals, meaning that the PE terminal and the GND (Ground) terminal are not at the same potential. Since the capacitor acts as a AC-passing and DC-blocking device, the circuit between the PSE motherboard in switch 2 and the primary power supply in switch 1 is disconnected. Therefore, when the primary power supply in switch 2 is not powered on, there is no voltage difference between the PSE port and GND terminal, or between the PSE port and PE terminal in switch 2. As a result, switch 2 cannot supply power to the connected powered devices, thus avoiding the aforementioned engineering field problems.

[0041] However, since most primary power supplies are outsourced components, and certification typically only performs Conduction Emission (CE) testing on the input, neglecting the output, and to reduce costs, filtering is rarely implemented at the output, interference from the primary power supply couples to the output. Because the positive terminal (PSE+) of the output is directly connected to the PSE port, interference at the primary power supply output is detected during CE testing at the PSE port. Furthermore, if the output filtering is ineffective, the CE test results at the PSE port may exceed the limits. Figure 3 This is a schematic diagram of the CE test results for the PSE port provided by the relevant technology provider, such as... Figure 3 As shown, when performing CE testing on the PSE port, the actual tested QP (Quasi-Peak) exceeded the QP limit in the 225kHz to 600kHz frequency band, and the actual tested AV (Average) exceeded the AV limit in the 225kHz to 2MHz frequency band.

[0042] Optionally, the powered device can be an IPC (IP Camera, network camera) or other powered device. Non-powered devices may include low-voltage power supply devices such as RS232 interface devices and RS485 interface devices, as well as PSE switches, etc., but this embodiment of the invention does not limit them.

[0043] Therefore, in response to the engineering field problems and the issue of PSE port 110 exceeding CE test standards in the aforementioned related technologies, this invention provides a PSE switch. Figure 4 This is a schematic diagram of the structure of the PSE switch provided in an embodiment of the present invention, as shown below. Figure 4 As shown, the PSE switch includes: a PSE motherboard 100 and a primary power supply 200, wherein: The PSE motherboard 100 includes at least one PSE port 110 and at least one positive power supply switch Q2. The positive power supply PSE+ of the at least one PSE port 110 is connected to the at least one positive power supply switch Q2. Each positive power supply switch Q2 is connected to the output terminal of the primary power supply 200. The on / off state of the positive power supply switch Q2 is used to control the output state of the corresponding positive power supply PSE+ of the PSE port 110. The PSE motherboard 100 is used to determine the type of device connected to each PSE port 110 based on the detection signal; and to determine the power supply control result of each PSE port 110 to the connected device based on the type of device connected to each PSE port 110, the output state of the positive power supply PSE+ and the output state of the negative power supply PSE-.

[0044] Specifically, in the PSE motherboard 100, the positive power supply terminal PSE+ of each PSE port 110 is connected to a corresponding positive power supply switch Q2. The on / off state of each positive power supply switch Q2 determines the output state of the positive power supply terminal PSE+ of the PSE port 110. For example, when the positive power supply switch Q2 is in the on state, the positive power supply terminal PSE+ of the corresponding PSE port 110 is in a powered state; conversely, when the positive power supply switch Q2 is in the off state, the positive power supply terminal PSE+ of the corresponding PSE port 110 is in a powered-off state. Each positive power supply switch Q2 is connected to the positive output terminal of the primary power supply 200, which supplies power to the connected devices corresponding to each PSE port 110 through each positive power supply switch Q2 and the corresponding positive power supply terminal PSE+ of the PSE port 110. Therefore, the output state of each PSE port 110 determines whether to supply power to the connected device. That is, the output state of the positive power supply terminal PSE+ and the output state of the negative power supply terminal PSE- of each PSE port 110 initially determines whether to supply power to the connected device.

[0045] In addition, each PSE port 110 needs to meet the PSE protocol or POE (Power Over Ethernet) protocol when outputting. That is, each PSE port 110 needs to meet the requirements of detection, classification, power supply and power failure when working normally. Figure 5 This is a schematic diagram of the PoE protocol power supply process provided in an embodiment of the present invention, as shown below. Figure 5 As shown.

[0046] (1) During the detection phase, the connected devices on each PSE port 110 can be detected based on the detection signal to determine the device type, which includes powered devices or non-powered devices. The detection signal can be a voltage signal in the range of 2V to 10V. During detection, the PSE switch outputs two different voltage values ​​with a voltage interval of more than 1V. The current values ​​corresponding to the two different voltage values ​​are detected. The voltage change value between the two different voltage values ​​and the current change value between the two different current values ​​are calculated respectively, and the ratio of the voltage change value to the current change value is calculated. The device type of the connected device is determined by this ratio.

[0047] (2) After detecting that the connected device is a powered device, the PSE switch enters the classification phase. The PSE switch continues to output a probe signal with a voltage range of 15.5V-20.5V, and the current limit of this probe signal is below 100mA. The powered device includes a classification resistor. After the powered device is connected to PSE port 110, this classification resistor is connected in series in the line. This classification resistor is used to identify the power requirements of the powered device. The PSE switch can determine the power consumption level of the connected powered device by measuring the magnitude of the returned characteristic current, thereby adjusting the output power of the corresponding PSE port 110 and saving energy. The duration of this classification phase is generally 10ms to 75ms.

[0048] (3) After detection and classification are completed, the power supply phase begins. During a configurable startup period (generally less than 15μs), the PSE switch supplies power to the powered device. The output voltage gradually increases from a low voltage until the supplied output voltage is within the range of 44V to 57V. That is, during the power supply phase, the voltage between the positive power supply terminal PSE+ and the negative power supply terminal PSE- of the PSE port 110 connected to the powered device in the PSE switch is within the range of 44V to 57V. In addition, the PSE switch can monitor the power supply status of each PSE port 110 and provide undervoltage protection and overcurrent protection.

[0049] (4) During the power outage phase, after the powered device is disconnected from the network, the PSE switch will quickly stop supplying power and repeat the detection phase to detect whether the powered device is connected on the network cable.

[0050] Therefore, after determining the output status of the positive power supply PSE+ and the negative power supply PSE- of each PSE port 110, the PSE motherboard 100 also needs to detect the type of device connected to the PSE port 110 to determine whether the PSE protocol or the PoE protocol is satisfied. If the PSE protocol or the PoE protocol is satisfied, the power supply control result of the PSE port 110 to the connected device is determined to be power supply, that is, the PSE port 110 supplies power to the connected device. If the PSE protocol or the PoE protocol is not satisfied, the power supply control result of the PSE port 110 to the connected device is determined to be power off, that is, the PSE port 110 does not supply power to the connected device.

[0051] Furthermore, the PSE motherboard 100 determines the power supply control result of each PSE port 110 for the connected device based on the device type connected to each PSE port 110, the output state of the positive power supply PSE+, and the output state of the negative power supply PSE-, including: For each of the PSE ports 110, if the device type connected to the PSE port 110 is a powered device, and the output states corresponding to the positive power supply PSE+ and the negative power supply PSE- are both in the power supply state, the power supply control result of the PSE port 110 for the connected device is determined to be power supply.

[0052] Specifically, for each PSE port 110 of the PSE switch, only when the device connected to PSE port 110 is a powered device, and the output states of the positive power supply PSE+ and negative power supply PSE- are in a powered state, does it indicate that the PSE port 110 of the PSE switch meets the PSE protocol or PoE protocol. In this case, the power supply control result of the PSE port 110 for the connected device is "power supply," that is, the PSE switch supplies power to the connected powered device through the PSE port 110. If at least one of the above three conditions is not met, it indicates that the PSE port 110 of the PSE switch does not meet the PSE protocol or PoE protocol. In this case, the power supply control result of the PSE port 110 for the connected device is "power off," that is, the PSE switch will not supply power to the connected device through the PSE port 110. For example, if the device connected to PSE port 110 is a non-powered device, PSE port 110 does not meet the PSE protocol or PoE protocol. In this case, the output states of the positive power supply PSE+ and the negative power supply PSE- of PSE port 110 are different. That is, if the output state of the positive power supply PSE+ of PSE port 110 is the power supply state, then the output state of the negative power supply PSE- of PSE port 110 is the power off state. Conversely, if the output state of the positive power supply PSE+ of PSE port 110 is the power off state, then the output state of the negative power supply PSE- of PSE port 110 is the power supply state, thus avoiding power supply to the powered device.

[0053] Furthermore, the first terminal of the positive power supply switch Q2 is used to receive a first control signal, which is used to control the on / off state of the positive power supply switch Q2; the second terminal of the positive power supply switch Q2 is connected to the output terminal of the primary power supply 200; the third terminal of the positive power supply switch Q2 is connected to the positive power supply PSE+ corresponding to the PSE port 110, the negative terminal of the diode, and the first terminal of the capacitor; the positive terminal of the diode is connected to the negative power supply PSE- corresponding to the PSE port 110 and the second terminal of the capacitor.

[0054] For example, the positive power supply switch Q2 can be a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). The first terminal of the positive power supply switch Q2 can be the gate of the MOSFET, the second terminal can be the drain of the MOSFET, and the third terminal can be the source of the MOSFET. The level of the first control signal determines the on / off state of the positive power supply switch Q2. That is, when the first control signal received at the gate of the positive power supply switch Q2 is a high-level signal, the positive power supply switch Q2 is in the on state, thereby supplying power to the positive terminal PSE+ of the connected PSE port 110. When the first control signal received at the gate of the positive power supply switch Q2 is a low-level signal, the positive power supply switch Q2 is in the off state, thereby de-energizing the positive terminal PSE+ of the connected PSE port 110.

[0055] Furthermore, Figure 6 This is a schematic diagram of the structure of the PSE motherboard provided in an embodiment of the present invention, as shown below. Figure 6 As shown, the PSE motherboard 100 also includes a PSE control chip 120, which is used to control the output state of the negative power supply terminal PSE- of each PSE port 110.

[0056] Furthermore, such as Figure 6 As shown, the PSE control chip 120 includes a microcontroller unit 121 and a negative power supply switch Q1, wherein: The microcontroller unit 121 is connected to the first terminal of the negative power supply switch Q1. The first terminal of the negative power supply switch Q1 is used to receive the second control signal sent by the microcontroller unit 121. The second control signal is used to control the on / off state of the negative power supply switch Q1. The second terminal of the negative power supply switch Q1 is connected to the negative power supply terminal PSE- corresponding to the PSE port 110. The third terminal of the negative power supply switch Q1 is grounded.

[0057] It should be noted that each PSE control chip 120 includes at least two PSE ports 110, that is, there is a one-to-many correspondence between each PSE control chip 120 and each PSE port 110. The PSE motherboard 100 includes at least one PSE control chip 120, and the number of PSE control chips 120 included in the PSE motherboard 100 depends on the number of PSE ports 110 included in each PSE control chip 120.

[0058] For example, the negative power supply switch Q1 can be a MOSFET. The first terminal of the negative power supply switch Q1 can be the gate of the MOSFET, the second terminal can be the drain of the MOSFET, and the third terminal can be the source of the MOSFET. The microcontroller unit 121 (MCU) generates a second control signal and sends it to the gate of the negative power supply switch Q1. The level of the second control signal determines the on / off state of the negative power supply switch Q1. That is, when the second control signal received at the gate of the negative power supply switch Q1 is a high-level signal, the negative power supply switch Q1 is in the on state, thereby supplying power to the negative terminal PSE- of the connected PSE port 110. When the second control signal received at the gate of the negative power supply switch Q1 is a low-level signal, the negative power supply switch Q1 is in the off state, thereby de-energizing the negative terminal PSE- of the connected PSE port 110.

[0059] Furthermore, when the positive power supply switch Q2 is located outside the PSE control chip 120, the first end of the positive power supply switch Q2 is connected to the processor in the PSE motherboard 100, and the first end of the positive power supply switch Q2 is used to receive the first control signal sent by the processor.

[0060] Specifically, Figure 7 This is a schematic diagram of the PSE motherboard structure when the positive power supply switch is external, as provided in an embodiment of the present invention. Figure 7 As shown, when the positive power supply switch Q2 is located outside the PSE control chip 120, the connection between the PSE control chip 120 and the positive power supply switch Q2 is as follows: Figure 6 As shown, the processor in the PSE motherboard 100 and the microcontroller unit 121 in the PSE control chip 120 work together. The processor controls the on / off state of the positive power supply switch Q2, and the microcontroller unit 121 controls the on / off state of the negative power supply switch Q1. That is, the processor in the PSE motherboard 100 can generate a first control signal and send it to the gate of the positive power supply switch Q2, and the microcontroller unit 121 can generate a second control signal and send it to the gate of the negative power supply switch Q1.

[0061] In addition, the positive power supply switch Q2 can be disposed either outside the PSE control chip 120 or inside the PSE control chip 120. When the positive power supply switch Q2 is disposed inside the PSE control chip 120, the first terminal of the positive power supply switch Q2 is connected to the microcontroller unit 121, and the first terminal of the positive power supply switch Q2 is used to receive the first control signal sent by the microcontroller unit 121.

[0062] Specifically, when the positive power supply switch Q2 is located inside the PSE control chip 120, the microcontroller unit 121 inside the PSE control chip 120 can simultaneously control the on / off states of the positive power supply switch Q2 and the negative power supply switch Q1 respectively. That is, the microcontroller unit 121 can generate a first control signal and a second control signal. The first control signal can be sent to the gate of the positive power supply switch Q2 to control the on / off state of the positive power supply switch Q2, and the second control signal can be sent to the gate of the negative power supply switch Q1 to control the on / off state of the negative power supply switch Q1.

[0063] For example, based on the PSE switches mentioned above, let's take the cascading of two PSE switches as an example. Figure 8 This is a schematic diagram of PSE switch cascading provided in an embodiment of the present invention, as shown below. Figure 8 As shown, PSE port 1101 in switch 1 and PSE port 1101 in switch 2 are connected via a network cable. The primary power supply 200 in switch 1 is powered on normally, while the primary power supply 200 in switch 2 is not powered on. The output states of the positive terminal PSE+ and the negative terminal PSE- of PSE port 1101 in switch 1 are controlled. Since switch 2 connected to PSE port 1101 is a non-powered device and does not meet the PSE or PoE protocols, PSE port 1101 in switch 1 will not supply power to switch 2. Furthermore, because the primary power supply 200 in switch 2 is not powered, switch 2 itself is not powered. Therefore, regardless of whether PSE port 1101 in switch 2 is connected to powered devices such as IPCs or low-voltage devices such as RS232 interface devices, switch 2 will not supply power to the connected devices, thus resolving the issue of mutual power supply between cascaded devices. Because switch 2 does not continuously output voltage, it will not cause the connected RS232 interface devices to malfunction. Secondly, since switch 2 is a non-powered device, switch 1 does not provide a continuous and stable voltage to switch 2. Therefore, there will be no large current in the network cable used for cascading the two switches, thus solving the problem of network cable burnout due to overcurrent. Furthermore, since switch 2 is a non-powered device, switch 1 does not provide a continuous and stable voltage to switch 2. Therefore, the loads on both switches will not simultaneously consume the power of the primary power supply 200V in switch 1. Thus, there will be no power shortage problem in either switch, preventing the entire load connected to both switches from losing power.

[0064] For example, such as Figure 8As shown, when the primary power supplies 200 in both switch 1 and switch 2 are powered on normally, even if the output voltages of the corresponding primary power supplies 200 in switch 1 and switch 2 are different, since switch 2 is a non-powered device and does not meet the PSE or PoE protocol, switch 1 will not provide a continuous and stable voltage to switch 2. The primary power supplies 200 in switch 1 and switch 2 supply power to their respective connected devices, and there will be no situation where all loads consume the power of the primary power supply 200 with the higher output voltage, thereby avoiding the problem of all loads losing power due to insufficient power of the primary power supply 200.

[0065] Furthermore, the PSE switch provided in this embodiment of the invention does not require the PSE motherboard 100 to be designed with separate grounding. Therefore, the return impedance of the primary power supply 200 output signal and the return impedance of the DC / DC switching frequency on the PSE motherboard 100 are relatively small. Most of the conducted interference flows inside the PSE switch and less flows to the test ISN through the network cable, so that the CE test of the PSE port 110 meets the limit requirements. Figure 9 This is a schematic diagram of the CE test results of the PSE port provided in an embodiment of the present invention, as shown below. Figure 9 As shown, across the entire frequency band, the actual tested QP at PSE port 110 is lower than the QP limit, and the actual tested AV is lower than the AV limit.

[0066] The PSE switch provided in this invention has a positive power supply switch connected to each PSE port on the PSE motherboard. The on / off state of each positive power supply switch controls the output state of the positive power supply of each PSE port. The PSE motherboard determines the device type connected to each PSE port based on detection signals, and further determines the power supply control result of each PSE port for the connected device based on the device type, the output state of the positive power supply, and the output state of the negative power supply. In this invention, by using the device type connected to the PSE port, the output state of the positive power supply, and the output state of the negative power supply, it determines whether the PSE protocol or PoE protocol is met, thereby providing power to connected devices that meet the PSE or PoE protocol. This avoids on-site engineering problems caused by mutual power supply when PSE switches are cascaded. Furthermore, by setting a positive power supply switch to control the output state of the positive power supply of the PSE port, the PSE motherboard does not need separate grounding design, thus avoiding the problem of PSE port CE test exceeding the standard.

[0067] This invention also provides a power supply control method, applied to a PSE switch as described in any of the preceding embodiments. Figure 10 This is a flowchart illustrating the power supply control method provided in an embodiment of the present invention, as shown below. Figure 10 As shown, the method includes steps 1010 to 1030.

[0068] Step 1010: Determine the output status of the positive power supply and the output status of the negative power supply corresponding to each PSE port.

[0069] Step 1020: Determine the device type connected to each PSE port based on the detection signal.

[0070] Step 1030: Based on the device type connected to each PSE port, the output status of the positive power supply and the output status of the negative power supply, determine the power supply control result of each PSE port for the connected device.

[0071] The power supply control method provided by this invention determines the output states of the positive and negative power supplies of each PSE port, identifies the device type connected to each PSE port based on detection signals, and then determines the power supply control result of each PSE port for the connected device based on the device type, the output states of the positive and negative power supplies. In this invention, by determining the device type connected to the PSE port, the output states of the positive and negative power supplies, and the corresponding output states, it is determined whether the PSE protocol or PoE protocol is met. This ensures that power is supplied to connected devices that meet the PSE or PoE protocol, avoiding on-site engineering problems caused by mutual power supply when PSE switches are cascaded. Furthermore, by controlling the output state of the positive power supply of the PSE port, the PSE motherboard does not need to be designed with separate grounding, thus avoiding the problem of PSE port CE testing exceeding limits.

[0072] Figure 11 This is a schematic diagram of the structure of the PSE motherboard provided in an embodiment of the present invention, as shown below. Figure 11 As shown, the PSE motherboard may include a processor 1110, a communications interface 1120, a memory 1130, and a communication bus 1140. The processor 1110, communications interface 1120, and memory 1130 communicate with each other via the communication bus 1140. The processor 1110 can call logic instructions in the memory 1130 to execute a power supply control method. This method includes: determining the output state of the positive and negative terminals of each PSE port; determining the device type connected to each PSE port based on detection signals; and determining the power supply control result of each PSE port for the connected device based on the device type connected to each PSE port, the output state of the positive and negative terminals of the power supply.

[0073] Furthermore, the logical instructions in the aforementioned memory 1130 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to related technologies, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0074] On the other hand, the present invention also provides a computer program product, which includes a computer program that can be stored on a computer-readable storage medium. When the computer program is executed by a processor, the computer is able to execute the power supply control method provided by the above-described methods. This method includes: determining the output state of the positive and negative terminals of the power supply corresponding to each PSE port; determining the device type connected to each PSE port based on a detection signal; and determining the power supply control result of each PSE port for the connected device based on the device type connected to each PSE port, the output state of the positive and negative terminals of the power supply.

[0075] In another aspect, the present invention also provides a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, is implemented to perform the power supply control method provided by the above methods. The method includes: determining the output state of the positive power supply terminal and the output state of the negative power supply terminal corresponding to each PSE port; determining the device type connected to each PSE port based on a detection signal; and determining the power supply control result of each PSE port for the connected device based on the device type connected to each PSE port, the output state of the positive power supply terminal, and the output state of the negative power supply terminal.

[0076] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0077] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the parts that contribute to the related technology, can be embodied in the form of software products. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0078] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A PSE switch, characterized in that, include: PSE motherboard and primary power supply, including: The PSE motherboard includes at least one PSE port and at least one positive power supply switch. The positive power supply terminal of the at least one PSE port is connected to the at least one positive power supply switch, and each positive power supply switch is connected to the output terminal of the primary power supply. The on / off state of the positive power supply switch is used to control the output state of the corresponding PSE port's positive power supply terminal. The PSE motherboard is used to determine the type of device connected to each PSE port based on the detection signal; and to determine the power supply control result of each PSE port to the connected device based on the type of device connected to each PSE port, the output state of the positive power supply and the output state of the negative power supply.

2. The PSE switch according to claim 1, characterized in that, The PSE motherboard determines the power supply control result of each PSE port for the connected device based on the device type connected to each PSE port, the output state of the positive power supply terminal, and the output state of the negative power supply terminal, including: For each of the PSE ports, if the device type connected to the PSE port is a powered device, and the output states corresponding to the positive and negative power supplies are both in the power supply state, then the power supply control result of the PSE port for the connected device is determined to be power supply.

3. The PSE switch according to claim 1, characterized in that, The first terminal of the positive power supply switch is used to receive a first control signal, which is used to control the on / off state of the positive power supply switch; the second terminal of the positive power supply switch is connected to the output terminal of the primary power supply; the third terminal of the positive power supply switch is connected to the positive power supply terminal of the corresponding PSE port, the negative terminal of the diode, and the first terminal of the capacitor; the positive terminal of the diode is connected to the negative power supply terminal of the corresponding PSE port and the second terminal of the capacitor.

4. The PSE switch according to claim 3, characterized in that, The PSE motherboard also includes a PSE control chip, which is used to control the output state of the negative power supply terminal of each PSE port.

5. The PSE switch according to claim 4, characterized in that, The PSE control chip includes a microcontroller unit and a negative power supply switch, wherein: The microcontroller is connected to the first terminal of the negative power supply switch. The first terminal of the negative power supply switch is used to receive a second control signal sent by the microcontroller. The second control signal is used to control the on / off state of the negative power supply switch. The second terminal of the negative power supply switch is connected to the negative power supply terminal of the corresponding PSE port. The third terminal of the negative power supply switch is grounded.

6. The PSE switch according to claim 5, characterized in that, When the positive power supply switch is located within the PSE control chip, the first terminal of the positive power supply switch is connected to the microcontroller unit, and the first terminal of the positive power supply switch is used to receive the first control signal sent by the microcontroller unit. When the positive power supply switch is located outside the PSE control chip, the first end of the positive power supply switch is connected to the processor in the PSE motherboard, and the first end of the positive power supply switch is used to receive the first control signal sent by the processor.

7. A power supply control method, characterized in that, Applied to the PSE switch as described in any one of claims 1-6, the method comprises: Determine the output status of the positive and negative power supply terminals corresponding to each PSE port; The type of device connected to each PSE port is determined based on the detection signal. Based on the device type connected to each PSE port, the output status of the positive power supply terminal, and the output status of the negative power supply terminal, the power supply control result of each PSE port for the connected device is determined.

8. A PSE motherboard, comprising a memory, a processor, and a computer program stored in the memory and running on the processor, characterized in that, When the processor executes the computer program, it implements the power supply control method as described in claim 7.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the power supply control method as described in claim 7.

10. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the processor, it implements the power supply control method as described in claim 7.

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