An address assignment method based on 8421 code encoding switch

Abstract

The application discloses an address allocation method based on 8421 code coding switch, relates to the technical field of industrial communication bus, and comprises the following steps: setting a target number through a digital addition and subtraction button on the switch to allocate an address, and using RC filtering and Schmidt shaping address signals; an MCU continuously reads address signals and synchronously checks the address, then sends an address declaration frame, and listens to bus feedback; and the 8421 code coding switch displays the current number state and the finally allocated CAN node address in real time. The application has the advantages of efficient and accurate configuration, adoption of intuitive 8421 code dialing, exemption from conversion between different bases, reduction of error rate and shortening of time consumption; stable and reliable communication, resistance to vibration interference and elimination of address jump through hardware filtering and triple checking; convenient and intuitive operation and maintenance, support of tool-free address changing and real-time visual display, quick positioning of faults; strong environmental adaptability, flexible expansion and multi-protocol compatibility, no address loss in power failure, and long-term stable operation of the system in extreme environments.

Description

Technical Field

[0001] This invention relates to the field of industrial communication bus technology, and in particular to an address allocation method based on an 8421 code encoding switch. Background Technology

[0002] With the rapid development of industrial automation and intelligent transportation systems, the CAN bus, due to its high reliability, real-time performance, and anti-interference capabilities, has been widely used in industrial control, automotive electronics, rail transportation, and other fields. Meanwhile, as the core communication architecture connecting various electronic control units, the Controller Area Network (CAN bus) is experiencing increasingly dense node deployments, placing higher demands on the flexibility and reliability of network configuration. Current CAN node address allocation technologies primarily rely on factory-fixed addresses, host computer software configuration, or traditional mechanical DIP switches (such as 8421 code DIP switches) for static settings. While these methods were effective in early, simple networks and constitute the current mainstream configuration in industrial settings, they are not universally applicable.

[0003] Currently, existing technologies have significant shortcomings in CAN node address allocation: On the one hand, although software programming can fix addresses, modifications rely on specialized equipment, leading to inconvenience in on-site maintenance. In mass production, human error during programming is prone to occur, resulting in a large workload and difficulty in flexibly responding to node replacement needs. On the other hand, using ordinary binary DIP switches requires operators to perform tedious binary-to-decimal conversions, which is prone to errors. Furthermore, the output signal lacks anti-jitter processing and is susceptible to mechanical vibration interference that can cause address jumps. More importantly, existing technologies generally lack hardware-level real-time verification mechanisms for address validity and bus conflicts. When multiple node addresses are duplicated, troubleshooting often relies on host computer software, resulting in low fault location efficiency and failing to meet the application requirements of high reliability and rapid deployment. Summary of the Invention

[0004] In view of the problems existing in the address allocation method based on 8421 code encoding switch, the present invention is proposed.

[0005] Therefore, the problem that this invention aims to solve is that the existing CAN node address allocation has the defects of difficult software burning and maintenance, easy error, and traditional DIP switches that require manual conversion, lack anti-bounce and are prone to jump, especially the lack of hardware-level address conflict real-time verification, which leads to low fault diagnosis efficiency.

[0006] To solve the above-mentioned technical problems, the present invention provides the following technical solution: In a first aspect, embodiments of the present invention provide an address allocation method based on an 8421 code encoding switch, which includes allocating an address by setting a target number through digital addition and subtraction buttons on the switch, and using RC filtering and Schmitt shaping of the address signal; The MCU continuously reads the address signal and synchronously verifies the address, then sends an address declaration frame and listens for bus feedback; The 8421 code encoder switch displays the current digital status and the final assigned CAN node address in real time.

[0007] As a preferred embodiment of the address allocation method based on the 8421 code encoding switch described in this invention, the method of allocating the address by setting the target number through the digital plus and minus buttons on the switch includes the device monitoring the trigger signal of the plus and minus buttons in real time, performing increment and decrement operations on the value in the register, and refreshing the updated value to the display unit for user confirmation. When the user completes the setting and triggers the confirmation command, the MCU uses the target number as the core parameter, generates the CAN node address according to the address mapping rules, and writes the CAN node address into the address configuration register to complete the allocation of the node address.

[0008] As a preferred embodiment of the address allocation method based on the 8421 code encoding switch described in this invention, the address signal using RC filtering and Schmitt shaping includes filtering out high-frequency interference components through an RC low-pass filter circuit to smooth the signal waveform, and using a Schmitt shaping circuit to perform hysteresis comparison and shaping on the filtered address signal to convert the address signal into a TTL digital signal with steep edges and stable level.

[0009] As a preferred embodiment of the address allocation method based on the 8421 code encoding switch described in this invention, the MCU continuously reads the address signal, which includes sampling the 8421 code address signal after RC filtering and Schmitt shaping three times consecutively each time the address is triggered for update, and comparing the three reading results to perform repeatability verification. Only when the three readings are completely consistent is it determined to be a valid address. If the readings are inconsistent, resampling is performed until it is stable.

[0010] As a preferred embodiment of the address allocation method based on the 8421 code encoding switch described in this invention, the MCU synchronous address verification includes the MCU performing legality verification on a stable address, and combining it with an offline address caching mechanism, comparing the finally verified address with the historical address cached in the EEPROM. If they match, the cached address is used directly; if they do not match, it is determined that the DIP switch has been modified, and a new encoding address is automatically enabled and the cache is updated. The determined unique node address is connected to the bus through the built-in CAN controller and transceiver chip.

[0011] As a preferred embodiment of the address allocation method based on the 8421 code encoding switch described in this invention, the offline address caching mechanism includes the following: after the initial address allocation or DIP switch change verification is passed, the MCU writes the 8421 code address, which has been verified for repeatability and legality, into the EEPROM for storage. When the device experiences a power outage and restart or encounters strong interference that causes real-time reading failure, the device system prioritizes loading the address stored in the EEPROM to quickly restore the communication link. At the same time, it has a built-in dynamic consistency comparison logic. Each time it is powered on, the read code is checked against the cached address. If the two are consistent, the cache is directly reused to shorten the initialization time. If they are inconsistent, it is determined to be a manual DIP switch change, and the new address is immediately enabled and the cache is updated synchronously.

[0012] As a preferred embodiment of the address allocation method based on the 8421 code encoding switch described in this invention, the monitoring bus feedback includes, within a preset arbitration window period after sending the address declaration frame, the MCU controls the CAN controller to switch to monitoring mode to listen for whether there are conflict indication signals issued by other nodes on the bus for the current node. If an abnormal feedback is detected within the specified timeout period, it is determined to be an address conflict and the conflict flag is recorded. The current address occupancy is stopped and a reselection or error reporting process is triggered. If no abnormal feedback is detected within the specified timeout period, the address is uniquely available in the network, and the address is officially locked as the logical node address of this site and enters normal communication state.

[0013] As a preferred embodiment of the address allocation method based on the 8421 code encoding switch described in this invention, the 8421 code encoding switch displays the current digital status in real time by using a set of four DIP switches to correspond to the weight bits of the 8421 code, and mapping the on / off combinations of the switches to the current binary value. The binary value is converted into a decimal number by the hardware circuit and presented on the local digital tube as the user's preset initial address expectation value.

[0014] As a preferred embodiment of the address allocation method based on 8421 code-encoded switches described in this invention, the final allocated CAN node address includes the following: after the CAN node completes the bus address arbitration and conflict detection process, if the DIP switch position is confirmed to be uniquely available on the network, the value represented by the 8421 code-encoded DIP switch combination used to set the CAN node address is locked by the system and officially becomes the final CAN logical node address. If a conflict occurs, the switch state needs to be manually adjusted to change the input value and re-trigger the allocation process to achieve consistency and visual monitoring of the physical switch position, displayed value, and final communication address.

[0015] Secondly, embodiments of the present invention provide an address allocation system based on an 8421 code encoding switch, comprising: an address setting and signal conditioning module, which allocates addresses by setting target numbers through digital addition and subtraction buttons on the switch, and uses RC filtering and Schmitt shaping of the address signals; The address arbitration and communication control module's MCU continuously reads the address signal and synchronously verifies the address, then sends an address declaration frame and listens for bus feedback; The real-time status display and visualization monitoring module uses an 8421 code encoding switch to display the current digital status and the final assigned CAN node address in real time.

[0016] The beneficial effects of this invention are as follows: First, it offers efficient and precise configuration. Its innovative and intuitive 8421 code DIP switch design completely eliminates the need for operators to perform tedious binary-to-decimal conversions on-site, significantly reducing human error rates and compressing single-node configuration time to the second level, drastically shortening overall project time. Second, it provides stable and reliable communication. Through a high-precision hardware filtering circuit combined with a unique triple-check mechanism, it effectively resists strong mechanical vibrations and complex electromagnetic interference in industrial environments, fundamentally eliminating address jumps caused by signal jitter and significantly reducing bus communication failure rates. Third, it offers convenient and intuitive operation and maintenance. It supports manual address changing without special tools and is equipped with real-time status visualization indicators, enabling maintenance personnel to quickly locate and resolve address conflict faults, greatly saving downtime. Finally, it boasts strong environmental adaptability, with flexible address range expansion and multi-protocol compatibility. Address information is not lost in extreme high or low temperatures or power outages, ensuring long-term stable operation of the system under harsh conditions, providing an ideal solution for high-density node networks. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Wherein: Figure 1 This is a schematic diagram of an encoding switch for an address allocation method based on an 8421 code encoding switch.

[0018] Figure 2 This is a schematic diagram of a system architecture for an address allocation method based on 8421 code encoding switches. Detailed Implementation

[0019] To make the above-mentioned objects, features, and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the protection scope of the present invention.

[0020] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of the invention. Therefore, the invention is not limited to the specific embodiments disclosed below.

[0021] Secondly, the term "one embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The phrase "in one embodiment" appearing in different places in this specification does not necessarily refer to the same embodiment, nor is it a single or selective embodiment that is mutually exclusive with other embodiments.

[0022] This invention is described in detail with reference to the schematic diagrams. When detailing the embodiments of this invention, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged, not adhering to the usual scale. Furthermore, the schematic diagrams are merely examples and should not be construed as limiting the scope of protection of this invention. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0023] Furthermore, in the description of this invention, it should be noted that the terms "upper," "lower," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. These terms are used solely for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. In addition, the terms "first," "second," or "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0024] Unless otherwise explicitly specified and limited, the terms "installation," "connection," and "joining" in this invention should be interpreted broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; similarly, they can refer to mechanical connections, electrical connections, or direct connections, or indirect connections through an intermediate medium, or internal connections between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0025] Example 1 Reference Figure 1 and Figure 2This is the first embodiment of the present invention, which provides an address allocation method based on an 8421 code encoding switch, including: S1: The target number is set by the digital plus or minus buttons on the switch to assign the address, and the address signal is RC filtered and Schmitt shaped.

[0026] The process of assigning an address by setting a target number using the digital plus and minus buttons on the switch involves the device monitoring the trigger signals of the plus and minus buttons in real time, performing increment and decrement operations on the value in the register, and refreshing the updated value to the display unit for user confirmation. When the user completes the setting and triggers the confirmation command, the MCU uses the target number as the core parameter, generates the CAN node address according to the address mapping rules, and writes the CAN node address into the address configuration register to complete the allocation of the node address.

[0027] S1.1: The address signal is filtered by RC filtering and Schmitt shaping, which includes filtering out high-frequency interference components through an RC low-pass filter circuit to smooth the signal waveform, and using a Schmitt shaping circuit to perform hysteresis comparison and shaping on the filtered address signal, converting the address signal into a TTL digital signal with steep edges and stable level.

[0028] S2: The MCU continuously reads the address signal and synchronously verifies the address, then sends an address declaration frame and listens for bus feedback.

[0029] The MCU's continuous address signal reading includes sampling the 8421 code address signal after RC filtering and Schmitt shaping three times consecutively each time the address is triggered for update. The MCU compares the three readings to perform repeatability verification. Only when the three readings are completely consistent is it determined to be a valid address. If the readings are inconsistent, the MCU resamples until it is stable.

[0030] S2.1: MCU synchronous address verification includes the MCU performing legality verification on a stable address and, in conjunction with an offline address caching mechanism, comparing the finally verified address with the historical address cached in the EEPROM. If they match, the cached address is used directly; if they do not match, it is determined that the DIP switch has been modified, and a new coded address is automatically enabled and the cache is updated. The determined unique node address is connected to the bus through the built-in CAN controller and transceiver chip.

[0031] S2.2: The offline address caching mechanism includes that after the initial address allocation or DIP switch change verification is passed, the MCU writes the 8421 code address, which has been verified for repeatability and legality, into the EEPROM for storage. When the device experiences a power outage and restart or encounters strong interference that causes real-time reading failure, the device system prioritizes loading the address stored in the EEPROM to quickly restore the communication link. At the same time, it has a built-in dynamic consistency comparison logic. Each time it is powered on, the read code is checked against the cached address. If the two are consistent, the cache is directly reused to shorten the initialization time. If they are inconsistent, it is determined that the DIP switch has been manually changed, and the new address is immediately enabled and the cache is updated synchronously.

[0032] S2.3: Listening to bus feedback includes, within a preset arbitration window period after sending the address declaration frame, the MCU controls the CAN controller to switch to listening mode to listen for any conflict indication signals sent by other nodes on the bus to the current node.

[0033] If an abnormal response is detected within the specified timeout period, it is determined to be an address conflict and the conflict flag is recorded. The current address occupancy is stopped and a reselection or error reporting process is triggered.

[0034] If no abnormal feedback is detected within the specified timeout period, the address is uniquely available in the network, and the address is officially locked as the logical node address of this site and enters normal communication state.

[0035] Furthermore, an MCU with a built-in CAN controller (such as the STM32 series) can be selected, which has three core logics: repeatability check: solves the address jump problem caused by DIP switch jitter; validity check: filters illegal addresses such as reserved addresses and broadcast addresses to prevent invalid addresses from accessing the bus; conflict check: detects address duplication problems in real time through the bus monitoring mechanism to avoid bus conflicts from the source.

[0036] Offline address caching and fault self-recovery: To address the problem of address loss or reading errors caused by power outages or interference in industrial settings, an "offline address caching + fault self-recovery" mechanism is designed.

[0037] After the initial address allocation is successful, the MCU automatically caches the original address of the "8421 code" to the EEPROM. When the device is powered off and restarted or the address reading fails due to strong interference, the MCU prioritizes reading the cached address from the EEPROM to quickly restore communication without needing to re-dial the code. A "cache address verification" logic is added: after each read of the cached address, it is compared with the current coded address. If they are inconsistent, it is determined that the code has been modified, and the new coded address is automatically used and the cache is updated. If they are consistent, the cached address is used directly to reduce the time spent on repeated verification.

[0038] The CAN bus transceiver module uses mainstream CAN transceiver chips such as TJA1042 to realize the conversion between the TTL level of the MCU and the differential level of the CAN bus.

[0039] S3: The 8421 code encoding switch displays the current digital status and the final assigned CAN node address in real time.

[0040] The 8421 code encoding switch displays the current digital status in real time by using a set of four DIP switches to correspond to the weight bits of the 8421 code. The on / off combinations of the switches are mapped to the current binary value. The binary value is converted into a decimal number by the hardware circuit and displayed on the local digital tube as the user's preset initial address expectation value.

[0041] S3.1: The final assigned CAN node address includes the value represented by the 8421 code-encoded DIP switch combination used to set the CAN node address after the CAN node completes the bus address arbitration and conflict detection process. If the DIP switch position is confirmed to be the only available one on the network, the value is locked by the system and officially becomes the final CAN logical node address. If a conflict occurs, the switch state needs to be manually adjusted to change the input value and re-trigger the allocation process to achieve consistency and visual monitoring of the physical switch position, displayed value and final communication address.

[0042] Furthermore, this embodiment also provides an address allocation system based on an 8421 code encoding switch, including: The address setting and signal conditioning module assigns addresses by setting target numbers using digital plus and minus buttons on the switch, and uses RC filtering and Schmitt triggering to shape the address signals.

[0043] The address arbitration and communication control module's MCU continuously reads the address signal and synchronously verifies the address, then sends an address declaration frame and listens for bus feedback.

[0044] The real-time status display and visualization monitoring module uses an 8421 code encoding switch to display the current digital status and the final assigned CAN node address in real time.

[0045] The computer device can be a terminal, comprising a processor, memory, communication interface, display screen, and input devices connected via a system bus. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The communication interface is used for wired or wireless communication with external terminals; wireless communication can be achieved through Wi-Fi, carrier networks, NFC (Near Field Communication), or other technologies. The display screen can be an LCD screen or an e-ink screen. The input devices can be a touch layer covering the display screen, buttons, a trackball, or a touchpad on the computer device's casing, or an external keyboard, touchpad, or mouse.

[0046] In summary, this invention discloses a CAN bus node address allocation device and method based on an 8421 code encoder switch, belonging to the field of industrial communication bus technology. It aims to completely solve the core pain points of traditional solutions, such as software programming relying on specialized equipment, difficult maintenance, and the error-prone nature of manual conversion of ordinary binary DIP switches, as well as poor vibration resistance leading to address jumps. This invention innovatively uses a KSA-1 (KM1) type 8421 code encoder switch as the core input unit, allowing operators to directly and intuitively set addresses using decimal values, completely eliminating the tedious base conversion process, significantly reducing human error rates and greatly shortening on-site configuration time. Simultaneously, the system deeply integrates RC filtering and Schmitt trigger shaping hardware debouncing technology, combined with address validity verification, triple logic verification, and an automatic bus conflict arbitration mechanism, constructing a highly reliable address allocation system that requires no programming and is plug-and-play. This effectively resists strong mechanical vibrations and electromagnetic interference in industrial environments, ensuring no address loss and zero communication failures even under extreme conditions. Its beneficial effects are reflected in the following aspects: it not only achieves efficient "zero-threshold" address configuration, but also enables maintenance personnel to quickly locate and resolve address conflicts through hardware-level real-time status visualization, greatly saving maintenance costs and downtime; the device has simple hardware circuitry, low cost, and excellent protocol compatibility and address expansion capabilities, and can be widely used in multi-node networking scenarios with extremely high stability requirements, such as industrial control, energy storage systems, rail transit, and automotive electronics, providing a highly valuable intelligent solution for improving the deployment efficiency and operational reliability of industrial communication networks.

[0047] Example 2 Reference Figures 1-2 This is the second embodiment of the present invention, which provides an address allocation method based on an 8421 code encoding switch. In order to verify the beneficial effects of the present invention, scientific demonstration is carried out through economic benefit calculation.

[0048] In the field deployment of battery management systems (BMS) for large-scale energy storage power stations, facing the challenge of rapidly networking hundreds of series-connected battery clusters and slave control modules within a narrow, high-vibration, and electromagnetically complex cabinet, the maintenance team has completely abandoned the inefficient traditional method of relying on a laptop connected to a programmer to issue addresses one by one or manually calculating binary DIP codes. Engineers only need to hold a screwdriver and, based on the physical arrangement of the battery clusters, directly dial the corresponding decimal address (e.g., 01 to 99) on the KSA-1 type 8421 code encoding switch on each circuit board, without any base conversion, completely eliminating human calculation errors. The moment the switch is closed, the integrated RC filter and Schmitt trigger circuit immediately filter out signal jitter caused by mechanical vibrations in the field. At the same time, the hardware logic unit performs address validity checks and automatic arbitration of bus conflicts in real time. If duplicate or illegal address values ​​are detected, the panel indicator light immediately turns red to alarm. Only when the address is unique and valid will the green light confirm its effectiveness, achieving "plug and play" and ensuring address retention even when power is off. In subsequent maintenance, if a faulty module needs to be replaced, the new module only needs to be switched to the same decimal number to seamlessly connect to the network, without the need for reprogramming or complex configuration. A comparison of the prior art and this invention is shown in Table 1 below: Table 1 Comparison between the prior art and the present invention

[0049] Table 1 shows that existing technologies rely on software programming or manual number system conversion, which suffers from drawbacks such as cumbersome configuration, susceptibility to errors, and weak anti-interference capabilities. In vibration environments, address jumps are easily caused, and fault location is difficult. In contrast, this invention adopts an intuitive 8421 DIP switch design, eliminating the conversion process and achieving precise configuration within seconds. Combined with hardware filtering and triple verification mechanisms, it completely eliminates address jumps. It supports tool-free address modification and status visualization, significantly shortening troubleshooting time. It also features address retention during power outages and multi-protocol compatibility. In summary, this invention is superior to existing technologies in terms of configuration efficiency, communication stability, and ease of maintenance, making it more suitable for harsh industrial scenarios.

[0050] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. An address allocation method based on an 8421 code encoding switch, characterized in that: include, The target number is set by the digital plus or minus buttons on the switch to assign the address, and the address signal is RC filtered and Schmitt shaped. The MCU continuously reads the address signal and synchronously verifies the address, then sends an address declaration frame and listens for bus feedback; The 8421 code encoder switch displays the current digital status and the final assigned CAN node address in real time.

2. The address allocation method based on the 8421 code encoding switch as described in claim 1, characterized in that: The process of setting a target number by using the digital plus and minus buttons on the switch to allocate an address involves the device monitoring the trigger signal of the plus and minus buttons in real time, performing increment and decrement operations on the value in the register, and refreshing the updated value to the display unit for user confirmation. When the user completes the setting and triggers the confirmation command, the MCU uses the target number as the core parameter, generates the CAN node address according to the address mapping rules, and writes the CAN node address into the address configuration register to complete the allocation of the node address.

3. The address allocation method based on the 8421 code encoding switch as described in claim 2, characterized in that: The address signal using RC filtering and Schmitt shaping includes filtering out high-frequency interference components through an RC low-pass filter circuit to smooth the signal waveform, and using a Schmitt shaping circuit to perform hysteresis comparison and shaping on the filtered address signal, converting the address signal into a TTL digital signal with steep edges and stable levels.

4. The address allocation method based on the 8421 code encoding switch as described in claim 3, characterized in that: The MCU continuously reads the address signal, which includes sampling the 8421 code address signal after RC filtering and Schmitt shaping three times consecutively when each address update is triggered. The MCU compares the three readings to perform a repeatability check. Only when the three readings are completely consistent is it determined to be a valid address. If the readings are inconsistent, the MCU resamples until it is stable.

5. The address allocation method based on the 8421 code encoding switch as described in claim 4, characterized in that: The MCU synchronous address verification includes the MCU performing a validity check on a stable address and, in conjunction with an offline address caching mechanism, comparing the finally verified address with the historical address cached in the EEPROM. If they match, the cached address is used directly; if they do not match, it is determined that the DIP switch has been modified, and a new coded address is automatically enabled and the cache is updated. The determined unique node address is then connected to the bus through the built-in CAN controller and transceiver chip.

6. The address allocation method based on the 8421 code encoding switch as described in claim 5, characterized in that: The offline address caching mechanism includes the following: after the initial address allocation or DIP switch change verification is passed, the MCU writes the 8421 code address, which has been verified for repeatability and legality, into the EEPROM for storage. When the device experiences a power outage and restart or encounters strong interference that causes real-time reading failure, the device system prioritizes loading the address stored in the EEPROM to quickly restore the communication link. At the same time, it has a built-in dynamic consistency comparison logic. Each time it is powered on, the read code is checked against the cached address. If the two are consistent, the cache is directly reused to shorten the initialization time. If they are inconsistent, it is determined that the DIP switch has been manually changed, and the new address is immediately enabled and the cache is updated synchronously.

7. The address allocation method based on the 8421 code encoding switch as described in claim 6, characterized in that: The monitoring bus feedback includes, within a preset arbitration window period after sending the address declaration frame, the MCU controls the CAN controller to switch to monitoring mode to listen for any conflict indication signals sent by other nodes on the bus to the current node. If an abnormal feedback is detected within the specified timeout period, it is determined to be an address conflict and the conflict flag is recorded. The current address occupancy is stopped and a reselection or error reporting process is triggered. If no abnormal feedback is detected within the specified timeout period, the address is uniquely available in the network, and the address is officially locked as the logical node address of this site and enters normal communication state.

8. The address allocation method based on the 8421 code encoding switch as described in claim 7, characterized in that: The 8421 code encoding switch displays the current digital status in real time by using a set of four DIP switches to correspond to the weight bits of the 8421 code. The on / off combinations of the switches are mapped to the current binary value. The binary value is converted into a decimal number by the hardware circuit and displayed on the local digital tube as the user's preset initial address expectation value.

9. The address allocation method based on the 8421 code encoding switch as described in claim 8, characterized in that: The final allocated CAN node address includes the value represented by the 8421 code-encoded DIP switch combination used to set the CAN node address after the CAN node completes the bus address arbitration and conflict detection process. If the DIP switch position is confirmed to be the only available one on the network, the value is locked by the system and officially becomes the final CAN logical node address. If a conflict occurs, the switch state needs to be manually adjusted to change the input value and re-trigger the allocation process to achieve consistency and visual monitoring of the physical switch position, displayed value and final communication address.

10. An address allocation system based on an 8421 code encoding switch, based on the address allocation method based on an 8421 code encoding switch as described in any one of claims 1 to 7, characterized in that: include, The address setting and signal conditioning module assigns addresses by setting target numbers using digital plus and minus buttons on the switch, and uses RC filtering and Schmitt trigger shaping of the address signals. The address arbitration and communication control module's MCU continuously reads the address signal and synchronously verifies the address, then sends an address declaration frame and listens for bus feedback; The real-time status display and visualization monitoring module uses an 8421 code encoding switch to display the current digital status and the final assigned CAN node address in real time.

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