Virtual-real synchronization method of comprehensive monitoring system based on digital twinning

Abstract

This invention relates to the field of digital twin technology and discloses a virtual-real synchronization method for a comprehensive monitoring system based on digital twins, comprising the following steps: S1, system initialization and global benchmark calibration stage; S2, interrupt behavior and latency jitter full-cycle perception stage; S3, interrupt affinity adaptive dynamic scheduling stage; S4, dual-dimensional clock synchronization and state alignment calibration stage; S5, synchronization effect closed-loop optimization and scenario adaptation stage. This invention addresses the root cause of virtual-real synchronization errors by effectively solving the data packet inbound latency jitter problem caused by unbalanced CPU network interrupt handling at edge nodes through real-time perception of interrupt behavior and adaptive dynamic scheduling of interrupt affinity. It suppresses the generation of nondeterministic queuing delays. Simultaneously, through a dual-dimensional clock synchronization and state alignment calibration mechanism, it compensates for the shortcomings of traditional clock-only time synchronization schemes, covering the entire link latency in data transmission and processing.

Description

Technical Field

[0001] This invention relates to the field of digital twin technology, and in particular to a method for synchronizing the virtual and real aspects of a comprehensive monitoring system based on digital twins. Background Technology

[0002] With the rapid development of digital twin technology, it has been widely applied in comprehensive monitoring systems across multiple fields such as industrial equipment, infrastructure, and urban operations. By constructing a digital twin that precisely maps to a physical entity, it enables real-time visualization, multi-dimensional analysis, and intelligent control of the physical entity's operational status. In a comprehensive monitoring system based on digital twins, high-frequency operational status sampling data of the physical entity needs to be uploaded to the digital twin platform through edge nodes to drive the twin model to complete real-time status updates. High-precision virtual-real synchronization between the physical and digital worlds is the core foundation for ensuring the consistency between the twin model and the physical entity's status, directly determining the reliability and control accuracy of the monitoring system.

[0003] Currently, the mainstream technical solutions for virtual-real synchronization in the industry mainly rely on clock synchronization protocols such as NTP and PTP to complete global clock synchronization between the physical sampling end, edge nodes and digital twin platform, thereby establishing a unified time reference for the entire link and ensuring the time consistency of data transmission.

[0004] Existing synchronization solutions focus only on aligning the hardware clock reference of all nodes, completely ignoring the impact of uneven CPU processing of network interrupts during actual operation of edge nodes. They cannot eliminate packet queuing congestion caused by interrupt affinity deviation and concentrated distribution of interrupt load, and thus cannot solve the nondeterministic queuing delay introduced by this, resulting in irregular jitter in packet inbound delay and failing to meet the stable transmission requirements in high-frequency sampling scenarios. Summary of the Invention

[0005] The purpose of this invention is to provide a method for synchronizing the virtual and real aspects of a comprehensive monitoring system based on digital twins, so as to solve the problems mentioned in the background art.

[0006] To achieve the above objectives, the present invention adopts the following technical solution:

[0007] The method for synchronizing the virtual and real aspects of a comprehensive monitoring system based on digital twins includes the following steps:

[0008] S1. System initialization and global benchmark calibration phase: Complete the full-link network initialization of the digital twin integrated monitoring system, establish communication links between physical sampling sensors, edge nodes, and the digital twin platform, complete the one-to-one mapping of metadata of physical entities, sampling units, edge node hardware resources, and twin models, complete the initial global clock synchronization of all nodes based on the PTP hardware clock protocol, establish a unified benchmark time axis, collect interrupt and delay benchmark data under multiple typical scenarios, and generate an interrupt load-processing delay benchmark library.

[0009] S2. Interruption behavior and latency jitter full-cycle perception stage: Receive high-frequency sampling data of physical entities, stamp each data packet with a network card hardware inbound timestamp, collect network interrupt processing data of each CPU core in real time, calculate interrupt load imbalance, identify interrupt affinity deviation, calculate data packet inbound queuing delay and latency jitter, and establish a mapping relationship between interrupt load imbalance and latency jitter.

[0010] S3, Interrupt affinity adaptive dynamic scheduling stage: two-level trigger thresholds are preset for interrupt load imbalance and packet inbound delay jitter. Real-time monitoring data is compared with the thresholds. When the trigger conditions are met, the CPU cores of the edge nodes are logically divided, the dedicated network interrupt processing core set is isolated, the real-time scheduling weight of each dedicated core is calculated, and the weighted minimum load priority strategy is adopted to complete the dynamic binding and migration of network card receive interrupts and CPU cores. The scheduling effect is checked and optimized again.

[0011] S4. In the dual-dimensional clock synchronization and state alignment calibration stage, perform full-node periodic hardware clock closed-loop calibration, correct link transmission delay and clock drift deviation, calculate the delay compensation amount for each sampled data packet, generate a calibration timestamp, set the calibration timestamp as the only triggering benchmark for the twin model state update, verify the consistency between the physical sampling sequence and the twin model update sequence, and trigger secondary compensation calibration for deviation exceeding the standard.

[0012] S5. In the closed-loop optimization and scenario adaptation stage of synchronization effect, core indicator data of synchronization effect throughout the entire cycle are collected, quantitative evaluation of system synchronization status is completed, scheduling and calibration parameters under different scenarios are iteratively optimized, optimal strategy library for multiple scenarios is generated, and the strategy library is updated and distributed.

[0013] As a further improvement to this technical solution, S1 specifically includes the following steps: completing the full-link network initialization of physical sampling sensors, edge acquisition nodes, and digital twin platform; establishing an end-to-end communication link; completing the one-to-one mapping of metadata of physical entities, sampling units, edge node hardware resources, and twin models; locking the correspondence between the state variables of the monitored objects and the model update variables; completing the initial global clock synchronization of physical sampling terminals, edge nodes, and twin platform based on the PTP hardware clock protocol; establishing a sub-microsecond unified reference time axis; collecting network card network interrupt distribution strategies, CPU core interrupt processing latency, data packet inbound queuing latency, and interrupt response interval data under three typical scenarios of edge node idle, rated load, and full load; generating an interrupt load-processing latency benchmark library; and calibrating the benchmark correspondence between physical sampling data timestamps and twin model state updates.

[0014] As a further improvement to this technical solution: S2 specifically includes the following steps: receiving high-frequency sampled data packets sent by the physical entity, completing basic parsing and caching of the data packets, stamping each data packet arriving at the edge node's network card with a network card hardware-level inbound timestamp, collecting in real time the number of network interrupts processed per unit time, the interrupt processing queue length, and the number of interrupt response timeouts for each CPU core of the edge node, calculating the interrupt load imbalance, comparing the interrupt load imbalance with a preset threshold, identifying the occurrence time, degree, and scope of the interrupt affinity deviation, comparing the data packet hardware inbound timestamp with the benchmark latency data in the benchmark library, calculating the end-to-end inbound queuing delay and latency jitter within a period, associating and matching the real-time calculated latency jitter data with the CPU core interrupt load data at the corresponding time, and establishing a mapping relationship between the interrupt load imbalance and latency jitter, wherein the calculation formula for the interrupt load imbalance is:

[0015]

[0016] in .

[0017] As a further improvement to this technical solution, S3 specifically includes the following steps: Preset two-level trigger thresholds for interrupt load imbalance and packet inbound delay jitter; compare the monitoring data uploaded by the sensing module with the preset thresholds in real time; initiate an adaptive scheduling process when either trigger condition is met; logically divide the edge node CPU cores to isolate a dedicated network interrupt handling core set; complete kernel parameter configuration; prohibit non-monitoring processes from occupying the CPU time slice of the dedicated core set; calculate the real-time scheduling weight for each CPU core in the dedicated interrupt handling core set; based on the calculated scheduling weight, adopt a weighted minimum load priority strategy to dynamically bind newly generated receive interrupts from the network card to the CPU core with the highest scheduling weight; perform dynamic migration for already bound high-load interrupts; after each scheduling is completed, perform a back-check of the scheduling effect within a sampling period; and perform secondary scheduling optimization for scenarios that do not meet the standards. The formula for calculating the scheduling weight during CPU verification is:

[0018]

[0019] in For the first Real-time scheduling weights of dedicated interrupt handling cores For the first The number of network interrupts handled per CPU core per unit of time. For the first The length of the interrupt handling queue for each CPU core. For the first Average interrupt response time per CPU core This is the queue length weighting coefficient. For response duration weighting coefficient, and All are preset positive numbers.

[0020] As a further improvement to this technical solution, S4 specifically includes the following steps: Based on the initially established PTP hardware clock reference, perform full-node periodic bidirectional hardware timestamp synchronization to correct the deviation caused by the fixed transmission delay of the link and clock drift, maintain the synchronization accuracy of the global reference time axis, calculate the accurate delay compensation amount for each sampled data packet based on the full-link delay data, generate a calibrated timestamp by superimposing the delay compensation amount on the original sampling timestamp of the data packet, set the calibrated timestamp as the sole triggering reference for the twin model state update, replacing the update mode based on the data packet reception timestamp, and verify the one-to-one correspondence between the timestamp sequence of physical sampling data, the physical state quantity sequence and the twin model state update sequence in each sampling update cycle, identify the sequence disorder and timestamp deviation exceeding the standard, and trigger the secondary compensation calibration process.

[0021] As a further improvement to this technical solution, S5 specifically includes the following steps: collecting core indicator data of the full-cycle synchronization effect, completing the quantitative evaluation of the system synchronization status, iteratively optimizing the scheduling threshold, affinity configuration strategy and latency compensation parameters under different scenarios based on the quantitative evaluation data, generating an optimal strategy library for multiple scenarios, and completing the update and distribution of the strategy library.

[0022] Compared with the prior art, the beneficial effects of the present invention are:

[0023] 1. This invention addresses the root cause of virtual-real synchronization errors by effectively resolving the packet inbound delay jitter caused by uneven CPU network interrupt handling at edge nodes through real-time perception of interrupt behavior and adaptive dynamic scheduling based on interrupt affinity. It also suppresses the generation of nondeterministic queuing delays. Furthermore, through a two-dimensional clock synchronization and state alignment calibration mechanism, it overcomes the shortcomings of traditional clock-only time synchronization schemes, covering the entire link latency in data transmission and processing. This achieves a strict correspondence between the physical world sampling timestamp and the state of the digital twin model, effectively eliminating lag and jitter issues during twin operation and significantly improving the accuracy and stability of virtual-real synchronization in the digital twin integrated monitoring system.

[0024] 2. This invention, through full-cycle quantitative evaluation of synchronization effects and closed-loop optimization of strategies, can adapt to different load states and different sampling frequencies of edge nodes. It can be deployed and applied without major modifications to the existing hardware architecture. While ensuring synchronization accuracy, it reduces the implementation cost of the solution, effectively improves the availability of the digital twin integrated monitoring system in high-frequency and high-precision monitoring scenarios, and expands the application boundaries of digital twin technology in various real-time monitoring and control scenarios.

[0025] The above description is merely an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention and to implement it according to the contents of the specification, the preferred embodiments of the present invention are described in detail below with reference to the accompanying drawings. Specific embodiments of the present invention are given in detail below with reference to the accompanying drawings. Attached Figure Description

[0026] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this application, illustrate exemplary embodiments of the invention and, together with their description, serve to explain the invention and do not constitute an undue limitation thereof. In the drawings:

[0027] Figure 1 This is a schematic diagram of the method structure for the virtual-real synchronization method of a comprehensive monitoring system based on digital twins. Detailed Implementation

[0028] The principles and features of the present invention are described below with reference to the accompanying drawings. The examples given are for illustrative purposes only and are not intended to limit the scope of the invention. The invention is described more specifically in the following paragraphs by way of example with reference to the accompanying drawings. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0029] Please see Figure 1 In this embodiment of the invention, the virtual-real synchronization method for a comprehensive monitoring system based on digital twins includes the following steps:

[0030] S1. System initialization and global benchmark calibration phase: Complete the full-link network initialization of the digital twin integrated monitoring system, establish communication links between physical sampling sensors, edge nodes, and the digital twin platform, complete the one-to-one mapping of metadata of physical entities, sampling units, edge node hardware resources, and twin models, complete the initial global clock synchronization of all nodes based on the PTP hardware clock protocol, establish a unified benchmark time axis, collect interrupt and delay benchmark data under multiple typical scenarios, and generate an interrupt load-processing delay benchmark library.

[0031] S2. Interruption behavior and latency jitter full-cycle perception stage: Receive high-frequency sampling data of physical entities, stamp each data packet with a network card hardware inbound timestamp, collect network interrupt processing data of each CPU core in real time, calculate interrupt load imbalance, identify interrupt affinity deviation, calculate data packet inbound queuing delay and latency jitter, and establish a mapping relationship between interrupt load imbalance and latency jitter.

[0032] S3, Interrupt affinity adaptive dynamic scheduling stage: two-level trigger thresholds are preset for interrupt load imbalance and packet inbound delay jitter. Real-time monitoring data is compared with the thresholds. When the trigger conditions are met, the CPU cores of the edge nodes are logically divided, the dedicated network interrupt processing core set is isolated, the real-time scheduling weight of each dedicated core is calculated, and the weighted minimum load priority strategy is adopted to complete the dynamic binding and migration of network card receive interrupts and CPU cores. The scheduling effect is checked and optimized again.

[0033] S4. In the dual-dimensional clock synchronization and state alignment calibration stage, perform full-node periodic hardware clock closed-loop calibration, correct link transmission delay and clock drift deviation, calculate the delay compensation amount for each sampled data packet, generate a calibration timestamp, set the calibration timestamp as the only triggering benchmark for the twin model state update, verify the consistency between the physical sampling sequence and the twin model update sequence, and trigger secondary compensation calibration for deviation exceeding the standard.

[0034] S5. In the closed-loop optimization and scenario adaptation stage of synchronization effect, core indicator data of synchronization effect throughout the entire cycle are collected, quantitative evaluation of system synchronization status is completed, scheduling and calibration parameters under different scenarios are iteratively optimized, multi-scenario optimal strategy library is generated, and the strategy library is updated and distributed.

[0035] Specifically, the functions of the core components and devices involved are as follows:

[0036] Physical sampling sensors are used to collect real-time operational status data of physical entities and generate high-frequency sampling data packets. They are the source of physical world state data collection.

[0037] Edge nodes are used to receive high-frequency sampling data uploaded by physical sampling sensors, perform network interrupt handling, data parsing, interrupt scheduling and preliminary latency calculation. They are the core relay nodes connecting the physical world and the digital twin platform. They have built-in hardware units such as multi-core CPUs and smart network cards to support interrupt handling and data forwarding functions.

[0038] A digital twin platform is used to carry a twin model corresponding to a physical entity, receive sampling data uploaded by edge nodes, and perform state updates of the twin model based on the calibrated timestamp to achieve state synchronization between the physical entity and the digital twin.

[0039] The PTP hardware clock protocol is used to provide high-precision initial clock synchronization for all nodes in the link, establish a globally unified time base, and solve the problem of inherent hardware clock deviation between different nodes.

[0040] The core execution logic and function of each step are as follows:

[0041] Step S1 is used to complete the full-link basic configuration before the system runs, establish the basic mapping relationship between the physical world and the digital world, build a globally unified time benchmark, and collect benchmark data in multiple scenarios to provide a basis for subsequent deviation identification and latency calculation.

[0042] Step S2 is used to monitor the network interrupt handling behavior and data packet transmission latency of edge node CPUs in real time, quantify the degree of imbalance in interrupt handling, identify interrupt affinity deviation problems, and establish the correlation between interrupt handling behavior and latency jitter, providing accurate data support for subsequent scheduling optimization.

[0043] Step S3 is used to perform CPU core resource isolation and dynamic interrupt scheduling for the identified interrupt affinity bias problem, thereby solving the data packet queuing congestion problem caused by unbalanced CPU interrupt processing from the root and eliminating the source of nondeterministic queuing delay.

[0044] Step S4 is used to compensate for the end-to-end latency of data packets on top of hardware clock synchronization, making up for the shortcomings of traditional methods that rely solely on clock synchronization, ensuring that the timestamp of the physical sampled data strictly corresponds to the state update time of the twin model, and avoiding lag and jitter problems in the twin.

[0045] Step S5 is used to monitor and evaluate the virtual-real synchronization effect of the system throughout its entire lifecycle. Based on actual operating data, the system operating parameters are iteratively optimized to adapt to different load scenarios and sampling scenarios, ensuring the stability of the synchronization effect throughout the system's entire lifecycle.

[0046] S1 specifically includes the following steps: completing the full-link network initialization of physical sampling sensors, edge acquisition nodes, and digital twin platform; establishing an end-to-end communication link; completing the one-to-one mapping of metadata of physical entities, sampling units, edge node hardware resources, and twin models; locking the correspondence between the state variables of the monitored objects and the model update variables; completing the initial global clock synchronization of physical sampling terminals, edge nodes, and twin platform based on the PTP hardware clock protocol; establishing a sub-microsecond unified reference time axis; collecting network card network interrupt distribution strategies, CPU core interrupt processing latency, data packet inbound queuing latency, and interrupt response interval data under three typical scenarios of edge node idle, rated load, and full load; generating an interrupt load-processing latency benchmark library; and calibrating the benchmark correspondence between physical sampling data timestamps and twin model state updates.

[0047] Specifically, the edge acquisition node is the same hardware device as the edge node in claim 1. The built-in smart network card is used to receive data packets from the physical sampling sensor, the built-in multi-core CPU is used to perform interrupt processing and data calculation, and the built-in storage unit is used to store the reference library data.

[0048] The sampling unit, which works in conjunction with the physical sampling sensor, is used to preprocess and package the raw data collected by the sensor to generate a high-frequency sampling data packet with the original sampling timestamp, ensuring the integrity of the sampling data and the accuracy of the timestamp.

[0049] The functions of each refinement step are as follows:

[0050] The full-link network initialization and end-to-end communication link establishment are used to ensure network connectivity between physical sampling terminals, edge nodes, and digital twin platforms, and to provide a stable communication channel for the transmission of high-frequency sampling data.

[0051] Metadata one-to-one mapping and state quantity correspondence locking are used to establish a one-to-one correspondence between the running state of physical entities, the data collected by sampling units, the hardware resources of edge nodes, and the state parameters of the twin model. This ensures that subsequent sampling data can accurately match the corresponding state update items of the twin model, avoiding the problem of data and model state mismatch.

[0052] The establishment of a sub-microsecond unified reference timeline is used to synchronize the hardware clocks of the three core nodes—physical sampling end, edge node, and twin platform—to sub-microsecond precision via the PTP hardware clock protocol, eliminating the inherent clock deviations between different nodes and providing a unified time reference for timestamp calculation and latency calculation across the entire link.

[0053] The system collects benchmark data for multiple typical scenarios and generates an interrupt load-processing latency benchmark library. This library is used to collect benchmark data related to interrupt processing and latency of edge nodes under different operating loads, clarify the normal operating parameter range under different load scenarios, and provide a standardized comparison benchmark for subsequent interrupt affinity deviation identification and latency jitter judgment.

[0054] The calibration of the benchmark correspondence between the timestamps of physical sampling data and the state update of the twin model is used to clarify the correspondence rules between the generation time of physical sampling data and the state update time of the twin model in unbiased scenarios, providing a benchmark reference for subsequent state alignment calibration.

[0055] S2 specifically includes the following steps: receiving high-frequency sampled data packets sent by physical entities, completing basic parsing and caching of data packets, stamping each data packet arriving at the edge node's network interface card (NIC) with a NIC hardware-level inbound timestamp, real-time collecting the number of network interrupts processed per unit time, interrupt processing queue length, and interrupt response timeouts for each CPU core at the edge node, calculating interrupt load imbalance, comparing the interrupt load imbalance with a preset threshold, identifying the occurrence time, degree, and scope of interrupt affinity deviation, comparing the data packet hardware inbound timestamp with the baseline latency data in the baseline library, calculating the end-to-end inbound queuing delay and latency jitter within a period, and associating and matching the real-time calculated latency jitter data with the corresponding CPU core interrupt load data to establish a mapping relationship between interrupt load imbalance and latency jitter. The formula for calculating interrupt load imbalance is as follows:

[0056]

[0057] in ;

[0058] Specifically, the edge node network card is a smart network card built into the edge node, used to receive high-frequency sampled data packets, mark the data packets with hardware-level incoming timestamps, and generate network interrupt signals corresponding to the data packet reception, which are then sent to the edge node CPU.

[0059] The edge node CPU cache unit is used to temporarily store the received high-frequency sampled data packets, ensuring that the data packets are not lost during parsing and forwarding, and guaranteeing the integrity of data transmission.

[0060] The functions of each refinement step are as follows:

[0061] High-frequency sampling data packet reception, parsing and buffering are used to complete the reception of physical sampling data, basic format parsing and temporary storage, to ensure the integrity of the sampling data, and to provide a complete data foundation for subsequent timestamp marking and delay calculation;

[0062] Hardware-level incoming timestamp tagging of network interface cards (NICs) is used to add a hardware timestamp based on a global reference time axis to the data packet at the first moment it arrives at the NIC. This avoids time deviation caused by software tagging, ensures the accuracy of the incoming timestamp, and provides an accurate time reference for subsequent latency calculations.

[0063] Real-time acquisition of CPU core interrupt handling data is used to continuously collect interrupt handling-related operational data of each CPU core, comprehensively understand the network interrupt handling load, processing capacity and operating status of each CPU core, and provide a complete data source for calculating interrupt load imbalance.

[0064] Interrupt load imbalance calculation and interrupt affinity deviation identification are used to calculate the degree of interrupt load distribution balance among CPU cores through a quantitative formula, compare the relevant information of interrupt affinity deviation with a preset threshold, and accurately locate the problem of interrupt handling imbalance.

[0065] The calculation of single-packet inbound queuing delay and latency jitter is used to accurately calculate the queuing delay and latency jitter of each data packet within a period by comparing the inbound timestamp of the data packet with the baseline latency data, and to quantify the impact of nondeterministic queuing delay.

[0066] The mapping relationship between interrupt load imbalance and latency jitter is established to clarify the correlation between the degree of interrupt handling imbalance and latency jitter amplitude, pinpoint the root cause of latency jitter, and provide a precise target basis for subsequent interrupt scheduling optimization.

[0067] The function and annotation of the core calculation formula:

[0068] This formula is used to quantify the degree of imbalance in network interrupt handling load among multiple CPU cores at an edge node. It is the core indicator for identifying interrupt affinity bias. The formula uses the calculation logic of the coefficient of variation to eliminate the influence of the total number of CPU cores and the overall load level on the judgment result, and can accurately reflect the balance of interrupt load distribution under different load scenarios.

[0069] The detailed annotations of each variable in the formula are as follows: This represents the interrupt load imbalance. The larger the value, the more uneven the interrupt load distribution among multiple CPU cores, and the more severe the interrupt affinity deviation. The closer the value is to 0, the more balanced the interrupt load distribution. The total number of CPU cores involved in network interrupt handling, i.e., the number of CPU cores allocated to edge nodes for handling network interrupts of the network interface card; For the first The number of network interrupts handled per CPU core per unit time is used to characterize the real-time interrupt handling load of a single CPU core. This is the average number of interrupts handled per unit time by all CPU cores involved in network interrupt handling, used to characterize the overall average interrupt handling load of all CPU cores.

[0070] S3 specifically includes the following steps: Preset two-level trigger thresholds for interrupt load imbalance and packet inbound latency jitter; compare the monitoring data uploaded by the sensing module with the preset thresholds in real time; initiate an adaptive scheduling process when either trigger condition is met; logically divide the edge node CPU cores to isolate a dedicated network interrupt handling core set; complete kernel parameter configuration; prohibit non-monitoring processes from occupying CPU time slices in the dedicated core set; calculate the real-time scheduling weight for each CPU core in the dedicated interrupt handling core set; based on the calculated scheduling weight, adopt a weighted minimum load priority strategy to dynamically bind newly generated receive interrupts from the network card to the CPU core with the highest scheduling weight; perform dynamic migration for already bound high-load interrupts; after each scheduling is completed, perform a scheduling effect review within a sampling period; and perform secondary scheduling optimization for scenarios that do not meet the standards. The formula for calculating the scheduling weight during CPU verification is as follows:

[0071]

[0072] in For the first Real-time scheduling weights of dedicated interrupt handling cores For the first The number of network interrupts handled per CPU core per unit of time. For the first The length of the interrupt handling queue for each CPU core. For the first Average interrupt response time per CPU core This is the queue length weighting coefficient. For response duration weighting coefficient, and All are preset positive integers;

[0073] Specifically, the edge node operating system kernel is used to execute the logical partitioning of CPU cores, interrupt affinity configuration, and process resource limits. It is the execution carrier for dynamic interrupt binding and migration, and can realize the binding configuration of network card interrupts with specified CPU cores.

[0074] The sensing module, which is the interrupt behavior and latency jitter sensing functional unit corresponding to claim 3, is used to provide real-time interrupt load and latency jitter monitoring data to the scheduling process and is the source of the trigger signal for starting the scheduling process;

[0075] The functions of each refinement step are as follows:

[0076] Two-level trigger threshold preset and real-time comparison are used to set the start conditions of the adaptive scheduling process. By using thresholds for two dimensions, namely interrupt load imbalance and latency jitter, it is ensured that the scheduling process can start in time when deviation problems occur, while avoiding the consumption of system resources caused by frequent scheduling.

[0077] CPU core logical partitioning and dedicated interrupt handling core set isolation are used to partition a dedicated core set for handling network interrupts from the CPU cores of edge nodes. Through kernel parameter configuration, non-monitored processes are prohibited from occupying the CPU time slice of this core set, ensuring that interrupt handling can obtain exclusive CPU resources, eliminating resource preemption by other processes for interrupt handling, and avoiding additional processing latency.

[0078] CPU verification scheduling weight calculation is used to comprehensively consider the interrupt handling load, queue backlog, and response speed of the CPU core through a quantitative formula, calculate the scheduling priority of each CPU core, and provide a precise quantitative basis for the dynamic binding and migration of interrupts.

[0079] The weighted least load priority strategy is implemented with dynamic interrupt binding and migration. Based on the calculated scheduling weight, the newly generated network card interrupts are allocated to the CPU core with the highest weight and lowest load. At the same time, interrupts already bound to high-load CPU cores are dynamically migrated to ensure that the interrupt load of all dedicated CPU cores is always balanced, thereby eliminating queuing congestion and nondeterministic latency caused by unbalanced interrupt handling from the root.

[0080] The scheduling effect feedback and secondary optimization are used to verify whether the interrupt load balancing and latency jitter meet the standards after each scheduling execution. For scenarios that do not meet the standards, secondary scheduling optimization is performed to ensure the effectiveness of the scheduling strategy and avoid the continued existence of deviation problems caused by scheduling failure.

[0081] The function and annotation of the core calculation formula:

[0082] This formula is used to comprehensively calculate the real-time scheduling weight of each dedicated interrupt handling core. The higher the weight value, the lower the interrupt handling load of the CPU core, the more sufficient the processing capacity, and the higher the scheduling priority. The formula comprehensively considers three core dimensions: the number of real-time interrupts handled by the CPU core, the length of the interrupt queue backlog, and the average interrupt response time. It can fully reflect the real-time processing capability of the CPU core and ensure the rationality of interrupt allocation.

[0083] The detailed annotations of each variable in the formula are as follows: For the first The real-time scheduling weight of a dedicated interrupt handling core. The larger the value, the higher the scheduling priority of that CPU core, and the more likely it is to be allocated new network card receive interrupts.

[0084] For the first The number of network interrupts handled per CPU core per unit time is used to characterize the real-time interrupt handling load of the CPU core. The larger the value, the higher the load.

[0085] For the first The interrupt handling queue length of each CPU core is used to characterize the interrupt backlog of the CPU core. The larger the value, the more interrupts are waiting to be processed and the longer the processing latency.

[0086] For the first The average interrupt response time of a CPU core is used to characterize the interrupt handling response speed of the CPU core. The larger the value, the slower the response speed and the less processing power.

[0087] This is the queue length weighting coefficient, used to adjust the influence of the interrupt handling queue length in the weight calculation. It is a preset normal number that can be adjusted according to the hardware performance of the edge node.

[0088] The response time weighting coefficient is used to adjust the proportion of the average interrupt response time in the weighting calculation. It is a preset normal number that can be adjusted according to the hardware performance of the edge node.

[0089] S4 specifically includes the following steps: Based on the initially established PTP hardware clock reference, perform full-node periodic bidirectional hardware timestamp synchronization to correct the deviation caused by the fixed transmission delay of the link and clock drift, maintain the synchronization accuracy of the global reference time axis, calculate the accurate delay compensation amount for each sampled data packet based on the full-link delay data, generate the calibrated timestamp by superimposing the delay compensation amount on the original sampling timestamp of the data packet, set the calibrated timestamp as the sole triggering reference for the state update of the twin model, replacing the update mode based on the data packet reception timestamp, and verify the one-to-one correspondence between the timestamp sequence of physical sampling data, the physical state quantity sequence and the state update sequence of the twin model within each sampling update cycle, identify the sequence disorder and timestamp deviation exceeding the standard, and trigger the secondary compensation calibration process;

[0090] Specifically, a twin model is a digital model deployed within a digital twin platform that corresponds one-to-one with a physical entity. It can update the model's state in real time based on sampled data and reproduce the real-time operating state of the physical entity. It is the core carrier of a digital twin system.

[0091] The functions of each refinement step are as follows:

[0092] The full-node periodic bidirectional hardware timestamp synchronization is used to continuously correct the time deviation caused by the fixed transmission delay of the link and the drift of the hardware clock during system operation, ensuring the long-term stability of the sub-microsecond synchronization accuracy of the global reference time axis, and providing a continuous and reliable reference for time calculation of the entire link.

[0093] The calculation of single packet delay compensation and the generation of calibrated timestamps are used to calculate the total delay generated during the entire link transmission for each sampled data packet, and add it to the original sampling timestamp of the data packet to generate a calibrated timestamp that is completely aligned with the physical sampling time. This fully covers the nondeterministic queuing delay introduced by the uneven interrupt handling and makes up for the shortcomings of the traditional clock synchronization method.

[0094] The twin model state update baseline setting is used to use the calibrated timestamp as the sole triggering baseline for twin model state updates, replacing the traditional update mode based on the data packet platform receiving timestamp. This ensures that the twin model state update time strictly corresponds to the physical entity sampling time, eliminating the twin lag problem caused by transmission delay.

[0095] Physical and twin sequence consistency verification is used to verify whether the time series and state quantity sequence of physical sampling data correspond one-to-one with the state update sequence of the twin model in each sampling update cycle, to ensure the accuracy of state synchronization between the physical world and the digital world, and to avoid twin jitter caused by state mismatch and sequence disorder.

[0096] The secondary compensation calibration process is triggered to immediately initiate secondary compensation calibration when timestamp deviations exceed the standard or sequence errors are detected, correcting the deviations and ensuring that the physical and twin states are always synchronized in accordance with accuracy requirements.

[0097] S5 specifically includes the following steps: collecting core indicator data of the full-cycle synchronization effect, completing the quantitative evaluation of the system synchronization status, iteratively optimizing the scheduling threshold, affinity configuration strategy and latency compensation parameters under different scenarios based on the quantitative evaluation data, generating an optimal strategy library for multiple scenarios, and completing the update and distribution of the strategy library.

[0098] Specifically, the functions of each detailed step are as follows:

[0099] The full-cycle synchronization effect core indicator data collection is used to continuously collect core indicator data such as interruption load balancing, data packet inbound latency jitter, physical and twin timestamp alignment error, and twin model state update lag during system operation, providing a complete data source for the quantitative evaluation of system synchronization status.

[0100] The system synchronization status quantitative evaluation is used to quantitatively determine the virtual-real synchronization effect of the system based on the collected core indicator data, clarify the synchronization accuracy and operational stability of the system in different scenarios, and identify the optimization space of parameter configuration.

[0101] Multi-scenario parameter iterative optimization is used to iteratively optimize scheduling trigger thresholds, interrupt affinity configuration strategies, and latency compensation-related parameters based on quantitative evaluation results and for different load scenarios and sampling frequency scenarios, to find the optimal parameter configuration for each scenario and improve the system's adaptability to different operating scenarios.

[0102] The system generates, updates, and distributes a multi-scenario optimal strategy library. This library is used to systematically archive the optimal parameter configurations, scheduling strategies, and calibration strategies for different scenarios, generating a reusable optimal strategy library. It also completes the real-time updates of the strategy library and distributes it to edge nodes and digital twin platforms, ensuring that the system can automatically match the optimal strategy according to the real-time operating scenario and guarantee the stability of the virtual-real synchronization effect throughout the entire lifecycle.

[0103] The method of use and working principle of this invention are as follows:

[0104] Usage: First, complete the full-link network initialization of the digital twin integrated monitoring system, establish communication links between physical sampling sensors, edge nodes, and the digital twin platform, complete the metadata mapping and binding between physical entities and the twin model, complete the initial global clock synchronization of all nodes based on the PTP hardware clock protocol, collect benchmark data under multiple typical scenarios and generate corresponding benchmark libraries, and complete all preparations before system operation. After the system is officially running, it continuously receives high-frequency sampling data from physical entities, marks each data packet with a hardware inbound timestamp, collects network interrupt handling data of each CPU core of the edge nodes in real time, calculates interrupt load imbalance and identifies interrupt affinity deviation, and calculates the inbound queuing delay and latency jitter of data packets, establishes the mapping relationship between the two, and then, according to the preset trigger threshold, triggers the system when the trigger conditions are met. The system logically partitions the CPU cores of edge nodes and isolates them with dedicated interrupt handling core sets. It calculates the real-time scheduling weight of each dedicated core, adopts a weighted minimum load priority strategy to dynamically bind and migrate network card receive interrupts and CPU cores, and performs feedback and secondary optimization of scheduling effects. It synchronously performs periodic hardware clock closed-loop calibration of all nodes, calculates the delay compensation amount for each sampled data packet and generates a calibrated timestamp, and uses the calibrated timestamp as the sole triggering benchmark for twin model state updates. It verifies the consistency between the physical sampling sequence and the twin model update sequence, triggers secondary compensation calibration for scenarios where deviation exceeds the standard, continuously collects core index data of synchronization effect throughout the entire system operation cycle, completes the quantitative evaluation of the system synchronization status, iteratively optimizes scheduling and calibration parameters under different scenarios, generates a multi-scenario optimal strategy library, and completes updates and distribution.

[0105] Working principle: First, a globally unified time base is established through PTP hardware clock synchronization across all nodes, providing a standardized reference for time calculation and state alignment throughout the entire link. Simultaneously, a benchmark reference system for interrupt load and processing latency is established through multi-scenario benchmark calibration, providing a basis for subsequent deviation identification. During system operation, the interrupt handling behavior of edge node CPUs and the latency jitter status of data packets are sensed in real time to quantify the degree of interrupt load imbalance, establish a strong correlation between interrupt affinity deviation and latency jitter, accurately pinpoint the root cause of latency jitter, and then isolate CPU core resources and interrupt affinity... The adaptive dynamic scheduling eliminates the queuing congestion problem caused by uneven CPU interrupt handling at its root, suppresses the generation of nondeterministic queuing delays, and at the same time, through a two-dimensional calibration mechanism that combines hardware clock closed-loop calibration and single packet delay compensation calibration, it makes up for the shortcomings of traditional clock synchronization methods that rely solely on clock synchronization, fully covers residual transmission and processing delays, ensures strict correspondence between physical sampling timestamps and twin model state update times, and finally achieves adaptive adaptation of the synchronization scheme to different operating scenarios through full-cycle synchronization effect evaluation and strategy iteration optimization, continuously ensuring the accuracy and stability of the system's virtual-real synchronization.

[0106] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention in any way. Those skilled in the art can readily implement the present invention based on the description and drawings above. However, any modifications, alterations, and variations made by those skilled in the art without departing from the scope of the present invention using the disclosed technical content are equivalent embodiments of the present invention. Furthermore, any modifications, alterations, and variations made to the above embodiments based on the essential technology of the present invention are still within the protection scope of the present invention.

Claims

1. A method for synchronizing virtual and real data in a comprehensive monitoring system based on digital twins, characterized in that, Includes the following steps: S1. System initialization and global benchmark calibration phase: Complete the full-link network initialization of the digital twin integrated monitoring system, establish communication links between physical sampling sensors, edge nodes, and the digital twin platform, complete the one-to-one mapping of metadata of physical entities, sampling units, edge node hardware resources, and twin models, complete the initial global clock synchronization of all nodes based on the PTP hardware clock protocol, establish a unified benchmark time axis, collect interrupt and delay benchmark data under multiple typical scenarios, and generate an interrupt load-processing delay benchmark library. S2. Interruption behavior and latency jitter full-cycle perception stage: Receive high-frequency sampling data of physical entities, stamp each data packet with a network card hardware inbound timestamp, collect network interrupt processing data of each CPU core in real time, calculate interrupt load imbalance, identify interrupt affinity deviation, calculate data packet inbound queuing delay and latency jitter, and establish a mapping relationship between interrupt load imbalance and latency jitter. S3, Interrupt affinity adaptive dynamic scheduling stage: two-level trigger thresholds are preset for interrupt load imbalance and packet inbound delay jitter. Real-time monitoring data is compared with the thresholds. When the trigger conditions are met, the CPU cores of the edge nodes are logically divided, the dedicated network interrupt processing core set is isolated, the real-time scheduling weight of each dedicated core is calculated, and the weighted minimum load priority strategy is adopted to complete the dynamic binding and migration of network card receive interrupts and CPU cores. The scheduling effect is checked and optimized again. S4. In the dual-dimensional clock synchronization and state alignment calibration stage, perform full-node periodic hardware clock closed-loop calibration, correct link transmission delay and clock drift deviation, calculate the delay compensation amount for each sampled data packet, generate a calibration timestamp, set the calibration timestamp as the only triggering benchmark for the twin model state update, verify the consistency between the physical sampling sequence and the twin model update sequence, and trigger secondary compensation calibration for deviation exceeding the standard. S5. In the closed-loop optimization and scenario adaptation stage of synchronization effect, core indicator data of synchronization effect throughout the entire cycle are collected, quantitative evaluation of system synchronization status is completed, scheduling and calibration parameters under different scenarios are iteratively optimized, optimal strategy library for multiple scenarios is generated, and the strategy library is updated and distributed.

2. The method for synchronizing virtual and real data in a comprehensive monitoring system based on digital twins according to claim 1, characterized in that, S1 specifically includes the following steps: completing the full-link network initialization of physical sampling sensors, edge acquisition nodes, and digital twin platform; establishing an end-to-end communication link; completing the one-to-one mapping of metadata of physical entities, sampling units, edge node hardware resources, and twin models; locking the correspondence between the state variables of the monitored objects and the model update variables; completing the initial global clock synchronization of physical sampling terminals, edge nodes, and twin platform based on the PTP hardware clock protocol; establishing a sub-microsecond unified reference time axis; collecting network card network interrupt distribution strategies, CPU core interrupt processing latency, data packet inbound queuing latency, and interrupt response interval data under three typical scenarios of edge node idle, rated load, and full load; generating an interrupt load-processing latency benchmark library; and calibrating the benchmark correspondence between physical sampling data timestamps and twin model state updates.

3. The method for synchronizing virtual and real data in a comprehensive monitoring system based on digital twins according to claim 1, characterized in that, S2 specifically includes the following steps: receiving high-frequency sampled data packets sent by physical entities, completing basic parsing and caching of data packets, stamping each data packet arriving at the edge node's network card with a network card hardware-level inbound timestamp, collecting in real time the number of network interrupts processed per unit time, the interrupt processing queue length, and the number of interrupt response timeouts for each CPU core of the edge node, calculating the interrupt load imbalance, comparing the interrupt load imbalance with a preset threshold, identifying the occurrence time, degree, and scope of impact of interrupt affinity deviation, comparing the data packet hardware inbound timestamp with the benchmark latency data in the benchmark library, calculating the end-to-end inbound queuing delay and latency jitter within a period, associating and matching the real-time calculated latency jitter data with the CPU core interrupt load data at the corresponding time, and establishing a mapping relationship between interrupt load imbalance and latency jitter, wherein the calculation formula for interrupt load imbalance is: in .

4. The method for synchronizing virtual and real data in a comprehensive monitoring system based on digital twins according to claim 1, characterized in that, S3 specifically includes the following steps: Preset two-level trigger thresholds for interrupt load imbalance and packet inbound delay jitter; compare the monitoring data uploaded by the sensing module with the preset thresholds in real time; initiate an adaptive scheduling process when either trigger condition is met; logically divide the edge node CPU cores to isolate a dedicated network interrupt handling core set; complete kernel parameter configuration; prohibit non-monitoring processes from occupying the CPU time slice of the dedicated core set; calculate the real-time scheduling weight for each CPU core in the dedicated interrupt handling core set; based on the calculated scheduling weight, adopt a weighted minimum load priority strategy to dynamically bind newly generated receive interrupts from the network card to the CPU core with the highest scheduling weight; perform dynamic migration for already bound high-load interrupts; after each scheduling is completed, perform a scheduling effect review within a sampling period; and perform secondary scheduling optimization for scenarios that do not meet the standards. The formula for calculating the scheduling weight during CPU verification is: in For the first Real-time scheduling weights of dedicated interrupt handling cores For the first The number of network interrupts handled per CPU core per unit of time. For the first The length of the interrupt handling queue for each CPU core. For the first Average interrupt response time per CPU core This is the queue length weighting coefficient. For response duration weighting coefficient, and All are preset positive numbers.

5. The method for synchronizing virtual and real data in a comprehensive monitoring system based on digital twins according to claim 1, characterized in that, S4 specifically includes the following steps: Based on the initially established PTP hardware clock reference, perform full-node periodic bidirectional hardware timestamp synchronization to correct the deviation caused by the fixed transmission delay of the link and clock drift, maintain the synchronization accuracy of the global reference time axis, calculate the accurate delay compensation amount for each sampled data packet based on the full-link delay data, generate a calibrated timestamp by superimposing the delay compensation amount on the original sampling timestamp of the data packet, set the calibrated timestamp as the sole triggering reference for the twin model state update, replacing the update mode based on the data packet reception timestamp, and verify the one-to-one correspondence between the timestamp sequence of physical sampling data, the physical state quantity sequence and the twin model state update sequence in each sampling update cycle, identify the sequence disorder and timestamp deviation exceeding the standard, and trigger the secondary compensation calibration process.

6. The method for synchronizing virtual and real data in a comprehensive monitoring system based on digital twins according to claim 1, characterized in that, The S5 specifically includes the following steps: collecting core indicator data of the full-cycle synchronization effect, completing the quantitative evaluation of the system synchronization status, iteratively optimizing the scheduling threshold, affinity configuration strategy and latency compensation parameters under different scenarios based on the quantitative evaluation data, generating an optimal strategy library for multiple scenarios, and completing the update and distribution of the strategy library.

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