Hardware synchronization method, network, device and medium for a compute cell array

Abstract

The application discloses a hardware synchronization method for a computing unit array, a network, a device and a medium, and the method comprises the following steps: generating a synchronization request containing an aggregation level field and a local barrier identifier for a computing unit; forwarding the synchronization request along a hierarchical synchronization network composed of one-dimensional and two-dimensional synchronization nodes alternately; at each level of the synchronization node, judging whether to execute aggregation at the current level according to the aggregation level field; if yes, executing an aggregation condition detection according to the node type and the request state recorded in the local register file; the aggregation condition of the one-dimensional synchronization node is receiving at least two requests from the same direction, and the aggregation condition of the two-dimensional synchronization node is receiving requests from the horizontal and vertical directions; when the aggregation condition is met, generating a local wake-up response and stopping the upward propagation of the request. The application can flexibly adapt to the spatial distribution of the computing unit, and improves the synchronization efficiency and the system scalability.

Description

Technical Field

[0001] This invention relates to the field of hardware synchronization network technology, and in particular to a hardware synchronization method, network, device and medium for computing unit arrays. Background Technology

[0002] In massively parallel computing systems such as on-chip multi-core processors and GPUs, there are numerous arrays of computing units. During the execution of parallel programs, these computing units often need to synchronize at a certain program point (i.e., a barrier point) to ensure that all participating computing units have completed the tasks of the previous stage before moving on to the next stage.

[0003] In existing technologies, there are several main ways to achieve this barrier synchronization. One is to broadcast through a mesh network or on-chip network (NoC) to spread synchronization requests and wake-up responses to all relevant nodes. Another is to use a centralized synchronization manager, where a central node is responsible for collecting synchronization requests from all computing units and issuing a unified wake-up signal after collection. A third method is to construct a static barrier tree network, where requests converge step-by-step along the tree path towards the root node.

[0004] However, as the scale of computing unit arrays continues to increase, the above-mentioned schemes have gradually revealed some inherent defects. First, the broadcast scheme generates a large amount of redundant network traffic, especially during response feedback. Without a special mechanism, it often needs to be broadcast again, causing network congestion and wasted power. Second, the single centralized synchronization manager is prone to forming performance hotspots. When a large number of computing units initiate synchronization simultaneously, the central node becomes a bottleneck. Furthermore, even small-scale local synchronization must pass through a remote central node, resulting in long paths, high latency, and poor scalability. Finally, the static tree-shaped network structure is rigid and makes it difficult to flexibly select the nearest and most efficient aggregation point based on the dynamic set of computing units actually participating in synchronization and their spatial distribution in the two-dimensional array, leading to low synchronization efficiency. Summary of the Invention

[0005] This invention provides a hardware synchronization method, network, device, and medium for computing unit arrays, which can solve the problems of central hotspots, broadcast storms, poor scalability, and inability to flexibly aggregate according to the spatial distribution of computing units in related synchronization mechanisms. The technical solution is as follows: On the one hand, a hardware synchronization method for computing unit arrays is provided, the method comprising: A synchronization request is generated for multiple computing units to be synchronized. The synchronization request includes a synchronization validity signal, an aggregation level field, and a local barrier identifier. The synchronization request is forwarded upwards through the fractional synchronization network, which is recursively composed of alternating one-dimensional and two-dimensional synchronization nodes. Each level of synchronization node is of a single type: a one-dimensional synchronization node or a two-dimensional synchronization node. Each level of synchronization node includes a local register file, which records the synchronization request status from each input port, indexed by at least a portion of the barrier identifier. The synchronization request status is distinguished according to the direction of the input port. At each synchronization node, the current level bit of the aggregation level field is used to determine whether to perform an aggregation operation at this level: If not, the aggregation level field is shifted, and the synchronization request is forwarded to a higher-level synchronization node. If so, then query the local registered files of the current synchronization node; Based on the type of the node at this level and the synchronization request status recorded in the local register file, the corresponding aggregation condition detection is performed, and when the aggregation condition is met, a local wake-up response is generated and the further uplink propagation of the synchronization request is stopped. Wherein, if it is a one-dimensional synchronization node, the aggregation condition is: in the local register file, the register bit corresponding to the barrier identifier has been set, and there are at least two different computing units that submit the synchronization request through the input port of the one-dimensional synchronization node in the same direction. If it is a two-dimensional synchronization node, the aggregation condition is: in the local register file, the register bit corresponding to the barrier identifier has been set, and there is at least one computing unit submitting the synchronization request through the horizontal input port, and at the same time there is at least one computing unit submitting the synchronization request through the vertical input port.

[0006] On the other hand, a hardware synchronization network for computing unit arrays is provided, the device comprising: Multiple computing units are used to generate synchronization requests, which include a synchronization validity signal, an aggregation level field, and a local barrier identifier; Multiple one-dimensional synchronization nodes and multiple two-dimensional synchronization nodes are arranged alternately and recursively to form a split-form synchronization network, wherein each level of synchronization node is of a single type: a one-dimensional synchronization node or a two-dimensional synchronization node. Each level of the synchronization node includes: a data receiving path, a local storage file, a control core, and a data sending path, wherein... A data receiving path is used to receive synchronization requests from lower-level nodes or the computing unit. The local storage file records the synchronization request status from each input port, indexed by at least some bits of the barrier identifier, and the synchronization request status is distinguished by the input port direction. The control core is used for: Determine whether to perform an aggregation operation at this level based on the current level bit of the aggregation level field: If not, the receiving data path will shift the aggregation level field and then forward the synchronization request to a higher-level synchronization node through the sending data path. If so, query the local registered file and, based on the type of this level node and the synchronization request status recorded in the local registered file, perform the corresponding aggregation condition check: When the local level is a one-dimensional synchronization node, the aggregation condition is: in the local register file, the register bit corresponding to the barrier identifier has been set, and there are at least two different computing units submitting the synchronization request through the input port in the same direction of the one-dimensional synchronization node. When the local level is a two-dimensional synchronization node, the aggregation condition is: in the local register file, the register bit corresponding to the barrier identifier has been set, and at least one computing unit submits the synchronization request through the horizontal input port, and at the same time, at least one computing unit submits the synchronization request through the vertical input port. A data transmission path is used to generate and output a local wake-up response when the aggregation condition is met, and to abort further uplink propagation of the synchronization request.

[0007] On the other hand, a computer device is provided, the computer device including a memory and a processor, the memory for storing computer programs, and the processor for executing the computer programs stored in the memory to implement the steps of the hardware synchronization method for computing unit arrays described above.

[0008] On the other hand, a computer-readable storage medium is provided, wherein a computer program is stored therein, and when the computer program is executed by a processor, it implements the steps of the hardware synchronization method for a computing unit array described above.

[0009] The technical solution provided by this invention can bring at least the following beneficial effects: By adopting a distributed synchronization network and aggregation hierarchy fields, synchronization requests from different spatial ranges can be aggregated on the hierarchy nodes that best match the spatial distribution of their participating computing units, rather than all of them having to be reported to a single central node. This effectively distributes the synchronization load, avoids performance hotspots on the central node, and improves the synchronization throughput and scalability of the entire system. By defining different aggregation conditions for one-dimensional and two-dimensional synchronization nodes and designing a mechanism for handling concurrent requests, the correctness of synchronization determination in complex scenarios is ensured, and state disorder or repeated wake-ups caused by race conditions are avoided. Attached Figure Description

[0010] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 This is a flowchart of an efficient hardware synchronization method for computing unit arrays provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of the overall structure of an efficient hardware synchronization network for computing unit arrays according to an embodiment of the present invention; Figure 3 This is a schematic diagram of the internal structure of a synchronization node according to an embodiment of the present invention; Figure 4 This is a schematic diagram of the hierarchical consumption and aggregation judgment process of the aggregation level field according to an embodiment of the present invention; Figure 5 This is a schematic diagram of the remote registered file reverse routing record and response return according to an embodiment of the present invention; Figure 6 This is a schematic diagram of a network recursive expansion structure according to an embodiment of the present invention; Figure 7 This is a schematic diagram of the software request generation recursive partitioning process according to an embodiment of the present invention; Figure 8 This is a hardware architecture diagram of a computer device provided in an embodiment of the present invention. Detailed Implementation

[0012] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are some embodiments of the present invention, but not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0013] As mentioned above, the embodiments of this application aim to provide an efficient hardware synchronization method and network for computing unit arrays, in order to solve the synchronization bottleneck problems existing in large-scale parallel computing systems in the background art, such as the hotspot problem of centralized managers, the traffic storm problem of broadcast networks, and the lack of flexibility of static tree structures. The specific implementation of the above concept is described below.

[0014] Please refer to Figure 1 This invention provides an efficient hardware synchronization method for computing unit arrays, the method comprising: Step 100: Generate a synchronization request for multiple computing units to be synchronized. The synchronization request includes a synchronization validity signal, an aggregation level field, and a local barrier identifier. Step 101: Forward the synchronization request upwards along the modular synchronization network level by level. The modular synchronization network is recursively composed of alternating one-dimensional synchronization nodes and two-dimensional synchronization nodes. Each level of synchronization node is of a single type: a one-dimensional synchronization node or a two-dimensional synchronization node. Each level of synchronization node includes a local register file, which records the synchronization request status from each input port, indexed by at least a portion of the barrier identifier. The synchronization request status is distinguished according to the direction of the input port. Step 102: At each synchronization node, determine whether to perform an aggregation operation at this level based on the current level bit of the aggregation level field. If not, proceed to step 103, shift the aggregation level field, and then continue to forward the synchronization request to a higher-level synchronization node; If so, proceed to step 104 to query the local registered files of the current synchronization node; and Based on the type of the node at this level and the synchronization request status recorded in the local register file, the corresponding aggregation condition detection is performed, and when the aggregation condition is met, a local wake-up response is generated and the further uplink propagation of the synchronization request is stopped. Wherein, if it is a one-dimensional synchronization node, the aggregation condition is: in the local register file, the register bit corresponding to the barrier identifier has been set, and there are at least two different computing units that submit the synchronization request through the input port of the one-dimensional synchronization node in the same direction. If it is a two-dimensional synchronization node, the aggregation condition is: in the local register file, the register bit corresponding to the barrier identifier has been set, and there is at least one computing unit submitting the synchronization request through the horizontal input port, and at the same time there is at least one computing unit submitting the synchronization request through the vertical input port.

[0015] In this embodiment of the invention, a distributed hardware network structure and a synchronization request carrying aggregated location information are used to distribute the synchronization aggregation operation to hardware nodes that spatially match the set of computing units participating in the synchronization. This effectively distributes the synchronization load, avoids performance hotspots of the central node, and improves the synchronization throughput and scalability of the entire system.

[0016] The following description Figure 1 and Figure 2 The execution method for each step is shown.

[0017] First, for step 100, a synchronization request is generated for multiple computing units to be synchronized. The synchronization request includes a synchronization validity signal, an aggregation level field, and a local barrier identifier. First, as attached Figure 2 As shown, when multiple computing units need to synchronize, a synchronization request 151 is generated for these units. This synchronization request 151 is a specially encoded hardware signaling message containing at least three key pieces of information: a synchronization validity signal to identify the validity of the signaling; an aggregation level field that encodes the target network level that the synchronization operation expects to complete; and a local barrier identifier to distinguish different synchronization events that the same computing unit may participate in. Through this design, the synchronization control information is completely encapsulated within the request itself, laying the foundation for subsequent distributed processing.

[0018] Step 101: Forward the synchronization request upwards along the modular synchronization network level by level. The modular synchronization network is recursively composed of alternating one-dimensional synchronization nodes and two-dimensional synchronization nodes. Each level of synchronization node is of a single type: a one-dimensional synchronization node or a two-dimensional synchronization node. Each level of synchronization node includes a local register file, which records the synchronization request status from each input port, indexed by at least a portion of the barrier identifier. The synchronization request status is distinguished according to the direction of the input port. Furthermore, after generating synchronization request 151, this request is injected into a fractional synchronization network and forwarded upwards along the network level by level. This fractional synchronization network is the core physical foundation of this scheme. Its topology is not a simple bus or tree structure, but rather consists of alternating and recursive arrangements of one-dimensional synchronization nodes 121 and two-dimensional synchronization nodes 131. This alternating and recursive structure allows it to naturally map the spatial characteristics of a two-dimensional computing unit array. Each level of synchronization nodes in the network, such as the first-level synchronization (1D) 102 or the second-level synchronization (2D) 103, has a single node type: either all one-dimensional synchronization nodes or all two-dimensional synchronization nodes. This design simplifies the processing logic at each level.

[0019] During the hierarchical forwarding of synchronization request 151, each level of synchronization node processes it. Specifically, each synchronization node, whether it is a one-dimensional synchronization node 121 or a two-dimensional synchronization node 131, has a local register file 212 configured internally. This local register file 212 uses at least some bits of the barrier identifier carried in the synchronization request as an address index to record and track the status of synchronization requests received from each input port of that node. To achieve aggregation judgment, this status information is stored separately according to the direction of the input port. For example, requests from east-bound ports and requests from west-bound ports will occupy different status bits in the local register file 212. This design solves the problem of unclear aggregation logic caused by the inability to distinguish the direction of request source in traditional schemes.

[0020] Step 102: At each synchronization node, determine whether to perform an aggregation operation at this level based on the current level bit of the aggregation level field. If not, proceed to step 103, shift the aggregation level field, and then continue to forward the synchronization request to a higher-level synchronization node; If so, proceed to step 104 to query the local registered files of the current synchronization node; and Based on the type of the node at this level and the synchronization request status recorded in the local register file, the corresponding aggregation condition detection is performed, and when the aggregation condition is met, a local wake-up response is generated and the further uplink propagation of the synchronization request is stopped. Wherein, if it is a one-dimensional synchronization node, the aggregation condition is: in the local register file, the register bit corresponding to the barrier identifier has been set, and there are at least two different computing units that submit the synchronization request through the input port of the one-dimensional synchronization node in the same direction. If it is a two-dimensional synchronization node, the aggregation condition is: in the local register file, the register bit corresponding to the barrier identifier has been set, and there is at least one computing unit submitting the synchronization request through the horizontal input port, and at the same time there is at least one computing unit submitting the synchronization request through the vertical input port.

[0021] Specifically, at each synchronization node, the aggregation level field in synchronization request 151 is first checked. The current level bit (e.g., the least significant bit) of this field is used to determine whether the aggregation operation needs to be performed by the node at this level. This is a crucial decision step, allowing the synchronization endpoint to be dynamically specified. If the current level bit indicates that aggregation is not needed at this level, it means the aggregation point is at a higher level. In this case, the node logically shifts the aggregation level field (e.g., shifts it left by one bit) so that the next-level node can read the new current level bit, and then forwards the updated synchronization request to the higher-level synchronization node. By consuming the aggregation level field level by level, programmable routing of synchronization requests in the network is achieved.

[0022] If the current level bit of the aggregation level field indicates that aggregation needs to be performed by the node at this level, then the process of synchronization request 151 terminates its propagation at this level. At this point, the local register 212 is queried, using the barrier identifier in the synchronization request as an index, to check if other synchronization request records from different input ports with the same barrier identifier already exist in the local register; the arrival status of other synchronization requests with the same barrier identifier as the current request is also checked. This is to determine whether all synchronization requests with the same barrier identifier from different input ports have reached the node at this level.

[0023] Subsequently, nodes perform corresponding aggregation condition checks based on their type (one-dimensional or two-dimensional). This node-type-based differentiated aggregation logic is key to the solution's ability to adapt to the locality of two-dimensional arrays. Aggregation condition checks are performed based on the direction-distinguished synchronization request status recorded in the local register file 212. If the aggregation condition is met, it means that a synchronization request with the same barrier identifier from a different input port has arrived at the local node. The node then generates a local wake-up response 152 and aborts further uplink propagation of the synchronization request 151. This abort operation is crucial; it limits synchronization traffic to a necessary local scope, preventing all requests from flooding the global root node, thus effectively alleviating network congestion and central hotspots.

[0024] Specifically, the definition of the aggregation condition is closely related to the node type. If the current node is a one-dimensional synchronization node 121, its aggregation condition is designed as follows: First, the register bit corresponding to the current barrier identifier in the local register file 212 has been set, indicating that at least one request has arrived; second, at least two different computational units have submitted synchronization requests through the input port in the same direction of this one-dimensional synchronization node. This condition typically corresponds to the scenario of synchronizing a row or column of computational units, for example, requests from the east and west converge at this node.

[0025] Conversely, if the current node is a two-dimensional synchronization node 131, its aggregation conditions are more complex to match the synchronization requirements in two-dimensional space. This condition is designed as follows: similarly, the register bit corresponding to the barrier identifier in the local register file 212 needs to be set; but more importantly, there must be at least one computing unit submitting a synchronization request through the horizontal input port, and simultaneously at least one computing unit submitting a synchronization request through the vertical input port. This condition corresponds to the scenario of synchronizing computing units within a rectangular or arbitrary two-dimensional region, for example, where requests from horizontal and vertical network branches converge at this node. In this way, this method cleverly maps the distribution characteristics of computing tasks in two-dimensional physical space into the hardware aggregation logic of the synchronization network.

[0026] Furthermore, in a preferred embodiment, the generation and return mechanism of the local wake-up response 152 has been optimized to achieve precise routing and avoid broadcasting. See also... Figure 2 and Figure 3 When a synchronization node 200 determines that the aggregation condition is met and prepares to generate a local wake-up response 152, its behavior will differ depending on whether it is the root synchronization node 104. For a non-root node (e.g., Figure 2 The one-dimensional synchronization node 121 or two-dimensional synchronization node 131 in the system has a local register file 212 and a remote register file 213 configured inside. This remote register file 213 is the key to realizing the return transmission.

[0027] When generating the local wake-up response 152, the hierarchy field of the local wake-up response is set to the physical hierarchy of the current node, and carries the same barrier identifier as the synchronization request 151 that triggered this wake-up. Then, the remote register file 213 is queried. This remote register file 213 records the source direction code of the request saved when the request was forwarded upward. Based on this queried direction code, the control core 211 instructs the data path 202 to send the local wake-up response 152 back to the corresponding lower-level node 421 only along the previously recorded source direction (i.e., the reverse path). This process is as follows: Figure 5As shown in stage two (420), the wake-up response sent by the superior node 423 reaches the local node 422. After querying the remote registered file 424, the local node accurately sends the response back to the subordinate node 421. Through this mechanism, the wake-up response forms a precise, point-to-point return path, instead of being broadcast to all subordinate nodes, which greatly saves network bandwidth and power consumption.

[0028] Conversely, when the synchronization node is the root synchronization node 104, since it is already at the highest level of the synchronization network and there is no path for further upward forwarding, it does not need to record reverse routing information. Therefore, the root synchronization node 104 does not need to configure the remote register file 213, thus saving chip area. When the aggregation conditions of the root synchronization node 104 are met, the local wake-up response 152 it generates will be directly output to the downstream network it connects to, and finally distributed to the computing unit array 101. This special treatment of the root node is a further optimization of the overall architecture.

[0029] In another preferred embodiment, the error handling capability of the wake-up response 152 is enhanced. Specifically, in addition to the wake-up signal, hierarchy, and barrier identifier, an error flag is added to the wake-up response. This error flag is set by the node currently generating the wake-up response (the responding node) under specific abnormal conditions. These abnormal conditions may include: detecting a barrier identifier mismatch (e.g., inconsistent IDs during neighbor node synchronization), signature invalidation in the remote register (possibly due to timeout or erroneous overwriting), overflow of the internal request or response FIFO, or loss of direction encoding during backhaul. When these hardware-level abnormalities occur, the node's control core 211 will set this error flag to valid when generating the wake-up response.

[0030] This wake-up response carrying the error information will be passed down the reverse path of the fractional synchronization network, just like a normal wake-up response. Ultimately, this error flag will be received by the computing unit 111 that initially initiated the synchronization or by the global management unit in the system. Upon receiving the response with the error flag, the processor can immediately trigger the corresponding exception handling mechanism, such as interrupting the service routine, logging the error, retrying the synchronization operation, or terminating the current task. By transmitting hardware-level exception states to the software through the synchronization network itself, this solution establishes a complete hardware-to-software error reporting and handling closed loop, significantly improving the system's robustness and debuggability.

[0031] Furthermore, the processing flow for synchronization request 151 during the uplink process if the aggregation conditions are not met has been refined. Please refer to [link / reference]. Figure 5In phase one (410), when a synchronization request arrives at a non-root local node 412 and its aggregation level field indicates that the aggregation point is at a higher level, the request needs to be forwarded upwards. Before forwarding, the local node 412 performs a crucial recording operation. It records relevant information about the current synchronization request in its remote register 414, including: the current synchronization level, the barrier identifier of the synchronization request, and the source direction encoding of the synchronization request (e.g., which port it came from, east, west, south, or north). This recording process can be understood as leaving a mark along the path as the request is forwarded upwards. After completing the recording, the node shifts the aggregation level field and forwards the request to the parent node 413.

[0032] The purpose of leaving a marker along the path is to ensure that the response can be routed back along the same path when it is sent down in the future (152). When the parent node finally completes the aggregation and sends a wake-up response, the response is passed down level by level. Each node, upon receiving the response, uses the level and barrier identifier in the response as an index to query its own remote register 414, finds the marker left earlier, and thus knows which direction to pass the response to for the next lower-level node. In this way, the problem of unclear response return paths and reliance on broadcasting is solved. As for the root node, since it is the highest level, it will not propagate upwards. Therefore, when it receives a request, even if the aggregation conditions are not met (e.g., waiting for requests from other branches), it only updates the state in its local register and does not need to, and cannot, record the direction code in the remote register.

[0033] In another preferred embodiment, a specific software implementation method is provided for the generation process of synchronization request 151, i.e., how to intelligently generate a request containing an aggregation hierarchy field and a barrier identifier from a user-specified set of computing units. Please refer to [link to relevant documentation]. Figure 7 This method is typically implemented by a driver or runtime library, and its core idea is to recursively partition based on the two-dimensional physical coordinates of the computing units. The method first executes step S1 (601) to obtain the set of two-dimensional coordinates of all computing units participating in this synchronization.

[0034] Next, in step S2 (602), the geometric span of the coordinate set is determined. Specifically, it is determined whether the coordinate span of the set in the horizontal direction exceeds a preset horizontal threshold and whether the coordinate span in the vertical direction exceeds a preset vertical threshold. These two thresholds are usually related to the hierarchical structure of the synchronization network. Based on the determination results, there are several cases: when the coordinate span of the two-dimensional coordinate set in the horizontal direction exceeds the horizontal threshold and the coordinate span in the vertical direction does not exceed the vertical threshold, then step S3 (607) is executed, which means that the current set of computing units is widely distributed in the horizontal direction and is suitable for aggregation in a horizontal aggregation level (i.e., 1D node layer) of the synchronization network. Therefore, the horizontal level bit is set in the aggregation level field of all corresponding computing units. Then, the two-dimensional coordinate set is divided into two subsets, left and right, and each subset is taken as the two-dimensional coordinate set. For each subset, steps S1 (601) to S6 (610) are recursively returned to be executed. This process is represented by step 611.

[0035] When the coordinate span of the two-dimensional coordinate set exceeds the vertical threshold in the vertical direction and does not exceed the horizontal threshold in the horizontal direction, step S4 (608) is executed. This is similar to the case of exceeding the horizontal threshold, only the direction is different. A vertical level position is set in the aggregation level field, and the set is divided into two subsets, upper and lower. Each subset is used as the two-dimensional coordinate set, and steps S1 (601) to S6 (610) are recursively returned for each subset. This process is represented by step 611.

[0036] When the coordinate span of the two-dimensional coordinate set exceeds the corresponding threshold in both the horizontal and vertical directions, step S5 (609) is executed. This indicates that the set of computing units is a "large" two-dimensional region, which is most suitable for aggregation in a two-dimensional aggregation node (2D node). Therefore, the horizontal and vertical level bits are set simultaneously in the aggregation level field of all corresponding computing units, without any division, and the set is directly marked as a two-dimensional node, and step S6 (610) is executed.

[0037] Finally, when the coordinate span of the two-dimensional coordinate set in both the horizontal and vertical directions does not exceed the corresponding threshold, that is, when the span of any (sub)set in both the horizontal and vertical directions does not exceed the threshold, it means that the recursion has reached the "leaf" level, and step S6 (610) is executed. In this step, the method determines the final aggregation node type based on the final distribution shape of the computing units in this small set (e.g., a straight line, a point, or a small rectangle), assigns a unique local barrier identifier to each computing unit in the set, and finally sets its synchronization valid signal, thereby generating a complete synchronization request 151. Through this recursive division from macro to micro, the software can synchronize tasks for computing units of arbitrary shapes, generate optimal hardware synchronization requests, and ensure that the synchronization operation is always completed on the hardware node closest to the participant, thus achieving software and hardware co-optimization.

[0038] Furthermore, the aggregation node types determined during the recursive partitioning process described above are explained in more detail. When the recursive process ends and proceeds to step S6 (610), the aggregation node type to which it belongs needs to be determined based on the distribution of computational units within the final subset. If the two-dimensional coordinate set contains multiple computational units in both the horizontal and vertical directions (e.g., a 2x2 or larger rectangular block), it is best suited to be processed by a two-dimensional synchronization node 131 and is therefore marked as a two-dimensional node type. If the set contains multiple computational units only in the horizontal direction (i.e., all computational units are in the same row), it is marked as a one-dimensional horizontal node type, and its synchronization task will be completed by a one-dimensional synchronization node 121 that processes the horizontal direction. Similarly, if it contains multiple computational units only in the vertical direction (in the same column), it is marked as a one-dimensional vertical node type, and its synchronization task will be completed by a one-dimensional synchronization node 121 that processes the vertical direction.

[0039] In a special case, if the final subset contains only one computational unit in both the horizontal and vertical directions—meaning it has only one member—it is an isolated participant. In this case, it cannot form an aggregation on its own and is therefore not marked as any aggregation node. Its synchronization requests will be generated directly by the computational unit and will depend on the aggregation being completed on the corresponding parent node when it merges with other subsets in higher-level recursive calls. This fine-grained node type classification ensures that each spatially distributed set of computational units can be mapped to the most suitable hardware aggregation resources.

[0040] Furthermore, the execution order of the recursive process is defined to ensure determinism and reproducibility. When a set is divided into left and right subsets, there are several ways to implement this. One approach is to use the left subset as the new two-dimensional coordinate set and the right subset as the new two-dimensional coordinate set, simultaneously executing the recursive process from steps S1 to S6 on both subsets until both are decomposed into indivisible leaf nodes. Another approach is to first use the left subset as the new two-dimensional coordinate set and execute the recursive process from steps S1 to S6 on it until the left subset is completely processed and decomposed into indivisible leaf nodes. Then, the right subset is used as the two-dimensional coordinate set, and the same recursive process from steps S1 to S6 is executed. A third approach is to first use the right subset as the new two-dimensional coordinate set and execute the recursive process from steps S1 to S6 on it until the right subset is completely processed and decomposed into indivisible leaf nodes. Then, the left subset is used as the two-dimensional coordinate set, and the same recursive process from steps S1 to S6 is executed.

[0041] Similarly, when a set is divided into two subsets, the upper subset and the lower subset can be used as the new two-dimensional coordinate set, and the recursive process from steps S1 to S6 can be performed on both subsets simultaneously until both subsets are decomposed into indivisible leaf nodes. Alternatively, the upper subset can be used as the new two-dimensional coordinate set, and the recursive process from steps S1 to S6 can be performed on it until it is completely processed and decomposed into indivisible leaf nodes. Then, the lower subset can be used as the two-dimensional coordinate set, and the recursive process from steps S1 to S6 can be performed in the same way. Alternatively, the lower subset can be used as the new two-dimensional coordinate set, and the recursive process from steps S1 to S6 can be performed on it until it is completely processed and decomposed into indivisible leaf nodes. Then, the upper subset can be used as the two-dimensional coordinate set, and the recursive process from steps S1 to S6 can be performed in the same way.

[0042] This explicit recursive order eliminates the ambiguity of the algorithm, ensuring that for any given set of input coordinates, a unique and definite set of aggregation level fields and barrier identifiers can always be generated.

[0043] In a preferred embodiment, the aggregation condition detection logic within the one-dimensional synchronization node 121 and the two-dimensional synchronization node 131 is described in more detail. For the one-dimensional synchronization node, its core task is to determine whether synchronization requests with the same barrier identifier have been received from at least two computational units in the same straight-line direction as the one-dimensional synchronization node. This is achieved through its internal local register file 212. This local register file maintains a state for synchronization requests from the same input port channel (e.g., all ports coming from the east), indexed by at least a portion of the barrier identifier. When the first synchronization request with the barrier identifier arrives, the corresponding first register bit is set from its initial state to a valid state; specifically, the corresponding first register bit in the local register file is set from its initial invalid state (e.g., 0) to a valid state (e.g., 1). This is equivalent to recording the first arriving synchronization request. When a subsequent synchronization request carrying the same barrier identifier arrives again from the same direction, it is checked whether this first register bit is in a valid state. If the first register bit is detected to be in a valid state, it means that both synchronization requests have arrived, the aggregation condition is met, and a local wake-up response 152 is immediately generated. If the first register bit is detected to be in an invalid state (which should theoretically not happen unless there is a logical error), its state is maintained and the system waits. This state-flipping-based detection mechanism is highly efficient, requiring only simple read, modify, and write operations to complete the aggregation judgment.

[0044] For the two-dimensional synchronization node 131, its aggregation logic needs to handle both horizontal and vertical dimensions simultaneously. Specifically, the synchronization request status of each computing unit from the horizontal input port channel connected to the two-dimensional synchronization node can be recorded in a local register file, indexed by at least some bits of the barrier identifier; the synchronization request status of each computing unit from the vertical input port channel connected to the two-dimensional synchronization node can also be recorded in a local register file, indexed by at least some bits of the barrier identifier; similarly, a local register file 212 is used to maintain the status of requests from the horizontal and vertical input port channels respectively. For example, a second register bit is used to record the request status from the horizontal direction, and a third register bit is used to record the request status from the vertical direction, both indexed by the same barrier identifier. When a request from the horizontal direction arrives, the second register bit is set; when a request from the vertical direction arrives, the third register bit is set. The aggregation condition of the two-dimensional node is defined as follows: the aggregation condition is satisfied if and only if both the second register bit and the third register bit, indexed by the same barrier identifier, are set. Furthermore, to ensure true two-dimensional aggregation, the scheme implicitly requires that the computational units triggering the horizontal channel state and the computational units triggering the vertical channel state must be different physical computational units, and their requests must originate from different physical paths. This design ensures that two-dimensional nodes are only activated when cross-dimensional synchronization is truly needed.

[0045] In hardware implementation, a challenging issue is concurrent access. A preferred embodiment provides a solution to the concurrent conflict problem during the query of local register 212. When multiple input ports submit synchronization requests with the same barrier identifier within the same clock cycle, failure to process these requests may result in repeated state bit flipping or multiple wake-up responses, leading to logical errors. To address this, this solution introduces an arbitration mechanism. When this occurs, only the first arriving synchronization request (e.g., based on a static priority of port number or physical distance) is allowed to trigger the setting operation of the corresponding direction register bit. For subsequent synchronization requests with the same barrier identifier arriving within the same cycle, a bypass or ignore control signal is generated, prohibiting them from writing to local register 212. In this way, it is ensured that in any given clock cycle, only one request can successfully update the state for the same barrier identifier, thus avoiding directional state confusion or repeated wake-ups caused by concurrent access and guaranteeing the atomicity of the synchronization operation.

[0046] In one alternative implementation, to further optimize local synchronization on a very small scale, the concept of a neighbor synchronization node is introduced. This neighbor synchronization node is positioned between two physically adjacent computing units, serving as a fast channel.

[0047] When two adjacent computing units simultaneously submit synchronization requests with identical barrier identifiers, the neighboring synchronization node bypasses the entire fractional synchronization network, directly generates a local wake-up response (152), identifies the hierarchy field in the local wake-up response as the neighbor hierarchy, and immediately sends the local wake-up response (152) back to both computing units, simultaneously terminating any uplink propagation of the synchronization request. This design significantly reduces the latency of synchronization between adjacent units. On the other hand, if the neighboring synchronization node detects inconsistencies in the barrier identifiers of the two requests, this typically indicates a programming error. In this case, the neighboring synchronization node outputs an error signal to terminate the synchronization process and notifies the upper-level nodes of the fractional synchronization network of the error signal for recording and processing. The introduction of this neighboring node adds a highly efficient low-level optimization to the entire synchronization system.

[0048] To make the hardware processing logic of the aggregation level field more efficient, a preferred encoding method is to use low-bit progressive consumption encoding. In this method, each bit of the aggregation level field corresponds to a synchronization level. For example, bit 0 corresponds to level 0, bit 1 corresponds to level 1, and so on. When a synchronization node processes a synchronization request, it does not need to parse the entire field, but only needs to read the current level bit corresponding to its physical level. If the bit is 1, the current level aggregation is executed; if it is 0, it is ignored. The remaining high-order bits in the field can be used to indicate the final aggregation root level. With this encoding method, each time a synchronization request is forwarded to the next level, the hardware logic automatically shifts the aggregation level field one bit to the left. Thus, when the request reaches the next level node, the original bit 1 becomes the new current level bit (i.e., bit 0), and is thus read by the next level node. This shift operation cleverly implements progressive control of progressive aggregation judgment, and the hardware implementation is very simple, requiring only a shifter.

[0049] In the entire fractional synchronization network, there is at least one root synchronization node 104, located at the top of the network. In a preferred embodiment, the behavior of the root node is specifically defined. When the root synchronization node 104 receives a synchronization request indicating that the aggregation level field is root-level, it directly executes its local aggregation judgment logic. Unlike non-root nodes, the root node does not need to record the direction code of the request source in its remote register file when processing such requests, because it is already the final node, and there are no higher-level nodes to forward to. Naturally, there is no need to prepare reverse routing information for higher-level nodes. When the root node detects that all requests from participating computing units (from its various subordinate branches) have arrived, it generates a global wake-up response and broadcasts it downwards to the entire network. Conversely, if the root node detects that at least one request from a participating computing unit has not arrived, it generates a global error response and sends it back along the source direction of all received synchronization requests to notify the relevant computing units of synchronization failure. This special treatment of the root node simplifies the top-level design and provides the ultimate guarantee for global synchronization.

[0050] To support computing arrays of varying sizes, the hardware synchronization network of this invention is designed to be parameterizable and recursively scalable. See also... Figure 6 The hierarchical structure of the distributed synchronous network expands recursively in proportion to the size of the two-dimensional computing unit array. Specifically, for a scale of 2... n ×2 n The computing unit array, the synchronization network contains n aggregation levels, each aggregation level is recursively composed of the sub-synchronization network of the previous level and a root synchronization node. For example... Figure 6 As shown, to achieve a larger-scale synchronization network, multiple lower-level sub-synchronization networks can be used as the previous-level sub-networks, aggregated through a higher-level root synchronization node, thus recursively constructing a complete n-level hierarchical structure. For example, Figure 6 The diagram shows four 4×4 subnetworks (i.e., 4×4 subnetwork A 511, 4×4 subnetwork B 512, 4×4 subnetwork C 513, and 4×4 subnetwork D 514) and a top-level root synchronization node 530, which together recursively form a larger-scale 16×16 synchronization network 520, corresponding to n=4 (i.e., 2^n × 10 ... 4 ×2 4 In an alternative implementation, the attached... Figure 6The markers 501, 502, 503, and 504 in the diagram schematically represent the lower-level synchronization nodes and connections that constitute each 4×4 sub-network. For clarity, their internal structure is not detailed in the diagram. To accommodate this parameterized recursive expansion, the resources within each synchronization node, particularly the capacity of the local register (212) and remote register (213) (i.e., how many concurrent barrier identifiers it can support), as well as the number of its input ports, are dynamically configured based on the number of input ports and the aggregation range of its level. Specifically, synchronization nodes at lower levels, due to their smaller aggregation range but needing to handle more local parallel tasks, have their register capacity and number of input ports configured to larger values; while higher-level synchronization nodes closer to the root node, due to their aggregation range covering the entire network but having fewer concurrent identifiers, have their resource capacity adjusted accordingly. Through this dynamic configuration method linked to level and aggregation range, this scheme can support the parameterized expansion of the synchronization network without redesigning the overall network architecture, thus flexibly adapting to expansion from 2×2 to 2×4. n ×2 n Arrays of computing units of different sizes.

[0051] Please see Figure 2 and Figure 3 This application also provides a hardware synchronization network for computing unit arrays. This network is the physical carrier of the above-described method, and its structure is tightly coupled with the method flow.

[0052] The network includes multiple computing units 111 and 112, as well as multiple one-dimensional synchronization nodes 121 and multiple two-dimensional synchronization nodes 131. The computing units 111 and 112 are the initiators of synchronization and are responsible for generating synchronization requests 151. The synchronization requests include a synchronization validity signal, an aggregation level field, and a local barrier identifier. Multiple one-dimensional synchronization nodes 121 and multiple two-dimensional synchronization nodes 131 are arranged alternately and recursively to form a fractional synchronization network. For example, as... Figure 1 As shown, the computing unit array 101 is first connected to the first-level synchronization (1D) 102, then to the second-level synchronization (2D) 103, and finally converges to the root synchronization node 104. This structure ensures that the type of each synchronization node (such as 102 or 103) is uniform, simplifying design and verification.

[0053] Each level of synchronization node 200, whether 1D or 2D type, has a similar internal microarchitecture. For example... Figure 2As shown, it mainly includes a data receiving path 201, a control core 211, a local register file 212, and a data sending path 202. The data receiving path 201 is responsible for receiving synchronization requests 151 from lower-level nodes or directly from the computing unit. The control core 211 and the local register file 212 are located within the processing logic 210 of this synchronization node.

[0054] Local register 212 records the synchronization request status from each input port, indexed by at least some bits of the barrier identifier, and the synchronization request status is distinguished by the direction of the input port. The control core 211 is the core unit for executing synchronization logic. It is responsible for parsing the aggregation level field in the received synchronization request 151 and determining whether to perform an aggregation operation at this level based on the current level bit of the aggregation level field. If the determination result is "no" (i.e., not to aggregate at this level), the control core 211 instructs the receive data path 201 to shift the aggregation level field, and then forwards the synchronization request to a higher-level synchronization node through the send data path 202. This process corresponds to... Figure 4 The path is 301→302→304→305.

[0055] If the judgment result is "yes" (i.e., aggregation at this level), the control core 211 will immediately query the local register 212. The local register 212 serves the same purpose as described in the method description; it records the arrival status of synchronization requests in different directions, indexed by the barrier identifier. The control core 211 will then perform the corresponding aggregation condition checks based on the synchronization request status recorded in the local register.

[0056] When the aggregation condition is detected (e.g., a 1D node detects two requests in the same direction, or a 2D node detects requests in the horizontal and vertical directions), the control core 211 generates and outputs a local wake-up response 152 via the data transmission path 202. Simultaneously, it sends a control signal to halt the upward propagation of the original synchronization request 151. This process corresponds to... Figure 4 The path is 301→302→303→306. Through this hardware-level collaborative work, an efficient, flexible, and scalable hardware synchronization mechanism is achieved.

[0057] It should be noted that the hardware synchronization network for computing unit arrays provided in the above embodiments is only an example of the division of the above functional modules. In practical applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above. In addition, the hardware synchronization network for computing unit arrays provided in the above embodiments and the hardware synchronization method embodiment for computing unit arrays belong to the same concept, and the specific implementation process is detailed in the method embodiment, which will not be repeated here.

[0058] The following specific embodiment, which integrates multiple technical features of the present invention, will fully demonstrate the workflow and overall technical effects of the invention. Assume that in a high-performance GPU integrating the synchronization network of the present invention, a computational thread block needs to perform a synchronization operation. This thread block contains 32 computational units, which are physically distributed across an 8x4 two-dimensional array area. This embodiment will fully describe the entire process from software-initiated synchronization to hardware wake-up.

[0059] First, the GPU driver or runtime library (software layer) captures synchronization instructions such as `syncthreads()` and obtains the physical coordinates (an 8x4 coordinate set) of the 32 computing units participating in the synchronization. The software executes the aforementioned recursive partitioning algorithm to generate individual synchronization requests 151 for these 32 computing units. Since the horizontal span (8) and vertical span (4) of the set are relatively large, the algorithm may determine a two-dimensional synchronization node 131 located at network layer 2 as the main aggregation point for this synchronization, and may specify a one-dimensional synchronization node 121 as an intermediate aggregation point for certain subsets (such as each row) at layer 1. Finally, the software generates a synchronization request for each computing unit containing a specific aggregation layer field (encoding the aggregation requirements of layer 1 and layer 2) and the same local barrier identifier.

[0060] Subsequently, these 32 computing units simultaneously inject the generated synchronization requests 151 into the fractional synchronization network. Taking one request as an example, it first arrives at a one-dimensional synchronization node 121 in the first-level synchronization (1D) 102 it is connected to. The control core 211 of this node checks the aggregation level field of the request and finds that the current level (level 1) requires aggregation. Therefore, the propagation of the request is paused, and the control core queries the local register file 212. As requests from other computing units in the same row arrive one after another, the aggregation conditions of the one-dimensional synchronization node 121 (e.g., requests from both the east and west directions arrive) are met. At this time, the 1D node does not immediately generate a wake-up response because the aggregation level field also indicates a higher-level aggregation requirement. Instead, the 1D node generates a new, aggregated synchronization request representing all units in this row, records the source direction of the aggregation request (from the computing unit below) in its remote register file 414, and then forwards this new aggregation request upwards to the two-dimensional synchronization node 131 in the second-level synchronization (2D) 103.

[0061] Synchronization requests from computational units in other rows of the 8x4 array underwent a similar process. Ultimately, the four aggregation requests representing these four rows all arrived at the same two-dimensional synchronization node 131, which served as the primary aggregation point. The control core 211 of this 2D node examined the requests and found that the current level (level 2) required aggregation, and that this was the final aggregation level. It queried the local register 212, and with the arrival of all four aggregation requests, its two-dimensional aggregation conditions (e.g., requests from different vertical branches had all arrived) were met. At this point, the two-dimensional synchronization node 131 generated a local wake-up response 152. This response carried the same barrier identifier as the original request.

[0062] Next comes the wake-up response 152 feedback phase. The control core 211 of the two-dimensional synchronization node 131 queries its remote register file 424 and finds the previously saved source direction codes based on the barrier identifier. It then precisely sends the wake-up response 152 to the corresponding lower-level one-dimensional synchronization nodes 121 in these four directions via the data transmission path 202. Each one-dimensional synchronization node 121, upon receiving the wake-up response, also queries its own remote register file and then precisely feeds back the response to all the computing units in the row it represents. Finally, all 32 computing units that initially initiated the synchronization received the wake-up response, and the synchronization was completed. Throughout the entire process, the wake-up signal was not broadcast to any irrelevant nodes in the network.

[0063] To demonstrate robustness, suppose one computational unit generates a barrier identifier different from the other 31 units due to a software error. When its synchronization request reaches the first-level one-dimensional synchronization node 121, the node will find that it cannot find a matching synchronization request for this erroneous barrier identifier in its local register file 212. After a timeout or a conflict is detected, the one-dimensional synchronization node 121 generates a special wake-up response in which the error flag is set. This response carrying error information is sent back to the erroneous computational unit along the path from which the error request originated, while the other 31 computational units may also receive the error response due to timeouts. In this way, the software layer can quickly locate the cause and approximate location of the synchronization failure.

[0064] As can be seen from the complete process described above, this embodiment combines multiple technical features, including intelligent request generation by software, hierarchical aggregation logic in hardware, state matching based on local registers, and precise response feedback based on remote registers, to achieve a highly efficient, scalable, and robust hardware synchronization system. Compared to traditional solutions, its comprehensive technical advantages are: First, distributed aggregation significantly reduces the pressure on the central node and synchronization latency; second, precise feedback greatly reduces network traffic and power consumption; third, through software and hardware collaboration, the synchronization mechanism can flexibly adapt to computing tasks of any shape and scale; and fourth, the built-in error detection and reporting mechanism improves the reliability and debuggability of the entire parallel computing system.

[0065] Embodiments of this application also provide a computer device, please refer to... Figure 7 The computer device includes a processor and a memory, the memory storing at least one instruction, at least one program, code set, or instruction set, wherein the at least one instruction, at least one program, code set, or instruction set is loaded and executed by the processor to implement a hardware synchronization method for a computing unit array provided in the above-described method embodiments.

[0066] Embodiments of this application also provide a computer-readable storage medium storing at least one instruction, at least one program, code set, or instruction set, wherein the at least one instruction, at least one program, code set, or instruction set is loaded and executed by a processor to implement a hardware synchronization method for computing unit arrays provided in the above-described method embodiments.

[0067] For ease of description, the above systems or devices are described separately as various modules or units based on their functions. Of course, in implementing this application, the functions of each unit can be implemented in one or more software and / or hardware components.

[0068] As can be seen from the above description of the embodiments, those skilled in the art can clearly understand that this application can be implemented by means of software plus necessary general-purpose hardware platforms. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in various embodiments or some parts of the embodiments of this application.

[0069] Finally, it should be noted that in this document, relational terms such as first, second, third, and fourth are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0070] The above description is only a preferred embodiment of this application. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of this application, and these improvements and modifications should also be considered within the scope of protection of this application.

Claims

1. A hardware synchronization method for computing unit arrays, characterized in that, The method includes: A synchronization request is generated for multiple computing units to be synchronized. The synchronization request includes a synchronization validity signal, an aggregation level field, and a local barrier identifier. The synchronization request is forwarded upwards through the fractional synchronization network, which is recursively composed of alternating one-dimensional and two-dimensional synchronization nodes. Each level of synchronization node is of a single type: a one-dimensional synchronization node or a two-dimensional synchronization node. Each level of synchronization node includes a local register file, which is indexed by at least some bits of the barrier identifier and records the synchronization request status from each input port. The synchronization request status is distinguished according to the direction of the input port. At each synchronization node, the current level bit of the aggregation level field is used to determine whether to perform an aggregation operation at this level: If not, the aggregation level field is shifted, and the synchronization request is forwarded to a higher-level synchronization node. If so, then query the local registered files of the current synchronization node; Based on the type of the node at this level and the synchronization request status recorded in the local register file, the corresponding aggregation condition detection is performed, and when the aggregation condition is met, a local wake-up response is generated and the further uplink propagation of the synchronization request is stopped. Wherein, if it is a one-dimensional synchronization node, the aggregation condition is: in the local register file, the register bit corresponding to the barrier identifier has been set, and there are at least two different computing units that submit the synchronization request through the input port in the same direction of the one-dimensional synchronization node. If it is a two-dimensional synchronization node, the aggregation condition is: in the local register file, the register bit corresponding to the barrier identifier has been set, and there is at least one computing unit submitting the synchronization request through the horizontal input port, and at the same time there is at least one computing unit submitting the synchronization request through the vertical input port.

2. The method as described in claim 1, characterized in that, The generation of the local wake-up response includes: When the synchronization node is a non-root node, the synchronization node also includes remote registered files; Set the level field of the local wake-up response to the physical level of the current synchronization node, and carry the same barrier identifier as the synchronization request; According to the source direction encoding of the synchronization request recorded in the remote register file, the local wake-up response is transmitted back to the lower-level node with the recorded source direction along the reverse path of the fractional synchronization network. When the synchronization node is the root node, the synchronization node is not configured with a remote register file, and the local wake-up response is directly output to the computing unit array.

3. The method as described in claim 1, characterized in that, Also includes: If no aggregation condition is found to be satisfied, then: When the synchronization node is a non-root node, the synchronization node also includes remote registered files; The current synchronization level, barrier identifier, and direction code of the synchronization request source are recorded in the remote register file, and the request is forwarded upward after shifting the aggregation level field. When the synchronization node is the root node, the synchronization request propagation is directly stopped, and the direction code is not recorded.

4. The method as described in claim 1, characterized in that, Generating the synchronization request includes: Step S1: Obtain the set of two-dimensional coordinates of the computing units participating in the synchronization; Step S2: Determine whether the two-dimensional coordinate set exceeds the horizontal threshold in the horizontal direction and whether the coordinate span in the vertical direction exceeds the vertical threshold. When the coordinate span of the two-dimensional coordinate set in the horizontal direction exceeds the horizontal threshold and the coordinate span in the vertical direction does not exceed the vertical threshold, step S3 is executed; Step S3: Set the horizontal level position in the aggregation level field of all corresponding calculation units, and divide the two-dimensional coordinate set into two subsets, left and right, and recursively execute steps S1 to S6 for each subset as the two-dimensional coordinate set. When the coordinate span of the two-dimensional coordinate set in the vertical direction exceeds the vertical threshold and the coordinate span in the horizontal direction does not exceed the horizontal threshold, step S4 is executed; Step S4: Set the vertical level position in the aggregation level field of all corresponding calculation units, and divide the two-dimensional coordinate set into two subsets, and recursively execute steps S1 to S6 for each subset as the two-dimensional coordinate set. When the coordinate span of the two-dimensional coordinate set exceeds the corresponding threshold in both the horizontal and vertical directions, step S5 is executed; Step S5: Simultaneously set the horizontal and vertical level positions in the aggregation level field of all corresponding calculation units, without making any division, directly mark the set as a two-dimensional node, and execute step S6. When the coordinate span of the two-dimensional coordinate set in both the horizontal and vertical directions does not exceed the corresponding threshold, step S6 is executed; Step S6: Determine the aggregation node type based on its distribution pattern, assign a local barrier identifier to each computing unit in the two-dimensional coordinate set, set its synchronization validity signal and aggregation level field, and generate the synchronization request.

5. The method as described in claim 4, characterized in that, The aggregation node types include: If the two-dimensional coordinate set contains multiple computational units in both the horizontal and vertical directions, it is marked as a two-dimensional node; If the two-dimensional coordinate set contains multiple computational units only in the horizontal direction, it is marked as a one-dimensional horizontal node; If the two-dimensional coordinate set contains multiple computational units only in the vertical direction, it is marked as a one-dimensional vertical node; If the two-dimensional coordinate set contains only one computational unit in both the horizontal and vertical directions, it is not marked as any aggregation node, and its synchronization request is directly generated by that computational unit.

6. The hardware synchronization method according to claim 1, characterized in that, For a one-dimensional synchronization node, determining that synchronization requests with the same barrier identifier have been received from at least two computing units in the same straight direction as the one-dimensional synchronization node includes: The synchronization request status of each computing unit from the same input port channel connected to the one-dimensional synchronization node is recorded by using at least some bits of the barrier identifier as an index in the local registered file. In response to the arrival of the first synchronization request with the barrier identifier, the corresponding first register bit is set from the initial state to the valid state; In response to the arrival of a subsequent synchronization request with the same barrier identifier, check whether the first register bit is in a valid state; If the detection result is valid, the aggregation condition is determined to be met, and a local wake-up response is generated. If invalid, maintain the registered bit state and continue to wait for subsequent requests.

7. The hardware synchronization method according to claim 1, characterized in that, For a two-dimensional synchronization node, determining that it has received synchronization requests from at least one computing unit in the horizontal direction and at least one computing unit in the vertical direction, all having the same barrier identifier, includes: The synchronization request status of each computing unit from the horizontal input port channel connected to the two-dimensional synchronization node is recorded by using at least some bits of the barrier identifier as an index in the local register file. The synchronization request status of each computing unit from the vertical input port channel connected to the two-dimensional synchronization node is recorded by using at least some bits of the barrier identifier as an index in the local registered file. The aggregation condition is satisfied if and only if the second register bit corresponding to the horizontal channel and the third register bit corresponding to the vertical channel are both set. The computing units corresponding to the horizontal and vertical channels are different, and their synchronization requests all originate from different physical computing units.

8. The method as described in claim 1, characterized in that, The query of the local registered files of the current synchronization node includes: When multiple input ports submit synchronization requests with the same barrier identifier within the same clock cycle, only the first arriving synchronization request is allowed to trigger the setting operation of the corresponding direction register bit. For subsequent synchronization requests with the same barrier identifier that arrive in the same period, a bypass or ignore control signal is generated to prevent them from being written to the local register file, in order to avoid direction state confusion or repeated wake-ups caused by concurrent access.

9. The method as described in claim 1, characterized in that, Also includes: Set up a neighbor synchronization node between two adjacent computing units; When two adjacent computing units submit the synchronization request at the same time and their barrier identifiers are the same, the neighbor synchronization node directly generates a local wake-up response and identifies the level field in the local wake-up response as the neighbor level, and terminates the uplink propagation of the synchronization request. When the barrier identifiers of the two adjacent computing units are inconsistent, the neighbor synchronization node outputs an error signal to terminate the synchronization process and notifies the upper-layer node of the fractional synchronization network of the error signal.

10. The method as described in claim 1, characterized in that, The aggregation level field adopts a low-bit progressive consumption encoding method, with each bit corresponding to a synchronization level. When a node processes a synchronization request, it only reads the current level bit to determine whether to execute the current level aggregation, while the remaining high bits are used to indicate the final aggregation root level. Each time the synchronization request is forwarded to the next higher level, the aggregation level field is shifted left by one bit, so that the next node reads the new current level bit, thereby realizing progressive control of aggregation judgment at each level.

11. The method as described in claim 1, characterized in that, The split-form synchronization network includes at least one root synchronization node. When the root synchronization node receives a synchronization request that is indicated as root level by the aggregation level field, it directly performs a local aggregation judgment without recording the direction encoding of the request source in the remote storage file. When the root synchronization node detects that all requests from the computing units participating in the synchronization have arrived, it generates a global wake-up response and broadcasts it downwards. When the root synchronization node detects that a request from at least one computing unit participating in the synchronization has not arrived, it generates a global error response and sends it back along the source direction of all received synchronization requests.

12. The method as described in claim 2, characterized in that, The wake-up response also includes an error flag, wherein: The error flag is set by the current responding node when generating the wake-up response, and is used to indicate the abnormality that occurred in the process of processing the synchronization request, including: barrier identifier mismatch, remote register signature failure, FIFO overflow or direction code loss; The error flag is transmitted along the reverse path of the fractional synchronization network along with the wake-up response, and is eventually received by the computing unit or system management unit that initiated the synchronization and triggers the corresponding exception handling mechanism.

13. The method according to claim 1, characterized in that, The hierarchical structure of the fractional synchronization network expands recursively in proportion to the size of the two-dimensional computing unit array. For a size of 2 n ×2 n The computing unit array, the synchronization network contains n aggregation levels, each aggregation level is recursively composed of the sub-synchronization network of the previous level and a root synchronization node; The capacity of the local and remote registers of each synchronization node is dynamically configured based on the number of input ports and aggregation range of its layer to support the parameterized expansion of the synchronization network.

14. A hardware synchronization network for computing unit arrays, characterized in that, include: Multiple computing units are used to generate synchronization requests, which include a synchronization validity signal, an aggregation level field, and a local barrier identifier; Multiple one-dimensional synchronization nodes and multiple two-dimensional synchronization nodes are arranged alternately and recursively to form a split-form synchronization network, wherein each level of synchronization node is of a single type: a one-dimensional synchronization node or a two-dimensional synchronization node. Each level of the synchronization node includes: a data receiving path, a local storage file, a control core, and a data sending path, wherein... A data receiving path is used to receive synchronization requests from lower-level nodes or the computing unit. The local storage file records the synchronization request status from each input port, indexed by at least some bits of the barrier identifier, and the synchronization request status is distinguished by the input port direction. The control core is used for: Determine whether to perform an aggregation operation at this level based on the current level bit of the aggregation level field: If not, the receiving data path will shift the aggregation level field and then forward the synchronization request to a higher-level synchronization node through the sending data path. If so, query the local registered file and, based on the type of this level node and the synchronization request status recorded in the local registered file, perform the corresponding aggregation condition check: When the local level is a one-dimensional synchronization node, the aggregation condition is: in the local register file, the register bit corresponding to the barrier identifier has been set, and there are at least two different computing units submitting the synchronization request through the input port in the same direction of the one-dimensional synchronization node. When the local level is a two-dimensional synchronization node, the aggregation condition is: in the local register file, the register bit corresponding to the barrier identifier has been set, and at least one computing unit submits the synchronization request through the horizontal input port, and at the same time, at least one computing unit submits the synchronization request through the vertical input port. A data transmission path is used to generate and output a local wake-up response when the aggregation condition is met, and to abort further uplink propagation of the synchronization request.

15. A computer device, characterized in that, The computer device includes a memory and a processor. The memory is used to store computer programs, and the processor is used to execute the computer programs stored in the memory to implement the steps of the method according to any one of claims 1-13.

16. A computer-readable storage medium, characterized in that, The storage medium stores a computer program, which, when executed by a processor, implements the steps of the method described in any one of claims 1-13.

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