A protocol packet matching and performance analysis method, device and computer equipment

Abstract

The application relates to a protocol message matching and performance analysis method and device and a storage medium. The method comprises the following steps: for various types of write transaction messages under different protocols and mechanisms, completing classified matching and caching by relying on initial sequence numbers and initial addresses, and realizing ordered collection of multiple types of messages. Corresponding messages are monitored and associated storage is completed through retransmission and cancellation mechanisms, message pairing between cross-protocols is completed by combining addresses and sequence numbers, and the time sequence and association relationship of the whole-process write transaction message are guaranteed to be complete. Meanwhile, after uniformly collecting cache data, performance analysis is carried out, protocol interaction operation data can be comprehensively collected, the message transmission state can be accurately mastered, operation abnormities can be found in a timely manner, and the control ability of on-chip protocol interaction and the comprehensiveness and accuracy of performance analysis can be effectively improved.

Description

Technical Field

[0001] This application relates to the field of microprocessors, and in particular to a method, apparatus, and computer device for protocol message matching and performance analysis. Background Technology

[0002] With the application of ARM architecture in embedded systems, desktop terminals, servers, and other fields, high-speed interface protocols such as CHI and AXI are also widely used in various chips. CHI is generally used for communication interconnection in NOC (Network on Chip) systems; while AXI is used in most products, including those handling high-speed I / O devices such as disks and network cards, integrated PCIe (Peripheral Component Interconnect Express) controllers, USB controllers connecting keyboards and mice, and DDR (Double Data Rate SDRAM) controllers connecting memory modules. Therefore, when chip performance analysis needs to adapt to transactions between these two types of buses, the issue of interchangeability between CHI and AXI protocols arises. Summary of the Invention

[0003] Given that CHI and AXI are two different high-bandwidth communication protocols with their own protocol specifications, order management, and message matching mechanisms, this paper provides a method, apparatus, computer equipment, and storage medium for protocol message matching and performance analysis. This enables the matching of AXI protocol messages to CHI protocol messages, providing technical support for subsequent performance analysis.

[0004] Firstly, this application provides a method for protocol message matching and performance analysis. This includes: Determine the write request message and write buffer array associated with the first protocol, and determine the initial sequence number and initial address corresponding to the write request message; When the first write response packet corresponding to the initial sequence number is detected based on the retransmission mechanism, the first write response packet is matched and cached through the write cache array; When the first write data packet associated with the first protocol is detected based on the cancellation mechanism, the first write data packet is matched and cached according to the initial sequence number and the write cache array; When a write address packet associated with the second protocol is detected, the write address packet is matched and cached according to the initial address and the write cache array; Determine the target sequence number corresponding to the write address packet, and match and cache the second write data packet and the second write response packet associated with the target sequence number according to the write cache array; Extract data from the write cache array after matching the cache, and perform performance data processing and analysis.

[0005] In one embodiment, when the first write response message corresponding to the initial sequence number is detected based on the retransmission mechanism, the first write response message is matched and cached through the write cache array, including: determining the current message type under the retransmission mechanism based on the field values ​​of the first write response message; the current message type includes retry response message and allow authorization message; determining the fields to be matched in the write cache array based on the current message type; and matching and caching the first write response message with the fields to be matched in the write cache array based on the current performance analysis requirements and the generation time of the first write response message.

[0006] In one embodiment, when a first write data packet associated with the first protocol is detected based on the cancellation mechanism, the first write data packet is matched and cached according to the initial sequence number and the write cache array, including: determining the corresponding operation type under the cancellation mechanism based on the field values ​​of the first write data packet; the operation type includes write data cancellation and non-cancellation; determining the fields to be operated on in the write cache array based on the operation type; and matching and caching the first write data packet with the fields to be operated on in the write cache array based on the generation time of the first write data packet.

[0007] In one embodiment, after matching and caching the first write response message, the method further includes: when the field information in the write request message indicates that a reply from the receiver is required, monitoring the first acknowledgment message corresponding to the initial sequence number; the first acknowledgment message is transmitted through the slave response channel SRSP of the first protocol, and the first write response message is transmitted through the master response channel CRSP of the first protocol; and matching and caching the first acknowledgment message based on the generation time of the first acknowledgment message and the write cache array.

[0008] In one embodiment, determining the target sequence number corresponding to the write address packet includes: obtaining the first register sequence number, the second register sequence number, and the circular sequence number in the write cache array; obtaining a new first register sequence number based on the first register sequence number and the historical sequence number; partitioning and padding the circular sequence number to obtain the padding result, and obtaining a new second register sequence number based on the padding result and the second register sequence number; performing an overflow judgment based on the circular sequence number, and selecting the target sequence number from the new first register sequence number and the new second register sequence number.

[0009] In one embodiment, the method further includes: determining the read request message and read cache array associated with the first protocol; when a read response message corresponding to the read request message is detected based on the retransmission mechanism, matching and caching the read response message through the read cache array; matching and caching the first read data message associated with the first protocol with the read cache array; when a read address message associated with the second protocol is detected, matching and caching the read address message according to the address information in the read request message and the read cache array; matching and caching the detected second read data message according to the identifier information of the read address message and the read cache array; extracting the data information in the matched and cached read cache array for performance data processing and analysis.

[0010] In one embodiment, when a read response message corresponding to a read request message is detected based on the retransmission mechanism, the read response message is matched and cached through a read cache array, including: determining the actual message type corresponding to the retransmission mechanism based on the field values ​​of the read response message; the actual message type includes retry response messages and allow authorization messages; determining the fields to be matched in the read cache array based on the actual message type; and matching and caching the read response message with the fields to be matched in the read cache array based on actual performance analysis requirements and the generation time of the read response message.

[0011] In one embodiment, the method further includes: monitoring a second acknowledgment message when the field information in the read request message indicates that a response from the receiver is required; the second acknowledgment message is transmitted through the slave response channel SRSP of the first protocol, and the read response message is transmitted through the master response channel CRSP of the first protocol; and matching and caching the second acknowledgment message with the read cache array based on the generation time and identification information of the second acknowledgment message.

[0012] Secondly, this application also provides a protocol message matching and performance analysis apparatus. It includes: The first protocol processing module is used to determine the write request message and write cache array associated with the first protocol, and to determine the initial sequence number and initial address corresponding to the write request message; when the first write response message corresponding to the initial sequence number is detected based on the retransmission mechanism, the first write response message is matched and cached through the write cache array; when the first write data message associated with the first protocol is detected based on the cancellation mechanism, the first write data message is matched and cached according to the initial sequence number and the write cache array.

[0013] The second protocol processing module is used to match and cache the write address message according to the initial address and the write cache array when a write address message associated with the second protocol is detected; determine the target sequence number corresponding to the write address message; and match and cache the second write data message and the second write response message associated with the target sequence number according to the write cache array.

[0014] The performance data processing module is used to extract data information from the write cache array after matching the cache, and to perform performance data processing and analysis.

[0015] Thirdly, this application also provides a computer device. The computer device includes a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the steps of the above-mentioned protocol message matching and performance analysis method.

[0016] Fourthly, this application also provides a computer-readable storage medium. The computer-readable storage medium stores a computer program, which, when executed by a processor, implements the steps of the above-described protocol message matching and performance analysis method.

[0017] The aforementioned protocol message matching and performance analysis methods, devices, computer equipment, and storage media, for various write transaction messages under different protocols and mechanisms, complete classification, matching, and caching based on initial sequence numbers and initial addresses, achieving orderly aggregation of multiple message types. Through retransmission and cancellation mechanisms, corresponding messages are monitored and associated storage is completed. Message pairing across protocols is achieved by combining addresses and sequence numbers, ensuring the integrity of the timing and association relationships of write transaction messages throughout the entire process. Simultaneously, performance analysis is conducted after unified aggregation of cached data, enabling comprehensive collection of protocol interaction operation data, accurate understanding of message transmission status, timely detection of operational anomalies, and effectively improving the on-chip protocol interaction control capabilities and the comprehensiveness and accuracy of performance analysis. Attached Figure Description

[0018] Figure 1 This is a system architecture diagram of a protocol message matching and performance analysis method in one embodiment; Figure 2 This is a system architecture diagram of the protocol message matching and performance analysis method in another embodiment; Figure 3 This is a flowchart illustrating a protocol message matching and performance analysis method in one embodiment; Figure 4 This is a schematic diagram of the overall structure of AXI protocol matching CHI protocol messages in one embodiment; Figure 5 This is a schematic diagram of the AXI sequence matching device in one embodiment; Figure 6 This is a flowchart illustrating the protocol message matching and performance analysis method in another embodiment; Figure 7 This is a flowchart illustrating the protocol message matching and performance analysis method in another embodiment; Figure 8 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0020] The protocol message matching and performance analysis method provided in this application embodiment can be applied to, for example... Figure 1 In the system architecture shown, the first protocol is such as the CHI protocol, and the second protocol is such as the AXI protocol. For ease of understanding, this application will use the CHI / AXI protocol for subsequent embodiments. When AXI matches the CHI protocol for pathways such as "processor core-PMM-PCIE controller-PCIE device", the conversion from CHI protocol to AXI protocol occurs in the conversion module between the PMM (Processor Local Bus Memory Map) and the PCIE controller (Peripheral Component Interconnect Express). On the CHI protocol side, the processor core is the RN node (Root Node) in the CHI protocol, the PMM is the HN node (Home Node) in the CHI protocol, and the CHI protocol is the communication between the RN node and the HN node.

[0021] The protocol message matching and performance analysis method provided in this application embodiment can also be applied to, for example, Figure 2 In the system architecture shown, when AXI matches the CHI protocol for pathways such as "processor core-on-chip network-DDR controller-memory", the conversion from CHI protocol to AXI protocol occurs in the conversion module between the on-chip network's directory management unit and the DDR controller (Double Data Rate SDRAM). The directory management unit is the HN node in the CHI protocol, and the DDR controller is the SN node (Slave Node) in the CHI protocol. The CHI protocol is the communication between the HN node and the SN node.

[0022] To analyze performance results such as latency distribution and data bandwidth bottlenecks in accessing peripherals like disks or memory modules, it is necessary to monitor the request, data, and response messages corresponding to the CHI protocol and the address, data, and response messages corresponding to the AXI protocol on each node. All messages belonging to the same read / write operation are matched, and information such as the generation time and read / write data volume of each message is extracted for subsequent specialized data processing and analysis. (Reference...) Figure 1 and Figure 2When read / write operations are initiated by the processor core, the CHI transaction on the NOC (Network on Chip) system precedes the AXI transaction on the PICE or DDR controller, requiring matching of AXI protocol to CHI protocol messages. Conversely, if the read / write operations are initiated by the network interface card (NIC), GPU, or other components, the AXI transaction on the PICE or DDR controller precedes the CHI transaction on the NOC system, again requiring matching of CHI protocol to AXI protocol messages. This application primarily uses the example of read / write operations initiated by the processor core for illustration.

[0023] In one embodiment, such as Figure 3 As shown, a method for protocol message matching and performance analysis is provided, through... Figure 1 and Figure 2 The conversion module in the code implements AXI to CHI protocol message matching, including the following steps: Step 302: Determine the write request message and write cache array associated with the first protocol, and determine the initial sequence number and initial address corresponding to the write request message.

[0024] The first protocol is a cache coherence interconnect protocol for multi-core on-chip systems, such as the CHI protocol, which includes the request channel REQ, write data channel WDAT, read data channel RDAT, master response channel CRSP, and slave response channel SRSP. Figure 4 This is a schematic diagram of the overall structure for matching AXI protocol messages to CHI protocol in one embodiment. The overall structure includes a sequence generator, sequence extractor, write buffer array, retransmission processing module, cancellation processing module, AXI sequence matcher, AXI sequence allocator, performance analyzer, and export control module associated with write operations, and a sequence generator, read buffer array, retransmission processing module, performance analyzer, and export control module associated with read operations.

[0025] Specifically, when the request channel REQ detects that the opcode field in the request message represents a "write operation," it allocates a free storage item in the write cache array for the write request message. The values ​​of the initial address (addr), transaction ID, source ID, and destination ID fields from the message are cached in the Addr_op, TxnID, SrcID, and TgtID fields of the allocated storage item, respectively. Simultaneously, information such as the creation time of the write request message is cached in the Infor_req field of the write cache array storage item.

[0026] Furthermore, although the CHI protocol does not allow multiple incomplete request messages with the same ID to appear simultaneously, for write operations initiated from the CHI end, the AXI end will complete later than the CHI end, and the time difference may be significant. While the CHI end of the same write operation has completed all message communication but the AXI end has not yet finished communicating, the CHI end may send another request message with the same ID, which will be monitored and cached in the write cache array. The previous write request message with the same ID may continue to be cached in the write cache array because the corresponding AXI end has not yet finished communicating; therefore, at this time, the write cache array contains more than one CHI request message with the same ID. To facilitate matching of all monitored messages, it is necessary to... Figure 4 The sequence generator in the CHI protocol generates an initial sequence number Req_o for write request messages and caches it in the Req_o field of the write cache array storage item.

[0027] In one embodiment, Figure 4 The read cache array and write cache array can be designed separately or uniformly, and the read and write attributes of each storage item in the array can be distinguished by special signals.

[0028] In one embodiment, regardless of whether the CHI write request message originates from... Figure 1 Is the data sent from the RN node to the HN node, or from... Figure 2 The HN node sends a message to the SN node. Depending on the implementation of the request receiver, as a response to the write request message, the write request receiver can send two response messages with opcode fields of DBIDResp and Comp respectively through the main response channel CRSP, or it can send only one response message with opcode field of CompDBIDResp through the main response channel CRSP.

[0029] Step 304: When the first write response message corresponding to the initial sequence number is detected based on the retransmission mechanism, the first write response message is matched and cached through the write cache array.

[0030] Specifically, when the main response channel detects a new first write response message, Figure 4 The sequence extractor extracts the initial sequence number Req_o from the write request message and assigns it to the crsp_o field of the first write response message. Therefore, after storing all types of ID fields and initial sequence numbers from all write request messages into the write cache array, the sequence extractor indexes the write cache array according to the corresponding types of ID fields in the first write response message, finds the matching entry, completes the information retrieval, and then clears the cache data.

[0031] because Figure 4The retransmission module in the CHI protocol provides a retransmission mechanism. When the receiver of a write request message is temporarily unable to process the write request, the retransmission mechanism is triggered by setting, for example, the opcode field to a specific value in the first write response message returned to the sender of the request message. Therefore, the retransmission judgment logic needs to check the field values ​​of the first write response message to determine the current message type corresponding to the retransmission mechanism. If the value indicates that the response message is a retry acknowledgment message, it means that the retransmission mechanism has been initiated. When it is detected that the receiver of the write request message sends a response message again and the opcode field is detected as a pass authorization message after retransmission judgment, it indicates that the receiver of the request message has the ability to receive new write request messages. When the write request message is retransmitted, it is treated as a new write operation, and write cache entries are reallocated and response information is cached.

[0032] Step 306: When the first write data packet associated with the first protocol is detected based on the cancellation mechanism, the first write data packet is matched and cached according to the initial sequence number and the write cache array.

[0033] Specifically, when the write data channel WDAT detects the first write data packet, Figure 4 The sequence extractor extracts the initial sequence number Req_o from the write request message and assigns it to the Dat_o field of the first write data message. Therefore, after storing all types of ID fields and initial sequence numbers from all write request messages into the write cache array, the write cache array is indexed and extracted based on the types of ID fields in the first write data message. Since... Figure 4 The cancellation processing module in the CHI protocol provides a write cancellation mechanism. If the sender of the write request message does not need to continue writing the current data for the purpose of maintaining the order, it will represent the write data cancellation in the first write data message it sends, for example, the opcode field value. After the write data message receiver detects this information, it will either stop sending the data or invalidate the valid position of the data when sending.

[0034] Step 308: When a write address message associated with the second protocol is detected, the write address message is matched and cached according to the initial address and the write cache array.

[0035] Among them, the second protocol is a high-performance on-chip bus protocol for memory-mapped peripherals, such as the address messages, data messages, and response messages involved in the AXI protocol. The timing of the generation of various messages in the AXI protocol is not consistent with that of the CHI protocol.

[0036] Specifically, Figure 1 or Figure 2 The conversion module will issue an AXI write operation after a certain period of time upon receiving the CHI write request message. When the write address message associated with AXI is detected, refer to... Figure 4As shown, the process iterates through each item in the write cache array. If the value of the awaddr field representing address information in the write address message matches the value of the initial address Addr_op field in the storage item, and the initial sequence number Req_o field has the earliest generation time among all address-matching storage items, then that storage item is a match. After matching is completed, the generation time of the write address message is cached in the Infor_waddr field of the matching item in the write cache array.

[0037] In one embodiment, for different versions of the AXI protocol, such as AXI3 and AXI4, although the write address and write response messages retain the `awid` and `bid` signals to distinguish different write address messages, the protocol only recommends using these signals, and a significant number of design implementations do not use them. Similarly, in the write data message of the AXI3 protocol, although the `wid` signal is retained to distinguish different write data messages, the protocol only recommends using this signal; while AXI4 directly discards this signal. In the DUT design, matching between the three can be completed according to the order in which the write address message, write data message, and write response message are received.

[0038] Step 310: Determine the target sequence number corresponding to the write address packet, and match and cache the second write data packet and the second write response packet associated with the target sequence number according to the write cache array.

[0039] Specifically, to achieve matching between AXI and CHI messages, AXI messages need to be cached in a write cache array. When a new write operation occurs, a traversal method is used to search for a free entry in the write cache array. Therefore, the storage order of AXI messages in the storage queue cannot be guaranteed. To ensure successful matching of AXI write address messages, AXI write data messages, and AXI write acknowledgment messages in various performance analyzer designs and implementations, a dedicated AXI order management mechanism is required. Therefore, when writing the time information of the write address message to the matching entry in the write cache array, [the mechanism is determined by...]. Figure 4 The AXI sequencer allocates a destination sequence number aw_o to the write address packet and assigns it to the Axi_worder field of the match. The AXI sequence generation strategy ensures that the write packet buffer array will not have multiple destination sequence numbers with the same value.

[0040] When the second write data packet associated with the second protocol is detected Figure 4 The AXI sequencer in the write buffer inserts a sequence number w_o to ensure that the value of w_o belonging to the same AXI write operation is consistent with the value of the target sequence number aw_o. Then, the AXI sequencer matches the value of w_o in the second write data packet with the value of Axi_worder in the storage item in the write buffer array. If they match, it means that the match is successful, and the generation time of the second write data packet is cached in the Infor_wdata field of the matching item in the write buffer array.

[0041] When monitoring the second write response message associated with the second protocol Figure 4 The AXI sequencer in the write buffer inserts a sequence number b_o to ensure that the value of b_o belonging to the same AXI write operation is consistent with the value of the target sequence number aw_o. Then, the AXI sequencer matches the value of b_o in the second write response message with the value of Axi_worder of the storage item in the write buffer array. If they match, it means that the match is successful, and then the generation time of the second write response message is cached in the Infor_b field of the matching item in the write buffer array.

[0042] Step 312: Extract the data information from the write cache array after matching the cache, and perform performance data processing and analysis.

[0043] Specifically, for write operations initiated by the processor core, the CHI and AXI protocol ends are decoupled; that is, the CHI end does not need to wait for the AXI end to return a second write response message before sending the first write response message. If there are no design flaws or performance defects in the DUT, the second write response message should be the last one among all CHI and AXI messages to write data in the write cache array. Therefore, after the generation time of the second write response message is assigned to the `Infor_b` field, the export of the corresponding storage item data in the write cache array can be triggered for subsequent performance data processing and analysis by the performance analyzer. Furthermore, in Figure 4 In the export control module shown, before exporting data, it can check whether all fields in the storage item have been filled in. If any fields are not filled in, an alarm can be triggered.

[0044] In the aforementioned protocol message matching and performance analysis method, various write transaction messages under different protocols and mechanisms are classified, matched, and cached based on initial sequence numbers and initial addresses, achieving orderly aggregation of multiple message types. Retransmission and cancellation mechanisms are used to monitor corresponding messages and complete associated storage. Message pairing across protocols is achieved by combining addresses and sequence numbers, ensuring the integrity of the timing and association relationships of write transaction messages throughout the entire process. Simultaneously, performance analysis is conducted after unified aggregation of cached data, enabling comprehensive collection of protocol interaction operation data, accurate understanding of message transmission status, timely detection of operational anomalies, and effectively improving the on-chip protocol interaction control capabilities and the comprehensiveness and accuracy of performance analysis.

[0045] In one embodiment, when the first write response message corresponding to the initial sequence number is detected based on the retransmission mechanism, the first write response message is matched and cached through the write cache array, including: determining the current message type under the retransmission mechanism based on the field values ​​of the first write response message; determining the fields to be matched in the write cache array based on the current message type; and matching and caching the first write response message with the fields to be matched in the write cache array based on the current performance analysis requirements and the generation time of the first write response message.

[0046] The current message types include retry response messages (such as RetryAck messages) and release authorization messages (such as PCrdGrant messages).

[0047] Specifically, if the current performance analysis requirement does not consider the time overhead caused by retransmission, then when a RetryAck message is detected, no information extraction or caching is performed, and the cached item is released directly after matching the corresponding storage item; if the current performance analysis requirement is to calculate the time overhead caused by message retransmission, when a RetryAck message is detected, the message times of the write request message, RetryAck message, subsequent PCrdGrant, and retransmission message recorded by the write cache array can be matched in a dedicated matching logic, and the generation time of each message can be recorded.

[0048] If the first write response message is a RetryAck message and the time overhead caused by retransmission needs to be calculated, then the fields to be matched in the write cache array are determined to be TxnID, TgtID, SrcID, and Req_o. The values ​​of the TxnID, SrcID, TgtID, and crsp_o fields of the first write response message are compared with the fields to be matched. If they all match, the match is successful. The PCrdType field value and the generation time of the first write response message are cached in the PCrdType and Info_crsp fields of the write cache array, respectively. If the first write response message is a PCrdGrant message and the time overhead caused by retransmission needs to be calculated, then the fields to be matched in the write cache array are determined to be PCrdType, TgtID, SrcID, and Req_o. The values ​​of the PCrdType, SrcID, TgtID, and crsp_o fields of the first write response message are compared with the fields to be matched. If they all match, the match is successful. The generation time of the first write response message is cached in the Info_crsp field of the write cache array.

[0049] If the first write response message is a normal response message other than RetryAck or PCrdGrant, then the fields to be matched in the write cache array are determined to be TxnID, TgtID, SrcID, and Req_o. The values ​​of the TxnID, SrcID, TgtID, and crsp_o fields of the first write response message are compared with the fields to be matched. If they all match, the match is successful; the generation time of the first write response message is cached in the Info_crsp field of the matching cache item. If the first write response message is a DBIDResp message or a CompDBIDResp message, then the value of the DBID field in the first write response message also needs to be cached in the DBID field of the corresponding write message matching cache item.

[0050] In this embodiment, the message type in the retransmission scenario is accurately determined based on the fields of the write response message, and the corresponding fields to be matched in the write cache array are locked. The matching cache is completed by combining performance analysis requirements and message generation time to ensure the stable operation of the retransmission mechanism, while providing complete and time-accurate message data support for subsequent performance analysis.

[0051] In one embodiment, when a first write data packet associated with the first protocol is detected based on the cancellation mechanism, the first write data packet is matched and cached according to the initial sequence number and the write cache array, including: determining the operation type corresponding to the cancellation mechanism based on the field value of the first write data packet; determining the field to be operated in the write cache array based on the operation type; and matching and caching the first write data packet with the field to be operated in the write cache array based on the generation time of the first write data packet.

[0052] The operation types include write data cancellation and non-cancellation.

[0053] Specifically, after detecting the first write data packet and inserting its Dat_o field, the cancellation processing module checks the opcode field in the first write data packet. If the opcode field indicates non-WriteDataCancel, meaning the write data is cancelled, the fields to be operated on in the write buffer array are determined to be DBID, SrcID, TgtID, and Req_o. Then, the values ​​of TxnID, SrcID, TgtID, and Dat_o in the first write data packet are compared with it. If they match, the value of the HomeNID field and the generation time in the first write data packet are cached in the HomeNID and Info_dat fields of the matching cache entry in the write buffer array, respectively. If the opcode field indicates WriteDataCancel, meaning the write data is not cancelled, after matching the TxnID, SrcID, TgtID, Dat_o fields and assigning the value to the Info_dat field, the cancel flag in the cache entry is set to a valid state, so that the amount of data that should have been transmitted in this write operation is ignored when calculating the data bandwidth in subsequent data operations.

[0054] In this embodiment, the operation type corresponding to the cancellation mechanism is accurately identified by the fields of the write data packet, and the field to be operated on within the write cache array is located. The matching cache is completed by combining the packet generation sequence, achieving precise association between the packet and the cache field.

[0055] In one embodiment, after matching and caching the first write response message, the method further includes: when the field information in the write request message indicates that a reply from the receiver is required, monitoring the first acknowledgment message corresponding to the initial sequence number; and matching and caching the first acknowledgment message based on the generation time of the first acknowledgment message and the write cache array.

[0056] The first acknowledgment message is transmitted through the slave response channel SRSP of the first protocol, and the first write response message is transmitted through the master response channel CRSP of the first protocol. The first acknowledgment message may be, for example, a CompAck message or another type of response message.

[0057] Specifically, refer to Figure 1 During communication between the RN node and the HN node, after the RN node receives the first write response message from the HN node via the main response channel CRSP, it will, depending on its implementation and program behavior, send the first write data message to the HN node via the write data channel WDAT. At this point, depending on the value of the ExpCompAck field in the write request message, it may also need to send a first acknowledgment message to the HN via the response channel SRSP, indicating that a response from the receiver is required. Therefore, when the first acknowledgment message is detected via the response channel SRSP, Figure 4 The sequence extractor extracts the initial sequence number Req_o from the write request message and assigns it to the srsp_o field of the first acknowledgment message. Then, the values ​​of the TxnID, SrcID, TgtID, and srsp_o fields in the first acknowledgment message are compared with the values ​​of the DBID, TgtID, HomeNID, and Req_o fields cached in each item of the write cache array. If they match, the generation time of the first acknowledgment message is cached in the Infor_srsp field of the matching item in the write cache array.

[0058] In this embodiment, the need for the receiver to send back an acknowledgment message is determined by the fields of the write request message, and acknowledgment messages with corresponding sequence numbers are monitored. By combining the message generation time with the write cache array to complete matching caching, precise message association and timing control are achieved.

[0059] In one embodiment, determining the target sequence number corresponding to the write address packet includes: obtaining the first register sequence number, the second register sequence number, and the circular sequence number in the write cache array; obtaining a new first register sequence number based on the first register sequence number and the historical sequence number; partitioning and padding the circular sequence number to obtain the padding result, and obtaining a new second register sequence number based on the padding result and the second register sequence number; performing an overflow judgment based on the circular sequence number, and selecting the target sequence number from the new first register sequence number and the new second register sequence number.

[0060] in, Figure 5 This is a schematic diagram of the AXI sequence matcher, which includes a loop control module, comparator 1, comparator 2, minimum sequence register 1, minimum sequence register 2, overflow judgment module, and selector.

[0061] Specifically, under the control of the loop control module, the value of axi_worder in the write cache array storage item is read sequentially. Here, axi_worder is the loop number. It is compared with the smallest first register number recorded in minimum register 1, and the smaller value and its corresponding write cache array index number are updated in minimum register 1 to obtain a new first register number. Simultaneously, the loop number is padded: if the loop number value is less than half the maximum value that the loop number field can represent, a 1 is added; if the loop number value is greater than half the maximum value that the loop number field can represent, a 0 is added. The padded result is then compared with the second register number recorded in minimum register 2, and the smaller value and its corresponding write message matching cache array index number are updated in minimum register 2 to obtain a new second register number.

[0062] Simultaneously, all valid cycle number values ​​in the write cache array are sent to the overflow detection module. If the overflow detection module detects that the cycle number values ​​recorded in the write cache array include values ​​near 0 and values ​​near the maximum value that the signal can record, it indicates that the values ​​near 0 are the incremented overflow values, and their generation time is later than the values ​​near the maximum value. Therefore, the overflow detection module guides the selector to output a new second register sequence number as the target sequence number. The second write data packet and the second write response packet corresponding to the AXI protocol write the extracted information into the write cache array according to this target sequence number. Otherwise, the overflow detection module guides the selector to output a new first register sequence number as the target sequence number.

[0063] In this embodiment, by reading two types of registered sequence numbers and cache circular sequence numbers, the registered sequence numbers are iteratively updated, and the circular sequence numbers are partitioned and padded to complete the numerical correction. Combined with overflow detection to filter out valid target sequence numbers, the sequence number iteration and anomaly verification can be accurately completed, avoiding sequence number disorder and overflow problems, ensuring orderly management of the write cache array sequence numbers, and ensuring stable and reliable message matching and transaction scheduling logic.

[0064] In one embodiment, such as Figure 6 As shown, another method for protocol message matching and performance analysis is provided. The above method also includes the following steps: Step 602: Determine the read request message and read cache array associated with the first protocol.

[0065] Specifically, when the request channel REQ detects that the opcode field in the request message represents a "read operation," it allocates a free storage item in the read cache array for the read request message. The values ​​of the initial address (addr), transaction ID, source ID, and destination ID fields from the message are cached in the Addr_op, TxnID, SrcID, and TgtID fields of the allocated storage item, respectively. Simultaneously, information such as the generation time of the read request message is cached in the Infor_req field of the write cache array storage item. To reduce read latency, the CHI protocol provides two mechanisms: DMT (Direct Memory Transfer) and DCT (Direct Cache Transfer). In these two mechanisms, the CHI read request message receiver can bypass the CHI read request message sender and directly provide data to the processor core, etc.

[0066] For read operations initiated from the CHI end, communication at the CHI end will be completed later than at the AXI end. Once the last CHI message of the read operation is monitored and matched, the data in the corresponding read message matching cache array is exported and released. When the DUT sends another request message with the same TxnID, SrcID, and TgtID, the previous request message with the same TxnID, SrcID, and TgtID has already been released from the read message matching cache array. Therefore, for read operations, it is not necessary to insert sequence numbers for the request message as with write operations.

[0067] In one embodiment, the CHI protocol read request message uses the ReturnNID field to specify the read data address and the ReturnTxnID field to identify the message ID. Therefore, the fields in the read request message, along with the ReturnNID and ReturnTxnID fields, also need to be assigned to the RetNID and RetTxnID fields of the read cache array storage item, respectively.

[0068] Step 604: When a read response message corresponding to a read request message is detected based on the retransmission mechanism, the read response message is matched and cached through the read cache array.

[0069] Specifically, when the receiver receives a read request message, it determines whether to return a read receipt message to the sender via the CRSP channel based on the different values ​​of the order field in the read request message. If a read receipt message needs to be returned, when a read response message is detected, the values ​​of its TxnID, SrcID, and TgtID fields are compared with the TxnID, TgtID, and SrcID cached in each item of the read cache array. If they all match, the match is successful, and the generation time of the read response message is cached in the Info_crsp field of the matching cache item.

[0070] Similarly, as with write operations, when the receiver of a read request message is temporarily unable to process the read request, a retransmission mechanism is triggered in the read response message returned to the sender of the request message by setting, for example, the opcode field to a specific value. If the value of the opcode field in the write response message indicates that the response message is a retry acknowledgment message, then the retransmission mechanism has been initiated. When the receiver of the write request message retransmits a response message and the retransmission check detects that the opcode field is a pass authorization message, it indicates that the receiver of the request message has the ability to receive new read request messages. When the read request message is retransmitted, it is treated as a new read operation, and read cache entries are reallocated and response information is cached.

[0071] Step 606: Match and cache the first read data packet associated with the first protocol with the read cache array.

[0072] Specifically, when the read data channel RDAT detects the first read data packet, it compares the values ​​of its various ID fields with the TxnID, TgtID, and SrcID cached in each item of the read cache array. If they all match, the match is successful. Then, the value of the HomeNID field and the generation time of the first read data packet are cached in the HomeNID and Info_dat fields of the matching cache item, respectively.

[0073] Step 608: When a read address message corresponding to the second protocol is detected, the read address message is matched and cached according to the address information in the read request message and the read cache array.

[0074] Specifically, a CHI read request will eventually be converted into an AXI read operation. When an AXI-associated read address packet is detected, since the read cache array cannot contain other read request packets with the same ID, the array is iterated through. Matching is completed simply by matching the aradir field representing the address information in the read request packet with the value of the Addr_op field in the storage item. Then, the aradid field value and generation time of the read address packet are cached in the Axi_arid and Infor_raddr fields of the matching item in the read cache array, respectively.

[0075] Step 610: Match and cache the detected second read data packet according to the identification information of the read address packet and the read cache array.

[0076] Specifically, unlike AXI write operations, AXI read operations are forcibly matched using the `arid` of the read address packet and the `rid` of the second read data packet. The value of the `arid` in the read address packet is related to the `TxnID` value and address range of the first read request packet of the CHI protocol. In contrast, in a DUT (Design Under Test), two CHI read operations with the same address range and identical `TxnID` will not be processed simultaneously. Based on the `arid` identifier of the AXI read address packet and the `rid` of the AXI read data packet, the matching between the AXI read data packet and the CHI read address packet in the read packet matching cache array can be completed. Therefore, when monitoring the second read data packet associated with the second protocol, the value of the `rid` field in the second read data packet is matched with the `arid` in the read cache array storage item. Once a match is successful, the generation time of the second read data packet is cached in the `Infor_rdata` field of the read cache array matching item.

[0077] Step 612: Extract the data information from the read cache array after matching the cache, and perform performance data processing and analysis.

[0078] Specifically, through Figure 4 The performance analyzer can trigger the export of corresponding storage item data from the write cache array for subsequent performance data processing and analysis. Before exporting the data, the export control module can check whether all fields in the storage item are filled in. If any fields are not filled in, an alarm can be triggered.

[0079] In the above embodiments, a read cache array, combined with a retransmission mechanism, is used to associate and cache the read response message and the first read data message. Based on the read request address, accurate matching of read address messages across protocols is achieved, and then the corresponding storage of the second read data message is completed using the message identifier. The entire process establishes a mapping association between read messages of different protocols, ensuring orderly protocol interaction and message flow.

[0080] In one embodiment, when a read response message corresponding to a read request message is detected based on the retransmission mechanism, the read response message is matched and cached through a read cache array, including: determining the actual message type corresponding to the retransmission mechanism based on the field values ​​of the read response message; determining the fields to be matched in the read cache array based on the actual message type; and matching and caching the read response message with the fields to be matched in the read cache array based on the actual performance analysis requirements and the generation time of the read response message.

[0081] The actual message types include retry response messages (such as RetryAck messages) and release authorization messages (such as PCrdGrant messages).

[0082] Specifically, if the actual performance analysis does not consider the time overhead caused by retransmission, when a RetryAck message is detected, no information extraction or caching is performed, and the cached item is released directly after matching the corresponding storage item. If the actual performance analysis requires to calculate the time overhead caused by message retransmission, when a RetryAck message is detected, the message times of the read request message, RetryAck message, subsequent PCrdGrant, and retransmission message recorded by the read cache array are matched in a dedicated matching logic, and the generation time of each message is recorded.

[0083] If the read response message is RetryAck and the time overhead caused by retransmission needs to be calculated, compare the values ​​of the TxnID, SrcID, TgtID, and crsp_o fields of the read response message with the TxnID, TgtID, SrcID, and Req_o cached in each item of the read cache array. If they all match, the match is successful, and the PCrdType field value and the generation time of the read response message are cached in the PCrdType and Info_crsp fields of the matching cache item, respectively. If the read response message is PCrdGrant and the time overhead caused by retransmission needs to be calculated, compare the values ​​of the PCrdType, SrcID, TgtID, and crsp_o fields of the read response message with the PCrdType, TgtID, SrcID, and Req_o cached in each item of the read cache array. If they all match, the match is successful, and the generation time of the read response message is cached in the Info_crsp field of the matching cache item.

[0084] If the read response message is a normal response message other than RetryAck or PCrdGrant, then the read cache array is traversed, and the values ​​of the TxnID, SrcID, TgtID, and crsp_o fields of the read response message are compared with the TxnID, TgtID, SrcID, and Req_o cached in each item of the read cache array. If they all match, the match is successful, and the generation time of the read response message is cached in the Info_crsp field of the matching cache item. If the read response message is a DBIDResp or CompDBIDResp message, then the value of the DBID field in the read response message also needs to be cached in the DBID field of the corresponding read cache item.

[0085] In this embodiment, the message type under the retransmission mechanism is determined by reading the fields of the response message, and the corresponding fields to be matched in the read cache array are located. Matching caches are completed by combining performance analysis requirements with message generation time, achieving accurate message archiving, ensuring the normal operation of the retransmission process, and providing complete time-series message data to support subsequent performance analysis.

[0086] In one embodiment, the method further includes: monitoring a second acknowledgment message when the field information in the read request message indicates that a response from the receiver is required; and matching and caching the second acknowledgment message with the read cache array based on the generation time and identification information of the second acknowledgment message.

[0087] The second acknowledgment message is transmitted through the slave response channel SRSP of the first protocol, and the read response message is transmitted through the master response channel CRSP of the first protocol. The second acknowledgment message may be, for example, a CompAck message or another type of response message.

[0088] Specifically, in a read operation, the read request is initiated by the CHI end, but the AXI end completes it before the CHI end. When the sender of the CHI read request message receives the second read data message from the RDAT channel, it determines whether to send an acknowledgment message to the receiver via the SRSP channel based on the value of the ExpCompAck field in the read request message. Generally, when the CHI write request is sent from the HN node to the SN node, an acknowledgment message cannot be sent; when the CHI write request is sent from the RN node to the HN node, an acknowledgment message needs to be sent. Therefore, when the second acknowledgment message is detected from the SRSP response channel, the values ​​of its TxnID, SrcID, and TgtID fields are compared with the DBID, TgtID, and HomeNID cached in each item of the read cache array. If they all match, the match is successful, and the generation time of the second acknowledgment message is cached in the Info_srsp field of the matching cache item.

[0089] In this embodiment, the need for the receiver to send back an acknowledgment message is determined by the fields of the read request message. The corresponding second acknowledgment message is monitored in a targeted manner, and the cache matching is completed by combining the message generation time and the identification information, so as to achieve effective transaction closure.

[0090] In one embodiment, such as Figure 7 As shown, another method for protocol message matching and performance analysis is provided, including the following steps: Step 1: Begin a new round of read and write operation matching.

[0091] Step 2: The REQ channel detected a new CHI request message.

[0092] Step 3: Determine the read / write type.

[0093] The conversion process from CHI protocol to AXI protocol is achieved through... Figure 1 or Figure 2 The conversion module performs the conversion, and the CHI request messages that need to be converted only contain read and write operations. Therefore, by analyzing the value of the opcode field in the CHI request message, it is determined whether it is a read or write operation. If it is a write operation, skip to Step 4; if it is a read operation, skip to Step 40.

[0094] Step 4: The sequence generator inserts an initial sequence number into the detected write request message.

[0095] Step 5: Traverse the write cache array and allocate free storage items.

[0096] Step 6: Extract the required information from the write request message and fill it into the corresponding fields of the new allocation item.

[0097] The values ​​of the addr, TxnID, SrcID, and TgtID fields, representing address information, transaction ID, source ID, and destination ID, as well as their generation time, from the read request packets monitored by the REQ channel, are cached in the Addr_op, TxnID, SrcID, TgtID, and Infor_req fields of the write cache array storage item, respectively. Simultaneously, the initial sequence number generated by the sequence generator for the write request packets is cached in the Req_o field of the write cache array storage item.

[0098] Step 7: Monitor the first write response message of the CRSP channel, including DBIDResp message, or Comp message, or CompDBIDResp message.

[0099] After receiving the write request message, the write request receiver must respond with DBIDResp and Comp messages. DBIDResp must be completed before the data message. However, depending on the implementation, the Comp message can be sent before or after the data message. If the Comp message is sent before the data message, it can be combined with DBID into a single CompDBIDResp message, or it can remain two separate messages: DBIDResp and Comp. If one or more messages are monitored on the CRSP channel, proceed to Step 8 for information extraction and caching. If all response messages before the data message have been monitored, proceed to Step 18.

[0100] Step 8: Extract the initial sequence number from the write request message.

[0101] The sequence extractor will extract the initial sequence number Req_o from the write request message and assign it to the crsp_o field of the first write response message.

[0102] Step 9: By matching IDs, index the various ID fields in the first write response message to the write cache array and find the storage item of the corresponding write request message in the write cache array.

[0103] Step 10: Extraction and caching of CRSP channel response message information.

[0104] The value of the DBID field and the message generation time in the first write response message are extracted and cached in the DBID and Info_crsp fields of the matching item, respectively. If the first write response message is a RetryAck message, the value of its PCrdType field and the message generation time are extracted and cached in the PCrdType and Info_crsp fields of the matching item, respectively.

[0105] Step 11: Check if the value of the opcode field of the first response message is a RetryAck message indicating that the message needs to be retransmitted. If it is a RetryAck message, proceed to Step 12; otherwise, proceed to Step 18.

[0106] If the write request receiver is temporarily unable to complete receiving the data, it will set the opcode value of the first write response message to RetryAck to inform the sender that this write operation is invalid. After the write request receives the RetryGrant message, it will request the sender to resend this write request.

[0107] Step 12: Monitor the RetryGrant messages given by the CRSP channel.

[0108] If a RetryGrant message is detected in the CRSP channel, it indicates that the write request receiver has the ability to receive data, and the write operation will be retransmitted at a later time.

[0109] Step 13: Extract the sequence number for the RetryGrant message of the CRSP channel.

[0110] This is a potential performance optimization point in the design, so relevant information needs to be recorded for subsequent performance analysis. Therefore, operations such as message matching, information extraction, and caching are required. The initial sequence number Req_o from the write request message will be extracted and assigned to the crsp_o field of the first write response message.

[0111] Step 14: Locate the storage item in the write cache array corresponding to the write request message of the first write response message by matching the ID.

[0112] The values ​​of the PCrdType, SrcID, TgtID, and crsp_o fields in the first write response message are compared with the fields PCrdType, TgtID, SrcID, and Req_o to be matched in the write buffer array, respectively. If they all match, the match is successful.

[0113] Step 15: Extraction and caching of CRSP channel response message information.

[0114] The generation time of the first response message of the CRSP channel is extracted and cached in the Info_crsp field of the matching item.

[0115] Step 16: Set the retry field of the storage item to guide subsequent performance analysis.

[0116] In subsequent performance analysis, the frequency of retry and the time spent on hardware resource readiness can be calculated mainly based on the generation time of RetryAck and RetryGrant messages. However, the performance data of this write operation cannot be used for other performance analyses such as memory access latency and data transfer bandwidth. Therefore, the data of this write operation is identified by setting the retry field of the storage item.

[0117] Step 17: Release the storage item in the write message matching cache array for this write operation.

[0118] You can invalidate the cached item allocated for this write operation by setting a field specifically indicating whether the storage item is valid. Subsequent write requests will then be treated as a new write operation and proceed to Step 1.

[0119] Step 18: Wait for WDAT channel data packets.

[0120] Step 19: Extract the sequence number. The sequence extractor will extract the initial sequence number Req_o from the write request message and assign it to the Dat_o field of the first write data message.

[0121] Step 20: Determine whether the write operation needs to be cancelled.

[0122] Analyze the value of the opcode field in the first write data packet. If it is WriteDataCancel, it means that the write operation needs to be canceled, so proceed to Step 21; otherwise, proceed to Step 22.

[0123] Step 21: By setting a field to indicate whether the storage item is valid, the cache item allocated for this write operation is directly invalidated.

[0124] Step 22: Locate the storage item in the write cache array for the write request message corresponding to the first data message by ID matching.

[0125] The values ​​of the TxnID, SrcID, TgtID, and dat_o fields of the first data packet of the WDAT channel are compared with the DBID, TgtID, SrcID, and Req_o cached in each item of the write cache array, respectively. If they match, it means that the match is successful.

[0126] Step 23: Extraction and caching of WDAT channel data packets.

[0127] The generation time of the first data packet of the WDAT channel is extracted and cached in the Info_dat field of the matching item.

[0128] Step 24: Monitor the SRSP channel for CompAck response messages.

[0129] After the CHI end sends a write data packet, the AXI end can then send an axi write address packet. Therefore, it is necessary to proceed to Step 25 and Step 34 respectively, while simultaneously monitoring the response packets of the SRSP channel of the CHI protocol end and various packets of the axi protocol end.

[0130] Step 25: Extract the sequence number of the CompAck message for the SRSP channel.

[0131] Step 26: Locate the storage item in the write message matching cache array for the request message corresponding to this response message by ID matching.

[0132] The values ​​of the TxnID, SrcID, TgtID, and SRsp_o fields in the SRSP channel response message are compared with the DBID, TgtID, SrcID, and Req_o values ​​cached in the write message matching cache array, respectively. If they match, it indicates a successful match.

[0133] Step 27: Extraction and caching of SRSP channel CompAck message information.

[0134] Extract the CompAck message generation time and cache it in the Info_srsp field of the matching item.

[0135] Step 28: Monitor AXI write address messages.

[0136] To meet the timing requirements of the AXI protocol, after receiving a CHI write request, the CHI write request receiver sends a CRSP first response message to confirm that it can process the write operation, and receives a CHI first write data message to confirm that the write cannot be canceled, the component can then send an AXI write address message.

[0137] Step 29: AXI message sequence allocation.

[0138] Step 30: Complete the matching of AXI write address messages and CHI write request messages.

[0139] If the value of the awaddr field representing address information in the write address message is consistent with the value of the initial address Addr_op field in the storage item, and the initial sequence number Req_o field is generated earliest among all address matching storage items, then the storage item is a matching item.

[0140] Step 31: Extract and cache address message information using AX.

[0141] The generation time of the AXI address message is extracted and cached in the Info_waddr field of the matching item.

[0142] Step 32: Monitor the second AXI write data packet Step 33: Complete the matching of the target sequence number between the AXI second write data packet and the write address packet.

[0143] Step 34: Extraction and caching of AXI data message information.

[0144] The time of the second write data packet generation is cached in the Infor_wdata field of the write cache array match.

[0145] Step 35: Monitor the AXI second write response message Step 36: Complete the matching of the target sequence number between the AXI second response message and the write address message.

[0146] The AXI sequencer allocator inserts a sequence number w_o to ensure that the value of w_o belonging to the same AXI write operation is consistent with the value of the target sequence number aw_o. Then, the AXI sequencer matcher compares the value of w_o in the second write data packet with the value of Axi_worder of the storage item in the write cache array. If they match, the match is successful.

[0147] Step 37: Extraction and caching of AXI response message information.

[0148] The generation time of the second write response message is cached in the Infor_b field of the write cache array match.

[0149] Step 38: Message integrity check and alarm.

[0150] Step 39: Export data and release stored items.

[0151] Step 40: Traverse the message reading and matching cache array, and allocate free storage items.

[0152] Step 41: Extract the required information from the REQ request message and fill it into the corresponding fields of the new allocation item.

[0153] The values ​​of the addr, TxnID, SrcID, TgtID, ReturnNID, and ReturnTxnID fields of the CHI read request message, as well as the message generation time, are cached in the Addr_op, TxnID, SrcID, TgtID, ReturnNID, ReturnTxnID, and Infor_req fields of the storage item, respectively.

[0154] Step 42: Check if there are any new read response messages in the CRSP channel.

[0155] Upon receiving a CHI read request message, the CHI read request message receiver may first return a ReadReceipt message via the CRSP channel and then return a data message later, or return a data message directly later, or return a RetryAck message via the CRSP channel if it is temporarily unable to process the read operation.

[0156] Therefore, if no new response message is detected in the CRSP channel, the process jumps directly to Step 51; if a new response message is detected in the CRSP channel, both ReadReceipt and RetryAck messages need to be matched and information extracted, so the process proceeds to Step 43.

[0157] Step 43: Complete the matching of CRSP response messages and request messages.

[0158] Traverse each item in the read buffer array. If the values ​​of the TxnID, SrcID, and TgtID fields of the CRSP channel read response message are compared with the TxnID, TgtID, and SrcID cached in each item of the read buffer array, and they match, it indicates a successful match.

[0159] Step 44: Extract and cache response message information from the CRSP channel.

[0160] The values ​​of the DBID field and the message generation time from the read response message are extracted and cached in the DBID and Info_crsp fields of the matching item, respectively. The value of the opcode field is also recorded to determine whether the response message is a ReadReceipt or a RetryAck message. If the response message is a RetryAck message, the values ​​of the PCrdType field and the message generation time are extracted and cached in the PCrdType and Info_crsp fields of the matching item, respectively. Step 45: Determine the CRSP channel response message type.

[0161] Based on the value of the opcode field in the CRSP channel response message, determine whether the response message is a ReadReceipt message or a RetryAck message. If it is a ReadReceipt message, since information extraction and caching have already been completed, proceed directly to Step 500; if it is a RetryAck message, skip to Step 46.

[0162] Step 46: Monitor the RetryGrant messages given by the CRSP channel.

[0163] If a RetryGrant message is detected in the CRSP channel, it indicates that the read request receiver has the ability to provide data, and the read operation will be retransmitted at a later time.

[0164] Step 47: Locate the storage item in the read cache array corresponding to the read request message in the read response message by matching the ID.

[0165] The values ​​of the PCrdType, SrcID, and TgtID fields in the CRSP channel read response message are compared with the PCrdType, TgtID, and SrcID values ​​in each item of the cache matching array. If they match, it indicates a successful match.

[0166] Step 48: Extract and cache response message information from the CRSP channel.

[0167] The time when the read response message is generated is extracted and cached in the Info_crsp field of the matching item.

[0168] Step 49: Set the retry field of the storage item to guide subsequent performance analysis.

[0169] In subsequent performance analysis, the frequency of retry and the time spent on hardware resource readiness can be calculated mainly based on the generation time of RetryAck and RetryGrant messages. However, the performance data of this read operation cannot be used for other performance analyses such as memory access latency and data transfer bandwidth. Therefore, the data of this read operation is identified by setting the retry field of the storage item.

[0170] Step 50: Release the stored item in the read message matching cache array for this read operation.

[0171] You can invalidate the cached item allocated for this read operation by setting a field specifically indicating whether the storage item is valid. Subsequent write requests will then be treated as a new read operation and proceed to Step 1.

[0172] Step 51: Monitor AXI read address messages. Once the CHI read request receiver receives the CHI write request and confirms that it has the processing capability, it can send an AXI read address message.

[0173] Step 52: Complete the matching of AXI read address messages and CHI read request messages.

[0174] If the value of the Addr_op field matches the address in the AXI address message, then a storage item is matched.

[0175] Step 53: AXI Address Message Information Extraction and Caching. Extract the arid value and message generation time from the AXI address message and cache them respectively in the axi_arid and Info_waddr fields of the matching item.

[0176] Step 54: Monitor AXI read data packets.

[0177] Step 55: Complete the matching of AXI sequence numbers between AXI read data packets and AXI address packets. Match the rid field value of the second read data packet identification information with the arid in the read cache array storage item.

[0178] Step 56: Extraction and caching of AXI data message information.

[0179] The generation time of the second read data packet is cached in the Infor_rdata field of the read cache array match.

[0180] Step 57: Monitor RDAT channel data packets.

[0181] Step 58: By matching IDs, find the storage item in the read message matching cache array that corresponds to the read request message of the first data message.

[0182] The value of the ID field of the first read data packet is compared with the TxnID, TgtID, and SrcID cached in each item of the read cache array. If they all match, the match is successful.

[0183] Step 59: Extraction and caching of RDAT channel data packet information. Extract the generation time of the first read data packet and cache it in the Info_dat field of the matching item.

[0184] Step 60: Monitor the SRSP channel for CompAck response messages.

[0185] If the ExpCompAck field in the CHI request message is set to valid, it means that after receiving the read data, the CHI read request sender needs to return a CompAck message to the read request receiver via the SRSP channel, and thus enters Stpe61 for CompAck message processing; if the ExpCompAck field in the CHI request message is not set, it means that after receiving the read data, the CHI read request sender does not need to return a CompAck message to the read request receiver via the SRSP channel, and thus enters Stpe63 for data export.

[0186] Step 61: Locate the storage item in the read cache array corresponding to the read response message by matching the ID.

[0187] The values ​​of the TxnID, SrcID, and TgtID fields in the SRSP channel response message are compared with the DBID, TgtID, and SrcID in each item of the cache array that are cached in the read message. If they match, it means that the match is successful.

[0188] Step 62: Extraction and caching of SRSP channel CompAck message information.

[0189] The generation time of the CompAck message in the SRSP channel is extracted and cached in the Info_srsp field of the matching item.

[0190] Step 63: Message integrity check and alarm.

[0191] Under normal circumstances, if the sender of the CHI request message does not need to return a CompAck message to the receiver of the read request message via the SRSP channel, the receiver's receipt of the data message indicates that the entire read operation is complete. If the sender of the CHI request message needs to return a CompAck message to the receiver of the read request message via the SRSP channel, the receiver's receipt of the CompAck message indicates that the entire read operation is complete. At this time, all CHI and AXI messages involved in the read operation have been completed and successfully monitored, matched, extracted, and cached by this device. However, to detect potential functional defects in the DUT or this device, before data export, it is possible to check whether all CHI and AXI messages involved in the write operation have been completed and successfully monitored, matched, extracted, and cached by this device. If the check fails, an alarm is triggered; if the check passes, proceed to Step 64.

[0192] Step 64: Data export and storage item release.

[0193] All information stored in this storage item is exported to a specific location for subsequent data analysis and processing to obtain performance analysis results. Simultaneously, once the data export is complete, the storage item is immediately released to facilitate caching of related message information for subsequent data read / write operations.

[0194] The above embodiments propose a matching mechanism for AXI protocol messages to CHI protocol messages. Based on fully utilizing the order management and message matching mechanisms of CHI or AXI themselves, an additional order management and message matching mechanism is provided to achieve matching of all CHI and AXI protocol messages, thereby summarizing information such as address, operation type, effective data size, and generation time in each message. This not only provides technical support for full-cycle monitoring of read and write operations such as processor cores accessing disks and other peripherals via PMM or processor cores accessing memory via DCU, but also facilitates subsequent performance analysis. Subsequent performance analysis calculates the time overhead of each component in the access path, the data transmission bandwidth on each critical path, etc., making it easier to locate potential performance defects in the aforementioned memory access paths, thereby optimizing the design, improving performance, power consumption, and area balance design capabilities, effectively improving chip performance and shortening the chip development cycle.

[0195] It should be understood that although the steps in the flowcharts of the above embodiments are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the above embodiments may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0196] Based on the same inventive concept, this application also provides a protocol message matching and performance analysis apparatus for implementing the protocol message matching and performance analysis method described above. The solution provided by this apparatus is similar to the implementation scheme described in the above method; therefore, the specific limitations in one or more embodiments of the protocol message matching and performance analysis apparatus provided below can be found in the limitations of the protocol message matching and performance analysis method described above, and will not be repeated here.

[0197] In one embodiment, a protocol message matching and performance analysis apparatus is provided, comprising: a first protocol processing module, a second protocol processing module, and a performance data processing module, wherein: The first protocol processing module is used to determine the write request message and write cache array associated with the first protocol, and to determine the initial sequence number and initial address corresponding to the write request message; when the first write response message corresponding to the initial sequence number is detected based on the retransmission mechanism, the first write response message is matched and cached through the write cache array; when the first write data message associated with the first protocol is detected based on the cancellation mechanism, the first write data message is matched and cached according to the initial sequence number and the write cache array. The second protocol processing module is used to match and cache the write address message according to the initial address and the write cache array when a write address message associated with the second protocol is detected; determine the target sequence number corresponding to the write address message; and match and cache the second write data message and the second write response message associated with the target sequence number according to the write cache array.

[0198] The performance data processing module is used to extract data information from the write cache array after matching the cache, and to perform performance data processing and analysis.

[0199] In one embodiment, a computer device is provided, which may be a server, and its internal structure diagram may be as follows: Figure 8 As shown, this computer device includes a processor, memory, input / output interfaces (I / O), and a communication interface. The processor, memory, and I / O interfaces are connected via a system bus, and the communication interface is also connected to the system bus via the I / O interfaces. The processor provides computational and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system, computer programs, and a database. The internal memory provides the environment for the operating system and computer programs stored in the non-volatile storage media. The database stores protocol message matching and performance analysis data. The I / O interfaces are used for exchanging information between the processor and external devices. The communication interface is used for communication with external terminals via a network connection. When executed by the processor, the computer program implements a protocol message matching and performance analysis method.

[0200] Those skilled in the art will understand that Figure 8 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0201] In one embodiment, a computer device is also provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps in the above method embodiments.

[0202] In one embodiment, a computer-readable storage medium is provided storing a computer program that, when executed by a processor, implements the steps in the above method embodiments.

[0203] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, etc., and are not limited to these.

[0204] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0205] The above embodiments are merely illustrative of several implementation methods of this application, and their descriptions are relatively specific and detailed. However, they should not be construed as limiting the scope of this application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A method for protocol message matching and performance analysis, characterized in that, The method includes: Determine the write request message and write cache array associated with the first protocol, and determine the initial sequence number and initial address corresponding to the write request message; When the first write response message corresponding to the initial sequence number is detected based on the retransmission mechanism, the first write response message is matched and cached through the write cache array; When the first write data packet associated with the first protocol is detected based on the cancellation mechanism, the first write data packet is matched and cached according to the initial sequence number and the write cache array; When a write address packet associated with the second protocol is detected, the write address packet is matched and cached according to the initial address and the write cache array; Determine the target sequence number corresponding to the write address packet, and match and cache the second write data packet and the second write response packet associated with the target sequence number according to the write cache array; Extract data from the write cache array after matching the cache, and perform performance data processing and analysis.

2. The method according to claim 1, characterized in that, When the first write response packet corresponding to the initial sequence number is detected based on the retransmission mechanism, the first write response packet is matched and cached through the write cache array, including: Based on the field values ​​of the first response message, the current message type corresponding to the retransmission mechanism is determined; the current message type includes retry response messages and release authorization messages. The fields to be matched in the write cache array are determined based on the current message type; Based on the current performance analysis requirements and the generation time of the first write response message, the first write response message is matched and cached with the fields to be matched in the write cache array.

3. The method according to claim 1, characterized in that, When a first write data packet associated with the first protocol is detected based on the cancellation mechanism, the first write data packet is matched and cached according to the initial sequence number and the write cache array, including: Based on the field values ​​of the first write data packet, determine the corresponding operation type under the cancellation mechanism; the operation type includes write data cancellation and non-cancellation; The field to be operated on in the write cache array is determined according to the operation type; Based on the generation time of the first write data packet, the first write data packet is matched and cached with the fields to be operated on in the write cache array.

4. The method according to any one of claims 1 to 3, characterized in that, After matching and caching the first write response message, the process also includes: When the field information in the write request message indicates that a response from the receiver is required, the first acknowledgment message corresponding to the initial sequence number is monitored; the first acknowledgment message is transmitted through the slave response channel SRSP of the first protocol, and the first write response message is transmitted through the master response channel CRSP of the first protocol. Based on the generation time of the first confirmation message and the write cache array, the first confirmation message is matched and cached.

5. The method according to claim 1, characterized in that, Determining the target sequence number corresponding to the write address packet includes: Obtain the first register sequence number, the second register sequence number, and the circular sequence number in the write cache array; A new first register number is obtained based on the first register number and the historical register number; The cyclic sequence number is partitioned and padded to obtain the padded result, and a new second register sequence number is obtained based on the padded result and the second register sequence number; Overflow judgment is performed based on the cycle number, and the target number is selected from the new first register number and the new second register number.

6. The method according to claim 1, characterized in that, The method further includes: Identify the read request message and read cache array associated with the first protocol; When a read response message corresponding to the read request message is detected based on the retransmission mechanism, the read response message is matched and cached through the read cache array; The first read data packet associated with the first protocol is matched and cached with the read cache array; When a read address message corresponding to the second protocol is detected, the read address message is matched and cached according to the address information in the read request message and the read cache array; Based on the identification information of the read address packet and the read cache array, the detected second read data packet is matched and cached; Extract data from the read cache array after matching the cache, and perform performance data processing and analysis.

7. The method according to claim 6, characterized in that, When a read response message corresponding to the read request message is detected based on the retransmission mechanism, the read response message is matched and cached through the read cache array, including: Based on the field values ​​of the read response message, the actual message type corresponding to the retransmission mechanism is determined; the actual message type includes retry response messages and release authorization messages. The fields to be matched in the read cache array are determined based on the actual message type. Based on actual performance analysis requirements and the generation time of the read response message, the read response message is matched and cached with the fields to be matched in the read cache array.

8. The method according to claim 6, characterized in that, The method further includes: When the field information in the read request message indicates that a response from the receiver is required, a second confirmation message is monitored; the second confirmation message is transmitted through the slave response channel SRSP of the first protocol, and the read response message is transmitted through the master response channel CRSP of the first protocol; Based on the generation time and identification information of the second confirmation message, the second confirmation message is matched and cached with the read cache array.

9. A protocol message matching and performance analysis device, characterized in that, The device includes: The first protocol processing module is used to determine the write request message and write cache array associated with the first protocol, and to determine the initial sequence number and initial address corresponding to the write request message; when the first write response message corresponding to the initial sequence number is detected based on the retransmission mechanism, the first write response message is matched and cached through the write cache array; when the first write data message associated with the first protocol is detected based on the cancellation mechanism, the first write data message is matched and cached according to the initial sequence number and the write cache array. The second protocol processing module is used to, when a write address packet associated with the second protocol is detected, match and cache the write address packet according to the initial address and the write cache array; determine the target sequence number corresponding to the write address packet, and match and cache the second write data packet and the second write response packet associated with the target sequence number according to the write cache array; The performance data processing module is used to extract data information from the write cache array after matching the cache, and to perform performance data processing and analysis.

10. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 8.

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