A hardware real-time row data compensation method for SLED stepwise misalignment

Abstract

This invention discloses a hardware real-time line data compensation method for SLED stepped misalignment, belonging to the field of LED printing control technology. The method includes: configuring a delay line parameter N for even-numbered SLED rows in the SLED printhead; configuring two independent BRAM buffers for each color channel during data forwarding from external memory (DDR) to line buffer memory (BRAM); when K is less than N, only the Kth row data is written to the normal line buffer; when K is greater than or equal to N, the Kth row data is written to the normal line buffer, while simultaneously reading the K-Nth rows and writing them to the delay line buffer; during the LED scan drive output stage, switching between the normal line buffer and the delay line buffer for reading based on the address type flag. This invention achieves real-time hardware processing, adapts to different printheads, and consumes low storage resources.

Description

Technical Field

[0001] This invention relates to the field of LED printing control technology, specifically to a hardware real-time line data compensation method for SLED stepped misalignment. Background Technology

[0002] In a scanning LED (SLED) printing system, the printhead consists of multiple groups (usually 20 groups) of SLED units arranged in a line along the printing line direction. To ensure that there are no gaps and that adjacent groups of SLEDs are tightly connected in the horizontal direction (main scanning direction), the SLED printhead usually adopts a stepped arrangement design: odd-numbered SLED units are arranged in a straight line, and even-numbered SLED units are arranged in another straight line parallel to it, with the two groups of SLEDs staggered up and down like steps.

[0003] While this stepped arrangement solves the problem of horizontal gaps, it introduces a vertical (sub-scanning direction) misalignment problem: odd-numbered SLEDs and even-numbered SLEDs have a fixed physical offset (i.e., step height) in the vertical direction. If the system outputs the same line of print data to both odd-numbered and even-numbered SLEDs simultaneously, regular, intermittent, staggered stripes will appear on the printed image, severely affecting print quality.

[0004] Regarding the above problems, the existing solutions and their shortcomings are as follows:

[0005] 1. Software Preprocessing Correction: When generating the print data file, the host computer pre-corrects the row data corresponding to even-numbered SLEDs by adjusting their position. This means that the even-numbered rows are written to the data file a certain number of rows ahead or behind based on the step height. This approach has the following drawbacks:

[0006] (1) Heavy computing burden on the host computer: It is necessary to perform complex row and column rearrangement calculations on the entire page of printed data, and the amount of data is huge (typical page 4864 pixels × 6882 rows ≈ 33 million pixels / color, 4 colors total more than 130 million pixels).

[0007] (2) Poor adaptability: The step height of different models of SLED printheads is different. Each time the printhead is replaced, the host computer needs to regenerate the corresponding data file, which makes it impossible to achieve hardware universality.

[0008] (3) Cannot be dynamically adjusted: The printhead step height parameter is fixed after the hardware design is finalized, and it is impossible to optimize the parameter during runtime through software configuration;

[0009] (4) Inability to flexibly adapt to different paper feed speeds: The amount of image misalignment caused by step misalignment is directly related to the paper feed speed. The amount of pre-correction required per page varies at different printing speeds. If software preprocessing is used, corresponding data files must be generated for each paper feed speed. It is impossible to dynamically switch printing speeds during runtime, which severely limits the flexibility and efficiency of the printing system.

[0010] 2. Additional row buffer memory: This method uses a large-capacity FIFO or SRAM to cache entire pages of data, and then separates odd and even rows during output using address offsets. The drawbacks of this approach are high storage resource consumption, high cost, and complex address management.

[0011] In summary, existing solutions suffer from problems such as heavy computational burden on the host computer for preprocessing, large data transmission volume, poor adaptability, and high storage resource consumption. Therefore, there is an urgent need for a row data compensation method that can perform odd-even row data compensation in real time at the hardware level, without requiring host computer preprocessing, with low storage resource consumption, and with flexibly configurable parameters. Summary of the Invention

[0012] The purpose of this invention is to provide a hardware real-time line data compensation method for SLED stepped misalignment, which achieves real-time hardware processing, adapts to different printheads, and consumes low storage resources.

[0013] To achieve the above objectives, the present invention provides a technical solution:

[0014] A hardware-based real-time line data compensation method for SLED stepped misalignment includes:

[0015] S1, Configure a delay line parameter N for the even-numbered SLED rows in the SLED printhead, wherein the delay line parameter N is the number of rows in which the even-numbered SLED rows are vertically misaligned relative to the odd-numbered SLED rows;

[0016] S2, during the data forwarding process from external memory DDR to row buffer memory BRAM, two independent BRAM buffers are configured for each color channel, including: normal row buffer and delayed row buffer, wherein the normal row buffer is used to store the normal row data required for odd SLED rows, and the delayed row buffer is used to store the delayed row data required for even SLED rows;

[0017] S3, when processing the Kth row of data, perform the following operation:

[0018] When K≥N, the Kth row of data is written to the normal row buffer, and the KNth row of data is read from the external memory DDR and written to the delayed row buffer.

[0019] When K<N, write the K-th row of data into the normal row buffer, do not read the delayed row data, and skip the write operation of the delayed row buffer;

[0020] S4, in the LED scanning drive output stage, set the address type flag bit rd_addr_XorY, and switch and select reading between the normal row buffer and the delayed row buffer according to the indication of the address type flag bit rd_addr_XorY; wherein, when outputting odd-numbered SLED data, read data from the normal row buffer; when outputting even-numbered SLED data, read data from the delayed row buffer.

[0021] Further, the delayed row parameter N is set according to the physical step height of the SLED print head, and is externally configured via the I²C bus, wherein N is a positive integer with a value ranging from 0 to 255.

[0022] Further, an LED printer adopts a line-by-line scanning printing method for printed image pixels, and a delayed row parameter N is set. If the current odd-numbered SLED row outputs the i-th row of data, the current even-numbered SLED row outputs the i-N-th row of data.

[0023] Further, in S2, both the normal row buffer and the delayed row buffer adopt a Ping-Pong double buffer architecture, wherein

[0024] The normal row buffer includes a normal row Ping half area and a normal row Pong half area, which alternately store and read normal data of odd-numbered SLED rows;

[0025] The delayed row buffer includes a delayed row Ping half area and a delayed row Pong half area, which alternately store and read delayed data of even-numbered SLED rows;

[0026] The write enable of the normal row Ping half area, the normal row Pong half area, the delayed row Ping half area and the delayed row Pong half area are independently controlled, and the reading side selectively outputs through the address type flag bit.

[0027] Further, in the data forwarding process from the external memory DDR to the row buffer memory BRAM, the print data stored in color partitions in the external memory DDR is written line by line into the BRAM buffer corresponding to the color channel.

[0028] Further, in S3, the K-N-th row of data is historical data delayed by N rows, and the delayed row buffer always stores historical row data that is N rows behind the current row, corresponding to the data row required for step misalignment of even-numbered SLED rows.

[0029] Furthermore, in S4, when an odd number of SLED data is output, the address type flag rd_addr_XorY=0, pointing to the normal row buffer, with an address range of 0~255, at which time normal row data is read;

[0030] When an even number of SLED data is output, the address type flag rd_addr_XorY=1, pointing to the delayed line buffer, with an address range of 256~511. At this time, historical data with a delay of N lines is read.

[0031] Furthermore, in S4, the value of the address type flag bit rd_addr_XorY is determined by the pin position counter cnt22: when cnt22=0~9, rd_addr_XorY=0, pointing to the odd-numbered SLED window; when cnt22=11~20, rd_addr_XorY=1, pointing to the even-numbered SLED window.

[0032] Furthermore, in S4, the BRAM read addresses for odd-numbered SLED rows and the BRAM read addresses for even-numbered SLED rows use different generation directions:

[0033] For the normal row buffer BRAM of odd SLED data, the read address is generated by a decreasing scan method, decreasing from 255 to 0; for the delayed row buffer BRAM of even SLED data, the read address is generated by an increasing scan method, increasing from 256 to 511.

[0034] Furthermore, within a complete SLED row scan cycle, odd-numbered SLED data and even-numbered SLED data are output alternately in time sequence, wherein...

[0035] During the first half of the scan cycle, the odd SLED data path is activated, the address type flag is kept in normal row mode, and data is read from the normal row buffer and output to the odd SLED unit.

[0036] During the latter half of the scan cycle, the even-numbered SLED data path is activated, the address type flag is switched to delayed row mode, and data is read from the delayed row buffer and output to the even-numbered SLED unit.

[0037] Compared with the prior art, the beneficial effects of the present invention are:

[0038] 1. The hardware real-time row data compensation method for SLED stepped misalignment of the present invention realizes real-time hardware processing with zero host computer overhead.

[0039] The host computer only needs to send the raw line-by-line printing data without any correction. The separation of odd and even lines and the delay compensation are all completed by the hardware in real time during the data forwarding and LED output stages.

[0040] The method of this invention overcomes the shortcomings of existing software preprocessing correction methods and achieves the following technical effects:

[0041] (1) Eliminate data rearrangement calculations in the host computer: No need to perform odd / even row offset correction on the entire page of data;

[0042] (2) Reduce data transmission volume: The original data file size remains unchanged, and there is no need to transmit the corrected redundant data;

[0043] (3) Shorten the first print delay: The data can be sent immediately after the host computer generates the data, without waiting for the preprocessing to be completed.

[0044] 2. The hardware real-time line data compensation method for SLED stepped misalignment of the present invention enables parameterized configuration and adapts to different printheads.

[0045] The delay line count parameter N is written via an external configuration interface (I²C bus) and supports flexible configuration within the range of 0 to 255 lines. When changing to a different model of SLED printhead, only the N value needs to be modified to adapt to the new step height, without modifying the hardware logic or regenerating the data file.

[0046] 3. The hardware real-time row data compensation method for SLED step-like misalignment of the present invention has low storage resource consumption.

[0047] Each color requires only 4 BRAMs (Ping + Pang + Ping_delayLine + Pang_delayLine), significantly reducing the total storage capacity compared to Scheme B (Extra Line Buffer Memory). The BRAM capacity is determined by the number of pixels per line (typically 4864 pixels / line = 4864 bits / color) and the number of delayed lines (typically 5~50 lines), rather than the total page size.

[0048] 4. The hardware real-time row data compensation method for SLED stepped misalignment of the present invention achieves uninterrupted data flow.

[0049] Normal and delayed row data are prefetched simultaneously during the DDR→BRAM stage, and seamlessly switched through the address type flag during the LED output stage. There is no waiting or data loss during the entire data stream process.

[0050] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0051] Figure 1 This is a flowchart of the hardware real-time row data compensation method for SLED stepped misalignment according to the present invention.

[0052] Figure 2 This is a system architecture diagram of the hardware real-time row data compensation method for SLED stepped misalignment according to the present invention.

[0053] Figure 3 This is a schematic diagram illustrating how printed data in the DDR of the present invention is read line by line and written to BRAM;

[0054] Figure 4 This is a schematic diagram illustrating the alternating output of odd and even row data during the SLED row scanning cycle of the present invention.

[0055] Figure 5 This is a flowchart illustrating the generation of BRAM read addresses for odd-numbered SLED rows according to the present invention.

[0056] Figure 6 This is a flowchart illustrating the generation of BRAM read addresses for even-numbered SLED rows in this invention.

[0057] Figure 7 This is a schematic diagram of the read address format of the present invention. Detailed Implementation

[0058] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0059] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0060] This invention proposes a hardware-based real-time line data compensation method for SLED stepped misalignment, applied to SLED printing systems. It addresses the vertical data misalignment caused by the physical stepped arrangement of the SLED printhead. This invention combines pre-classified storage at the data end with output address type selection to achieve real-time hardware-level compensation for odd and even SLED lines.

[0061] Reference Figure 1-7 As shown, this disclosure provides a hardware real-time line data compensation method for SLED stepped misalignment, including:

[0062] S1, configures the delay line parameter N for the even-numbered SLED rows in the SLED printhead.

[0063] Specifically, the delay row parameter N is the number of rows that the even-numbered SLED rows are vertically offset from the odd-numbered SLED rows, and it can be configured externally through an external configuration interface (such as the I²C bus). N is a positive integer, ranging from 0 to 255. That is, the delay row parameter N can be dynamically adjusted within the range of 0 to 255 rows during runtime, enabling flexible configuration.

[0064] In this invention, the delay line parameter is set according to the physical step height of the SLED printhead. When replacing with a different model of SLED printhead, only the N value needs to be modified to adapt to the new step height, without modifying the hardware logic or regenerating the data file.

[0065] Specifically, N depends on the vertical (paper feed direction) stagger distance of the odd and even SLEDs in the current SLED printhead and the paper feed speed. The specific value of N needs to be preset and adjusted according to whether the actual printing effect is aligned. The printouts can be aligned by setting an appropriate value of N.

[0066] Because the step-like misalignment error caused by the vertical spacing of SLEDs is often only 1mm, and it is not convenient to measure it accurately directly, it needs to be adjusted according to the actual printing results. For example, if the step-like misalignment is very obvious, N should be increased appropriately until the printed image is aligned.

[0067] If we set the derivation formula for N, it can be:

[0068] N=

[0069] Where dpi is the vertical row resolution and z is the vertical error distance of the step misalignment.

[0070] S2 configures two independent BRAM buffers for each color channel during the data forwarding process from external memory DDR to line buffer memory BRAM: a normal line buffer and a delayed line buffer.

[0071] refer to Figure 2 The external memory DDR stores print data according to color partitions. During the data forwarding process from the external memory DDR to the line buffer memory BRAM, the print data stored in the external memory DDR according to color partitions is written line by line into the BRAM buffer of the corresponding color channel.

[0072] Specifically, there are two independent BRAM buffers: a normal row buffer and a delayed row buffer. The normal row buffer stores the normal row data required for odd-numbered SLED rows, while the delayed row buffer stores the delayed row data required for even-numbered SLED rows.

[0073] In this invention, both the normal line buffer and the delayed line buffer adopt a Ping-Pong double buffering architecture.

[0074] The normal row buffer includes the normal row Ping half and the normal row Pang half, which alternately store and read normal data from odd-numbered SLED rows.

[0075] The delayed line buffer consists of a delayed line Ping half-area and a delayed line Pang half-area, which alternately store and read delayed data for even-numbered SLED lines.

[0076] That is, each color channel is provided with two independent BRAM buffers, which together comprise four BRAM storage areas: the normal row Ping half-area, the normal row Pang half-area, the delayed row Ping half-area, and the delayed row Pang half-area. Write and read operations are performed alternately in these four half-areas to ensure that data writing and reading occur simultaneously without conflict.

[0077] The normal row buffer includes the normal row Ping half and the normal row Pang half, which alternately store and read normal data from odd-numbered SLED rows.

[0078] The delayed line buffer consists of a delayed line Ping half-area and a delayed line Pang half-area, which alternately store and read delayed data of even-numbered SLED lines (i.e., historical data lagging behind N lines).

[0079] LED printers use a line-by-line scanning printing method to print the pixels of the image. During the paper scan, only the current line of data is printed at a time. Let the delay line parameter N be: if the current odd-numbered SLED line outputs the i-th line of data, then the current even-numbered SLED line outputs the iN-th line of data.

[0080] For example, N=2, meaning a delay of 2 lines. If the current odd-numbered SLED output is the data from the i-th line, then the current even-numbered SLED output is the data from the (i-2)-th line. In other words, when the paper scrolls to the first line of odd-numbered SLED output, even-numbered SLEDs do not output. Then, when scrolling to the second line of odd-numbered output, even-numbered SLEDs also do not output. When the third line of odd-numbered output is reached, even-numbered SLEDs output the data of the corresponding pixel from the first line, and so on.

[0081] In the present invention, the write enable of the normal row Ping half area, the normal row Pang half area, the delayed row Ping half area and the delayed row Pang half area are independently controlled, and the reading side performs selective output through an address type flag bit.

[0082] Only 4 BRAMs are required for each color (normal row Ping half area Ping + normal row Pang half area Pang + delayed row Ping half area Ping_delayLine + delayed row Pang half area Pang_delayLine). The BRAM capacity is determined by the number of pixels per single row (typically 4864 pixels per row = 4864 bits per color) and the number of delayed rows (typically 5 to 50 rows), instead of the data amount of the entire page.

[0083] S3, when processing the K-th row of data, perform the following operations:

[0084] When K<N, write the K-th row of data into the normal row buffer, do not read delayed row data, and skip the write operation to the delayed row buffer.

[0085] When K≥N (the first N rows starting from the page), write the K-th row of data into the normal row buffer, and simultaneously read the (K-N)-th row of data (that is, the historical data delayed by N rows) from the external memory DDR and write it into the delayed row buffer.

[0086] Through the above operations, the delayed row buffer always stores historical row data that lags the current row by N rows, which exactly corresponds to the data rows required for the step misalignment of even-numbered SLED rows.

[0087] Refer to Figure 2 , in this step, the DDR address of the delayed row calculated by the data forwarding controller is:

[0088] Delayed row address = current processing row number - N.

[0089] If the current processing row number is less than N (when K<N, in the page starting stage), the delayed row data will not be read, because the required delayed row data is outside the page range. Among the first N rows of data starting from the page, no data needs to be written into the delayed row buffer (because the required delayed row is outside the page). Whether it is necessary to read delayed row data is determined by judging whether the current row number is less than N, so as to avoid out-of-bounds access.

[0090] As Figure 3 shows, in the data forwarding stage, the print data stored by color partition in the external memory DDR is read row by row and written into the BRAM. Taking the K-th row as an example:

[0091] When K<N (the first N lines before the start of the page): only the normal-line BRAM is written, and the delayed-line BRAM is not written. When K≥N: the normal-line BRAM writes the K-th line data lineK, and meanwhile the delayed-line BRAM writes the (K-N)-th line data lineK-N.

[0092] Hereinafter, with reference to Figure 3 and Table 1, the corresponding relationship of DDR→BRAM row data forwarding is described by taking N=5 as an example.

[0093] Table 1 Corresponding relationship table of DDR row data forwarding (N=5)

[0094] DDR read row number Normal line BRAM write Delayed line BRAM write 0 line0 (Not written) 1 line1 (Not written) 2 line2 (Not written) 3 line 3 (Not written) 4 line 4 (Not written) 5 line 5 line0 6 line 6 line1 7 line 7 line2 ... ... ... K lineK lineK-N

[0095] S4, in the LED scanning drive output stage, the LED output controller sets an address type flag bit rd_addr_XorY, and switches and selects reading between the normal line buffer and the delayed line buffer according to the indication of the address type flag bit rd_addr_XorY.

[0096] Specifically, S4: in the LED scanning drive output stage, according to whether the currently output data is odd SLED data or even SLED data, the address type flag bit rd_addr_XorY (1bit) is used to select to read data from the corresponding BRAM buffer.

[0097] In the present invention, the value of the address type flag bit rd_addr_XorY is determined by the pin position counter cnt22.

[0098] When cnt22=0~9, rd_addr_XorY=0, which points to the odd SLED window;

[0099] When cnt22=11~20, rd_addr_XorY=1, which points to the even SLED window.

[0100] Specifically, when outputting odd SLED data (the pin position counter is in the odd SLED output window), the address type flag bit rd_addr_XorY=0, which points to the normal line buffer with an address range of 0~255, and data is read from the normal line buffer.

[0101] When outputting even SLED data (the pin position counter is in the even SLED output window), the address type flag bit rd_addr_XorY=1, which points to the delayed line buffer with an address range of 256~511, and historical data delayed by N lines is read from the delayed line buffer.

[0102] This invention uses the address type flag rd_addr_XorY to switch between two sets of buffers. That is, the corresponding buffer is selected by the address type flag.

[0103] like Figure 4 As shown, odd-numbered SLED data and even-numbered SLED data are output alternately in time sequence within a complete SLED row scan cycle (e.g., 6692 clock cycles).

[0104] 1. Initialization: Clock cycle from 0 to 2, cnt6692 = 0 to 2.

[0105] It should be noted that the number of clock cycles corresponds to the total number of rows. When the total number of rows is 6692, it corresponds to 6692 clock cycles, denoted as cnt6692. cnt6692 is a count from 0 to 6691, corresponding to the total number of rows. When the total number of rows changes, the clock cycle cntcnt, as a parameterized variable, also changes accordingly.

[0106] 2. X group windows (odd SLED windows): clock cycle from 2 to 10, cnt6692=2 to 10.

[0107] During the first half of the scan cycle, the odd SLED data path is activated (pin_selected_X is loaded and shifted, address type flag rd_addr_XorY=0), the address type flag remains in normal row mode, and data is read from the normal row buffer and output to the odd SLED cell.

[0108] 3. Transition gap: Clock cycle from 10 to 13, cnt6692 = 10 to 13.

[0109] By leaving an isolation gap between the two time windows, conflicts can be avoided when switching data.

[0110] 4. Y group window (even-numbered SLED window): clock cycle from 13 to 21, cnt6692 = 13 to 21.

[0111] During the latter half of the scan cycle, the even-numbered SLED data path is activated (pin_selected_Y is loaded and shifted, address type flag rd_addr_XorY=1), the address type flag is switched to delayed row mode, and data is read from the delayed row buffer and output to the even-numbered SLED cell.

[0112] 5. Remaining Stages: Clock cycle from 21 to 5643, cnt6692 = 21 to 5643: Valid data output. Clock cycle from 5644 to 6691, cnt6692 = 5644 to 6691: Line termination.

[0113] The timing of BRAM address generation is explained below.

[0114] In this invention, the BRAM read addresses of odd-numbered SLED rows and the BRAM read addresses of even-numbered SLED rows are generated in different directions, and the two sets of address generation are completely independent.

[0115] like Figure 5 As shown, the X group read address generation (decreasing mode, corresponding to odd SLED): For the normal row buffer BRAM of odd SLED data, the read address is generated by decreasing scan mode, and the read address decreases from 255 to 0.

[0116] The BRAM read address for the odd-numbered SLED rows is represented by address group X, and the generation process is as follows:

[0117] 1. cnt6692=0: This indicates the moment when cnt6692 counts to 0, and is initialized; the initial address is rd_addr_X_tmp=255;

[0118] 2. Each time pin_selected_X(0)=1, that is, the operation at the current moment is the 0th data of group X, and the address is decremented by 1; where, since there are multiple odd SLED units, the 0th one represents the specific SLED.

[0119] 3. In decreasing mode, the address sequence is: 255, 254, 253, ..., 1, 0, 255, ..., that is, it decreases from 255 down to 0 and then returns to 255 and repeats the decreasing cycle.

[0120] 4. SLED printhead scanning and reading: Data is output from right to left.

[0121] like Figure 6 As shown, the read address generation for group Y (incrementing mode, corresponding to an even number of SLEDs) is as follows:

[0122] For even-numbered SLED data, the delayed row buffer BRAM is generated using an incremental scanning method, with the read address increasing from 256 to 511.

[0123] The BRAM read address for even-numbered SLED rows is represented by address group Y, and the generation process is as follows:

[0124] 1. cnt6692=10: This indicates the moment when cnt6692 counts to 10, and is initialized; the initial address is rd_addr_Y_tmp=256;

[0125] 2. Each time pin_selected_Y(0)=1, that is, the operation at the current moment is the 0th data of group Y, and the address is incremented by 1; where, since there are multiple even-numbered SLED units, the 0th one represents the specific SLED.

[0126] 3. In incrementing mode, the address sequence is: 256, 257, 258, ..., 510, 511, 256, ..., and so on, repeating in this manner.

[0127] 4. SLED printhead reads delayed line data: data is output from left to right.

[0128] like Figure 7 As shown, the read address format (14 bits) is as follows:

[0129] bit

[14] : rd_addr_XorY address type flag;

[0130] bit[13:0]: Data address.

[0131] That is, the highest bit, bit

[14] , represents the flag bit, and the remaining bits represent the address.

[0132] In this context, the address type flag rd_addr_XorY=0: Addresses 0~255 in group X point to the normal row BRAM; the address type flag rd_addr_XorY=1: Addresses 256~511 in group Y point to the delayed row BRAM.

[0133] Through the above steps, odd-numbered and even-numbered SLEDs each acquire their corresponding row data, thus compensating for the vertical misalignment caused by the stepped physical arrangement of the SLED printheads in real time at the hardware level. The physical mapping relationship is as follows:

[0134] X group output → odd number SLED(1,3,5,...,19) → Kth row of data lineK data;

[0135] Y group output → even number SLED(2,4,6,...,20) → KNth row of data lineK-N data (step misalignment has been compensated).

[0136] In summary, this invention employs a delayed row data prefetching and output selection mechanism: During the DDR→BRAM data forwarding phase, based on the configurable delayed row number parameter N, historical data lagging by N rows is prefetched from the external memory DDR and written into a dedicated delayed row BRAM buffer. During the LED output phase, the corresponding data source is selected between the normal row buffer and the delayed row buffer using the address type flag bit (rd_addr_XorY), ensuring that odd-numbered SLEDs and even-numbered SLEDs each obtain the correct row data, thus compensating for the vertical misalignment caused by the stepped physical arrangement in real time at the hardware level.

[0137] In the description of this invention, it should be understood that the indicated orientation or positional relationship is based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing this invention and simplifying the description, and is not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this invention.

[0138] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0139] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A hardware real-time line data compensation method for SLED stepped misalignment, characterized in that, Comprising: S1, configuring a delayed line parameter N for even-numbered SLED rows in a SLED printhead, wherein the delayed line parameter N is the number of rows that the even-numbered SLED rows are misaligned longitudinally relative to odd-numbered SLED rows; S2, in the process of data forwarding from an external memory DDR to a line buffer memory BRAM, configuring two independent groups of BRAM buffers for each color channel, comprising a normal line buffer and a delayed line buffer, wherein the normal line buffer is configured to store normal line data required by odd-numbered SLED rows, and the delayed line buffer is configured to store delayed line data required by even-numbered SLED rows; S3, when processing the K-th line of data, performing the following operations: when K≥N, writing the K-th line of data into the normal line buffer, and simultaneously reading the (K-N)-th line of data from the external memory DDR and writing it into the delayed line buffer; when K<N, writing the K-th line of data into the normal line buffer, not reading delayed line data, and skipping the writing operation for the delayed line buffer; S4, in the LED scan driving output stage, setting an address type flag bit rd_addr_XorY, and switching and selecting reading between the normal line buffer and the delayed line buffer according to the indication of the address type flag bit rd_addr_XorY; wherein when outputting odd-numbered SLED data, data is read from the normal line buffer; when outputting even-numbered SLED data, data is read from the delayed line buffer.

2. The hardware real-time row data compensation method for SLED stepped misalignment according to claim 1, characterized in that, The delayed line parameter N is set according to the physical step height of the SLED printhead, and is externally configured via an I²C bus, wherein N is a positive integer, with a value range of 0~255.

3. The hardware real-time row data compensation method for SLED stepped misalignment according to claim 1, characterized in that, An LED printer adopts a progressive scan printing mode for printed image pixels, and the delayed line parameter N is set; if the current odd-numbered SLED row outputs the i-th line of data, then the current even-numbered SLED row outputs the (i-N)-th line of data.

4. The hardware real-time row data compensation method for SLED stepped misalignment according to claim 1, characterized in that, In S2, both the normal line buffer and the delayed line buffer adopt a Ping-Pong double buffer architecture, wherein the normal line buffer comprises a normal line Ping half area and a normal line Pong half area, which alternately store and read normal data of odd-numbered SLED rows; the delayed line buffer comprises a delayed line Ping half area and a delayed line Pong half area, which alternately store and read delayed data of even-numbered SLED rows; The write enable of the normal line Ping half area, the normal line Pong half area, the delayed line Ping half area and the delayed line Pong half area are independently controlled, and the reading side selectively performs output through the address type flag bit.

5. The hardware real-time row data compensation method for SLED stepped misalignment according to claim 1, characterized in that, In the process of data forwarding from the external memory DDR to the line buffer memory BRAM, the print data stored in color partitions in the external memory DDR is written line by line into the BRAM buffer of the corresponding color channel.

6. The hardware real-time row data compensation method for SLED stepped misalignment according to claim 1, characterized in that, In S3, the (K-N)-th line of data is historical data delayed by N lines, and the delayed line buffer always stores historical line data that lags N lines behind the current line, corresponding to the data lines required by even-numbered SLED rows due to step misalignment.

7. The hardware real-time row data compensation method for SLED stepped misalignment according to claim 1, characterized in that, In S4, when an odd number of SLED data is output, the address type flag rd_addr_XorY=0, pointing to the normal row buffer, with an address range of 0~255, and at this time, normal row data is read. When an even number of SLED data is output, the address type flag rd_addr_XorY=1, pointing to the delayed line buffer, with an address range of 256~511. At this time, historical data with a delay of N lines is read.

8. The hardware real-time row data compensation method for SLED stepped misalignment according to claim 7, characterized in that, In S4, the value of the address type flag bit rd_addr_XorY is determined by the pin position counter cnt22: when cnt22=0~9, rd_addr_XorY=0, pointing to the odd-numbered SLED window; when cnt22=11~20, rd_addr_XorY=1, pointing to the even-numbered SLED window.

9. The hardware real-time row data compensation method for SLED stepped misalignment according to claim 7, characterized in that, In S4, the BRAM read addresses for odd-numbered SLED rows and the BRAM read addresses for even-numbered SLED rows use different generation directions: For the normal row buffer BRAM of odd SLED data, the read address is generated by a decreasing scan method, decreasing from 255 to 0; for the delayed row buffer BRAM of even SLED data, the read address is generated by an increasing scan method, increasing from 256 to 511.

10. The hardware real-time row data compensation method for SLED stepped misalignment according to claim 1, characterized in that, Within a complete SLED row scan cycle, odd-numbered SLED data and even-numbered SLED data are output alternately in time sequence. During the first half of the scan cycle, the odd SLED data path is activated, the address type flag is kept in normal row mode, and data is read from the normal row buffer and output to the odd SLED unit. During the latter half of the scan cycle, the even-numbered SLED data path is activated, the address type flag is switched to delayed row mode, and data is read from the delayed row buffer and output to the even-numbered SLED unit.

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