A universal interface control method, system, device and medium based on FPGA

Abstract

The application provides a general interface control method, system, device and medium based on FPGA. The method comprises the following steps: configuring the host interface protocol type for communicating with the upper computer, and allocating an isolated access address for a multi-path external condition receiving end to establish a processing channel; sending a tentative instruction and detecting a returned error flag bit, adjusting the read-write establishment time, data retention time and clock sampling phase according to the error flag bit, and determining a target timing window; establishing a communication link with the condition receiving end based on the target timing window; receiving a multi-path scrambled transmission stream, and respectively writing into corresponding processing channels for buffering and de-bouncing processing to generate a constant code rate transmission stream; and sending the constant code rate transmission stream to the condition receiving end through the communication link for descrambling, and sending the returned descrambled plaintext transmission stream to the upper computer. The application can improve the interface compatibility and communication stability of the condition receiving end, and realize stable descrambling and transmission of multi-path code streams.

Description

Technical Field

[0001] This application relates to the field of digital video broadcasting technology, and in particular to a general-purpose interface control method, system, device and medium based on FPGA. Background Technology

[0002] With the development of digital television broadcasting and multimedia communication technologies, the demand for concurrent processing of multi-channel high-definition and ultra-high-definition encrypted video streams continues to rise. When processing scrambled transport streams, digital front-end receiving equipment requires an external multiplexer (CAM (Conditional Access Module) card) for descrambling. In this process, managing the communication interfaces of the multiplexer and maintaining the transmission of multiple scrambled transport streams within the device are fundamental requirements for achieving video descrambling.

[0003] In existing technologies, the Common Interface (CI) control for conditional receivers is typically implemented using application-specific integrated circuits (ASICs) such as CIMAX chips. At the communication timing level, existing solutions often employ fixed read / write setup times and fixed data hold times based on the DVB-CI (Digital Video Broadcasting Common Interface) standard for signaling interaction with the conditional receiver. At the data flow level, a shared internal bus and centralized buffer resources are typically used to coordinate the transmission and reception of multiple streams. However, conditional receivers from different batches or manufacturers exhibit objective physical tolerances in their hardware level response, and scrambled streams input from external networks are often accompanied by bit rate fluctuations. In practical applications, existing technologies based on setting fixed timing parameters and centrally allocating hardware resources face risks such as interface communication handshake failures and data congestion between multiple channels leading to abnormal descrambled images when dealing with conditional receivers with different electrical response characteristics and concurrent input of multiple streams with fluctuating bit rates. Summary of the Invention

[0004] In view of this, this application provides a general interface control method, system, device and medium based on FPGA to solve the above problems.

[0005] Firstly, a general interface control method based on FPGA is provided, which includes:

[0006] Configure the host interface protocol type for communication with the host computer, and assign isolated access addresses to multiple external conditional receivers to establish multiple processing channels;

[0007] For each conditional receiver, a probe command is sent to the conditional receiver during initial access, and the error flag bit in the response status returned by the conditional receiver is checked.

[0008] Based on the error flag, cyclically adjust at least one of the read / write setup time, data hold time, and clock sampling phase of the access condition receiver until a target timing window with no error indication is determined.

[0009] Configure the communication timing of the processing channel corresponding to the conditional receiver to the timing parameters corresponding to the target timing window, and perform link negotiation and protocol interaction with the conditional receiver to establish a communication link;

[0010] The system receives multiple scrambled transport streams as input and writes each scrambled transport stream into the corresponding processing channel for independent buffering and dejittering based on a preset stream mapping relationship, thereby generating a constant bit rate transport stream.

[0011] Based on communication timing, a constant bit rate transport stream is sent to the conditional receiver via a communication link;

[0012] The receiving end receives the descrambled plaintext transport stream and sends it to the host computer.

[0013] The above technical solution, by configuring isolated parallel processing channels, dynamically and cyclically adjusting timing parameters to determine error-free target timing windows, and combining stream mapping relationships to perform independent asynchronous buffering and de-jitter processing on multiple scrambled streams, achieves stable adaptive physical access of a Field Programmable Gate Array (FPGA) to multiple external conditional receivers, ensuring constant bit rate transmission and accurate descrambling and backhaul of multiple scrambled transport streams in complex hardware delay environments.

[0014] Optionally, based on the error flag, at least one of the read / write setup time, data hold time, and clock sampling phase of the access condition receiver is cyclically adjusted until a target timing window with no error indication is determined. Specifically, this includes:

[0015] The read / write setup time and data hold time are fixed at the initial default parameters, the clock sampling phase is adjusted sequentially, and the status of the error flag is checked.

[0016] When the clock sampling phase completes the entire cycle and the error flag still indicates an error, the parameter values ​​for read / write setup time and data hold time are increased according to a preset ratio.

[0017] Based on the read / write setup time and data hold time after increasing the parameter values, the clock sampling phase is adjusted again in a loop until the target timing window with no error indication is determined.

[0018] The above technical solution provides a two-dimensional timing optimization mechanism from fast variables to slow variables by using read / write setup time and data hold time as fixed benchmarks to prioritize and sequentially adjust the clock sampling phase. When errors still exist after a complete phase traversal cycle, the benchmark time parameter is increased proportionally for a second loop traversal. This avoids the system from falling into blind exhaustive search or deadlock and ensures that a usable timing window can be determined under different hardware aging levels and trace delay characteristics.

[0019] Optionally, the parameter values ​​for read / write setup time and data retention time can be increased according to a preset ratio, specifically including:

[0020] Extract the bus feedback delay cycle number when sending the probe command;

[0021] Input the number of bus feedback delay cycles into the preset timing compensation mapping table, and look up the asymmetric increase ratio as the preset ratio.

[0022] Based on the asymmetric increase ratio, the non-symmetrical parameter increments for read / write setup time and data retention time are calculated respectively, resulting in the read / write setup time and data retention time after the parameter values ​​are increased.

[0023] The above technical solution extracts the actual feedback delay cycle number of the initial probe command on the bus and uses this cycle number to look up the asymmetric increase ratio in a table to calculate the asymmetric increment of read / write setup time and data hold time respectively. This directly introduces the actual objective delay feedback of the physical link into the timing adjustment model, achieving precise asymmetric timing compensation for specific hardware interface characteristics.

[0024] Optionally, the communication timing of the processing channel corresponding to the conditional receiver is configured with the timing parameters corresponding to the target timing window, and link negotiation and protocol interaction are performed with the conditional receiver to establish a communication link, specifically including:

[0025] The processing channel corresponding to the conditional receiver is identified as the target processing channel, and the timing parameters are written into the internal interface register of the target processing channel to start the link initialization mode.

[0026] In link initialization mode, a negotiation request message carrying the identifier of the target processing channel is sent to the condition receiver;

[0027] Based on communication timing, the receiving end establishes a communication link corresponding to the target processing channel based on the negotiation response feature code returned by the negotiation request message.

[0028] The above technical solution, by substantially writing the determined target timing parameters into the internal interface register of the channel and using the negotiation request message carrying a specific channel identifier to perform feature code handshake interaction in the link initialization mode, completes the establishment of the upper layer logical end-to-end protocol link from the solidification of the underlying physical timing parameters, ensuring the channel exclusivity and link reliability when the scrambled service data stream is sent out.

[0029] Optionally, the system receives multiple scrambled transport streams as input and, based on a preset stream mapping relationship, writes each scrambled transport stream into its corresponding processing channel for independent buffering and dejittering to generate a constant bit rate transport stream. Specifically, this includes:

[0030] Each scrambled transport stream is stored in the asynchronous first-in-first-out buffer queue corresponding to the processing channel;

[0031] Real-time monitoring of the current data level in the asynchronous first-in-first-out cache queue;

[0032] Based on the preset standard output clock tick, empty packet filling or redundant packet removal is dynamically performed according to the current data level to generate a constant bit rate transport stream.

[0033] The above technical solution, by storing each scrambled transport stream into the asynchronous first-in-first-out buffer queue corresponding to the processing channel and monitoring the water level of the physical buffer in real time, and combining the standard output clock beat to dynamically trigger empty packet filling or redundant packet removal actions based on the water level status, absorbs the instantaneous data jitter caused by the sudden input of the upstream bus and outputs a constant bit rate transport stream that strictly matches the processing clock of the downstream conditional receiver.

[0034] Optionally, based on a preset standard output clock tick, empty packet filling or redundant packet removal is dynamically performed according to the current data level to generate a constant bit rate transport stream, specifically including:

[0035] The current data water level is compared with the preset high water level safety threshold and low water level safety threshold respectively;

[0036] When the current data level is lower than the low water level safety threshold, a preset program reference clock correction empty packet is inserted into the scrambled transport stream to generate a constant bit rate transport stream.

[0037] When the current data level is higher than the high-level safety threshold, non-payload padding data packets in the scrambled transport stream are filtered out, and a constant bit rate transport stream is generated.

[0038] The above technical solution sets high and low water level safety thresholds as hard trigger boundaries. When the water level is below the low water level, a preset program reference clock is inserted to correct empty packets to prevent the underlying buffer from being read empty. When the water level is above the high water level, non-payload data packets are filtered to prevent the underlying buffer from overflowing. Under the premise of not destroying the effective video payload data at all, the closed-loop self-balancing of the hardware buffer queue water level is achieved.

[0039] Optionally, the receiving end receives the descrambled plaintext transport stream and sends it to the host computer, specifically including:

[0040] The received descrambled plaintext transport stream is written into the source address space of the preset high-speed direct memory access engine.

[0041] The data transfer completion status based on the high-speed direct memory access engine triggers a zero-copy transfer interrupt signal;

[0042] In response to a zero-copy transmission interrupt signal, the descrambled plaintext transport stream is sent to the target system memory of the host computer via an external component-extended interconnect bus.

[0043] The above technical solution directly writes the descrambled plaintext transmission stream into the source physical address space of the high-speed direct memory access engine, and relies entirely on the hardware engine's transmission completion status to trigger a zero-copy interrupt signal. The data is then directly sent to the host computer's target system memory via an external component-extended interconnect bus. This avoids the multi-level intermediate data transfer process involving the host computer's central processing unit, significantly reducing system computing power overhead and multi-path concurrent transmission latency.

[0044] Secondly, a general-purpose interface control system based on FPGA is provided, the system including:

[0045] The channel configuration module is used to configure the host interface protocol type for communication with the host computer, and to allocate isolated access addresses to multiple external conditional receivers to establish multiple processing channels;

[0046] The status detection module is used to send a probe command to each conditional receiver during initial access and to detect the error flag in the response status returned by the conditional receiver.

[0047] The timing optimization module is used to cyclically adjust at least one of the read / write setup time, data hold time, and clock sampling phase of the access condition receiver based on the error flag bit, until a target timing window with no error indication is determined.

[0048] The link negotiation module is used to configure the communication timing of the processing channel corresponding to the conditional receiver to the timing parameters corresponding to the target timing window, and to perform link negotiation and protocol interaction with the conditional receiver to establish a communication link.

[0049] The buffer dejitter module is used to receive the input multi-channel scrambled transport streams and write each scrambled transport stream into the corresponding processing channel for independent buffering and dejittering based on the preset stream mapping relationship, thereby generating a constant bit rate transport stream.

[0050] The bitstream delivery module is used to send a constant bitrate transport stream to the conditional receiver via a communication link based on communication timing.

[0051] The plaintext return module is used to receive the descrambled plaintext transport stream returned by the conditional receiver and send the descrambled plaintext transport stream to the host computer.

[0052] Thirdly, an electronic device is provided, including a processor, a memory, a user interface, and a network interface, wherein the memory is used to store instructions, the user interface and the network interface are both used to communicate with other devices, and the processor is used to execute the instructions stored in the memory to cause the electronic device to perform the method as described in any of the above.

[0053] Fourthly, a computer-readable storage medium is provided, the computer-readable storage medium storing instructions that, when executed, perform the method as described in any of the preceding claims.

[0054] In summary, implementing one or more technical solutions provided in this application has at least the following technical effects or advantages:

[0055] By constructing a deeply collaborative underlying interface scheduling architecture that integrates multi-channel physical link timing adaptive optimization, refined data stream jitter reduction conforming to digital video broadcasting standards, and zero-copy direct memory access mechanism in a global closed loop, this system not only overcomes the compatibility and stability bottlenecks caused by traditional fixed timing configurations and improves the system's adaptability to external hardware devices from multiple sources, heterogeneous structures, and different aging states, but more importantly, by completely offloading the high-concurrency scrambling stream routing and distribution and underlying water level management to the FPGA hardware layer for independent execution, the system reduces its reliance on the computing power of the host computer's central processing unit. This breaks through the bandwidth limitations of concurrent descrambling of multiple high-definition video services at the macro-system level, and constructs a video stream processing system with high data throughput, low system bus transmission latency, and robustness to the physical environment. Attached Figure Description

[0056] Figure 1 This is an exemplary system architecture diagram of an FPGA-based general interface control method or an FPGA-based general interface control system applied in this application.

[0057] Figure 2 This is a flowchart illustrating a general interface control method based on FPGA disclosed in this application;

[0058] Figure 3 This is a schematic diagram of a module of a general interface control system based on FPGA disclosed in this application;

[0059] Figure 4 This is a schematic diagram of the structure of an electronic device disclosed in this application.

[0060] Figure reference numerals: 100, System architecture; 101, First conditional receiver; 102, Second conditional receiver; 103, Third conditional receiver; 104, Communication bus; 105, Host computer; 106, FPGA-based general interface control board; 301, Channel configuration module; 302, Status detection module; 303, Timing optimization module; 304, Link negotiation module; 305, Buffer debouncing module; 306, Code stream delivery module; 307, Plaintext return module; 401, Processor; 402, Communication bus; 403, User interface; 404, Network interface; 405, Memory. Detailed Implementation

[0061] To enable those skilled in the art to better understand the technical solutions in this specification, the technical solutions in the embodiments of this specification will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0062] In the description of the embodiments of this application, the words "for example" or "for instance" are used to indicate examples, illustrations, or explanations. Any embodiment or design that is described as "for example" or "for instance" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design options. Rather, the use of the words "for example" or "for instance" is intended to present the relevant concepts in a specific manner.

[0063] In the description of the embodiments of this application, the term "multiple" means two or more. For example, multiple systems means two or more systems, and multiple screen terminals means two or more screen terminals. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the indicated technical features. Thus, a feature defined with "first" or "second" may explicitly or implicitly include one or more of that feature. The terms "comprising," "including," "having," and variations thereof all mean "including but not limited to," unless otherwise specifically emphasized.

[0064] Figure 1 An exemplary system architecture diagram is shown, illustrating an embodiment of an FPGA-based general interface control method or an FPGA-based general interface control system to which this application can be applied.

[0065] like Figure 1 As shown, the system architecture 100 may include a first conditional receiver 101, a second conditional receiver 102, a third conditional receiver 103, a communication bus 104, a host computer 105, and an FPGA-based general-purpose interface control board 106. In the physical deployment scenario of this application, the first conditional receiver 101, the second conditional receiver 102, and the third conditional receiver 103 are configured as multiple external conditional receivers (e.g., multiple CAM descrambling cards or different hardware conditional receiver modules connected in parallel); the FPGA-based general-purpose interface control board 106 serves as the core control hardware entity, and is physically directly connected to the multiple conditional receivers respectively; the host computer 105 is configured as the host computer (e.g., a broadcast television front-end data service server or a main control board); the communication bus 104 is configured as a host interface communication bus or a low-level data interaction link (e.g., a peripheral component expansion interconnect bus (PCIe bus) or a local bus), used to provide a physical medium for signaling interaction and service code stream transmission between the FPGA-based general-purpose interface control board 106 and the host computer 105.

[0066] The host computer 105 serves as the control core for issuing global service routing and management commands. In the control signaling direction, the host computer 105 sends host interface protocol type configuration, isolation access address allocation commands, and link handshake signaling to the FPGA-based general interface control board 106 via the communication bus 104. In the data flow direction, the host computer 105 receives the descrambled plaintext transmission stream after processing by the underlying hardware and sends the descrambled plaintext transmission stream into the target system memory of the host computer 105 for subsequent data distribution, video decryption, or encoding / decoding storage processing.

[0067] The first conditional receiver 101, the second conditional receiver 102, and the third conditional receiver 103, as external hardware entities, are respectively plugged into the physical card slots of the general interface control system and connected to the FPGA-based general interface control board 106 through multiple isolated and parallel bidirectional service paths. Each conditional receiver has different hardware level response characteristics, trace delays, and internal register configurations. They are used to receive a constant bit rate transport stream issued by the FPGA-based general interface control board 106 based on a target timing window through the bidirectional service paths, and to perform authorization verification and low-level descrambling on the constant bit rate transport stream using the internally integrated security chip. Subsequently, the generated descrambled plaintext transport stream is returned to the FPGA-based general interface control board 106 through the bidirectional service paths.

[0068] The communication bus 104 serves as the underlying hardware interconnect architecture, encompassing various bus physical topologies or standard communication interface specifications. An FPGA-based general-purpose interface control board 106 acts as the core control node, bridging the communication bus 104 with the first conditional receiver 101, the second conditional receiver 102, and the third conditional receiver 103, or it can be directly integrated into the host computer 105 via the communication bus 104 as a dedicated interface control card. The FPGA-based general-purpose interface control board 106 is responsible for executing the channel configuration, access probing, timing optimization, link negotiation, buffer debouncing, bitstream distribution, and plaintext return actions of this application.

[0069] It should be noted that, Figure 1 The number and physical form of the conditional receivers, communication buses, and host computers shown are merely illustrative. Depending on the multi-channel concurrent expansion requirements of an actual digital video broadcasting front-end system, it can have any number of conditional receivers, communication buses, and host computers. In particular, when multiple processing channels and the host computer are integrated on the same chassis or the same logic board, the communication bus 104 in the above system architecture is directly embodied as the physical printed traces inside the board or the System-on-Chip (SoC) bus.

[0070] At the hardware implementation level, the general interface control method described in this application fully relies on the high-concurrency processing architecture of FPGA and its flexible programmable underlying hardware resources (such as distributed logic units, block RAM, high-precision delay primitives, and instantiated IP cores). Compared with traditional general-purpose processors (CPUs) or application-specific integrated circuits (ASICs) with fixed timing, FPGAs can provide nanosecond-level, non-blocking deterministic timing control for high-frequency scrambled transport streams with multiple parallel inputs. This forms the hardware carrier foundation for this application to achieve multi-channel physical isolation, timing adaptive optimization, and zero-copy backhaul.

[0071] Figure 2 This is a flowchart illustrating a general-purpose interface control method based on FPGA, as described in this application. This method can be implemented using a computer program, a microcontroller, or run on a general-purpose interface control system based on FPGA. The computer program can be integrated into the application or run as a standalone utility application. The specific steps of the general-purpose interface control method based on FPGA are described in detail below.

[0072] S201: Configure the host interface protocol type for communication with the host computer, and assign isolated access addresses to multiple external conditional receivers to establish multiple processing channels.

[0073] In this embodiment, the conditional receiver refers to an external independent hardware module used for authorization verification and decryption processing of scrambled digital transport streams, such as a PCMCIA descrambling card containing a smart card that is plugged into a digital TV universal interface slot.

[0074] Specifically, based on the underlying logical architecture, the system configures the host interface protocol type for communication with the host computer (where the host computer refers to the central processing unit or main control board responsible for global business routing and control command issuance, and the host interface protocol type represents the standard communication specification for instruction and data interaction between the underlying logic devices and the host computer, such as PCIe protocol or local bus protocol), to establish a basic interaction link between the underlying processing core and the upper control platform. To meet the descrambling requirements of high concurrency, for multiple external conditional receivers, an isolated access address is allocated to each external device in the internal register space or memory mapping area (the isolated access address represents a memory base address or space offset that is independent of each other during bus addressing and has no overlapping physical boundaries). Based on the allocated isolated access addresses, corresponding independent timing control logic and data flow queues are instantiated for each conditional receiver in the underlying logical resources, establishing multiple processing channels at the physical and logical layers. This ensures that multiple concurrent digital transmission streams do not interfere with each other during parallel interaction and processing, completing the initial physical isolation and initialization of the channels.

[0075] S202: For each conditional receiver, send a probe command to the conditional receiver during initial access and check the error flag in the response status returned by the conditional receiver.

[0076] In the embodiments of this application, the probe command refers to a control message with a specific format or basic query function sent to the peripheral device in the early stage of physical link establishment in order to detect whether the hardware interface of the other end is ready and whether the bus communication is reliable. For example, it is a low-level query control command used to read the basic card information structure (CIS) of the external descrambling card.

[0077] Specifically, for each conditional receiver with an established processing channel, during the initial access phase (where initial access indicates that the external device has just completed electrical connection and has not yet entered the handshake probe period for stable service data transmission) after a physical plug-in / plug-out action or after the underlying logic has just completed a power-on reset, a pre-built probe command is actively sent to the conditional receiver via the underlying control bus. After the command is sent, the response status returned by the conditional receiver to the probe command is captured and parsed in real time (the response status indicates the execution result of the peer hardware in response to the received probe command or the current level logic status of the interface), and the error flag bit carried in the response status is carefully extracted and detected (the error flag bit is a specific logical flag bit in a specific field of the response message or in the status register used to identify whether the communication parity check has failed, whether the wait has timed out, or whether the timing is violated). Through the above process of active probing and return status parsing, the reliability of bus interaction under the current physical parameters is accurately determined, and the detection of error flag bits is completed.

[0078] S203: Based on the error flag, cyclically adjust at least one of the read / write setup time, data hold time, and clock sampling phase of the access condition receiver until a target timing window with no error indication is determined.

[0079] For example, due to differences in interface characteristics among different hardware manufacturers, parasitic delays caused by physical traces on circuit boards, or device aging, the default communication timing often fails to align with valid data (i.e., sampling points easily fall into ambiguous areas of signal transitions). In this case, the system dynamically performs multi-dimensional "sliding fine-tuning" of the bus interaction time boundary and sampling reference based on error feedback during the exploration phase. Through continuous trial and error correction, it eventually locks in a target timing match point that can avoid signal jitter and attenuation areas and achieve error-free read and write operations, thereby improving the cross-device compatibility and environmental adaptability of the underlying link.

[0080] In one possible implementation, based on the error flag, at least one of the read / write setup time, data hold time, and clock sampling phase of the access condition receiver is cyclically adjusted until a target timing window with no error indication is determined. Specifically, this includes: fixing the read / write setup time and data hold time to initial default parameters, sequentially adjusting the clock sampling phase, and detecting the state of the error flag; when the clock sampling phase has traversed a complete cycle and the error flag still indicates an error, increasing the parameter values ​​of the read / write setup time and data hold time by a preset ratio; and based on the read / write setup time and data hold time after the parameter values ​​have been increased, cyclically adjusting the clock sampling phase again until a target timing window with no error indication is determined.

[0081] In the embodiments of this application, the target timing window refers to the effective timing parameter combination range in high-speed digital underlying communication that can ensure that data is read and written accurately and stably without triggering the peripheral interface bus error response. For example, within a communication cycle, it is a continuous time interval that enables the underlying sampled data to meet the preset setup and hold margin requirements and achieve error-free interaction.

[0082] Specifically, the system fixes the read / write setup time (where read / write setup time represents the shortest time span during which the signal on the data bus must remain stable before the arrival of the clock valid sampling edge) and the data hold time (data hold time refers to the shortest duration during which the signal on the data bus needs to maintain the current logic level after the occurrence of the clock valid sampling edge) of the access condition receiver to the initial default parameters. With these two basic parameters locked, the phase is treated as a fast variable, and the clock sampling phase (the clock sampling phase represents the relative offset angle or delay of the clock edge that triggers internal data sampling throughout the entire clock cycle) is adjusted sequentially. After each phase fine-tuning, the status of the feedback error flag is checked. During this traversal, when the clock sampling phase has traversed a complete cycle (i.e., completed a 360-degree full phase scan offset) and the error flag still indicates an error, it means that under the current bus interaction reference time, no matter how the sampling point is found, it cannot meet the actual delay of the physical link. At this time, the parameter values ​​of read / write setup time and data hold time are amplified and increased according to a preset ratio to lengthen the overall timing reference. Based on the read / write setup time and data hold time after increasing the parameter values, the phase is reset and the clock sampling phase is adjusted again in a loop. Through the above two-dimensional optimization logic of "first fixing the slow variable, then traversing the fast variable", the process is iterated until the target timing window with no error indication is determined.

[0083] In one possible implementation, the parameter values ​​of read / write setup time and data hold time are increased according to a preset ratio. Specifically, this includes: extracting the number of bus feedback delay cycles when sending a probe command; inputting the number of bus feedback delay cycles into a preset timing compensation mapping table, and querying to obtain the asymmetric increase ratio as the preset ratio; and calculating the non-symmetrical parameter increments of read / write setup time and data hold time according to the asymmetric increase ratio to obtain the read / write setup time and data hold time after the parameter values ​​are increased.

[0084] In the embodiments of this application, the timing compensation mapping table refers to a static query structure that is pre-configured and burned into the underlying logic resources (such as the internal block RAM of the FPGA) to represent the correspondence between the actual measured instruction round-trip physical delay on the hardware bus and the required adjustment weights of various timing parameters. For example, a look-up table (LUT) that uses the actual measured total number of delay clock ticks as the memory access address and directly outputs the different compensation coefficients of the matching read and write actions.

[0085] Specifically, when it is necessary to lengthen the overall timing reference to expand the sampling search range, the system extracts the bus feedback delay cycle number when sending the probe command from the underlying state counter (this cycle number is used to characterize the actual physical clock ticks experienced by the probe message from the local bus to the remote hardware response, objectively reflecting the real physical attenuation of the current link due to trace length or device aging); the extracted bus feedback delay cycle number is used as an address index to input into the preset timing compensation mapping table for lookup matching, thereby obtaining the asymmetric increase ratio as a preset ratio (this asymmetric increase ratio represents the consideration of the signal's register on the hardware link). The generated capacitance causes different degrees of distortion in the setup and hold phases, thus assigning completely unequal expansion coefficients to the setup and hold phases. Based on the asymmetric increase ratio obtained from the query, the underlying computing unit performs multiplication operations with the current reference time to calculate the asymmetric parameter increments for read / write setup time and data hold time respectively (the asymmetric parameter increments are used to indicate that the absolute value of the setup time expansion is different from the absolute value of the hold time expansion, in order to offset the asymmetric deformation of the hardware link). The calculated increments are then superimposed on the original time parameters to obtain the read / write setup time and data hold time after the parameter values ​​are increased.

[0086] Specifically, the initial read / write setup time is set to... The data retention time is The bus feedback delay cycle number is pre-programmed within the LUT. With asymmetric increase in proportion set The mapping relationship. For example, when the number of delay cycles is measured. At that time, look up the table to output the time dilation factor. Maintain the time dilation coefficient (Because the distributed capacitance of the link has a more severe effect on the edge drag during the setup phase, therefore) Subsequently, the underlying DSP processing unit calls the following formula to perform multiplication: adjusted read / write setup time Adjusted data retention time By calculating the non-equivalent parameters with clear quantitative basis as described above, the timing configuration parameters after adding parameter values ​​are obtained.

[0087] Furthermore, in order to make the above parameters take effect at the physical layer, the system calls the input delay primitives and output delay primitives bound to the input and output pins of the underlying programmable logic device, converts the increased parameter values ​​into corresponding hardware delay step numbers, and dynamically configures the step registers of the above delay primitives. Without changing the global clock frequency, the system independently applies picosecond to nanosecond level physical delays to the signal transmission paths of the corresponding physical pins in the processing channel, thereby truly approximating and locking the target timing window on the bus physical link, and completing the hardware adaptive tuning process of increasing the parameter values ​​of read / write setup time and data hold time according to a preset ratio.

[0088] S204: Configure the communication timing of the processing channel corresponding to the conditional receiver to the timing parameters corresponding to the target timing window, and perform link negotiation and protocol interaction with the conditional receiver to establish a communication link.

[0089] For example, after obtaining the optimal underlying physical transmission timing, the system will solidify it as the working benchmark of the channel. On this basis, the interaction between the system and the external device will officially enter the handshake stage at the logical protocol level from pure hardware level probing. The two parties will complete the mutual confirmation of identity and channel through interactive control signaling, thereby officially upgrading the physical path that originally only had basic electrical connection attributes into a logical communication link with exclusive binding relationship and which can be securely transmitted digital service code streams at any time.

[0090] In one possible implementation, the communication timing of the processing channel corresponding to the conditional receiver is configured with the timing parameters corresponding to the target timing window, and link negotiation and protocol interaction are performed with the conditional receiver to establish a communication link. Specifically, this includes: determining the processing channel corresponding to the conditional receiver as the target processing channel, writing the timing parameters into the internal interface register of the target processing channel, and starting the link initialization mode; in the link initialization mode, sending a negotiation request message carrying the identifier of the target processing channel to the conditional receiver; based on the communication timing, receiving the negotiation response feature code returned by the conditional receiver in response to the negotiation request message, and establishing a communication link corresponding to the target processing channel according to the negotiation response feature code.

[0091] In the embodiments of this application, the link initialization mode refers to a special underlying control signaling interaction state that the underlying hardware interface enters specifically to complete the identity verification, channel binding and protocol handshake of the two communicating parties before the formal transmission of high-frequency service data stream. For example, in the DVB-CI standard, the handshake preparation phase in which the host and the external conditional access card exchange configuration management commands after the device has just completed an electrical reset.

[0092] Specifically, the system will determine the processing channel that matches the current conditional receiver after physical parameter optimization in the previous stage as the target processing channel (where the target processing channel represents the specific logical channel currently in the configuration activation process and about to establish a dedicated binding relationship with the peer hardware). The system will then substantively write the optimal timing parameters corresponding to the determined target timing window into the internal interface register of the target processing channel (the internal interface register refers to the underlying hardware storage configuration unit inside the programmable logic device used for directly latching and driving bus level switching cycles). This will solidify the communication parameters at the physical layer and initiate the link initialization mode accordingly. In the entered link initialization mode, regular service data is temporarily blocked, and a negotiation request message carrying the identifier of the target processing channel is sent to the conditional receiver via the underlying control bus (the negotiation request message represents an initial signaling data packet containing the channel's unique allocation identifier and the initiator's handshake intention, used to request the peripheral device to confirm the logical binding relationship). Based on the communication timing already in effect in the register, stable and error-free bus sampling is performed. After successfully parsing the request, the receiving end responds to the negotiation response feature code returned by the negotiation request message (the negotiation response feature code is used to characterize the exclusive response verification sequence or acknowledgment identifier that the peer device has successfully received and agreed to bind to the specific channel identifier). At the logic control level, the authentication comparison mechanism completes two-way identity verification based on the negotiation response feature code, thereby completing the closed loop from physical layer parameters to upper layer protocol handshake and establishing a communication link corresponding to the target processing channel.

[0093] S205: Receives the input multi-channel scrambled transport stream, and writes each scrambled transport stream into the corresponding processing channel for independent buffering and dejittering based on the preset stream mapping relationship, generating a constant bit rate transport stream.

[0094] For example, the underlying control logic can parse the service identifiers (such as packet identifiers or source port numbers) carried in the concurrent input bitstream from the front end, which is equivalent to consulting a hardware routing table. This allows it to separate the originally mixed and intertwined multiple data streams and guide them to their respective dedicated physical channels. In this process, for the "burst" phenomenon of data packet arrival intervals that are sometimes fast and sometimes slow due to front-end bus preemption or network transmission fluctuations, the channel uses storage media as a data buffer unit to first cache the data with uneven arrival time intervals. Then, it discards the irregular timing at the input end and rearranges and releases the data at a fixed rate that conforms to the preset receiving parameters of the downstream device, thereby completing the bitstream shaping process from jittery and out-of-order to a fixed rate.

[0095] In one possible implementation, the system receives multiple scrambled transport streams as input and writes each scrambled transport stream into its corresponding processing channel for independent buffering and dejittering based on a preset stream mapping relationship, thereby generating a constant bit rate transport stream. Specifically, this includes: storing each scrambled transport stream into an asynchronous first-in-first-out (FIFO) buffer queue corresponding to the processing channel; monitoring the current data level of the asynchronous FIFO buffer queue in real time; and dynamically performing empty packet filling or redundant packet removal based on a preset standard output clock beat and the current data level, thereby generating a constant bit rate transport stream.

[0096] In the embodiments of this application, the asynchronous first-in-first-out buffer queue refers to a dual-port storage structure of underlying hardware used for data buffering and rate matching during data transmission across clock domains. Its write and read operations are driven by independent clock domains, such as an independent buffer module built in the underlying logic device through block random access memory, used to absorb high-frequency service data from sudden front-end inputs and smoothly output them according to a preset external timing sequence.

[0097] Specifically, after receiving the input multi-channel scrambled transport stream (where the multi-channel scrambled transport stream represents undecrypted concurrent digital video service streams with timestamp jitter), the system, based on a preset stream mapping relationship (the stream mapping relationship refers to the routing and distribution rules between pre-configured service stream identifiers and underlying hardware processing channels), writes each scrambled transport stream into its corresponding processing channel for independent buffering and de-jittering (de-jittering is used to eliminate uneven arrival time intervals or clock rhythm disturbances caused by high-frequency data burst transmissions on the bus). In the specific physical implementation, each scrambled transport stream is stored in the asynchronous first-in-first-out buffer queue corresponding to the processing channel according to its respective input clock.

[0098] During data buffering, the current data level of the asynchronous FIFO buffer queue is monitored in real time (the current data level represents the instantaneous depth boundary of the valid data load accumulated in the current physical storage space that has not yet been read). To avoid metastability caused by cross-clock domain acquisition, the system is configured with a Gray code conversion unit and a two-stage flip-flop synchronization array in the underlying logic. The write pointer under the write clock domain and the read pointer under the read clock domain of the asynchronous FIFO buffer queue are extracted respectively; the Gray code conversion unit converts the write pointer and read pointer into their corresponding Gray codes; using the two-stage flip-flop synchronization array, the Gray code-converted write pointer is synchronized to the read clock domain, and the Gray code-converted read pointer is simultaneously synchronized to the write clock domain; the synchronized write pointer and read pointer are decoded and compared within the same clock domain to calculate the current data level with an absolutely definite logic level.

[0099] Furthermore, completely detached from the input clock domain, based on a preset standard output clock beat (the standard output clock beat refers to the fixed frequency readout pulse strictly following the communication protocol of the downstream conditional receiver card), it dynamically performs empty packet filling (empty packet filling refers to actively inserting invalid padding packets conforming to digital video broadcasting specifications into the data stream to prevent the queue from emptying) or redundant packet removal (redundant packet removal refers to actively identifying and discarding non-core payload placeholder data packets in the original bitstream to prevent queue overflow when the bitstream rises sharply and approaches the overflow threshold) according to the real-time current data level. Through the above mechanism of dynamic compensation and trimming entirely based on the real-time depth of the physical buffer, the irregularity of the front-end data influx is absorbed, generating a constant bitrate transport stream.

[0100] In one possible implementation, based on a preset standard output clock tick, empty packet filling or redundant packet removal is dynamically performed according to the current data level to generate a constant bit rate transport stream. Specifically, this includes: comparing the current data level with preset high-level safety thresholds and low-level safety thresholds respectively; when the current data level is lower than the low-level safety threshold, inserting preset program reference clock correction empty packets into the scrambled transport stream to generate a constant bit rate transport stream; when the current data level is higher than the high-level safety threshold, filtering out non-payload filling data packets in the scrambled transport stream to generate a constant bit rate transport stream.

[0101] In the embodiments of this application, the program reference clock correction null packet refers to a special logical data packet in a digital video broadcast transport stream that is specially constructed to maintain the overall time synchronization reference and fixed physical transmission rate. It does not contain actual audio and video service payload but can be used for time synchronization and placeholders. For example, it is a placeholder correction data packet that is encapsulated with the latest PCR (Program Clock Reference) timestamp according to the underlying protocol specification on the basis of an invalid null packet structure with a transport stream packet identifier (PID) of 0x1FFF to correct downstream clock drift.

[0102] Specifically, based on the preset standard output clock tick, in order to match the preset receiving timing of the downstream external hardware, the system performs high-frequency logical comparisons between the current data level (which represents the backlog depth of the valid transmission stream data within the current asynchronous cache) collected in real time at the underlying layer and the preset high-water level safety threshold (the high-water level safety threshold refers to the upper limit warning value of the storage depth with a preset safety margin before the physical overflow boundary of the cache) and the low-water level safety threshold (the low-water level safety threshold refers to the lower limit warning value of the storage depth with a certain read margin before the physical read-empty boundary of the cache). When the comparison result shows that the current data level is lower than the low-water level safety threshold, it means that the sudden input rate of the front-end data has reached a trough, and the cache is facing the physical risk of being read empty. At this time, the underlying lower limit compensation mechanism is triggered, actively adjusting the original continuous data level. Preset program reference clock correction empty packets are interspersed in the scrambled transport stream to actively occupy physical transmission bandwidth and maintain decoding clock synchronization at the downstream receiver, generating a constant bitrate transport stream. Conversely, when the comparison result shows that the current data level is higher than the high-level safety threshold, it means that the front-end data is flooding in too fast, the buffer is facing the risk of overflow and loss of key video frames. At this time, the upper limit pruning mechanism is triggered. The hardware logic identifies and filters out non-payload padding data packets in the scrambled transport stream (non-payload padding data packets refer to redundant padding packets in the original bitstream that were originally used to roughly pad the bandwidth and have no actual descrambling significance). By stripping these invalid data, the amount of data backlog in the buffer is quickly consumed and reduced. Thus, under the premise of completely protecting the core service payload from damage, the dynamic redundant packet removal action is completed, and a constant bitrate transport stream is also generated.

[0103] S206: Based on communication timing, a constant bit rate transport stream is sent to the conditional receiver via a communication link.

[0104] In the embodiments of this application, a constant bitrate transport stream refers to a continuous data stream whose data packet output rate remains strictly fixed on the physical time axis after being processed by the underlying logical buffer and dynamic allocation of empty / redundant packets. For example, an audio and video multiplexed TS stream that strictly follows the underlying communication specifications of digital video broadcasting and whose output beat is always maintained at a fixed rate (such as a specific Mbps) regardless of how the front-end data fluctuates.

[0105] Specifically, after buffering and smoothing the high-frequency service data at the front end, the underlying transmit pin state machine is driven strictly based on the communication timing established in the preceding physical optimization phase (where the communication timing represents the target clock sampling and control parameters that can adapt to the latency of the peripheral hardware bus and ensure that the underlying data is read and written without errors). Using this stable communication timing as the physical clock benchmark, the constant bit rate transmission stream generated by the smoothing process is continuously sent to the corresponding conditional receiver (the conditional receiver is an external hardware module plugged into a general interface, specifically responsible for receiving the current scrambled service stream and performing underlying authorization decryption actions) through the communication link constructed in the preceding negotiation and interaction phase (the communication link refers to the dedicated end-to-end service data transparent transmission channel established between the underlying processing channel and the external device through protocol handshake and feature code verification). Through the above-mentioned push mechanism that relies entirely on the optimal hardware timing clock and dedicated channel, the risk of instantaneous packet loss caused by phase drift or bus congestion is avoided, and the constant bit rate transmission stream is sent to the conditional receiver.

[0106] S207: Receive the descrambled plaintext transport stream returned by the receiving end and send the descrambled plaintext transport stream to the host computer.

[0107] For example, after the conditional receiver completes authorization verification and outputs decrypted data, the underlying logic can reassemble the received serial or parallel descrambled plaintext transmission stream across clock domains and splice the data bit width. Then, as a transparent data transmission bridge, it smoothly and continuously transmits the recovered original audio and video service bit stream to the host computer through the basic communication bus or buffer gateway between the host and the client, so that the host computer's operating system driver layer or multimedia application process can perform subsequent service distribution, video decoding and rendering, or disk storage.

[0108] In one possible implementation, receiving the descrambled plaintext transport stream returned by the conditional receiver and sending the descrambled plaintext transport stream to the host computer specifically includes: writing the received descrambled plaintext transport stream into the source address space of a preset high-speed direct memory access engine; triggering a zero-copy transmission interrupt signal based on the data transmission completion status of the high-speed direct memory access engine; and in response to the zero-copy transmission interrupt signal, sending the descrambled plaintext transport stream to the target system memory of the host computer through an external component-extended interconnect bus.

[0109] In the embodiments of this application, a high-speed direct memory access engine refers to a data transfer hardware module that allows the underlying peripheral hardware subsystem to independently and directly read and write the system main memory without the full intervention of the central processing unit (CPU). For example, a PCIe DMA IP core that is instantiated and configured inside the FPGA and is specifically responsible for high-speed pass-through and transfer of large batches of audio and video streams between the local hardware endpoint and the host computer main memory.

[0110] Specifically, after completing the underlying authorization and decryption interaction, the system receives the descrambled plaintext transmission stream returned by the conditional receiver (wherein, the descrambled plaintext transmission stream is used to represent the original digital video service data that has been decrypted and restored by the external smart card and stripped of scrambling protection). In order to avoid the latency and computing power consumption caused by traditional software reading, the conventional central processing unit relay step is skipped, and the received descrambled plaintext transmission stream is directly written into the source address space of the preset high-speed direct memory access engine (the source address space represents the physical boundary of the initial cache that is defined and mapped inside the underlying programmable logic of the hardware engine).

[0111] During this process, the host computer pre-allocates a circular physical contiguous buffer in the target system memory and generates a discrete collection and aggregation descriptor linked list pointing to each buffer block; the high-speed direct memory access engine actively retrieves the descriptor linked list from the bus and caches it in its internal registers; based on the cached descriptor addresses, the engine automatically completes the payload transfer of the descrambled plaintext transmission stream through direct memory access.

[0112] During the automatic startup and execution of high-throughput data block transfer by the hardware engine, the underlying logic monitors the transfer progress of the physical link in real time and strictly triggers a zero-copy transfer interrupt signal to the global control logic based on the data transfer completion status of the high-speed direct memory access engine (the data transfer completion status refers to the physical level indicator that the underlying descriptor linked list has been completed or the burst data volume of the set threshold has been successfully pushed into the bus transmit queue across the clock domain, that is, when the data block corresponding to a single descriptor is transferred and the bus physical level write-back confirmation signal is valid, it represents that the data transfer completion status has been reached). (The zero-copy transfer interrupt signal represents a hardware notification pulse that is directly triggered by the end of the underlying physical transfer action without going through multiple redundant memory copies from the operating system kernel space to the user space. For example, the hardware interrupt pin of the engine generates a level transition and sends the zero-copy transfer interrupt signal to the kernel driver layer of the host computer through the message-triggered interrupt mechanism.) Upon responding to a zero-copy transmission interruption signal, the global bus controller takes over the routing authority of the physical link. Through the peripheral component extended interconnect bus (the peripheral component extended interconnect bus is used to represent high-speed serial computer extended bus specifications such as PCIe, which provide extremely high communication bandwidth and low-latency point-to-point connection characteristics), it sends the descrambled plaintext transmission stream to the target system memory of the host computer in a low-level hardware pass-through manner. (The target system memory refers to the contiguous physical memory area that the host computer operating system has pre-allocated and locked in the motherboard DDR, dedicated to receiving the underlying video service stream), thereby completing the full-link video stream backhaul.

[0113] Figure 3This is a schematic diagram of a module of a general-purpose interface control system based on FPGA according to an embodiment of this application. This system can be implemented through software, hardware, or a combination of both, becoming all or part of the overall system. Figure 3 As shown, the system includes:

[0114] The channel configuration module 301 is used to configure the host interface protocol type for communication with the host computer, and to allocate isolated access addresses for multiple external conditional receivers to establish multiple processing channels;

[0115] The status detection module 302 is used to send a probe command to each conditional receiver during initial access and to detect the error flag bit in the response status returned by the conditional receiver.

[0116] Timing optimization module 303 is used to cyclically adjust at least one of the read / write setup time, data hold time, and clock sampling phase of the access condition receiver based on the error flag bit, until a target timing window with no error indication is determined.

[0117] The link negotiation module 304 is used to configure the communication timing of the processing channel corresponding to the conditional receiver to the timing parameters corresponding to the target timing window, and to perform link negotiation and protocol interaction with the conditional receiver to establish a communication link.

[0118] The buffer dejitter module 305 is used to receive the input multi-channel scrambled transport stream and write each scrambled transport stream into the corresponding processing channel for independent buffering and dejittering based on the preset stream mapping relationship, thereby generating a constant bit rate transport stream.

[0119] The bitstream delivery module 306 is used to send a constant bitrate transport stream to the conditional receiver via a communication link based on communication timing.

[0120] The plaintext return module 307 is used to receive the descrambled plaintext transport stream returned by the conditional receiver and send the descrambled plaintext transport stream to the host computer.

[0121] Based on the above embodiments, as an optional embodiment, the timing optimization module 303 is specifically used to: fix the read / write setup time and data hold time to the initial default parameters, adjust the clock sampling phase sequentially, and detect the status of the error flag bit; when the clock sampling phase traverses a complete cycle and the error flag bit still indicates an error, increase the parameter values ​​of the read / write setup time and data hold time according to a preset ratio; based on the read / write setup time and data hold time after increasing the parameter values, adjust the clock sampling phase again in a loop until a target timing window with no error indication is determined.

[0122] Based on the above embodiments, as an optional embodiment, the timing optimization module 303 is specifically used to: extract the number of bus feedback delay cycles when sending the probe command; input the number of bus feedback delay cycles into a preset timing compensation mapping table, and query the asymmetric increase ratio as a preset ratio; calculate the non-equivalent parameter increments of read / write setup time and data hold time according to the asymmetric increase ratio, and obtain the read / write setup time and data hold time after increasing the parameter value.

[0123] Based on the above embodiments, as an optional embodiment, the link negotiation module 304 is specifically used to: determine the processing channel corresponding to the conditional receiver as the target processing channel, write the timing parameters into the internal interface register of the target processing channel, and start the link initialization mode; in the link initialization mode, send a negotiation request message carrying the identifier of the target processing channel to the conditional receiver; based on the communication timing, receive the negotiation response feature code returned by the conditional receiver in response to the negotiation request message, and establish a communication link corresponding to the target processing channel according to the negotiation response feature code.

[0124] Based on the above embodiments, as an optional embodiment, the buffer debouncing module 305 is specifically used to: store each scrambled transport stream into the asynchronous first-in-first-out buffer queue corresponding to the processing channel; monitor the current data level of the asynchronous first-in-first-out buffer queue in real time; and dynamically perform empty packet filling or redundant packet removal according to the current data level based on the preset standard output clock beat to generate a transport stream with a constant bit rate.

[0125] Based on the above embodiments, as an optional embodiment, the buffer dejitter module 305 is specifically used to: compare the current data level with the preset high-level safety threshold and the low-level safety threshold respectively; when the current data level is lower than the low-level safety threshold, insert a preset program reference clock correction empty packet into the scrambled transport stream to generate a constant bit rate transport stream; when the current data level is higher than the high-level safety threshold, filter out the non-payload padding data packets in the scrambled transport stream to generate a constant bit rate transport stream.

[0126] Based on the above embodiments, as an optional embodiment, the plaintext return module 307 is specifically used to: write the received descrambled plaintext transmission stream into the source address space of a preset high-speed direct memory access engine; trigger a zero-copy transmission interrupt signal based on the data transmission completion status of the high-speed direct memory access engine; and in response to the zero-copy transmission interrupt signal, send the descrambled plaintext transmission stream to the target system memory of the host computer through the peripheral component extended interconnect bus.

[0127] It should be noted that the system provided in the above embodiments is only illustrated by the division of the above functional modules. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above. In addition, the system and method embodiments provided in the above embodiments belong to the same concept, and the specific implementation process can be found in the method embodiments, which will not be repeated here.

[0128] This embodiment also discloses an electronic device, as shown in the reference. Figure 4 The electronic device may include: at least one processor 401, at least one system bus 402, user interface 403, network interface 404, and at least one memory 405.

[0129] The system bus 402 is used to enable communication between these components.

[0130] The user interface 403 may include a display screen and a camera. Optionally, the user interface 403 may also include a standard wired interface and a wireless interface.

[0131] The network interface 404 may optionally include a standard wired interface or a wireless interface (such as a Wi-Fi interface).

[0132] The processor 401 may include one or more processing cores. The processor 401 connects to various parts of the server using various interfaces and lines, and performs various server functions and processes data by running or executing instructions, programs, code sets, or instruction sets stored in memory 405, and by calling data stored in memory 405. Optionally, the processor 401 may be implemented using at least one hardware form of Digital Signal Processing (DSP), Field-Programmable Gate Array (FPGA), or Programmable Logic Array (PLA). The processor 401 may integrate one or a combination of several of the following: Central Processing Unit (CPU), Graphics Processing Unit (GPU), and modem. The CPU primarily handles the operating system, user interface, and applications; the GPU is responsible for rendering and drawing the content required for display; and the modem handles wireless communication. It is understood that the modem may also be implemented as a separate chip without being integrated into the processor 401.

[0133] The memory 405 may include random access memory (RAM) or read-only memory. Optionally, the memory 405 may include a non-transitory computer-readable storage medium. The memory 405 may be used to store instructions, programs, code, code sets, or instruction sets. The memory 405 may include a program storage area and a data storage area, wherein the program storage area may store instructions for implementing an operating system, instructions for at least one function (such as touch function, sound playback function, image playback function, etc.), instructions for implementing the above-described method embodiments, etc.; the data storage area may store data involved in the above-described method embodiments, etc. Optionally, the memory 405 may also be at least one storage device located remotely from the aforementioned processor 401. Figure 4 As shown, the memory 405, which serves as a computer storage medium, may include an operating system, a network communication module, a user interface module, and an application program based on a general interface control method for FPGA.

[0134] exist Figure 4 In the electronic device shown, the user interface 403 is mainly used to provide an input interface for the user and to obtain the user input data; while the processor 401 can be used to call an application program stored in the memory 405 that is a general interface control method based on FPGA. When executed by one or more processors 401, the electronic device executes one or more methods as described in the above embodiments.

[0135] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that this application is not limited to the described order of actions, as some steps may be performed in other orders or simultaneously according to this application. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions and modules involved are not necessarily essential to this application.

[0136] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0137] In the several embodiments provided in this application, it should be understood that the disclosed apparatus can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the shown or discussed mutual couplings or direct couplings or communication connections may be through some service interfaces; indirect couplings or communication connections between apparatuses or units may be electrical or other forms.

[0138] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0139] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0140] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage device (CMD). Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a memory 405 and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned memory 405 includes various media capable of storing program code, such as a USB flash drive, external hard drive, magnetic disk, or optical disk.

[0141] The above description is merely an exemplary embodiment of this application and should not be construed as limiting the scope of this application. Any equivalent changes and modifications made in accordance with the teachings of this application shall still fall within the scope of this application. Those skilled in the art will readily conceive of other embodiments of this application upon considering the disclosure of this specification. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not described in this application. The specification and embodiments are considered exemplary only, and the scope of disclosure of this application is defined by the claims.

Claims

1. A general interface control method based on FPGA, characterized in that, The method includes: Configure the host interface protocol type for communication with the host computer, and assign isolated access addresses to multiple external conditional receivers to establish multiple processing channels; For each of the aforementioned conditional receivers, a probe command is sent to the conditional receiver upon initial access, and the error flag bit in the response status returned by the conditional receiver is detected. Based on the error flag, at least one of the read / write setup time, data hold time, and clock sampling phase for accessing the conditional receiver is cyclically adjusted until a target timing window is determined to have no error indication from the error flag. Configure the communication timing of the processing channel corresponding to the conditional receiver to the timing parameters corresponding to the target timing window, and perform link negotiation and protocol interaction with the conditional receiver to establish a communication link; The system receives multiple scrambled transport streams as input and writes each scrambled transport stream into the corresponding processing channel for independent buffering and dejittering based on a preset stream mapping relationship, thereby generating a transport stream with a constant bit rate. Based on the communication timing, the constant bit rate transport stream is sent to the conditional receiver via the communication link; The system receives the descrambled plaintext transport stream returned by the conditional receiver and sends the descrambled plaintext transport stream to the host computer.

2. The method according to claim 1, characterized in that, The step of cyclically adjusting at least one of the read / write setup time, data hold time, and clock sampling phase for accessing the conditional receiver based on the error flag bit, until a target timing window is determined to have no error indication by the error flag bit, specifically includes: The read / write setup time and the data hold time are fixed to the initial default parameters, the clock sampling phase is adjusted sequentially, and the state of the error flag is detected. When the clock sampling phase completes a full cycle and the error flag still indicates an error, the parameter values ​​of the read / write setup time and the data hold time are increased by a preset ratio. Based on the read / write setup time and data hold time after increasing the parameter values, the clock sampling phase is adjusted again in a loop until the target timing window with no error indication is determined by the error flag bit.

3. The method according to claim 2, characterized in that, The parameter values ​​for increasing the read / write setup time and the data retention time according to a preset ratio specifically include: Extract the number of bus feedback delay cycles when sending the probe command; Input the number of bus feedback delay cycles into a preset timing compensation mapping table, and look up the asymmetric increase ratio as the preset ratio. Based on the asymmetric increase ratio, the non-symmetrical parameter increments of the read / write setup time and the data retention time are calculated respectively to obtain the read / write setup time and the data retention time after the parameter values ​​are increased.

4. The method according to claim 1, characterized in that, The step of configuring the communication timing of the processing channel corresponding to the conditional receiver to the timing parameters corresponding to the target timing window, and performing link negotiation and protocol interaction with the conditional receiver to establish a communication link, specifically includes: The processing channel corresponding to the condition receiver is determined as the target processing channel, and the timing parameters are written into the internal interface register of the target processing channel to start the link initialization mode. In the link initialization mode, a negotiation request message carrying the identifier of the target processing channel is sent to the condition receiver; Based on the communication timing, the conditional receiver receives the negotiation response feature code returned by the conditional receiver in response to the negotiation request message, and establishes the communication link corresponding to the target processing channel according to the negotiation response feature code.

5. The method according to claim 1, characterized in that, The received input multi-channel scrambled transport stream is written into the corresponding processing channel for independent buffering and dejittering based on a preset stream mapping relationship, generating a constant bit rate transport stream, specifically including: Each of the scrambled transport streams is stored in the asynchronous first-in-first-out buffer queue corresponding to the processing channel; Real-time monitoring of the current data level of the asynchronous first-in-first-out cache queue; Based on a preset standard output clock tick, empty packet filling or redundant packet removal is dynamically performed according to the current data level to generate the constant bit rate transport stream.

6. The method according to claim 5, characterized in that, The process of dynamically performing empty packet filling or redundant packet removal based on the current data level, according to a preset standard output clock tick, to generate the constant bit rate transport stream, specifically includes: The current data water level is compared with the preset high water level safety threshold and low water level safety threshold respectively; When the current data level is lower than the low water level safety threshold, a preset program reference clock correction empty packet is inserted into the scrambled transport stream to generate the constant bit rate transport stream; When the current data level is higher than the high-level safety threshold, non-load-filled data packets in the scrambled transport stream are filtered out, and the constant bit rate transport stream is generated.

7. The method according to claim 1, characterized in that, The step of receiving the descrambled plaintext transport stream returned by the conditional receiver and sending the descrambled plaintext transport stream to the host computer specifically includes: The received descrambled plaintext transport stream is written into the source address space of a preset high-speed direct memory access engine. Based on the data transmission completion status of the high-speed direct memory access engine, a zero-copy transmission interrupt signal is triggered; In response to the zero-copy transmission interrupt signal, the descrambled plaintext transmission stream is sent to the target system memory of the host computer via the peripheral component-extended interconnect bus.

8. A general-purpose interface control system based on FPGA, characterized in that, The system includes: The channel configuration module is used to configure the host interface protocol type for communication with the host computer, and to allocate isolated access addresses to multiple external conditional receivers to establish multiple processing channels; The status detection module is used to send a probe command to each of the condition receivers during initial access and to detect the error flag bit in the response status returned by the condition receiver. The timing optimization module is used to cyclically adjust at least one of the read / write setup time, data hold time, and clock sampling phase for accessing the conditional receiver based on the error flag bit, until a target timing window with no error indication is determined. The link negotiation module is used to configure the communication timing of the processing channel corresponding to the conditional receiver to the timing parameters corresponding to the target timing window, and to perform link negotiation and protocol interaction with the conditional receiver to establish a communication link. The buffer dejitter module is used to receive the input multi-channel scrambled transport streams and write each of the scrambled transport streams into the corresponding processing channel for independent buffering and dejittering based on a preset stream mapping relationship, thereby generating a constant bit rate transport stream. A bitstream delivery module is used to send the constant bitrate transport stream to the conditional receiver via the communication link based on the communication timing. The plaintext return module is used to receive the descrambled plaintext transport stream returned by the conditional receiver and send the descrambled plaintext transport stream to the host computer.

9. An electronic device, characterized in that, The device includes a processor, a memory, a user interface, and a network interface. The memory is used to store instructions. The user interface and the network interface are both used to communicate with other devices. The processor is used to execute the instructions stored in the memory to cause the electronic device to perform the method as described in any one of claims 1-7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores instructions that, when executed, perform the method as described in any one of claims 1-7.

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