Time division multiplexing four camera merging into single MIPI system

Abstract

This invention relates to the field of vehicle image processing and transmission technology, specifically disclosing a time-division multiplexed four-camera merging into a single MIPI system. The system includes four LVDS cameras, each capturing images from the front, rear, left, and right directions of the vehicle, forming four camera channels. This time-division multiplexed four-camera merging into a single MIPI system utilizes an FPGA camera four-in-one module. This module simultaneously receives signals from four LVDS cameras and, through its internally integrated LVDS decoding module, RAM data cache module, data time-division multiplexing module, and MIPI signal processing module, combines the four data channels into a single MIPI signal, which is directly output to the vehicle's central control motherboard. Since an external independent 360° panoramic host and vehicle codec box are no longer needed, the amount of wiring in the vehicle is reduced. Only four cameras need to be connected to the FPGA module, and then a single MIPI cable connects them to the vehicle's central control motherboard, reducing construction difficulty, shortening installation time, and achieving non-destructive and rapid installation.

Description

Technical Field

[0001] This invention relates to the field of vehicle image processing and transmission technology, specifically to a time-division multiplexed four-camera system that merges into a single MIPI system. Background Technology

[0002] In-vehicle 360° surround view systems have become an important active safety technology for improving driving safety and assisting parking, and are widely used in various passenger vehicles. Their basic working principle involves wide-angle or fisheye cameras installed in the front, rear, left, and right directions of the vehicle to capture real-time images of the vehicle's surroundings. These images are then processed by an image processing unit for distortion correction, perspective transformation, and image stitching, ultimately generating a panoramic view that is displayed on the central control screen. In the existing aftermarket, many original vehicle central control chips only support single-channel MIPI camera input and cannot directly connect to four surround view cameras. Therefore, traditional solutions generally adopt an architecture of "external independent 360° surround view host + vehicle-mounted codec box": the four cameras first transmit signals to the independent surround view host for image stitching and processing, and the processed image is then transmitted to the codec box, which switches and overlays the signal with the original vehicle's signal before finally outputting it to the central control display. This architecture achieves 360° surround view functionality, but the system structure is relatively complex, involving multiple independent hardware modules, and has some drawbacks, such as: Because an additional panoramic host and codec box are required, the number of wiring in the vehicle increases significantly. During installation, the original center console, host, and many interior parts must be disassembled for wire cutting, conversion, and signal connection. This makes the construction difficult and time-consuming. Frequent disassembly and assembly can easily cause vehicle noise, interior damage, or poor wiring contact. In addition, with many external devices and conversion nodes, stability issues such as signal interference, poor contact, crashes, or black screens are prone to occur in harsh environments such as vehicle vibration and high temperature. The failure rate is relatively high. Furthermore, the signal undergoes multiple transmissions and format conversions, which introduces some image quality loss and transmission delay, affecting the real-time performance and clarity of the panoramic image.

[0003] To address the aforementioned issues, there is an urgent need for innovative design based on the existing in-vehicle panoramic surround view system. Summary of the Invention

[0004] The purpose of this invention is to provide a time-division multiplexed four-camera system that merges into a single MIPI system, in order to solve the problems mentioned in the background art, such as the increased number of wiring in the vehicle, the need to disassemble the original vehicle's center console, main unit, and many interior parts during installation, and the resulting difficulty in construction, long construction time, and numerous external devices and connection nodes. In harsh environments such as vehicle vibration and high temperature, stability problems such as signal interference, poor contact, system crashes, or black screens are prone to occur. Furthermore, the signal undergoes multiple transmissions and format conversions, which introduces certain image quality loss and transmission delay, affecting the real-time performance and clarity of the panoramic image.

[0005] To achieve the above objectives, the present invention provides the following technical solution: a time-division multiplexed four-camera system combined into a single MIPI system, including an LVDS camera, wherein a total of four camera devices are provided to collect images from the front, rear, left and right directions of the vehicle, respectively, forming a four-camera system; The FPGA camera quad-module simultaneously receives LVDS differential signals from four LVDS cameras and combines the data from the four cameras into a single MIPI signal for output. The vehicle infotainment system's central control motherboard has a single-channel MIPI camera input interface, which receives the single-channel MIPI signal, and the image is processed by the vehicle infotainment system's central control chip before being output to the central control display screen. The FPGA camera four-in-one module includes: The LVDS decoding module is used to convert four LVDS differential signals into parallel image data and synchronization control signals, respectively. The clock module is used to generate the system master clock and provide working clocks for each module. The working clocks include pixel decoding clock, data read / write clock, data scheduling clock, and MIPI protocol encoding clock. The frequency of the MIPI protocol encoding clock is greater than four times the signal frequency of the LVDS camera. The RAM data caching module has four independent dual-port RAM caching units, which respectively receive and cache the four parallel image data streams; The data time-division multiplexing module, based on the data scheduling clock, uses time-division multiplexing technology to poll and schedule the parallel data read from the four RAM cache units into a single serial data stream, and inserts a channel identifier into it; The MIPI signal processing module receives the serial data stream, performs data packet encapsulation and parallel-to-serial conversion according to the MIPICSI-2 protocol, and outputs the single-channel MIPI signal through the MIPIDPHY physical layer driver.

[0006] By adopting the above technical solution, the four LVDS signals are combined into a single MIPI output through the FPGA camera four-in-one module, enabling the vehicle central control motherboard, which only supports single MIPI input, to simultaneously connect to four surround view cameras. This eliminates the need for an external panoramic host, simplifies the system structure, and reduces installation difficulty.

[0007] Preferably, the LVDS decoding module has a built-in signal anomaly detection mechanism that outputs a fault prompt signal when a certain LVDS signal is lost or abnormal.

[0008] By adopting the above technical solution, the LVDS decoding module has a built-in signal anomaly detection mechanism, which can output fault prompt signals in real time, making it easier for the system to quickly locate camera signal loss or interference problems and improve system reliability.

[0009] Preferably, the clock module includes an automotive-grade crystal oscillator and an internal clock management unit. The internal clock management unit divides the main clock to generate multiple working clocks adapted to different modules.

[0010] The above technical solution uses an automotive-grade crystal oscillator in conjunction with an internal clock management unit to generate multiple working clocks through frequency division, ensuring clock synchronization and accuracy for each module and meeting the requirements of the automotive environment for clock stability.

[0011] Preferably, each dual-port RAM cache unit in the RAM data cache module supports asynchronous writing and synchronous reading, and the data time-division multiplexing module synchronously reads the image data in the four RAM data cache modules according to a preset timing sequence to ensure that the four data reading rates are consistent.

[0012] Using the above technical solution, the RAM cache unit supports asynchronous writing and synchronous reading, and the data time-division multiplexing module synchronously reads four data channels and ensures consistent rates, avoiding data timing errors or frame drops, and ensuring synchronous output of four video channels.

[0013] Preferably, the time-division multiplexing module further performs format normalization processing on the four-channel image data to unify the data bit width, pixel format, and transmission rate.

[0014] Using the above technical solution, the time-division multiplexing module performs format normalization processing on the four-channel image data, unifies the data bit width, pixel format and transmission rate, eliminates the differences in data formats from multiple cameras, and ensures the standardization of subsequent MIPI encapsulation.

[0015] Preferably, the MIPI signal processing module includes: The MIPI initialization unit is used to configure the number of transmission channels, data transmission rate, and operating mode of the MIPICSI-2 protocol controller, and to initialize the MIPIDPHY physical layer. The VC channel multiplexing unit is used to assign independent virtual channel IDs to the image data of the four LVDS cameras and encapsulate them according to the MIPICSI-2 protocol. The MIPI protocol encoding unit is used to add data packet headers, check bits, and data packet trailers to the image data transmitted through the virtual channel, completing the parallel-to-serial conversion. The DPHY driver control unit is used to drive the MIPIDPHY physical layer, convert the encoded protocol data into MIPI differential high-speed signal output, and automatically switch between high-speed transmission mode and low-power mode.

[0016] Using the above technical solution, the MIPI signal processing module integrates initialization, VC multiplexing, protocol encoding and DPHY driving, completes the conversion from parallel serial data stream to single-channel MIPI differential signal, and supports automatic switching between high-speed and low-power modes, taking into account both transmission efficiency and vehicle power consumption.

[0017] Preferably, the virtual channel IDs are VC0, VC1, VC2, and VC3, which correspond to the front, rear, left, and right LVDS cameras, respectively.

[0018] By adopting the above technical solution, virtual channel IDs VC0 to VC3 are assigned to the four cameras (front, rear, left, and right) respectively, enabling the vehicle's central control chip to accurately separate the original images of each channel through the channel identifier, and realize crosstalk-free transmission of multiple data under a single physical link.

[0019] Preferably, the vehicle infotainment system's central control motherboard uses the virtual channel identifier in the received single-channel MIPI signal to separate four channels of original image data, and performs fisheye correction, edge stitching, and panoramic fusion processing.

[0020] Using the above technical solution, the vehicle's central control motherboard uses virtual channel identifiers to separate the four original images and directly performs fisheye correction, edge stitching, and panoramic fusion without the need for an external processing unit, reducing latency and improving the real-time performance of the panoramic image.

[0021] Preferably, the FPGA camera four-in-one module is connected to the corresponding part of the vehicle's central control motherboard through the original vehicle wiring.

[0022] Using the above technical solution, the FPGA camera four-in-one module is connected to the vehicle's central control motherboard through the original vehicle wiring, without the need to break wires or modify the original vehicle wiring, achieving non-destructive installation, reducing construction complexity and the risk of wiring failure.

[0023] Compared with the prior art, the beneficial effect of the present invention is that it combines four cameras into a single MIPI system in a time-division multiplexing manner. 1. An FPGA camera quad-module is adopted. This module simultaneously receives signals from four LVDS cameras. Through the internally integrated LVDS decoding module, RAM data cache module, data time-division multiplexing module, and MIPI signal processing module, the four data channels are combined into a single MIPI signal and directly output to the vehicle's central control motherboard. Since there is no need for an external independent 360-degree panoramic host and vehicle codec box, the number of wiring in the vehicle is reduced. Only four cameras need to be connected to the FPGA module, and then connected to the vehicle's central control motherboard by a single MIPI cable. At the same time, the FPGA camera quad-module can directly replace the corresponding part in the original vehicle's central control motherboard. It can be connected through the original vehicle wiring without disassembling the center console, host, and interior parts, or cutting wires or performing additional signal connections. This reduces the difficulty of construction, shortens the installation time, and achieves non-destructive and rapid installation. 2. All signal processing functions are integrated into the FPGA-based four-in-one camera module. The signal link from the camera to the vehicle's central control motherboard consists of only this one active module. The FPGA module uses an automotive-grade crystal oscillator and an internal clock management unit to provide a stable and synchronized operating clock for each module. The LVDS decoding module has a built-in signal anomaly detection mechanism that can monitor and report signal faults in real time. The MIPI signal processing module monitors signal transmission quality in real time and performs dynamic compensation through the DPHY drive control unit. Due to the significant reduction in the number of external devices and adapter nodes, and the automotive-grade design of the FPGA module, which is vibration-resistant and high-temperature resistant, the problems of poor contact, signal interference, system crashes, and black screens caused by multi-level adapters are effectively avoided, significantly improving the stability and reliability of the system in harsh automotive environments. 3. This invention employs a fully digital signal direct transmission method. The differential signals output from the four LVDS cameras are decoded by the LVDS within the FPGA module, then directly buffered by the RAM data cache module. The data time-division multiplexing module then polls and schedules the signals at four times the high-speed clock. The MIPI signal processing module completes protocol encapsulation and parallel-to-serial conversion in one step, ultimately outputting a single MIPI signal to the vehicle's central control motherboard. Throughout this process, the signal undergoes only one format conversion (LVDS to MIPI) within the FPGA, without any additional encoding / decoding or format conversion stages. Simultaneously, the MIPI protocol encoding clock frequency is configured to be greater than four times the camera signal frequency, ensuring no bandwidth bottleneck during time-division multiplexing and maintaining complete original image information after data interleaving. This avoids image quality loss caused by multiple transmissions and conversions, reduces transmission latency, and guarantees the real-time performance and clarity of the panoramic image. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of the overall architecture of the present invention; Figure 2 This is a schematic diagram of the internal functional module framework of the FPGA of the present invention; Figure 3 This is a schematic diagram of the time-division multiplexing data scheduling structure of the present invention; Figure 4 This is a schematic diagram of the MIPI virtual channel (VC) multiplexing transmission of the present invention. Detailed Implementation

[0025] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0026] Please see Figures 1-4 The present invention provides a technical solution: a time-division multiplexed four-camera system merging into a single MIPI system, comprising four LVDS cameras, an FPGA camera four-in-one module, and a vehicle infotainment control motherboard; Four LVDS cameras are installed at the front, rear, left and right of the vehicle to capture real-time images of the vehicle's surroundings and output LVDS differential signals. The FPGA camera quad-module serves as the core signal processing unit. Its input terminals are simultaneously connected to four LVDS cameras, and its output terminal is connected to the vehicle's central control motherboard via a single MIPI interface. This module integrates an LVDS decoding module, a clock module, a RAM data cache module, a data time-division multiplexing module, and a MIPI signal processing module. The vehicle infotainment system's central control motherboard has a single-channel MIPI camera input interface, which receives the single-channel MIPI signal output by the FPGA module. The central control chip of the vehicle infotainment system completes image processing such as fisheye correction, edge stitching, and panoramic fusion, and finally outputs the 360° panoramic image to the central control display screen. The LVDS decoding module receives four LVDS differential signals in real time. Each signal is converted from an LVDS differential signal to a single-ended TTL / CMOS level signal through a differential signal receiver, restoring the original digital image data, line synchronization signal, field synchronization signal and pixel clock signal. The four independent parallel image data, synchronization control signal and pixel clock signal after decoding are synchronously transmitted to the subsequent RAM data buffer module. Meanwhile, the LVDS decoding module has a built-in signal anomaly detection mechanism. When an LVDS signal is lost or interfered with, the module outputs a fault prompt signal in real time for the system to perform fault diagnosis and processing.

[0027] The clock module uses an automotive-grade crystal oscillator as the clock reference to generate the system's main clock signal. The internal clock management unit (CMU) divides the main clock to generate multiple operating clocks adapted to different modules. Provide pixel decoding clock for the LVDS decoding module; Provides a data read / write clock for the RAM data cache module; Provides a data scheduling clock for the data time-division multiplexing module; Provides the MIPI protocol encoding clock for the MIPI signal processing module.

[0028] The frequency of the MIPI protocol encoding clock is configured to be greater than four times the signal frequency of the LVDS camera, thereby providing sufficient bandwidth redundancy for time division multiplexing and ensuring that four data streams can be combined into one without signal synchronization abnormalities. The RAM data cache module adopts four independent dual-port RAM cache units, each corresponding to one LVDS camera. Each dual-port RAM supports asynchronous writing and synchronous reading, realizing the separation of data writing and reading operations. During data writing, the RAM data cache module receives four channels of image data output by the LVDS decoding module, writes each frame of image data into the corresponding RAM cache space in the order of pixels, rows, and fields, and marks the data storage address and frame number in real time. During data reading, the RAM data cache module, according to the control instructions of the time-division multiplexing module, synchronously reads image data from the four RAM channels according to a preset timing sequence, ensuring that the reading rates of the four data channels are completely consistent and achieving synchronous output of the four data channels. The cache capacity is reasonably configured according to the camera resolution and transmission frame rate to ensure reliable storage of complete single-frame image data, and has overflow protection and empty read protection functions.

[0029] The time-division multiplexing module receives four parallel image data streams output from the RAM data buffer module. Based on the data scheduling clock (four times the high-speed clock), it uses time-division multiplexing technology to poll and switch the four parallel data streams in a fixed time sequence and integrate them into one serial data stream. The specific scheduling process is as follows: The FPGA sequentially polls and reads data from four RAM cache units at four times the clock speed. After reading each data unit, it immediately inserts the corresponding virtual channel identifier (VC0~VC3) according to the MIPI protocol format, forming a serial stream containing four data streams, such as... Figure 3 As shown, the time-division multiplexing module simultaneously normalizes the format of the four image data streams, unifying the data bit width, pixel format, and transmission rate, thus eliminating data format differences between the four cameras. The module also dynamically adjusts the multiplexing scheduling timing according to the transmission rate requirements of the MIPI signal processing module, ensuring that the data transmission rate fully matches the MIPI interface specifications. The MIPI signal processing module integrates four major functions: MIPI initialization, VC channel multiplexing, MIPI protocol encoding, and DPHY drive control. It converts the time-division multiplexed serial data stream into a single-channel MIPI differential signal that conforms to the MIPI CSI-2 protocol. The module completes the hardware initialization of the MIPICSI-2 protocol controller, configures core parameters such as the number of transmission channels, data transmission rate, and working mode, initializes the MIPIDPHY physical layer, completes differential impedance matching and signal drive capability calibration, establishes a MIPI communication link with the vehicle's central control motherboard, performs handshake communication with the vehicle's central control motherboard to confirm normal interface connection, reports the device's working status, and waits for the central control chip's read command. Based on MIPICSI-2 virtual channel (VC) technology, independent virtual channel IDs (VC0, VC1, VC2, VC3) are assigned to the image data of four LVDS cameras, corresponding to the front, rear, left, and right cameras respectively. Each data channel is packetized according to the standard MIPI protocol to ensure that the data of each virtual channel is independent of each other and there is no data crosstalk or packet loss. According to the MIPI CSI-2 protocol specification, the image data transmitted by each virtual channel is encapsulated into data packets, and a data packet header, check bit, and data packet trailer are added to ensure the integrity of data transmission; the parallel-to-serial conversion of image data is completed to adapt to the MIPI protocol transmission format; at the same time, the horizontal and vertical synchronization signals and control signals are encapsulated into protocols to generate control data packets that conform to the MIPI specification, so as to realize the synchronous transmission of image data and control signals. The MIPI PHY physical layer is driven to convert the encoded protocol data into MIPI differential high-speed signals, which are then transmitted to the vehicle's central control motherboard via a single MIPI interface. The DPHY drive control unit supports automatic switching between high-speed transmission mode and low-power mode, balancing transmission rate and vehicle power consumption requirements; simultaneously, it monitors the MIPI signal transmission quality in real time, dynamically compensating for signal attenuation or interference to ensure the stability of differential signal transmission and meet automotive-grade signal transmission requirements.

[0030] When using this system, it is connected to the vehicle's electrical system. After the system is powered on, the four LVDS cameras begin to collect images of the vehicle's surroundings and output LVDS differential signals respectively. The FPGA camera quad-module simultaneously receives these four LVDS differential signals. The LVDS decoding module converts the four signals into parallel image data and synchronization control signals, respectively, and sends them to the corresponding four-channel dual-port RAM buffer units for buffering. The clock module provides a unified time base for the entire FPGA, where the MIPI protocol encoded clock is configured to be greater than four times the camera signal frequency, providing sufficient bandwidth for time-division multiplexing. The data time-division multiplexing module reads data from four RAM cache units by polling at four times the high speed clock, interleaving the four parallel data streams into one serial data stream, and inserting VC0 to VC3 channel identifiers into each data packet. This serial data stream is then sent to the MIPI signal processing module. The MIPI signal processing module performs protocol encapsulation, parallel-to-serial conversion, and DPHY driving on the serial data stream, and finally outputs a single MIPI differential signal, which includes a pair of differential clocks and one or more pairs of differential data lines, depending on the configuration. The vehicle's central control motherboard receives the signal through its single-channel MIPI camera input interface. The central control chip parses the data from four virtual channels (VC0 to VC3) according to the MIPI protocol, thereby obtaining four original images from the front, rear, left, and right. The chip further executes image processing algorithms such as fisheye correction, edge stitching, and panoramic fusion to generate a seamless 360° panoramic view, which is then output to the central control display screen for display. This system overcomes the hardware limitation of the original vehicle central control chip, which only supports single-channel MIPI camera input, by using FPGA time-division multiplexing and MIPI virtual channel multiplexing technology. It eliminates the need for the independent 360-degree panoramic host and codec box in traditional solutions, reducing peripherals, wiring and fault points. It adopts direct digital signal transmission throughout the process, reducing image quality loss and transmission delay. At the same time, it replaces the motherboard with the original vehicle wiring, achieving non-destructive modification, simplified construction and stable and reliable system application effects.

[0031] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A time-division multiplexing four-camera system merging into a single MIPI system, characterized in that, include: The LVDS camera has a total of 4 cameras, which respectively capture images from the front, rear, left and right directions of the vehicle, forming a four-way camera. The FPGA camera quad-module simultaneously receives LVDS differential signals from four LVDS cameras and combines the data from the four cameras into a single MIPI signal for output. The vehicle infotainment system's central control motherboard has a single-channel MIPI camera input interface, which receives the single-channel MIPI signal, and the image is processed by the vehicle infotainment system's central control chip before being output to the central control display screen. The FPGA camera four-in-one module includes: The LVDS decoding module is used to convert four LVDS differential signals into parallel image data and synchronization control signals, respectively. The clock module is used to generate the system master clock and provide working clocks for each module. The working clocks include pixel decoding clock, data read / write clock, data scheduling clock, and MIPI protocol encoding clock. The frequency of the MIPI protocol encoding clock is greater than four times the signal frequency of the LVDS camera. The RAM data caching module has four independent dual-port RAM caching units, which respectively receive and cache the four parallel image data streams; The data time-division multiplexing module, based on the data scheduling clock, uses time-division multiplexing technology to poll and schedule the parallel data read from the four RAM cache units into a single serial data stream, and inserts a channel identifier into it; The MIPI signal processing module receives the serial data stream, performs data packet encapsulation and parallel-to-serial conversion according to the MIPICSI-2 protocol, and outputs the single-channel MIPI signal through the MIPIDPHY physical layer driver.

2. The time-division multiplexing four-camera merging into a single MIPI system according to claim 1, characterized in that: The LVDS decoding module has a built-in signal anomaly detection mechanism, which outputs a fault prompt signal when a certain LVDS signal is lost or abnormal.

3. The time-division multiplexing four-camera merging into a single MIPI system according to claim 1, characterized in that: The clock module includes an automotive-grade crystal oscillator and an internal clock management unit. The internal clock management unit divides the main clock to generate multiple working clocks that are adapted to different modules.

4. A time-division multiplexing four-camera system merging into a single MIPI system according to claim 1, characterized in that: Each dual-port RAM cache unit in the RAM data cache module supports asynchronous writing and synchronous reading, and the data time-division multiplexing module synchronously reads the image data in the four RAM data cache modules according to a preset timing sequence to ensure that the four data reading rates are consistent.

5. A time-division multiplexing four-camera merging system into a single MIPI according to claim 1, characterized in that: The time-division multiplexing module also performs format normalization processing on the four-channel image data to unify the data bit width, pixel format, and transmission rate.

6. A time-division multiplexing four-camera system merging into a single MIPI system according to claim 1, characterized in that: The MIPI signal processing module includes: The MIPI initialization unit is used to configure the number of transmission channels, data transmission rate, and operating mode of the MIPICSI-2 protocol controller, and to initialize the MIPIDPHY physical layer. The VC channel multiplexing unit is used to assign independent virtual channel IDs to the image data of the four LVDS cameras and encapsulate them according to the MIPICSI-2 protocol. The MIPI protocol encoding unit is used to add data packet headers, check bits, and data packet trailers to the image data transmitted through the virtual channel, completing the parallel-to-serial conversion. The DPHY driver control unit is used to drive the MIPIDPHY physical layer, convert the encoded protocol data into MIPI differential high-speed signal output, and automatically switch between high-speed transmission mode and low-power mode.

7. A time-division multiplexing four-camera merging system into a single MIPI according to claim 6, characterized in that: The virtual channel IDs are VC0, VC1, VC2, and VC3, which correspond to the front, rear, left, and right LVDS cameras, respectively.

8. A time-division multiplexing four-camera merging system into a single MIPI according to claim 1, characterized in that: The vehicle's central control motherboard uses the virtual channel identifier in the received single-channel MIPI signal to separate four channels of original image data, and performs fisheye correction, edge stitching, and panoramic fusion processing.

9. A time-division multiplexing four-camera system merging into a single MIPI system according to claim 1, characterized in that: The FPGA camera four-in-one module is connected to the corresponding part of the vehicle's central control motherboard through the original vehicle wiring.

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