A visual inspection control panel and method based on optical technology
Patent Information
- Application Number
- CN202610759995.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-05-29
- Publication Date
- 2026-09-22
AI Technical Summary
[0010]本发明目的是:提供一种基于光学技术的视觉检测控制板及视觉检测方法,旨在解决现有技术中存在的环境适应性差、处理速度慢、系统集成复杂、功能单一、缺乏自诊断能力等问题,实现高精度、高速度、强适应性、高可靠性的视觉检测功能
[0014]1. 自适应光照补偿:通过环境光传感器+图像质量评估+多参数闭环反馈,在环境光照变化±50%条件下,输出图像亮度波动控制在±5%以内,无需人工调试。
Smart Images

Figure CN122802799A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the fields of machine vision and industrial inspection, and particularly to a vision inspection control board and vision inspection method based on optical technology. Background Technology
[0002] With the rapid development of intelligent manufacturing, visual inspection technology is playing an increasingly important role in product quality control and automated production lines. Visual inspection systems, through image acquisition, processing, and analysis, can achieve non-contact functions such as dimensional measurement, defect identification, color comparison, and barcode reading, greatly improving production efficiency and product quality stability.
[0003] However, current mainstream visual inspection systems still generally face the following technical bottlenecks and challenges in practical industrial applications:
[0004] 1. Poor environmental adaptability: Existing visual inspection systems are highly sensitive to changes in ambient lighting. Fluctuations in external light, such as natural light and workshop lighting, directly affect the quality of image acquisition, causing problems such as uneven image brightness, decreased contrast, shadows, or reflections. This necessitates frequent manual adjustments to light source and camera parameters (such as exposure time and gain), which not only increases maintenance costs but also makes it difficult to maintain stable detection accuracy under different working environments, severely limiting the system's deployment flexibility and robustness.
[0005] 2. Slow processing speed and insufficient real-time performance: Traditional vision inspection systems typically rely on the main control CPU (such as an industrial computer) for image processing. In high-speed production line scenarios, as image resolution and frame rate increase, the massive image data consumes a significant amount of CPU computing resources, resulting in excessively long image processing and analysis cycles. This bottleneck in processing speed makes it difficult to meet the demands of online inspection systems with extremely high real-time requirements.
[0006] 3. Complex system integration and high cost: A fully functional traditional vision inspection system typically consists of multiple independent hardware units, including industrial cameras, lenses, independent light source controllers, image acquisition cards, and a host computer running processing algorithms. This distributed architecture not only leads to high overall system costs and large physical space requirements, but also requires devices to connect via different communication protocols, making integration and debugging difficult and posing challenges to system stability and reliability.
[0007] 4. Limited functionality and poor flexibility: Most existing systems are designed for specific inspection tasks, and their hardware and algorithms are usually fixed. When the production line needs to change product models or add inspection items, the system hardware often needs to be reconfigured or replaced. The system lacks intelligent adaptability and reconfigurability, and cannot quickly respond to changes in production needs.
[0008] 5. Lack of self-diagnostic capabilities: Existing systems typically lack the ability to monitor their own hardware status in real time and provide early warnings of faults. When light sources age, sensors malfunction, or communication failures occur, the system cannot detect and report them in a timely manner, which may lead to the output of erroneous test results for a long period of time without being noticed, resulting in batch quality incidents.
[0009] Therefore, there is an urgent need for a highly integrated, intelligent, high-performance vision inspection control board with strong environmental adaptability and self-diagnostic capabilities to fundamentally solve the above problems. This invention is proposed precisely to address this need. Summary of the Invention
[0010] The purpose of this invention is to provide a vision inspection control board and vision inspection method based on optical technology, aiming to solve the problems of poor environmental adaptability, slow processing speed, complex system integration, single function, and lack of self-diagnosis capability in the existing technology, and to achieve high-precision, high-speed, strong adaptability and high reliability vision inspection function.
[0011] The technical solution of this invention is:
[0012] A vision inspection control board based on optical technology includes: a core processing unit comprising a main control MCU, an image coprocessor for hardware-accelerated image processing, and a memory, wherein the main control MCU and the image coprocessor interact via shared memory; an optical imaging module comprising a CMOS image sensor and an adjustable focal length lens, wherein the optical imaging module employs a global shutter design; an intelligent light source system comprising a multi-channel independently controllable LED light source array, a PWM dimming unit, and an ambient light sensor; a communication interface; and a fault diagnosis unit. The control board monitors ambient light parameters in real time through the ambient light sensor and, based on image quality assessment results, adaptively adjusts the brightness of the LED light source array and the exposure time and gain of the CMOS image sensor through closed-loop feedback to achieve adaptive illumination compensation.
[0013] Compared with the prior art, the present invention has the following beneficial effects:
[0014] 1. Adaptive illumination compensation: Through ambient light sensor + image quality assessment + multi-parameter closed-loop feedback, the output image brightness fluctuation is controlled within ±5% under ambient light change of ±50%, without the need for manual adjustment.
[0015] 2. Hardware-accelerated high-speed processing: FPGA pipeline parallel processing improves image preprocessing performance by 4-5 times and shortens the overall detection cycle to less than 200ms, meeting the real-time online detection requirements of high-speed production lines.
[0016] 3. Highly integrated single-board design: Image acquisition, processing, light source control, environmental perception, fault diagnosis and communication interface are integrated into a single control board, reducing external devices, reducing system cost by more than 50%, and making it compact and easy to integrate.
[0017] 4. Multi-mode intelligent detection: It integrates multiple algorithm modes such as size measurement, defect detection, color recognition, and barcode reading on a unified hardware platform, which can be quickly switched through communication commands without changing the hardware.
[0018] 5. Low power consumption design: Through DVFS dynamic voltage and frequency adjustment and intelligent light source energy-saving control, the average operating power consumption is less than 5W, which is about 40% lower than the power consumption of traditional solutions.
[0019] 6. Fault self-diagnosis: It has comprehensive self-diagnostic functions such as power monitoring, sensor self-test, light source status monitoring, coprocessor heartbeat detection, memory verification, and temperature monitoring. The MTBF is greater than 50,000 hours. When abnormal, it automatically outputs fault codes and performs protection operations. Attached Figure Description
[0020] The present invention will be further described below with reference to the accompanying drawings and embodiments:
[0021] Figure 1 This is a system architecture diagram of the vision inspection control board of the present invention;
[0022] Figure 2 Here is a flowchart of the adaptive lighting compensation process;
[0023] Figure 3 This is a hardware block diagram of the control board;
[0024] Figure 4 This is a functional diagram of the fault detection unit;
[0025] Figure 5 This is a schematic diagram of the mode switching of the DVFS dynamic power management unit.
[0026] Explanation of reference numerals in the attached figures
[0027] Detailed Implementation
[0028] Example 1: System Overall Architecture and Adaptive Illumination Compensation
[0029] This embodiment details the overall system architecture of the visual inspection control board of the present invention and the implementation of its adaptive illumination compensation function.
[0030] like Figure 1 and Figure 3 As shown, the vision inspection control board of the present invention is divided into four layers according to its architecture:
[0031] Hardware layer: includes CMOS image sensor 201, adjustable focal length lens 202, LED light source array 301, shared memory 103, and interface circuit.
[0032] Processing layer: includes main control MCU 101, image coprocessor 102, PWM dimming unit 302, and communication management unit.
[0033] Algorithm layer: includes image preprocessing, feature extraction, pattern recognition, and decision-making.
[0034] Application layer: includes size measurement, defect detection, color recognition, and barcode reading.
[0035] The specific hardware configuration is as follows:
[0036] • Main control MCU 101: Adopts STMicroelectronics STM32H743 microcontroller, based on ARM Cortex-M7 core, with a main frequency of 400MHz, built-in 1MB SRAM and 2MB Flash, responsible for system control, algorithm scheduling and communication management.
[0037] • Image coprocessor 102: A Xilinx Artix-7 series FPGA (model XC7A35T) is selected for hardware-accelerated image preprocessing. It is connected to the shared memory 103 via a 16-bit parallel bus.
[0038] • Shared memory 103: External 128MB SDRAM, used as a data exchange buffer between the MCU and FPGA, and also for image frame buffering (double buffering mechanism).
[0039] • CMOS image sensor 201: 1280×1024 resolution, supports global shutter, adjustable frame rate from 30 to 60fps, connected to FPGA via LVDS interface, and image data is transferred to shared memory via FPGA DMA controller.
[0040] • Adjustable focal length lens 202: 6-12mm electric zoom, with the focal length adjustment motor controlled via the MCU's I2C interface.
[0041] • Ambient light sensor 303: It adopts a TCS34725 RGB color and light sensor, communicates with the MCU through the I2C interface, has a sampling frequency of 10Hz, and can simultaneously acquire ambient light intensity (Lux) and color temperature (K).
[0042] • LED Light Source Array 301: Contains 4 independently controllable white LED arrays, each with a maximum power of 3W and a total luminous flux of up to 1200lm. The driving circuit of each LED integrates PWM dimming function (frequency 20kHz, resolution 12bit), which can realize continuous brightness adjustment from 0-100%.
[0043] • Communication Interface 400: Provides 2 UARTs (configurable as RS232 or RS485, baud rate up to 921600bps), 1 SPI (up to 50MHz), 1 I2C (400kHz), 1 Ethernet (100Mbps, optional), 1 USB 2.0 (480Mbps), and 1 external trigger input (optically isolated, response time <1μs).
[0044] like Figure 2 As shown, the software workflow for adaptive illumination compensation is as follows:
[0045] Step S1: System Initialization and Parameter Setting
[0046] After the system powers on, all hardware modules are initialized. Default image quality target parameters are loaded: target brightness Targetμ=128 (8-bit grayscale median), target signal-to-noise ratio TargetSNR=40dB, target overexposure Rover<1%, and target contrast C>0.3.
[0047] Step S2: Real-time monitoring of ambient light
[0048] An independent timer task is started to read data from the TCS34725 sensor via I2C at a frequency of 10Hz, acquiring ambient light intensity (range 0–65535 Lux) and estimating color temperature (range 2500K–10000K). When an ambient light intensity change is detected to exceed 10% of the current value, an adaptive adjustment process is triggered.
[0049] Step S3: Image Acquisition and Quality Assessment
[0050] The FPGA controls the image sensor to acquire a single image frame, which is then transferred to shared SDRAM via DMA. The FPGA hardware accelerates the calculation of the following metrics:
[0051] - Average brightness μ: The average grayscale value of all pixels in the entire frame of the image;
[0052] - Contrast ratio C: The ratio of grayscale standard deviation σ to average brightness μ, C=σ / μ;
[0053] - Signal-to-noise ratio (SNR): SNR = 20 × log10 (μ / σnoise), where σnoise is the standard deviation of noise in the dark area;
[0054] - Overexposure Rover: The proportion of pixels with a grayscale value ≥250 out of the total number of pixels.
[0055] Step S4: Multi-parameter coordinated adjustment
[0056] Compare the current image quality index with the target value, and adjust using a proportional feedback mechanism:
[0057] LED brightness adjustment: Lnew = Lcurrent × K1 × (Targetμ / Currentμ);
[0058] Exposure time adjustment: Tnew = Tcurrent × K2 × (Targetμ / Currentμ);
[0059] Gain adjustment: Gnew = Gcurrent × K3 × (TargetSNR / CurrentSNR);
[0060] The weighting coefficients were determined experimentally: K1=0.7 (prioritize adjusting the light source), K2=0.3 (assist in adjusting exposure), and K3=0.5.
[0061] After adjustment, the following limits are applied: LED brightness is limited to 5%–100%, exposure time is limited to 0.1ms–50ms, and gain is limited to 1×–16×.
[0062] Prioritization strategy: First adjust LED brightness (fast response, no noise introduction), then adjust exposure time (may cause motion blur), and finally adjust gain (increases noise). When overexposure ratio > 5%, forcibly reduce LED brightness and exposure time.
[0063] Step S5: Closed-loop feedback and iterative optimization
[0064] After applying the new parameters, reacquire a frame and repeat steps S3 and S4. The closed loop iterates a maximum of 3 times, or stops when all quality indicators are within the tolerance range (brightness error <5%, SNR error <3dB). The convergence time of the entire adaptive adjustment process is less than 300ms.
[0065] Actual test results: When the ambient light changed by ±50%, the brightness fluctuation of the output image remained stable within ±3%.
[0066] Example 2: FPGA Hardware Accelerated Image Processing
[0067] This embodiment focuses on how to use the FPGA coprocessor 102 to achieve hardware acceleration of image processing algorithms.
[0068] 1. Hardware Acceleration Architecture
[0069] The image data stream is designed as follows: CMOS sensor 201 → LVDS interface → FPGA input FIFO → image processing pipeline → FPGA output FIFO → DMA → shared SDRAM 103 → MCU 101.
[0070] The FPGA is internally implemented as a highly parallelized three-stage pipelined processing unit, with each stage connected by a line buffer to achieve pixel-level pipelined processing.
[0071] 2. FPGA Processing Module Implementation
[0072] Gaussian filtering module: Employs a 3×3 Gaussian convolution kernel (weight matrix [1,2,1;2,4,2;1,2,1] / 16). A three-stage pipeline is designed: the first stage has 3 rows of buffered input, the second stage uses 9 multipliers for parallel computation, and the third stage performs addition tree summation and normalization. It processes one pixel per clock cycle, achieving a processing time of approximately 16ms for a 1280×1024 image at a 100MHz operating frequency.
[0073] Sobel edge detection module: Calculates the horizontal gradient Gx and vertical gradient Gy in parallel, and quickly calculates the gradient magnitude |G|=|Gx|+|Gy| using a lookup table (LUT) (approximate calculation to avoid square root operations). Processing time is approximately 20ms.
[0074] Morphological operation module: Implements erosion and dilation operations, supporting 3×3 and 5×5 structure elements. Neighborhood windows are constructed using shift registers, and combinational logic is used for maximum / minimum value comparisons. Processing time is approximately 15ms.
[0075] Histogram statistics module: Uses dual-port RAM to implement 256-bin histogram accumulation, and the histogram calculation time for a single frame image is approximately 13ms.
[0076] 3. Performance Comparison
[0077]
[0078] The overall detection cycle (from triggering to outputting results) is approximately 166ms: image acquisition 30ms + FPGA preprocessing 51ms + MCU algorithm processing 80ms + result output 5ms. This meets the requirement of processing more than 5 products per second. The FPGA's additional power consumption is only about 0.8W.
[0079] Example 3: Multi-mode intelligent detection algorithm
[0080] This embodiment illustrates the specific algorithm application of the control board under different detection modes.
[0081] 1. Size Measurement Mode
[0082] Algorithm flow:
[0083] (1) Use FPGA to perform Sobel edge detection preprocessing and output edge images;
[0084] (2) The MCU performs sub-pixel interpolation positioning of edge points (using Gaussian fitting method) to improve the positioning accuracy to 0.1 pixels;
[0085] (3) Fit the contour points with the minimum bounding rectangle (rotation caliper algorithm) to obtain accurate geometric features;
[0086] (4) Calculate based on the pixel-to-millimeter conversion matrix M, which has been pre-calibrated using standard gauge blocks:
[0087] Actual size = pixel size × M, where M is obtained through Zhang Zhengyou's calibration method.
[0088] Performance metrics:
[0089] - Working distance: Adjustable from 100mm to 500mm;
[0090] - Measurement resolution: 0.01mm / pixel (300mm working distance);
[0091] - Repeatability: ±0.05mm;
[0092] - Measurement range: 10mm~500mm;
[0093] - Single measurement time: <150ms.
[0094] 2. Defect Detection Mode
[0095] Algorithm flow:
[0096] (1) Training phase: Collect 50 to 100 good product images and use Gaussian mixture model (GMM, K=5 Gaussian components) to establish a background statistical model;
[0097] (2) Detection stage: Calculate the Mahalanobis distance of each pixel in the image to be tested to the background model, and extract the foreground (potential defect area) through adaptive threshold segmentation.
[0098] (3) Extract feature vectors from the segmented connected regions: area, perimeter, circularity, aspect ratio, gray mean, gray variance, and LBP texture features;
[0099] (4) Input the feature vector into the pre-trained SVM classifier (RBF kernel function) to determine the defect type (scratches, stains, cracks, dents) or classify it as a good product.
[0100] Performance metrics:
[0101] - Minimum detectable defect size: 0.2mm;
[0102] - False positive rate: <2%;
[0103] - False negative rate: <1%;
[0104] - Single detection time: <200ms.
[0105] 3. Color Recognition Mode
[0106] Algorithm flow:
[0107] (1) Acquire images after adaptive illumination compensation has stabilized (ensure illumination consistency);
[0108] (2) Convert the image from RGB color space to HSV color space (insensitive to changes in brightness);
[0109] (3) Calculate the two-dimensional histogram of H and S components within the user-defined ROI region (H: 36bin, S: 32bin);
[0110] (4) Calculate the Bhattacharyya distance between the histogram and each color template in the pre-stored standard color chart.
[0111] (5) Take the template color with the smallest distance as the recognition result, and calculate the CIELab color difference ΔE as the confidence index.
[0112] Performance metrics:
[0113] - Color resolution: ΔE<3 (CIELab color difference formula);
[0114] - Supported color chart capacity: up to 256 standard colors;
[0115] - Recognition time: <50ms.
[0116] 4. Barcode reading mode
[0117] Algorithm flow:
[0118] (1) Perform adaptive threshold binarization on the image (Otsu method or local adaptive thresholding).
[0119] (2) One-dimensional barcode: The barcode area is located by detecting parallel line segments through Hough transform;
[0120] QR code: positioning by searching for positioning patterns (such as the "hollow square" shape of QR Code, and the L-shaped boundary of Data Matrix);
[0121] (3) Perform perspective transformation correction and downsampling on the positioned barcode area;
[0122] (4) Call a decoding engine to perform decoding and verification (check bit verification is supported).
[0123] Performance indicators:
[0124] - Supported symbologies: Code39, Code128, EAN-13, QR Code, Data Matrix;
[0125] - Reading success rate: >99.5%;
[0126] - Reading time: <100ms;
[0127] - Supported tilt angle: ±45°.
[0128] Example 4: Fault Diagnosis and DVFS Power Management
[0129] This example illustrates the fault self-diagnosis function and dynamic power management strategy of the control board, which is one of the important improvements of the present invention over the prior art.
[0130] 1. Fault diagnosis unit 500
[0131] As shown in Figure 4 , the fault diagnosis unit 500 is implemented by an independent watchdog task in the main control MCU 101, and periodically executes the following self-check items at a frequency of 1Hz:
[0132] (1) Power supply voltage monitoring: sample each path of power supply voltage (3.3V, 5V, LED driving voltage) through the internal ADC of the MCU, compare with the nominal value, and trigger an alarm when the deviation exceeds ±10%.
[0133] (2) Image sensor self-check: read the sensor status register through I2C before each acquisition to confirm that the sensor is online and configured correctly; check whether the acquired image is completely black or completely white (which are fault characteristics of the sensor).
[0134] (3) Light source status monitoring: monitor the driving current of each path of LED through a current sampling resistor, compare with the PWM set value, and determine that the light source is abnormal (aging or open circuit) when the deviation exceeds 20%.
[0135] (4) FPGA heartbeat detection: The MCU sends a heartbeat request to the FPGA every second, and the FPGA returns a response within 10ms. If the timeout occurs, the FPGA is judged to be abnormal.
[0136] (5) Memory verification: When the system is idle, read and write verification is performed on the reserved area of SDRAM (March C algorithm) to detect memory bit flipping faults.
[0137] (6) Temperature monitoring: The temperature of the core area of the PCB is monitored by the onboard NTC thermistor. If the temperature exceeds 85°C, frequency reduction protection is triggered, and if the temperature exceeds 95°C, a safe shutdown is triggered.
[0138] Fault Level and Handling Strategy:
[0139]
[0140] Fault codes are output in a standard format via the 400 communication interface: [timestamp][fault level][module ID][fault code][description], which facilitates fault recording and remote diagnosis by the host computer or PLC.
[0141] 2. DVFS Dynamic Power Management Unit 600
[0142] like Figure 5 As shown, the control board dynamically adjusts power consumption according to the working status to achieve energy-saving goals:
[0143] (1) Full-speed mode (in detection): The MCU operates at 400MHz, the FPGA runs at full speed, and the LED light source is turned on as needed. The system power consumption in this mode is about 6-8W.
[0144] (2) Low-speed mode (waiting for trigger): The MCU frequency is reduced to 100MHz, the FPGA enters low-power standby, the LED light source is turned off, and only the communication interface and trigger input remain active. The power consumption in this mode is about 1.5 to 2W.
[0145] (3) Sleep mode (long-term inactivity): The MCU enters Stop mode, and only the RTC and external interrupt wake-up sources are active. Power consumption in this mode is <0.5W.
[0146] Mode switching strategy:
[0147] - Upon receiving an external trigger signal or communication command → Wake up from low speed / sleep mode to full speed mode (wake-up time <5ms);
[0148] - If no new triggers occur within 500ms after the detection is complete, switch to low-speed mode;
[0149] - No trigger after 30 seconds in low speed mode → Switch to sleep mode.
[0150] Actual power consumption data: In a typical industrial scenario (detection cycle of 2 pieces / second, duty cycle of 40%), the average power consumption is about 4.2W, which is 44% lower than the full-speed always-on solution (about 7.5W).
[0151] Example 5: Communication Interface Application Scenarios
[0152] This embodiment illustrates the specific uses of each communication interface in practical industrial applications:
[0153] (1) UART / RS485 interface (2 channels):
[0154] - Channel 1: Connects to a host computer or PLC to receive detection commands (start / stop / mode switching / parameter configuration) and report detection results (OK / NG / measured value / fault code). The protocol used is Modbus RTU with a baud rate of 115200bps.
[0155] - Channel 2: Connect to an external display screen or alarm for on-site display of test results and status.
[0156] (2) SPI interface: Connects to an external Flash memory to store detection algorithm parameters, calibration data, standard color card templates and historical detection records (the most recent 10,000 records).
[0157] (3) I2C interface: connects ambient light sensor 303, lens focal length control motor, and onboard temperature sensor.
[0158] (4) Ethernet interface (optional): used for high-speed transmission of raw image data to a remote server for archiving or in-depth analysis, supports TCP / IP protocol, and has a transmission rate of 100Mbps.
[0159] (5) USB 2.0 interface: used for firmware upgrades, parameter import and export, and connecting USB cameras (extended applications).
[0160] (6) External trigger input: Optocoupler isolated input, receives synchronous trigger signal (rising edge trigger) from production line PLC, response time <1μs, ensuring precise synchronization with production cycle.
[0161] Application areas
[0162] This invention can be widely applied in the following fields:
[0163] 1. Electronics manufacturing: PCB board defect detection, component appearance inspection, solder joint quality inspection, and silkscreen character recognition.
[0164] 2. Automobile manufacturing: Component size measurement, surface defect detection, assembly integrity inspection, VIN code identification.
[0165] 3. Food Packaging: Packaging integrity inspection, label location inspection, production date identification, and foreign object detection.
[0166] 4. Pharmaceutical industry: Drug appearance inspection, packaging sealing inspection, batch number identification, and defect classification.
[0167] 5. Textile industry: Fabric defect detection, color consistency inspection, pattern alignment inspection, and size measurement.
[0168] 6. Semiconductor industry: wafer surface defect detection, chip pin inspection, and package appearance inspection.
[0169] The above embodiments are only for illustrating the technical concept and features of the present invention, and are intended to enable those skilled in the art to understand the content of the present invention and implement it accordingly. They should not be construed as limiting the scope of protection of the present invention. All modifications made according to the spirit and essence of the main technical solution of the present invention should be covered within the scope of protection of the present invention.
Claims
1. A vision inspection control board based on optical technology, characterized in that, include: The core processing unit includes a main control MCU, an image coprocessor for hardware-accelerated image processing, and a memory; the main control MCU and the image coprocessor interact with each other through shared memory. An optical imaging module includes a CMOS image sensor and an adjustable focal length lens. The optical imaging module adopts a global shutter design, and the image data of the CMOS image sensor is transferred to the shared memory via DMA. The intelligent light source system includes a multi-channel independently controllable LED light source array, a PWM dimming unit, and an ambient light sensor; A communication interface used for data exchange with external devices; The fault diagnosis unit is used to perform periodic self-tests on each functional module of the control board and output diagnostic information. The control board monitors ambient light parameters in real time through the ambient light sensor, and based on the quality assessment results of the images acquired by the CMOS image sensor, performs adaptive closed-loop feedback adjustment on at least two parameters among the brightness of the LED light source array, the exposure time of the CMOS image sensor, and the gain, so as to achieve adaptive illumination compensation.
2. The vision inspection control board according to claim 1, characterized in that, The adaptive illumination compensation includes the following steps: Step S1: The ambient light intensity and color temperature are monitored in real time at a preset frequency using the ambient light sensor. Step S2: Evaluate the quality of the image acquired by the CMOS image sensor and calculate at least two of the following indicators: average brightness, contrast, signal-to-noise ratio, and overexposure rate. Step S3: Based on the evaluation results of step S2, dynamically adjust the brightness of the LED light source array, the exposure time and gain of the CMOS image sensor through a proportional feedback mechanism; Step S4: After adjustment, re-acquire the image and evaluate it. If the target image quality is not achieved, iterate and adjust until the target is achieved or the maximum number of iterations is reached.
3. The vision inspection control board according to claim 2, characterized in that, In step S3, the parameter adjustment is performed using the following formula: LED brightness adjustment: Lnew = Lcurrent × K1 × (Targetμ / Currentμ), Exposure time adjustment: Tnew = Tcurrent × K2 × (Targetμ / Currentμ), Gain adjustment: Gnew = Gcurrent × K3 × (TargetSNR / CurrentSNR), Where K1, K2, and K3 are weighting coefficients, Targetμ is the target brightness, Currentμ is the current average brightness of the image, TargetSNR is the target signal-to-noise ratio, and CurrentSNR is the current image signal-to-noise ratio; In step S4, the maximum number of iterations is 3, and the convergence time is less than 300ms.
4. The vision inspection control board according to claim 1, characterized in that, The image coprocessor is an FPGA or DSP, and its internal implementation is a pipelined processing architecture, used for hardware acceleration to perform at least one image preprocessing operation among image filtering, edge detection, morphological operations and histogram statistics. The image preprocessing time of the image coprocessor is less than 30% of the pure software processing time.
5. The vision inspection control board according to claim 1, characterized in that, The main control MCU runs a multi-mode intelligent detection algorithm, supporting at least two of the following modes: size measurement mode, defect detection mode, color recognition mode, and barcode reading mode. The multi-mode intelligent detection algorithm can receive external commands through the communication interface to switch modes.
6. The vision inspection control board according to claim 5, characterized in that, The algorithm flow for the size measurement mode includes: Edge detection is performed on the image to extract the body contour, subpixel edge localization is performed, minimum bounding rectangle fitting is performed on the contour, and calculations are performed based on a pre-established pixel-to-physical size transformation matrix to achieve a measurement accuracy of ±0.1mm.
7. The vision inspection control board according to claim 5, characterized in that, The algorithm flow of the defect detection mode includes: Background modeling based on Gaussian mixture model, foreground segmentation to extract abnormal regions, extraction of area, perimeter, roundness and texture features of abnormal regions, and defect type determination using support vector machine classifier; The defect detection mode can detect defects with a minimum size of 0.2 mm, with a false detection rate of less than 2% and a false negative rate of less than 1%.
8. The vision inspection control board according to claim 5, characterized in that, The algorithm flow for the color recognition mode includes: The image is converted from the RGB color space to the HSV color space, color histogram statistics are performed on the target area, and the statistical results are compared with the color data of the preset standard color card to achieve color resolution with a color difference ΔE of less than 3.
9. The vision inspection control board according to claim 5, characterized in that, The algorithm flow for the barcode reading mode includes: The system performs adaptive threshold binarization on images, identifies and locates barcode regions through Hough transform or positioning patterns, and decodes and verifies the located barcode regions to support 1D and 2D barcodes including Code39, Code128, QR Code, and Data Matrix, with a reading time of less than 100ms.
10. The vision inspection control board according to claim 1, characterized in that, The control panel also includes: The dynamic voltage and frequency adjustment unit is used to dynamically adjust the operating frequency and power supply voltage of the main control MCU according to the computational load of the current detection task. An intelligent light source energy-saving control unit is used to automatically reduce or turn off the output of the LED light source array during non-detection periods; This ensures that the power consumption of the control board is less than 8W during full-load detection, less than 2W during standby, and less than 5W during average operation.
11. The vision inspection control board according to claim 1, characterized in that, The fault diagnosis unit performs the following self-test items: Power supply voltage monitoring: Monitor whether the power supply voltage of each circuit is within the allowable range; Image sensor self-test: checks whether the image sensor communication is normal and whether the image data is valid; Light source status monitoring: Detects whether the drive current of each LED light source is normal; Coprocessor heartbeat detection: Monitors whether the image coprocessor is responding normally; Memory verification: Performing periodic read and write verifications on the memory; Temperature monitoring: Monitor whether the temperature in the core area of the control board exceeds the limit; When the fault diagnosis unit detects an anomaly, it outputs a fault code through the communication interface and performs an alarm or safety shutdown operation according to the fault level.
12. The vision inspection control board according to claim 1, characterized in that, The communication interface includes: At least one serial communication interface is provided for exchanging detection results and control commands with a host computer or PLC; At least one high-speed data interface for outputting raw image data or detection process data; At least one trigger input interface is provided to receive external synchronization trigger signals to achieve synchronization with the production line.
13. A visual inspection method based on the visual inspection control board according to any one of claims 1-12, characterized in that, include: Step A: Acquire an image of the target under test using the intelligent light source system and optical imaging module; Step B: The acquired image is preprocessed using the image coprocessor with hardware acceleration. Step C: The main control MCU calls the intelligent detection algorithm corresponding to the detection task to analyze the preprocessed image and obtain the detection result; Step D: Output the detection result through the communication interface; Step E: The fault diagnosis unit performs periodic self-checks on the system to ensure the reliability of the test results; In step A, the adaptive illumination compensation is continuously performed to maintain stable image quality.
14. The visual inspection method according to claim 13, characterized in that, In step B, the hardware acceleration preprocessing includes: By using an FPGA pipeline to perform Gaussian filtering, Sobel edge detection, and morphological operations in parallel, the preprocessing time for a single frame image is reduced to less than 60ms.
15. The visual inspection method according to claim 13, characterized in that, Also includes: Before step A, based on an external trigger signal or a preset detection cycle, the main control MCU is woken up from a low-power standby state to a full-speed working state through the dynamic voltage and frequency adjustment unit, and the LED light source array is turned on simultaneously. After step D, if no new detection is triggered within a preset time, the operating frequency of the main control MCU is reduced and the LED light source array is turned off, entering a low-power standby state.